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GaAs MESFET

:
Fabrication and Characterization
Written and fllustrated by
Jeffrey Frederick Gold
Fitzwilliam College
University of Cambridge
Michaelmas 1996
GaAs MESFET: Fabrication and Characterization
Jeffrey Frederick Gold
Fitzwilliam College
University of Cambridge
Cambridge CB3 ODG
United Kingdom
Microelectronics Research Centre
Cavendish Laboratory
Department of Physics
University of Cambridge
Cambridge CB3 OHE
United Kingdom
Created November 23, 1996
Run December 13, 1996
Copyright @1996
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Copyright © 1996 by Jeffrey F. Gold. All rights reserved.
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the manuscript .
Contents
Acknowledgements Vll
Introduction vm
1 History of MESFET Technology 1
1.1 Introduction . . . 1
1.2 History . . . . . . . . . . . . 1
1.3 Gallium Arsenide . . . . . . . 1
1.4 Gallium Arsenide Technology 3
1.5 MESFET Technology 4
2 MESFET Operation 5
2.1 Introduction . . . . 5
2.2 MESFET Operation 5
2.3 Schottky Contact . . 5
2.4 Qualitative Description of Model for MESFET Operation 8
2.5 Quantitative Description of Model for MESFET Operation 9
2.6 Theoretical Characteristics . . . . . . . . . . . . . . . . . . 10
3 MESFET Fabrication
3.1 Introduction .....
3.2 Principal Fabrication Processes
3.2.1 Chip Preparation .. .
3.2.2 Photolithography .. . .
3.2.3 Metallization Process
3.2.4 I-V Characteristics Before Annealing
3.2.5 Annealing of Ohmic Contacts . . . .
3.2.6 I-V Characteristics After Annealing
3.2.7 Wet Etching of Mesas .. .
3.2.8 Talystep Profiling . . . . .
3.2.9 Electron Beam Lithography
3.2.10 Gate Metallization . ....
3.2.11 Conclusion of MESFET Fabrication
3.3 Improvements in Fabrication Processes . . .
11
11
11
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13
13
13
13
14
14
14
16
16
16
16
4 Experimental Characteristics of MESFET Devices
4.1 Introduction ........... . . .
4.2 Device Testing and Characterization
4.2.1 Transconductance .....
4.2.2 Transmission Line Method
4.2.3 C- V Characteristics
4.3 Performance Limits .
5 Summary
6 Conclusion
7 References
8 Appendix
8.1 Scanning Electron Microscopy of MESFET Devices .
8.2 Scanning Electron Microscopy of Test Structures
8.3 Lithographic Layout Files . . . . . . . . . . . . . . .
11
18
18
18
18
21
21
21
23
24
25
27
27
27
27
List of Figures
1.1 Gallium arsenide is a direct band-gap material. The band
structure includes satellite valleys which give rise to the Gunn
effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Operation of MESFET device: (a) At zero gate voltage, the
MESFET device exhibits surface depletion and a larger deple-
tion region immediately below the gate contact, (b) increased
gate voltage causes the depletion region to expand until (c)
the depletion region "pinches off" the conduction channel. . . 6
2.2 Energy- band diagrams for metal-semiconductor interface: qci>m
represents the work function of the metal, qX represents
the electron affinity of the semiconductor, qcJ> s represents the
work function of the semiconductor, Ec is the conduction
band energy level, Ev is the valence band energy level, and
E F is the Fermi energy level. illustrations (a) through (d)
represent the succeeding stages of a metal being placed in
intimate contact with a semiconductor. . . . . . . . . . . . . . 7
2.3 Depletion region occurring between metal-semiconductor in-
terface.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Current-Voltage characteristics (Shockley curves) of typical
MESFET device. The dotted line represents the points at
which "pinch-off" occurs. . . . . . . . . . . . . . . . . . . . . 10
3.1 Cross-section of modulation-doped GaAs substrate. The layer
below the mesa n-doped region is considered to be "semi-
insulating" because of the large band-gap energy of GaAs. . . 12
3.2 Source-Drain 1-V Characteristic of gate recess etch monitor-
ing structure before annealing. Note the non-ohmic contact
characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
lll
3.3 Source- Drain I-V Characteristic of gate recess etch monitor-
ing structure after annealing. Note ohmic contact charac-
teristic due to diffusion of germanium from alloy contact into
iv
bulk semiconductor. During the annealing procedure, gallium
preferentially diffuses out of the GaAs melt and the semicon-
ductor side of the interface reconfigures as a highly n-doped
semiconductor by the gallium-germanium substitution. . . . . 15
3.4 Geometry of final MESFET device. Gate widths consisted
of three varieties: 1 J.tm, 2 J.tm, and 3 J.tm. Source to drain
width was 10 J.lm. . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Experimental set-up for testing of I-V characteristics of MES-
FET device. The gate and drain contacts were held at a
positive voltage   ~ 0) relative to the source contact. . . . . . 19
4.2 Current-Voltage characteristics of MESFET device giving the
typical Shockley curve for zero gate voltage. Device satura-
tion occurs at approximately 4 Volts. . . . . . . . . . . . . . . 19
4.3 Current-Voltage characteristics of MESFET device for reverse
bias test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4 Current-Voltage characteristics of MESFET device with mi-
croscope light on/off. This shows the effect of light on device
characteristics. Note a shifting of approximately 0.5 mA in
device performance. It may also account for a slight bias in
the saturation voltage. . . . . . . . . . . . . . . . . . . . . . . 20
4.5 Current-Voltage characteristics of MESFET device for differ-
ing gate voltages resulting in a series of typical Shockley curves. 21
4.6 Circuit diagram for Transmission Line Test. Measurement of
the current allowed measurement of Ttotal = 2Rcontact + Rsheet. 22
4. 7 Graph of Contact Spacing ( s) vs. Semiconductor Sheet Re-
sistance (r). The straight line is given by r = .0193s- 9.11,
with R
2
= .999. There were only four data points obtained
from this experiment since the 5 J.lm spacing was shorted. It is
conceivable to get many more data points by measuring sheet
resistances across the contacts as well. The sheet resistance
varied between 1.41 f!/(J.tm)
2
and 1.99 f!/(J.tm)
2
. . . . . . . . 22
8.1 Scanning Electron Micrograph of MESFET device. Ideally,
the lower contact should be the source, in order to increase the
transconductance, as the gate contact is well positioned away
from the drain contact. Note the periphery of the gate con-
tact, produced by Electron Beam Lithography, as compared
to the source and drain contacts, produced by Photolithog-
raphy. Symmetry of etching around perimeter of source and
drain contacts, indicate that the problem lies in the etching
rates (longer etching rates may cause non-uniform etching
to occur) and/or the particular lithographic method (pho-
tolithography vs. electron beam lithography and chemistry of
v
resists). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2 Scanning Electron Micrograph of MESFET device. Note that
gate width (3 J.Lm) is larger than that of Fig. 8.1. . . . . . . . 29
8.3 Oblique view of MESFET device. Note surface uniformity
of gate contact in contrast to pitting and other malignancies
on source and drain contacts. The non-uniformity of gate
contact occurs in region where contact folds over the GaAs
mesa-etched structure. . . . . . . . . . . . . . . . . . . . . . . 30
8.4 Scanning Electron Micrograph of drain-gate-source region of
MESFET. Ideally, the gate contact is closer to the source
contact. Note the quality of the gate contact as compared to
the alloyed source and drain contacts. . . . . . . . . . . . . . 31
8.5 Scanning Electron Micrograph of MESFET. Visible are the
gate, source, and drain contacts situated on the mesa-etched
GaAs. By visual inspection of the morphology, it is clearly
seen that the gate contact, created by Electron Beam Lithog-
raphy, is superior in quality to that of the photolithographi-
cally created source and drain contacts. . . . . . . . . . . . . 32
8.6 Scanning Electron Micrograph of ohmic contact sub-field, or
"spider" test structure. The 6 contact pads are spaced at 5
J.Lm, 10 J.Lm, 15 J.Lm, 20 J.Lm, and 25 J.Lm. This device was used
in the Transmission Line Method (TLM) to measure sheet
resistance of underlying mesa-etched GaAs. . . . . . . . . . . 33
8.7 Scanning Electron Micrograph of test structure. . . . . . . . . 34
8.8 Layout for mesa and ohmic contact structures of the mask.
The pattern was approximately 4 mm by 4 mm and was
designed to fit on 5 mm by 5 mm GaAs wafers. . . . . . . . . 35
8.9 Detail of various test structures not shown in Fig. 8.8. . . . . 36
8.10 Layout of ohmic contact sub-field, affectionately known as a
"spider" . Probing of the contact pads enables determination
of the sheet resistance of underlying conducting layer of GaAs
and resistance of the contact pads. The 6 contact pads are
spaced at 5 J.Lm, 10 J.Lm, 15 J.Lm, 20 J.Lm, and 25 J.Lm. . . . . . 37
Vl
8.11 Layout for FATFET C-V test structure. This device would
have ideally been used to measure C-V characteristics of the
gate metal-semiconductor junction and measure the doping
profile of the semiconductor. . . . . . . . . . . . . . . . . . . . 37
8.12 Layout of the gate-recess etch monitoring structure. The
oversized pads allowed for repeated testing of device before
and after strip annealing. . . . . . . . . . . . . . . . . . . . . 38
8.13 Layout of MESFET device. The gate is ideally positioned
closer to the source, rather than positioned centrally. . . . . . 38
Acknowledgements
I am indebted to the professors of the Microelectronics Research Centre for
extending me the opportunity to study at the University of Cambridge.
In relation to this practical, I would especially like to thank our lab
assistants Songphol Kanjanachuchai and Candice Yuca for their valuable
help. I would also like to extend my gratitude to the other 1996 MPhil
students for making this experience an enjoyable and unforgetful one; they
are: Ioana Simionescu (St. John's), Nick "Park" Clark (Fitzwilliam), Steven
Keller (Churchill), Mark Hersam (Churchill), Firouzeh Sabri (Trinity), and
Jason Tan (Downing).
Thanks are also in order for those who provided devices in those circum-
stances in which it was not possible to obtain data from my own devices.
Vll
Introduction
The following manuscript was submitted as part of the MPhil program
in Microelectronic Engineering and Semiconductor Physics at the Micro-
electronics Research Centre of the Cavendish Laboratory at the University
of Cambridge. The manuscript concerns the fabrication and characteriza-
tion of MESFET devices undertaken as part of the MESP practicals during
Michaelmas term 1996.
Vlll
Chapter 1
History of MESFET
Technology
1.1 Introduction
Herein we describe the history of MESFET technology and the various prop-
erties of gallium arsenide (GaAs) which lend themselves to the technology
in question.
1.2 History
The experimental work of J. Gunn in the early sixties led to the discov-
ery of sustained electronic oscillations when gallium arsenide was subjected
to a sufficiently large direct current (DC) bias. This remarkable property
heralded the production of bulk microwave and millimeter-wave devices and
concomitantly provided the impetus for intensive research into the solid state
physics of compound semiconductor devices. Later, the work of Ruch sug-
gested that the non-steady state aspects of semiconductor transport would
improve the operating speed of devices by an order of magnitude from the
then available technology. Further research eventually led to High Electron
Mobility Transistors (HEMTs) , considered by many the current phase of
gallium arsenide technology.
1.3 Gallium Arsenide
All of this, of course, is facilitated by the unique properties of III-V binary
semiconductors such as GaAs. Gallium arsenide is a direct band-gap ma-
terial, as illustrated in Fig. 1.1. The satellite conduction bands combined
with the resulting negative differential resistance is what allows for these
devices to be used for the aforementioned microwave and millimeter-wave
technologies.
1
CHAPTER 1. HISTORY OF MESFET TECHNOLOGY 2
Energy (eV)
0
-6
-12
L r X K r
k
Figure 1.1: Gallium arsenide is a direct band-gap material. The band struc-
ture includes satellite valleys which give rise to the Gunn effect.
CHAPTER 1. HISTORY OF MESFET TECHNOLOGY 3
Useful properties of GaAs are its direct band-gap, which gives rise to
optical applications, and its high electron mobility. For example, the ideal
room temperature electron mobility is found to be between 8,000 cm
2
/V s
and 10,000 cm
2
/V s. In n-doped silicon, for example, the electron mobility
at the same conditions is only about 1500 cm
2
/V s. The effective low-field
mobilities and direct band-gap energies of various binary compound semi-
conductors are listed in Table 1.1.
Other useful properties of GaAs include its high impedance; negative
temperature coefficient (current decrease with temperature increase) which
allows for uniform temperature distribution throughout the bulk material
and simultaneously prevents thermal breakdown; its unipolar conduction
mechanism, which allows for high switching speeds because of the absence
of minority carrier storage effects; and its hardiness to radiation.
Table 1.1: Characteristics of some binary compound
semicond uctors.
1
Compound Effective Electron Direct Energy
Mass Low-Field Mobility Band-Gap
GaAs 0.063 9,200 em 'I. jV s 1.424 eV
AlAs 0.71 300 em 'I. /V s 2.98 eV
InSb 0.0136 77,000 cm
2
jV s 0.230 eV
1.4 Gallium Arsenide Technology
Although gallium arsenide is slowly becoming mainstream technology, sil-
icon continues to dominate the semiconductor industry for good reasons.
Exposed gallium arsenide surfaces cannot withstand the high temperatures
required for diffusion processes; therefore, ion implantation techniques are
being currently actively pursued to eliminate this deficiency.
Another outstanding problem concerns the problem of a native oxide
with the dielectric strength or surface passivating qualities that already exist
in the mature technology of silicon dioxide-silicon systems. Even without the
insulating layers ubiquitous in silicon technology, extremely efficient, if not
speciallized, devices can be manufactured from this alternative to silicon.
These shortcomings can make gallium arsenide an expensive technology;
however, the demand for speed in the computer industry outweighs any cost
considerations. Gallium arsenide can operate at the frequencies of 20 GHz
as opposed to the 'saturnine' operating speeds of silicon. Because GaAs
possesses a large band-gap, this makes it suitable to utilize it as substrates
1
Effective mass is factor of free electron mass at conduction band minima. Table
adapted from [Madelung, 1987].
CHAPTER 1. HISTORY OF MESFET TECHNOLOGY 4
that electrically isolate structures, which themselves are then composed of
dopant-varying top-layers.
1.5 MESFET Technology
Field Effect Thansistors (FETs) are unipolar devices, meaning the conduc-
tion carriers are of one polarity, i.e., the conduction mechanism is facilitated
either by electrons or holes, but not both simultaneously. This type of
device, specifically the Junction Field Effect Transistor ( JFET), was first
envisioned by Shockley in 1952.
A MESFET is a JFET device in which the gate junction consists of a
metal-semiconductor Schottky contact. Gallium arsenide has a high density
of states at the interface with insulators; therefore MESFETs must utilize
metal-semiconductor rectifying Schottky contacts.
MESFETs, conceptually similar to unijunction transistor devices, oper-
ate on the principal of regulating the conduction channel conductivity rather
than varying the number of carriers. A problem with junction transistor
devices is their sensitivity to any influences which affect minority carrier
concentrations. Unfortunately, unijunction devices are also susceptible to
the effects of temperature and exposure to atomic radiation; they are also
low-impedance devices.
Chapter 2
MESFET Operation
2.1 Introduction
Herein we describe the physics of MESFET technology.
2.2 MESFET Operation
A MESFET may be characterized as a voltage controlled resistor. As shown
in Fig. 2.1, the region between the source and the drain and immediately
beneath the metal gate contact (Schottky barrier contact) consists of the
conduction channel which is regulated by a depletion region. In essence,
the resistance of the conduction channel is regulated by varying the voltage
applied to the metal gate, i.e., the Schottky barrier contact regulates the
channel conductivity.
The channel region is partially depleted by the voltage applied to the
gate, as the conduction channel has a finite cross section, even at zero gate
voltage, as illustrated in Fig. 2.l(a).
2.3 Schottky Contact
The use of a Schottky gate is motivated by the absence of a stable oxide or
insulating layer for gallium arsenide.l Alloy contacts to the bulk semicon-
ductor tend to reduce surface states and the barrier height. In the case of
the MESFET devices described herein, the Schottky barrier contacts were
constructed of a gold-germanium-nickel (AuGeNi) alloy which served as the
interface between the semiconductor and the overlying gold (Au) contact.
Upon deposition, germanium tends to diffuse into the semiconductor and
occupy vacant gallium sites, which has the effect of increasing the effective
1
A poor quality oxide exists for GaAs, but no effective insulating materials have as of
yet been identified.
5
CHAPTER 2. MESFET OPERATION 6
Depletion Region
Figure 2.1: Operation of MESFET device: (a) At zero gate voltage, the
MESFET device exhibits surface depletion and a larger depletion region
immediately below the gate contact, (b) increased gate voltage causes the
depletion region to expand until (c) the depletion region "pinches off" the
conduction channel.
CHAPTER 2. MESFET OPERATION 7
8
T
 

 
(a)
T qV

Figure 2.2: Energy- band diagrams for metal-semiconductor interface: qi}m
represents the work function of the metal, qX represents the electron affinity
of the semiconductor, qi}
8
represents the work function of the semiconductor,
Ec is the conduction band energy level, Ev is the valence band energy level,
and Ep is the Fermi energy level. illustrations (a) through (d) represent
the succeeding stages of a metal being placed in intimate contact with a
semiconductor.
CHAPTER 2. MESFET OPERATION
8
Metal ,w
Depletion Region
Figure 2.3: Depletion region occurring between metal-semiconductor inter-
face.
donor concentration (up to 5 x 10-
19
cm-
1
).
The energy-band diagrams for a Schottky metal-semiconductor contact are
shown in Fig. 2.2.
2.4 Qualitative Description of Model for MESFET
Operat ion
Although many models exist for MESFET operation, none are directly ap-
plicable in the case of our modulation-doped MESFET devices. As such, a
model which is a slight modification of an existing model is proposed.
In the case of our MESFET devices, the mesa-etched active layers consist
of 10 nm GaAs, 45 nm Alo.33Gao.67As, and 25 nm i-Alo.33Gao.67As, as
illustrated in Figure 3.1. (it is assumed that no relevant physics occurs in
the 20 nm layer of i-GaAs, top layer of semi-insulating layer but part of the
mesa-etch.
With the preliminaries out of the way, the model is introduced as a
variant of the Shockley model: the Shockley model is assumed for each of
the three active layers independently, with the proviso that each succeeding
layer, already having its own compositional parameters, is regulated not by
the gate voltage but by the voltage experienced at that penetration depth at
which the new layer interfaces with the preceding one.
2
Thus, the problem
can be easily broken into three manageable pieces for mathematical charac-
terization. That is to say, the top layer, consisting of 10 nm GaAs will be
characterized by a gate voltage of
Viayer 1 = VaaAs = Vgate ,
2
It is also assumed that no other effects modify the voltage each layer experiences.
This may be sufficient for a first-order approximation, but would not be sufficient for a
realistic description of the relevant physics.
CHAPTER 2. MESFET OPERATION 9
while the next layer, namely the 45 nm layer of Alo.33Ga
0
.
6
1As, will be
characterized by a 'gate voltage' of
Viayer 2 = VA/
0
.
33
Ga
0
.
67
As = Vgat e ( 1 - ::) = 0.875 · Vgat e ,
and the final active layer of 25 nm i-Alo.33Ga
0
.
6
1As is characterized by a
'gate voltage' of
(
55 nm)
Viayer 3 = Vi-Alo.33 Ga.o.67AS = Vgate 1- 80 nm = 0.375. Vgat e .
It must be noted however, that this model should exhibit some minute be-
havior, perhaps at a level of refinement not seen in our experiments, where
one discerns the individual saturation of each layer. The saturation current,
however, should be the combined saturation currents of all three layers .
Another strategy might consist of modelling the modulation-doped MES-
FET device as a group of 6 variable resistors in parallel, two resistors for each
of the three active layers; the two resistors would then represent the variable
resistances of the depletion region and the conduction channel, respectively,
for each active layer.
2. 5 Quantitative Description of Model for MES-
FET Operation
We find in Sze, Pierret, Wang, and others the derivations of the relevant
equations that characterize the behavior of MESFET devices. The funda-
mental equation of MESFETs is given by the drain-source current equation
I _ [v _ 2(Vv + Vbi -   (Vbi -  
ds - 9o D
3
JV; ,
where the conductance of the doped conduction channel is given by
qJ.LnNvW A
9o = A ,
and the pinch-off voltage is
V. _ qNvA
2
po - 2E
and Vbi is the built-in voltage, Vv is the source-to-drain voltage drop in
the conduction channel under the gate, Vi ayer is the voltage applied to each
layer, N D is the dopant concentration, L is the gate length, and the depletion
region thickness is given by
1
A = Ad( L) = [2E(Vv + Vbi - Viayer )]
2
qNv
CHAPTER 2. MESFET OPERATION 10
Gate Voltage {V) = 0
¥1
*' 1• Gate Voltage (V) < 0
Drain Voltage
Figure 2.4: Current-Voltage characteristics (Shockley curves) of typical
MESFET device. The dotted line represents the points at which "pinch-
off" occurs.
for the pinch-off condition. Combining this with information from the con-
stant mobility model (Shockley model) , one obtains the drain-source satu-
ration current
Vpo 2 (Vbi -  
2
[
3 l
(Ids)sat =go 3 + 3J"V; - vbi + .
Thus, according to our model, the saturation current is then given by
2.6 Theoretical Characteristics
The device characteristics , if the model is to agree with experimental results ,
must be commensurate with the typical Shockley curves, shown in Fig. 2.4,
derived from such devices.
Chapter 3
MESFET Fabrication
3.1 Introduct ion
Herein we describe of fabrication of MESFET devices.
3.2 Principal Fabrication Processes
The fabrication process consisted of the following sequential procedures:
3.2.1 Chip Preparation
The two wafers selected for the fabrication of MESFET devices already ex-
isted in a 5 mm by 5 mm format. The wafers consisted of a typical Vapour
Deposition Epitaxy (VPE)-grown MESFET material, whose cross-sectional
view is given in Fig. 3.1. Each wafer was also already marked in one corner
for orientation, although following the source/ drain metallization process, it
was sufficient to inspect the wafers visually.
The surface was prepared by soaking the wafers in acetone (ultrasound)
for a duration of approximately 4 minutes. The same procedure was re-
peated, albeit with isopropyl alcohol (IPA) for 3 minutes, and then dried
with gaseous nitrogen. Microscopy was then used to inspect the surface for
defects and other malignancies. This was done to ensure good adhesion of
the photo-resist to the surface. The wafers were then baked for approxi-
mately 20 minutes at 70 °C. Photo-resist (S1813) was then spun on for 30
seconds at 5000 rpm. This would ideally deposit a 1.2 J.Lm layer of photo-
resist on the surface of the wafers . The wafers were then again baked for
a duration of 30 minutes at approximately 70 °C. The wafer surfaces were
again inspected for impurities and dust.
11
CHAPTER 3. MESFET FABRICATION
Mesa
n-doped
GaAs
12
Figure 3.1: Cross-section of modulation-doped GaAs substrate. The layer
below the mesa n-doped region is considered to be "semi-insulating" because
of the large band-gap energy of GaAs.
CHAPTER 3. MESFET FABRICATION 13
3.2.2 Photolithography
The wafers were aligned to a mask on an optical mask aligner, and exposed
to ultra-violet (UV) light for 20 seconds. Each wafer was then immersed in
chlorobenzene for 1 minute, and dried with gaseous nitrogen. The wafers
were agitated in the developer, MF319, for 3 minutes and bathed in de-
ionized water and dried with nitrogen. (The actual process of development
consisted of 2 minutes agitation in the developer MF319, optical microscopic
inspection, another 30 seconds in the developer, inspection, and a final 30
seconds in the developer, until the desired result was achieved. This was
chiefly done by inspection of the registration marks). The wafers were then
exposed to plasma-ionized oxygen in a PlasmaPrep 300. This procedure
lasted 2 minutes and was performed to remove the remaining layer of resist
(approximately 10- 20 nm). The PlasmaPrep 300 was operated at about 258
Watts ( 3 Watts reflected) at 0.3 Torr. The wafers were then soaked in
a 10:1 H
3
P0
4
: H
2
0 solution for 40 seconds, cleaned in de-ionized water,
and dried using gaseous nitrogen.
3.2.3 Metallization Process
The thermal vapour deposition chamber was prepared as were the boats
that held the gold and gold-germanium-nickel alloy for deposition. The
wafers were loaded above the boats, and the alloy was deposited, followed
by deposition of gold. The wafers were soaked in acetone in order to lift-
off the Au/ AuGeNi from the main surface, leaving the remainder of the
deposition in the undercut regions not exposed to the resist. This process
resulted in the fabrication of the metallic source and drain contacts. The
wafers were then soaked in IPA and dried using nitrogen. Upon drying, the
wafers were visually inspected under a microscope. Then the wafers were
baked for approximately 30 minutes at 70 °C.
3.2.4 1-V Characteristics Before Annealing
The 1-V (current-voltage) characteristics were measured for a gate-recess
etch monitoring structure on one wafer. Using the probing station, we deter-
mined the non-linear I-V characteristic before the Strip Annealing process.
This is provided in Fig. 3.2.
3.2.5 Annealing of Ohmic Contacts
The metallic source and drain contacts resulting from the previous procedure
were annealed in a 5% hydrogen, 95% nitrogen environment at 390 °C for
10 seconds. This allowed for the germanium atoms in the alloy to diffuse
into the bulk semiconductor and form ohmic contacts.
CHAPTER 3. MESFET FABRICATION 14
Figure 3.2: Source-Drain I-V Characteristic of gate recess etch monitoring
structure before annealing. Note the non-ohmic contact characteristic.
3.2.6 I-V Characteristics After Annealing
The new and linear I-V characteristics, shown in Fig. 3.3, were then mea-
sured on the same gate-recess etch monitoring structure.
3.2. 7 Wet Etching of Mesas
Photo-resist (81813) was spun on at 5000 rpm for 30 seconds, resulting
in a 1.2 J.Lm layer of photoresist on each wafer. They were then exposed
to a mask for 20 seconds . The wafers were developed for 45 seconds in
MF319, cleaned in de-ionized water, and dried. Then they were exposed to
ionized oxygen in the PlasmaPrep 300 (described earlier) for approximately
60 seconds. Following this procedure, each wafer was etched in a bath of
1:2:40 H
3
P0
4
: H
2
0
2
: H
2
0 for 2 minutes. Each wafer was bathed in
acetone for 10 to 20 seconds to remove any remaining photoresist.
3.2.8 Talystep Profiling
Each wafer's surface profile was measured using a Talystep. The height of
the mesas were found to be near 100 J.Lm, as anticipated. One chip was used
to test the etching procedure, but was found to be 80 J.Lm, which indicated
that the etching procedure had been prolonged. The chips were then visually
CHAPTER 3. MESFET FABRICATION 15
1. 00
0 . 80
0 . 60
(} . 4 (}
I
.
0
0 . 20
......
u
0 . 00
...
-0 20
- 0.40
- 0 . 60
-0. 80
-=r-·-
---=
==
- ;;;
--
     

llill

-
i-
-- .
-· -
·-- ··-
'
Ill
I
• t ==
I
_j_ . l


=--iliiiii - --- --
t--
• --=
·-·-·-+-=
---e--·
-;;;;;;;;;;
t-=
- 1 .uo
-1.00 -0. 80 -0. 60 -0. 20 0 . 00 0 . 20 0 .40 0 . 60 O.BO 1. 00
Vds
Figure 3.3: Source- Drain I-V Characteristic of gate recess etch monitoring
structure after annealing. Note ohmic contact characteristic due to diffu-
sion of germanium from alloy contact into bulk semiconductor. During the
annealing procedure, gallium preferentially diffuses out of the GaAs melt
and the semiconductor side of the interface reconfigures as a highly n-doped
semiconductor by the gallium-germanium substitution.
CHAPTER 3. MESFET FABRICATION
Go/d-Gennanium-Nickel
(AuGeNi)
Gold (Au)
Meta/Gate
(Schottky
Contact)
Ohmic
Drain
Contact
(Au)
16
Figure 3.4: Geometry of final MESFET device. Gate widths consisted of
three varieties: 1 J.Lm, 2 J.Lm, and 3 J.Lm. Source to drain width was 10 J.Lm.
inspected, and then exposed to ionized oxygen in the PlasmaPrep 300 for 5
minutes at 400 Watts ( 5 Watts reflected).
3.2.9 Electron Beam Lithography
The wafers were coated with a layer of PMMA at 5000 rpm for 30 seconds,
and baked for approximately 50 minutes. An Electron Beam (0.4 nA) was
then used to etch the gate contact patterns. The beam width was tuned
to 200-250 nm (beam diameter was about 220 nm), and the dose was 400
J.LC/cm
2
• The write time was about 6 minutes per wafer.
3.2.10 Gate Metallization
The wafers were again loaded into the Thermal Vapor Deposition chamber,
whereupon they were coated with 35 nm of titanium (Ti) and 150 nm of
gold (Au), respectively. The Ti/ Au was then lifted-off using acetone, and
the wafers were dried with nitrogen.
3.2.11 Conclusion of MESFET Fabrication
The final geometry of the GaAs MESFET devices described in the fabrica-
tion procedures above is shown in Fig. 3.4. The devices were then ready for
testing and characterization, as described in the following chapter.
3.3 Improvements in Fabrication Processes
Because device characteristic degradation was encountered within a week of
device fabrication, the following precautions would be advised in any future
fabrication procedures:
CHAPTER 3. MESFET FABRICATION 17
• Use of platinum between the titanium and gold layers of the gate met-
allization process. This would prevent the migration of gold atoms
through the titanium layer and depositing within the bulk semicon-
ductor. This process is well worth the effort and would only require
for an extra step in the Thermal Vapor Deposition procedure.
The following recommendations are of a general nature.
• Use of electron beam lithography for all gate and contact formation
steps. This would allow for better control of physical parameters for
electrical and mathematical characterization of devices.
• Alignment of each quadrant of wafer in the electron beam lithography
procedure. This would create better gate alignment with respect to
rest of device and would result in higher device yield.
• Fabrication of additional wafers for testing.
Chapter 4
Experimental Characteristics
of MESFET Devices
4.1 Introduction
Herein we describe the experimental characteristics of the MESFET devices.
4.2 Device Testing and Characterization
The devices were tested on a probing station which allowed for electrical
contacts to be made with the gate, source, and drain contacts. The electrical
set-up is illustrated in Fig. 4.1.
4.2.1 Transconductance
The saturation condition implies that
id = g'mv
9
= 9m(v
9
- idRs),
where id is the drain current and 9m is the transconductance. This may be
rewritten as
· 9m
Zd = 1 + 9mRs Vg '
which is equivalent to the reduced transconductance
1 9m
g =
m 1 + 9mRs
Thus, in order to increase the effective transconductance it is necessary
to reduce the source-gate resistance, i. e., the source-gate spacing should
be reduced as much as possible. Another, yet heuristic, argument is as
follows: the bulging of the depletion layer is biased t oward the drain contact,
therefore it may act ually be beneficial for device performance to extend the
gate-drain separation, thereby creating cut-off, or saturation, at a higher
voltage.
18
CHAPTER 4. EXPERIMENTAL CHARACTERISTICS
Ohmic
Source
Contact
+
Metal Gate
(Schottky
Contact)
19
Figure 4.1: Experimental set-up for testing of I-V characteristics of MES-
FET device. The gate and drain contacts were held at a positive voltage
(2: 0) relative to the source contact .
Figure 4.2: Current-Voltage characteristics of MESFET device giving the
typical Shockley curve for zero gate voltage. Device saturation occurs at
approximately 4 Volts.
CHAPTER 4. EXPERIMENTAL CHARACTERISTICS 20
Figure 4.3: Current-Voltage characteristics of MESFET device for reverse
bias test.
Figure 4.4: Current-Voltage characteristics of MESFET device with micro-
scope light on/off. This shows the effect of light on device characteristics.
Note a shifting of approximately 0.5 mAin device performance. It may also
account for a slight bias in the saturation voltage.
CHAPTER 4. EXPERIMENTAL CHARACTERISTICS 21
Figure 4.5: Current-Voltage characteristics of MESFET device for differing
gate voltages resulting in a series of typical Shockley curves.
4.2.2 Transmission Line Method
The transmission line method was used to measure the sheet resistance of
the bulk semiconductor. The circuit set-up is illustrated in Fig. 4.6. This
allowed for the determination of the sheet resistance of the bulk semicon-
ductor without the necessity to subtract resistances due to the probing tips
and connecting circuitry.
4.2.3 C-V Characteristics
Unfortunately, C- V characteristics were not obtained due to device degrada-
tion during the trial period. Measurement of the C-V characteristics would
have given the doping-profile of the modulation-doped semiconducting lay-
ers.
4.3 Performance Limits
Device breakdown was not achieved as the device characteristics were de-
stroyed before this test could be performed.
CHAPTER 4. EXPERIMENTAL CHARACTERISTICS 22
Figure 4.6: Circuit diagram for Transmission Line Test. Measurement of
the current allowed measurement of Ttotal = 2Rcontact + Rsheet.
Contact Spacing vs. Semiconductor Sheet Resistance
30.00
25.00
~
.;:!.
  ~
20.00
u
~
...
u
s
c:
15.00
8
10.00
BOO 1000 1200 1400 1600 1800
Sheet Resistance {!2)
Figure 4. 7: Graph of Contact Spacing ( s) vs. Semiconductor Sheet Resis-
tance (r). The straight line is given by r = .0193s- 9.11, with R
2
= .999.
There were only four data points obtained from this experiment since the 5
J..Lm spacing was shorted. It is conceivable to get many more data points by
measuring sheet resistances across the contacts as well. The sheet resistance
varied between 1.41 fl/(J..Lm)
2
and 1.99 fl/(J..Lm)
2
.
Chapter 5
Summary
A number of MESFET devices were fabricated; some devices were created
as bona fide transistor devices, while others were fabricated to allow for the
testing and characterization of those MESFET devices. Although the device
yield was low, in my case (1 device) , owing to the temperamental nature
of the electron beam process, the device operated as expected; however,
device performance could only be obtained for a short time (less than 1
week). This is thought to be a result of migration of gold atoms through
the underlying titanium layer into the bulk semiconductor. It is conjectured
that a platinum layer sandwiched between the Au/Ti interface would have
mitigated this problem.
23
Chapter 6
Conclusion
The MESFET devices described herein met the expected characteristics of
similar devices. Although improvements can be made in any system, the pro-
cedures presented already represent a condensation of the usual processes
ubiquitous in the semiconductor industry.
This practical was especially helpful to those who have limited knowledge
of semiconductor technology and fabrication of semiconductor devices. It
allowed one to hang certain concepts and ideas on the words so often cited
in the current literature.
24
Chapter 7
References
[1] Beeforth, T. H. and H. J . Goldsmid. Physics of Solid State Devices. Pion
Limited, London, 1970.
[2] R. A. Dunlap, Experimental Physics. Oxford University Press, New York,
1988.
[3] J. B. Gunn, Solid State Communications 1, 88 (1963).
[4] Madelung, 0. and M. Schulz, Eds. Numerical Data and Functional Rela-
tionships in Science and Technology/Landolt-Bornstein, Vol. 22. Springer-
Verlag, Berlin, 1987.
[5] C. A. Mead. Schottky Barrier Gate Field-Effect Transistor. Proc. IEEE,
54, 307 (1966).
[6] Morgan, D. V. and K. Board. An Introduction to Semiconductor Mi-
crotechnology, Second Edition. John Wiley & Sons Ltd. , Chichester , 1990.
[7] Myers, H. P. Introductory Solid State Physics. Taylor & Francis, London,
1994.
[8] Parker, Greg. Introductory Semiconductor Device Physics. Prentice Hall
International (UK) Limited, Hertfordshire, 1994.
[9] Pierret , Robert F. Semiconductor Device Fundamentals. Addison- Wesley
Publishing Company, Reading, Massachusetts, 1996.
[10] J. G. Ruch. Electron Dynamics in Short Channel Field Effect Transis-
tors. IEEE Transactions, Electron Devices ED-19B, 652 (1972).
25
CHAPTER 7. REFERENCES 26
[11] Sze, S. M. Physics of Semiconductor Devices, 2nd Edition. John Wiley
& Sons Ltd., New York, 1981.
[12] Wang, Cheng T., Ed. Introduction to Semiconductor Technology: GaAs
and Related Compounds. John Wiley & Sons, Inc., New York, 1990.
[13] Wood, David. Optoelectronic Semiconductor Devices. Prentice Hall In-
ternational (UK) Limited, Hertfordshire, 1994.
Chapter 8
Appendix
8.1 Scanning Electron Microscopy ofMESFET De-
.
VICeS
8.2 Scanning Electron Microscopy of Test Struc-
tures
8.3 Lithographic Layout Files
27
CHAPTER 8. APPENDIX 28
Figure 8.1: Scanning Electron Micrograph of MESFET device. Ideally, the
lower contact should be the source, in order to increase the transconduc-
tance, as the gate contact is well positioned away from the drain contact.
Note the periphery of the gate contact, produced by Electron Beam Lithog-
raphy, as compared to the source and drain contacts, produced by Pho-
tolithography. Symmetry of etching around perimeter of source and drain
contacts, indicate that the problem lies in the etching rates (longer etch-
ing rates may cause non-uniform etching to occur) and/or the particular
lithographic method (photolithography vs. electron beam lithography and
chemistry of resists).
CHAPTER 8. APPENDIX 29
Figure 8.2: Scanning Electron Micrograph of MESFET device. Note that
gate width (3 J.Lm) is larger than that of Fig. 8.1.
CHAPTER 8. APPENDIX
30
Figure 8.3: Oblique view of MESFET device. Note surface uniformity of
gate contact in contrast to pitting and other malignancies on source and
drain contacts. The non-uniformity of gate contact occurs in region where
contact folds over the GaAs mesa-etched structure.
CHAPTER 8. APPENDIX 31
Figure 8.4: Scanning Electron Micrograph of drain-gate-source region of
MESFET. Ideally, the gate contact is closer to the source contact. Note
the quality of the gate contact as compared to the alloyed source and drain
contacts.
CHAPTER 8. APPENDIX 32
Figure 8.5: Scanning Electron Micrograph of MESFET. Visible are the gate,
source, and drain contacts situated on the mesa-etched GaAs. By visual in-
spection of the morphology, it is clearly seen that the gate contact, created
by Electron Beam Lithography, is superior in quality to that of the pho-
tolithographically created source and drain contacts.
CHAPTER 8. APPENDIX 33
Figure 8.6: Scanning Electron Micrograph of ohmic contact sub-field, or
"spider" test structure. The 6 contact pads are spaced at 5 J.Lm, 10 J.Lm,
15 J.Lm, 20 J.Lm, and 25 J.Lm. This device was used in the Transmission Line
Method (TLM) to measure sheet resistance of underlying mesa-etched GaAs.
CHAPTER 8. APPENDIX 34
Figure 8.7: Scanning Electron Micrograph of test structure.
CHAPTER 8. APPENDIX 35
Figure 8.8: Layout for mesa and ohmic contact structures of the mask. The
pattern was approximately 4 mm by 4 mm and was designed to fit on 5 mm
by 5 mm GaAs wafers.
CHAPTER 8. APPENDIX 36
Figure 8.9: Detail of various test structures not shown in Fig. 8.8.
CHAPTER 8. APPENDIX 37
Figure 8.10: Layout of ohmic contact sub-field, affectionately known as a
"spider". Probing of the contact pads enables determination of the sheet
resistance of underlying conducting layer of GaAs and resistance of the con-
tact pads. The 6 contact pads are spaced at 5 J.Lm, 10 J.Lm, 15 J.Lm, 20 J.Lm,
and 25 J.Lm.
Figure 8.11: Layout for FATFET C-V test structure. This device would
have ideally been used to measure C-V characteristics of the gate metal-
semiconductor junction and measure the doping profile of the semiconductor.
CHAPTER 8. APPENDIX
38
Figure 8.12: Layout of the gate-recess etch monitoring structure. The over-
sized pads allowed for repeated testing of device before and after strip an-
nealing.
Figure 8.13: Layout of MESFET device. The gate is ideally positioned
closer to the source, rather than positioned centrally.