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EXPERIMENT NO.

1
AIM:Design all gates using VHDL.

a. AND GATE
VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity and_gate is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC); end and_gate; architecture Behavioral of and_gate is begin Y<=A AND B; end Behavioral;

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b. OR GATE
VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity and_gate is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC); end and_gate; architecture Behavioral of and_gate is begin Y<=A AND B; end Behavioral;

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c. NOT GATE
VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity not_gate is Port ( A : in STD_LOGIC; Y : out STD_LOGIC); end not_gate; architecture Behavioral of not_gate is begin Y<=NOT A; end Behavioral;

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d. NAND GATE
VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity nand_gate is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC); end nand_gate; architecture Behavioral of nand_gate is begin Y<=A NAND B; end Behavioral; RTL View

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e. NOR GATE
VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity nor_gate is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC); end nor_gate; architecture Behavioral of nor_gate is begin Y<=A NOR B; end Behavioral;

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f. XOR GATE
VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity nor_gate is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC); end nor_gate; architecture Behavioral of nor_gate is begin Y<=A NOR B; end Behavioral;

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g. XNOR GATE
VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity xnor_gate is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC); end xnor_gate; architecture Behavioral of xnor_gate is begin Y<=A XNOR B; end Behavioral;

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EXPERIMENT NO.2
AIM:Write VHDL programs for the following circuits, check the wave forms and the hardware generated a. Half Adder b. Full Adder

a. HALF ADDER
VHDL Code using Data Flow Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity halfdder_1 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC; S : out STD_LOGIC); end halfdder_1; architecture Behavioral of halfdder_1 is begin C<=A AND B; S<=A XOR B; end Behavioral;

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VHDL Code using Behavioural Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity halfadder_2 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC; S : out STD_LOGIC); end halfadder_2; architecture Behavioral of halfadder_2 is begin process(A,B) begin if(A='0' and B='0')then C<='0'; S<='0'; elsif(A='0' and B='1')then C<='0'; S<='1'; elsif(A='1' and B='0')then C<='0'; S<='1'; else C<='1'; S<='0'; end if; end process; end Behavioral;

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VHDL Code using Structural Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity halfadder_3 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC; S : out STD_LOGIC); end halfadder_3; architecture Behavioral of halfadder_3 is component xor1 Port(IN1,IN2:in STD_LOGIC;OUT1:out STD_LOGIC); end component; component and1 Port(IN3,IN4:in STD_LOGIC;OUT2:out STD_LOGIC); end component; begin a0:and1 port map(A,B,C); a1:xor1 port map(A,B,S); end Behavioral;

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b. FULL ADDER
VHDL Code using Data Flow Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fulladder_1 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; CIN : in STD_LOGIC; COUT : out STD_LOGIC; S : out STD_LOGIC); end fulladder_1; architecture Behavioral of fulladder_1 is begin COUT<=(A AND B)OR(B AND CIN)OR(A AND CIN); S<=(A XOR B XOR CIN);

end Behavioral;

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VHDL Code using Behavioural Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fulladder_2 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; CIN : in STD_LOGIC; COUT : out STD_LOGIC; S : out STD_LOGIC); end fulladder_2; architecture Behavioral of fulladder_2 is begin process(A,B,CIN) begin if(A='0' and B='0' and CIN='0')then COUT<='0'; S<='0'; elsif(A='0' and B='0' and CIN='1')then COUT<='0'; S<='1'; elsif(A='0' and B='1' and CIN='0')then COUT<='0'; S<='1'; elsif(A='0' and B='1' and CIN='1')then COUT<='1'; S<='0'; elsif(A='1' and B='0' and CIN='0')then COUT<='0'; S<='1'; elsif(A='1' and B='0' and CIN='1')then COUT<='1'; S<='0'; elsif(A='1' and B='1' and CIN='0')then COUT<='1'; S<='0'; else
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COUT<='1'; S<='1'; end if; end process;

end Behavioral;

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VHDL Code using Structural Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fulladder_3 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; CIN : in STD_LOGIC; COUT : out STD_LOGIC; S : out STD_LOGIC); end fulladder_3; architecture Behavioral of fulladder_3 is signal l,m,n:STD_LOGIC; component and1 Port(IN1,IN2:in STD_LOGIC;OUT1:out STD_LOGIC); end component; component or1 Port(IN3,IN4,IN5:in STD_LOGIC;OUT2:out STD_LOGIC); end component; component xor1 Port(IN6,IN7,IN8:in STD_LOGIC;OUT3:out STD_LOGIC); end component; begin a0:and1 port map(A,B,l); a1:and1 port map(B,CIN,m); a2:and1 port map(A,CIN,n); a3:or1 port map(l,m,n,COUT); a4:xor1 port map(A,B,CIN,S); end Behavioral;

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EXPERIMENT NO.3
AIM:Write VHDL programs for the following circuits, check the wave forms and the hardware generated a. Half Subtractor b. Full Subtractor

a. HALF SUBTRACTOR
VHDL Code using Data Flow Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity halfsub_1 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; BOUT : out STD_LOGIC; D : out STD_LOGIC); end halfsub_1; architecture Behavioral of halfsub_1 is begin BOUT<=(NOT A) AND B; D<=A XOR B; end Behavioral;

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VHDL Code using Behavioural Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity halfsub_2 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; BOUT : out STD_LOGIC; D : out STD_LOGIC); end halfsub_2; architecture Behavioral of halfsub_2 is begin process(A,B) begin if(A='0' AND B='0')then BOUT<='0'; D<='0'; elsif(A='0' AND B='1')then BOUT<='1'; D<='1'; elsif(A='1' AND B='0')then BOUT<='0'; D<='1'; else BOUT<='0'; D<='0'; end if; end process; end Behavioral;

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VHDL Code using Structural Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity halfsub_3 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; BOUT : out STD_LOGIC; D : out STD_LOGIC); end halfsub_3; architecture Behavioral of halfsub_3 is signal Abar:STD_LOGIC; component not1 Port(IN1:in STD_LOGIC;OUT1:out STD_LOGIC); end component; component and1 Port(IN2,IN3:in STD_LOGIC;OUT2:out STD_LOGIC); end component; component xor1 Port(IN4,IN5:in STD_LOGIC;OUT3:out STD_LOGIC); end component; begin a0:not1 port map(A,Abar); a1:and1 port map(Abar,B,BOUT); a2:xor1 port map(A,B,D); end Behavioral;

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b. FULL SUBTRACTOR
VHDL Code using Data Flow Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fullsub_1 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; BIN : in STD_LOGIC; BOUT : out STD_LOGIC; D : out STD_LOGIC); end fullsub_1; architecture Behavioral of fullsub_1 is begin BOUT<=((NOT A) AND B)OR(B AND BIN)OR((NOT A) AND BIN); D<=A XOR B XOR BIN; end Behavioral;

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VHDL Code using Behavioural Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fullsub_2 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; BIN : in STD_LOGIC; BOUT : out STD_LOGIC; D : out STD_LOGIC); end fullsub_2; architecture Behavioral of fullsub_2 is begin process(A,B,BIN) begin if(A='0' and B='0' and BIN='0')then BOUT<='0'; D<='0'; elsif(A='0' and B='0' and BIN='1')then BOUT<='1'; D<='1'; elsif(A='0' and B='1' and BIN='0')then BOUT<='1'; D<='1'; elsif(A='0' and B='1' and BIN='1')then BOUT<='1'; D<='0'; elsif(A='1' and B='0' and BIN='0')then BOUT<='0'; D<='1'; elsif(A='1' and B='0' and BIN='1')then BOUT<='0'; D<='0'; elsif(A='1' and B='1' and BIN='0')then BOUT<='0'; D<='0'; else
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BOUT<='1'; D<='1'; end if; end process;

end Behavioral;

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VHDL Code using Structural Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fullsub_3 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; BIN : in STD_LOGIC; BOUT : out STD_LOGIC; D : out STD_LOGIC); end fullsub_3; architecture Behavioral of fullsub_3 is signal Abar,l,m,n:STD_LOGIC; component not1 Port(IN1:in STD_LOGIC;OUT1:out STD_LOGIC); end component; component and1 Port(IN2,IN3:in STD_LOGIC;OUT2:out STD_LOGIC); end component; component or1 Port(IN4,IN5,IN6:in STD_LOGIC;OUT3:out STD_LOGIC); end component; component xor12 Port(IN7,IN8,IN9:in STD_LOGIC;OUT4:out STD_LOGIC); end component; begin a0:not1 port map(A,Abar); a1:and1 port map(Abar,B,l); a2:and1 port map(B,BIN,m); a3:and1 port map(Abar,BIN,n); a4:or1 port map(l,m,n,BOUT); a5:xor12 port map(A,B,BIN,D); end Behavioral;
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EXPERIMENT NO.4
AIM:Write VHDL programs for the following circuits, check the wave forms and the hardware generated a. 4:1 Multiplexer b. 1:4 Demultiplexer

a. 1:4 MULTIPLEXER
VHDL Code using Data Flow Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mux_1 is Port ( S : in STD_LOGIC_VECTOR (1 downto 0); I : in STD_LOGIC_VECTOR (3 downto 0); Y : out STD_LOGIC); end mux_1; architecture Behavioral of mux_1 is begin Y<=I(0) when S="00" else I(1) when S="01" else I(2) when S="10" else I(3); end Behavioral;

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VHDL Code using Behavioural Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mux_2 is Port ( S : in STD_LOGIC_VECTOR (1 downto 0); I : in STD_LOGIC_VECTOR (3 downto 0); Y : out STD_LOGIC); end mux_2; architecture Behavioral of mux_2 is begin process(S,I) begin case S is when "00"=> Y<=I(0); when "01"=> Y<=I(1); when "10"=> Y<=I(2); when others=> Y<=I(3); end case; end process; end Behavioral;

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VHDL Code using Structural Style of Modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mux_3 is Port ( S : in STD_LOGIC_VECTOR (1 downto 0); I : in STD_LOGIC_VECTOR (3 downto 0); Y : out STD_LOGIC); end mux_3; architecture Behavioral of mux_3 is signal a,b,l,m,n,o:STD_LOGIC; component not1 Port(IN1:in STD_LOGIC;OUT1:out STD_LOGIC); end component; component and1 Port(IN2,IN3,IN4:in STD_LOGIC;OUT2:out STD_LOGIC); end component; component or1 Port(IN5,IN6,IN7,IN8:in STD_LOGIC;OUT3:out STD_LOGIC); end component; begin a0:not1 port map(S(1),a); a1:not1 port map(S(0),b); a2:and1 port map(a,b,I(0),l); a3:and1 port map(a,S(0),I(1),m); a4:and1 port map(S(1),b,I(2),n); a5:and1 port map(S(1),S(0),I(3),o); a6:or1 port map(l,m,n,o,Y); end Behavioral;

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b. 4:1 DEMULTIPLEXER

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