R-2R Binary Ladder DAC

R= 10k 2R = 20k

Req3

Req2

Req1

Vref = 10 Vdc Circuit analysis

et438b-3.ppt

1

R-2R ladder analysis (cont.)
V=10 Vdc V1 I1 I 20k I2 10k V2 I’ 20k I3 20k 20k 10k V3

Voltages and currents

I4

R-2R network produces binary weighted currents from 2 values of resistance
et438b-3.ppt 2

ITRf et438b-3. I2 and use formula V0 = .Example: Find the output voltage for the R-2R DAC shown below. R= 15k 2R = 30k Rf = 15k I2 I1 I0 Req IT Vref = 5 Vdc Find currents I0.ppt 3 . I1. The digital input is 1102.

ppt . 1 bit change produces change of 1/256 in I0 Equations: D = decimal equivalent of binary input Iref = Vref Rref 4  D  I0 = Iref    256  Ifs = Vref  255    Rref  256  Full scale output et438b-3. Iref 14 4 2 8-bit binary code converted to 256 levels of I0 Full scale value set by reference current. TTL compatiable.Commerical DACs DAC0800 Family Devices used in practical designs use intergrated R-2R networks and transistor switching.

5kΩ a.) Digital input 000011012 b.ppt 5 . The reference voltage is +10 Vdc and the Reference resistance is 5kΩ. The value of Rf = 2.) Digital input 100011012 et438b-3.IC DAC Example: Use OP AMP to convert current to voltage.

ppt 6 .) input 100011012 et438b-3.IC DAC example (cont.

Analog-to-digital Conversion Convert continuous signals to digital values Requires 3 steps 1.) Convert analog value to digital value et438b-3.ppt 7 .) Sample analog signal (Nyquist rate) Need a minimum of 2 x max frequency of interest Higher sample rates.) Hold analog sample value while conversion in progress 3. easier to reconstruct signal 2.

Types of Analog-to-Digital Converters Integrating • High accuracy • Low speed • low cost Not used in data acquisition systems Tracking (Counter) • High speed in tracking mode • Slow conversion time (some sub-types) • susceptible to noise Successive Approximation • conversion time independent of value “Flash” Parallel Multicomparator type of conversion • Highest speed • HIgh cost et438b-3.ppt 8 .

) AND gate passes clock signal when pt.) Counter incremented by signal B 4. Not shown.Counter Analog-to-Digital (A/D) Converters When V+ = VV V+ + VClock V Digital output A B AND C O U N T E R D A C 1.) DAC output increases as counter output increases et438b-3. Requires a sample and hold circuit.ppt 9 .) Input a constant value. 2. A logic high 3.

Counter-type A/D converter input V+ + VClock V A B AND C O U N T E R D A C 5.ppt 10 .) Counter stops when DAC V exceeds input V input V input DAC output time Conversion time depends on the input level Tracking A/D converters us up/down counters to minimize conversion times et438b-3.

else bit = 1 (VDAC < Vin) 4. Test input.ppt 11 . Set MSB to 1 2. where n = the number of bits in digital signal et438b-3. Move to next bit and repeat steps 1 . Vin.Successive Approximation A/D Converters Counter A/D converters conversion time proportional to the input level Improve conversion speed using a binary search technique.3 The input is converted to digital value in n steps. If VDAC > Vin. reset bit to 0. against DAC output. Procedure 1. VDAC 3.

ppt 12 .Successive-Approximation A/D Converters et438b-3.

Use the successive approximation algorithm given previously to determine the binary value.77 MHz et438b-3.Example: an 8-bit successive approximation ADC is presented with a analog value that has a value of 143. Assuming that each test takes a single clock cycle.ppt 13 . determine the maximum conversion time for the ADC if it is clocked at 4.

Example continued et438b-3.ppt 14 .

conversion from binary to decimal n = 1x27+1x26+0x25+0x24+0x23+1x22+1x21+0x20 n = 1x128+1x64+1x4+1x2 = 198 198 decimal equivalent of binary number et438b-3. 1 and 0’s bits groups of bits 8-bits = byte 16-bits = 2 bytes = 1 word All collections of bits are power of 2 Addressing bits in a byte 7 1 6 1 5 0 4 0 3 0 2 1 1 1 0 0 Address location Bit Weighted number system .Digital Input/Output Signals (Digital I/O) Boolean logic level 1 = logic high 0 = logic low Boolean levels form basis of numbering system and computer structure.ppt 15 .

7 mA Logic 1 Threshold voltage V>= 2.4 Vdc Switch source of current +5 Switch sink of current Load Load et438b-3. Makes chips from same family compatible with each other Transistor-Transistor Logic (TTL) Nominal 5 Vdc logic high and 0 Vdc logic low Practical TTL output port characteristics Source current 200 µA Sink current 1.Digital Hardware Standards Specifies voltage levels of logic high and logic low current output and input levels.ppt 16 .

ppt 17 .Simple TTL gate Sink and Source Vcc = + 5 Vdc IL RL Rb Vin Vo IL flows to ground when Vin = logic 1 Vin = 5 V for Logic high and 0 V for logic low Switch model of gate Vcc = + 5 Vdc IL Load RL Vo Vin Load will draw current went Vin = 5 Vdc switch (Transistor) must sink load current ILL When Vin = 5 Vdc Vo = 0 V When Vin = 0 Vdc Vo = 5 V Logic Inverter input output 1 0 0 1 et438b-3.

current sourcing Vcc = + 5 Vdc IL Load Vo Vin ILL When Vin is logic 1 load is de-activated (switch closed) When Vin is logic 0 load draws current from source With Transistors current sourcing Load ILL Vin sourcing current TTL Inverter symbol Load ILL et438b-3.ppt 18 .Switch model of gate .

TTL Sinking LEDs Output byte port feeding loads from inverters (buffering) Resistor used to limit current through gate When input is logic 1 (+5 Vdc) output is logic 0 (ground) Limits of TTL buffers .1.use discrete transistor or relay (electromechanical or solid state) et438b-3.7 mA For high current output .ppt 19 .

ppt 20 .Solid State Relay Ac supplies only Optically coupled device +5 Vdc AC AC Ground Typical Application +5 Vdc Motor Load 1/4 HP 120 Vac M 120 V Grd Output bit low motor is on Output bit high motor is off Must remember output logic level to get desired action in device Output Bit et438b-3.

ppt 21 .Electromechanical Relays + 12 Vdc Typical diode voltage spike protector Relay coil dc resistance load to transistor To output bit Resistor sized to allow TTL level to turn on relay To high power load AC or DC NPN transistor Relay interface using TTL gate (open collector) Lower current handling ability + 12 Vdc Typical Current limited by the TTL chip To high power loads AC or DC To output bit LS7406 chip et438b-3.

ppt 22 .Digital Input Interface Limit current and change voltage levels Using mechanical switches + 5 Vdc Input port constructed of TTL chips 2.2 k To data acquisition board Resistor sized to limit current to value below port sinking limit Mechanical switch + 5 Vdc Digital interface for a byte of inputs. All resistors sized to limit sink current Switches can be either momentary contact or toggle et438b-3.

LED energized LED and Optical transistor integrated on same chip energizing LED causes optical transistor to conduct Transistor off .Digital Interface Non-TTL Levels +24 Vdc + 5 Vdc 2.ppt 23 .inverter input +5 Vdc output 0 V Transistor on .LED de-energized Switch open .inverter input 0 Vdc output 5 V et438b-3.2k Typical 2.2k Typical To TTL input R TTL inverter gate (7404 or 7414) Optocoupler Switch closed .

+24 Vdc + 5 Vdc 2.2k R = 100 2.2k To TTL input Logic open switch = 0 = 0 V close switch = 1 = 5 V et438b-3.ppt 24 .Example: determine the logic levels and currents in the digital interface circuit shown below Assume that the optocoupler diode has an on-state voltage drop of 1.4 V.4 V and the optical transistor has a on-state drop of 0.

ppt 25 .Example (cont.) et438b-3.

Relay Interface Example Ic +24Vdc Relay Coil model Size Rb such that Q1 will activate with a TTL input 10 mH Transistor Parameters 500 Ω Vs + Rb + Vbe 2N3904 Vce Q1 hfe = 200 (nominal) Vce(sat) = 0.2 V Vbe(sat) = 0.ppt 26 .8 V Ib Assume transistor is in saturation and compute value of Ic et438b-3.

et438b-3. If also clamps the induced voltage to the forward drop of the diode.Relay Interface Example (cont.) Freewheeling diode +24Vdc 10 mH D1 500 Ω Vs Rb 2N3904 Q1 Relay Coil model Diode D1 provides a path for the current induced when the transistor is switched off.ppt 27 .

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