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COURSE STRUCTURE FOR M.E. (E & TC) (VLSI & Embedded Systems) (w. e. f. June - 2013)
SEMESTER II CODE SUBJECT TEACHING SCHEME Lect./ Pr EXAMINATION SCHEME Paper In Semester Assessment 504207 504208 504209 504210 504211 504212 Analog CMOS Design System on Chip Embedded Signal Processors Elective II Lab Practice II Seminar I Total 4 4 4 5 4 4 25 50 50 50 50 200 End Semester Assessment 50 50 50 50 200 50 50 100 50 50 100 100 100 100 100 100 100 600 4 4 4 5 4 4 25 TW Oral/ Presentation Total CREDITS
Allen and D. Weak inversion. Current and voltage references. 2. Opamp. Hurst. low noise opamp. P. Razavi. Module IV Low Noise Amplifier Low Noise Amplifier (LNA) design. Analysis and Design of Analog Integrated Circuits. noise and power trade off. Gray. micro power opamp. Holberg. Advanced trends in Radio Frequency (RF) chip design. Output amplifier. R. B. Thomas Lee. H. Analog to Digital Converters. (Low Price Edition) 23 . high speed opamp.Wiley. “The Design of CMOS Radio – Frequency Integrated Circuits”. S. The CMOS Inverter as an Amplifier. P. Design of mixer. cascode and differential amplifiers. Fourth Edition. Current mirrors. band gap reference.504207 Teaching Scheme: Lectures 4 Hrs/ Week Analog CMOS Design Examination scheme: Theory : 50 Marks (In Semester) 50 Marks (End Semester) Credits : 4 Module I Current sources and References MOSFET as switch. Tuned amplifiers. Module II CMOS Opamp Inverters. McGraw-Hill 3. Lewis and R. MOS Small-signal Models. Bandwidth estimation open and short circuit techniques. P. switched capacitors. Meyer. Zeros as bandwidth enhancers. E. Second Edition. 2001. Cambridge. diode and active resistor. Short channel regime. CMOS Analog Circuit Design. Second edition. Design of Analog CMOS Integrated Circuits. optimizations. J. Common Source Amplifier. Module III Low and High Bandwidth Design Digital to Analog Converters. Current sinks and sources. References 1. Oxford University Press 4.
the existence of cross talk in each case. The student will show the skills of designing CMOS analog circuits. Suggest and design suitable technique to enhance the bandwidth. To design cascode current mirror for output current of 100 µA. 5. prepare layout and simulate CMOS differential amplifier for CMRR of 40 dB. bandwidth of 100 MHz. Course Outcomes: 1. 24 . Prepare layout and simulate. Verify the cross talk and its mitigation through simulation. The student will demonstrate the ability for using backend tools in analog IC technology. To design. Simulate each added technique step by step. To design. Comment on ICMR. and source impedance of 50 Ω. The student will understand the fundamentals of CMOS Technology in Analog Domain. Comment on output resistance. Explore in detail. Prepare layout of the final schematic and simulate. 2. prepare layout and simulate multistage CMOS RF amplifier in 90 nm technology for voltage gain of 60 dB.Analog CMOS Design Laboratory Assignments/Experiments: 1. 3. What are the mitigation techniques? Prepare case study for one of them. 2. 4. List the sources of cross talk. 3. To design CMOS RF amplifier for voltage gain of 60 dB. Comment on the improvement resulted each time.
the need for concurrent models. design principles . Springer 25 . timing parameters for digital logic. synchronization schemes. cycle based bit parallel hardware. sequential arcs. handling Micro-program interrupt and pipelining . verification. FSMD data-path . Programmer’s model . implication on synthesis and on backend. causes and factors affecting power. Schaumont. processors. language mapping for FSMD. soc memory system design. testing and physical design. hardware model . clock domain crossing . System on Chip. Module IV Research topics in SOC design: A SOC controller for digital still camera. software and hardware implementation of data flow. data and control design. Designing Complex Systems on-Chip”. data-path. Sapan Garg . “Principles of VLSI RTL Design A Practical Guide”. Youn-Long Steve Lin. control flow modelling and the limitations of data flow models. Sanjay Churiwala. Springer 3. concept. multimedia IP development image and video CODECS. memory mapped Interfaces . analysis of control flow and data flow. “Essential Issues in SOC Design. switching activity. References 1. Importance of low power. SOC prototyping. embedded software. timing analysis. coprocessor control shell design. analyzing synchronous data flow graphs. SOC modelling. Micro-programmed machine implementation . General purpose embedded cores . “A Practical Introduction to Hardware/Software Co design”. coprocessor interfaces. Springer 2. preventing data loss through FIFO. and energy management techniques for SOC design. factors affecting delay and slew. Finite State Machine with data-path. portable multimedia system. simulation and RTL synthesis. hardware/software interfaces . data flow modelling and implementation.bus synchronization . encoding . program organization. Module III RTL intent : Simulation race. simulation limitation.504208 Teaching Scheme: Lectures 4 Hrs/ Week System on Chip Examination scheme: Theory : 50 Marks (In Semester) 50 Marks (End Semester) Credits : 4 Module I Basic Concepts: The nature of hardware and software. The RISC pipeline. simulation-synthesis mismatch. analyzing the quality of compiled code. Micro-programmed : control. Patrick R. Module II Micro-programmed Architectures : limitations of FSM .
Why gated clock is not preferred in digital design? Write Verilog code to implement CMOS layout which will generate glitch also design a RTL by Write VHDL will generate glitch and also measure it using electronic test equipment. “Modern VLSI Design Systems on Chip”.4. Shelake. Rajanish K. SOC prototyping. Control bits 00 01 10 11 Count update after every sec. 4. Pearson Education 5. fan out and power by implementing this design using different state encoding styles? 2.. Kamat. Vinod G. implement and test SOC.. Implement temperature logging system as a co-design by Interfacing FPGA & μC 8051 as follows : i) LM 35 interfaced with ADC ii) ADC interfaced with FPGA iii) FPGA interfaced with μC 8051 iv) μC 8051 is interfaced with LCD To display real-time room temperature. testing and physical design. 2. The student will able to design . . embedded software and energy management techniques for SOC design. The student will study SOC modeling and interfacing. Design. verification. The student will learn SOC memory system design. 4. “Unleash the System On Chip using FPGAs and Handel C”. Santhosh A. 0. 3. What is effect on area. speed. Course Outcomes: 1. Design and implement MOD4 counter on PLD and verify multi-clock operations by probing logic analyzer. simulate and implement FSM on PLD for detection of either of input sequence X = … 1001. Wayne Wolf. Shinde. 26 . or …1101… sequence and set output flags Y = ’1’ or Z=’1’ respectively.25 sec 0. If temperature is greater than 250 C Bi-colours LED should change its normal Green color to RED color via opto-isolator by actuation of relay. The student will learn to design flow graphs and flow modeling.5 sec 1 sec 4 sec 3. Springer System on Chip Laboratory Assignments/Experiments: 1.
Mitra. Prentice-Hall of India. Selections of DSP processors. Wiley-IEEE Press 2007 2. Rabiner and Bernard Gold. 3. Adaptive algorithms: system identification. Algorithms of Adaptive Filters. “Theory and application of Digital signal Processing”. Real time implementation Considerations. Prentice-Hall. McCraw Hill. FFT algorithms. Barrel shifter. Sen M. Memory System and Data Transfer. Dividers. Code Optimization Module IV Practical DSP Applications: Audio Coding and Audio Effects. DSP processor architecture. 2006. DTMF generation and detection. 27 . prediction. Design of FIR Filters Design of IIR Filters. DSP processor architectures: TMS 320C54XX. “ Digital Signal Processing: A Computer based approach”. “Embedded Signal Processing With the Micro Signal Architecture”. memory management. noise cancellation. Introduction to Digital Systems. Hardware interfacing. Digital Image Processing. Multipliers. On chip resources. “ Digital Signal Procesors: architectures. Structures and Characteristics of IIR Filters. Simple Low pass Filters Design and applications of Notch Filters. Sanjit K. I/O management. Digital Filters Realization of FIR Filters. Time-Domain Digital Signals. ALU. Lawrence R. Image Enhancement. Fast Fourier Transform. Module III Introduction to Digital signal processing systems. Wavelet algorithms. Moving-Average Filters: Structures and Equations. Module II Frequency-Domain Analysis and Processing. 1998. 4. Nonlinear Filters Implementation. Woon-Seng Gan and Sen M. Software developments. MAC. References 1. Kuo. Discrete Fourier Transform. TwoDimensional Filtering. Design and Applications of Adaptive Filters. TMS 320C67XX Blackfin processor: Architecture overview.504209 Teaching Scheme: Lectures 4 Hrs/ Week Embedded Signal Processors Examination scheme: Theory : 50 Marks (In Semester) 50 Marks (End Semester) Credits : 4 Module I Introduction to Real-Time Embedded Signal Processing. inverse modeling. Kuo and Woon-Seng Gan. programming considerations. implementations and applications”..
3. The student will be capable of designing the system for linear filtering using DFT. 4. The student will exhibit the knowledge of implementing DSP algorithms on DSP Processor Platforms. Design and simulate N tap FIR filter by targeting suitable DSP processor platform. 2. 3. The student will demonstrate the ability to analyze filter structures. 5. 2. The student will demonstrate the design of adaptive filters. Design and simulate N point FFT by targeting suitable DSP processor platform. The student will show skills for design of FIR and IIR filters for any application. Course Outcomes: 1. 4. Design and simulate LMS adaptive filter.Embedded Signal Processors Laboratory Assignments/Experiments: 1. Performance comparison of different filter structures. 28 .
Partitioning of the design into its software and hardware components. P Marwedel. communication protocols. Custom Single-purpose processors. driver development. RTOS porting. Study of any TWO real life embedded products in detail. Software. “Embedded System Hardware/Software Introduction”.S/W:Tradeoffs. maintenance.504210 Teaching Scheme: Lectures 4 Hrs/ Week Embedded Product Design ELECTIVE-II Examination Scheme: Theory : 50 Marks (In Semester) 50 Marks (End Semester) Credits : 4 Module I Overview of embedded products: Need. Design Technology. their selection criterion Certification and documentation: Mechanical Packaging. validation and development. turnkey product design. firmware design. Module III Modules of H/W. FPGA design. “Embedded System Design”. reliability and failure analysis. Frank Vahid and Tony Givargis . their features. Design and verification. optimization. Iteration and refinement of the partitioning. testing. Design technology-Hardware design. re-engineering. specifications of product need of hardware and software. product survey. Certification (EMI / RFI) and Documentation.different tools. Memory. Module II Deign models and techniques: various models of development of hardware and software. cost reduction. John Wiley publication 2. General-purpose processors. IC technology. different Processor technology. Testing. Integration of the hardware and software components. Springer publication Design: A Unified 29 . Module IV Testing and verification: Embedded products-areas of technology. References 1. Design challenges. prototyping. Interfacing.
Course Outcomes: 1. biometrics system. laptop. The student will study Embedded System & Product specifications. Testing. EMG/ECG machine etc. Certification (EMI / RFI) and Documentation 4. To design any one embedded product to solve any real life problem/s. 30 . To estimate techno-commercial feasibility of any one embedded product such as mobile phone. set top box etc. The student will demonstrate the knowledge embedded product design related hardware and software design tools. 5. 2. To simulate the software designed for the above assignment (3) using suitable tool. tablet PC.Embedded Product Design Laboratory Assignments/Experiments: 1. To study design considerations of any one embedded product e. To test the hardware designed for above assignment (3) using suitable tool. The student will understand the aspects of Mechanical Packaging. programmable calculator. 4. 3. challenges 2. The student will be able to do cost estimation of Embedded product 3. reliability and failure analysis. video conferencing system. surveillance/ security system.g.
Michel S. Goyal. Future interconnects. References 1. slow wave mode. Green’s function method. Springer Publication 31 . Zhang. resistances. O. RLC models. capacitances. “Modeling and Simulation of High Speed VLSI Interconnects”. Module III Propagation modes. Transmission line equations. Interconnect model based on scattering matrix. Optimizations. Second Edition. slow wave mode. John Wiley Publications 2. Analysis of tree structure. Parasitic inductances. Ground planes. Nano technology circuit interconnects. Optical interconnects.504210 Teaching Scheme: Lectures 4 Hrs/ Week VLSI Interconnections ELECTIVE-II Examination Scheme: Theory : 50 Marks (In Semester) 50 Marks (End Semester) Credits : 4 Module I Metal interconnects. Electromagnetic analysis of multi conductor interconnects. Ashok K. Parasitic inductances. Nakhla. hierarchical interconnects. “High Speed VLSI Interconnections”. Switch box routing in PLDs. super conducting interconnects. resistances. RC models. Ground planes. Mesh interconnects. IEEE Press. Module II Propagation modes. J. Analysis. Interconnect delays Module IV Micro strip line model. capacitances.
Simulate a transmission line and evaluate VSWR. Reflection coefficient considering different loading considerations using analog simulation 4. The student will understand the interconnect models. Plot stability circle.VLSI Interconnections Laboratory Assignments/Experiments: 1. for given values of S parameters. 3. 2. 3. Simulate RC circuit and comment on transient response. parameters tool. 2. Simulate startup model of RLC. 32 . The student will study delay aspects due to high speed operations. The student will study futuristic aspects of interconnection. Course Outcomes: 1.
Spectral density view. guard rings. AAF and RCF. 2nd edition. Noise-shaping data converters: First order noise shaping. Miltibit modulators. 33 . Charge-scaling. SNR & SNDR. “CMOS: Mixed Signal Circuit Design”. Sample and hold characteristics. Phillip E. Quantization noise. Clock jitter. Averaging to improve SNR. 2. Pipeline. Mixed signal layout issues: floor planning. Jacob Baker. Interpolating filters for DACs. “CMOS: Circuit Design. RMS quantization noise voltage. DAC specifications. layout and simulation”. Circuit concerns for implementing S/H.. Douglus R. “CMOS Analog Circuit Design”. R. shielding. calculating RMS quantization noise voltage from a spectrum Module IV Data converter SNR: Effective number of bits. Cascaded modulators. Adding noise dither to ADC input. Holberg. Impulse sampling. S/H spectral response. Allen. Decimating filters for ADCs. Successive approximation. ADC specifications. R-2R ladder networks. Pipeline. fully differential design/ matching. Second order noise shaping. Noise shaping topologies: Higher-order modulators. Wiley IEEE press publications. The sample and hold. Oxford University Press publications. 2nd edition. Dual slope.504210 Teaching Scheme: Lectures 4 Hrs/ Week Mixed Signal Circuit Design ELECTIVE-II Examination Scheme: Theory : 50 Marks (In Semester) 50 Marks (End Semester) Credits : 4 Module I Analog versus discrete time signals. Decimating filters for ADC. Data converter linearity requirements. References 1.. interconnect considerations. treating quantization noise as a random variable. Current steering. Module III Data converter modelling: Sampling and aliasing: A modelling approach. Module II DAC architectures: Resistor string. Converting analog signal to digital signal. R. ADC architectures: Flash. Spurious free dynamic range. Signal to noise plus distortion ratio. 3. Time domain description of reconstruction. Relaxed requirements on AAF. Wiley IEEE press publications. Jitter and averaging. power supply and grounding issues. dynamic range. Oversampling ADC. Jacob Baker.
with 8 MHz sine wave sampled at 100 MHz. 2. Course Outcomes: 1. 6. 4. 2. 5. Plot ideal transfer curves for 3 bit and 4 bit DAC. Find the resolution for a DAC if the output voltage is desired to change in 1 mV increments. using VRef = 5V and 3V. Design and simulate sample and hold circuit. 4. left by 1/2 LSB and calculate DNL. The student will understand the issues mixed signal issues in circuit design.5 V. The student will understand delta-sigma or sigma-delta converter. Calculate SNR and plot ADC input and DAC output for cascaded 8 bit ADC and DAC operated on VDD=1. 34 . The student will understand methods to improve SNR. Sampling frequency = 100 MHz.75VPP). 3. and its issues. The student will understand types and modeling of ADCs & DACs. Vin = 24 MHZ (0. VRef = 5V. Design and simulate anti-aliasing filter with two input sine waves having frequencies 4MHz & 40 MHz. Plot ideal transfer curve and quantization error. 3.Mixed Signal Circuit Design Laboratory Assignments/Experiments:[Perform any 5] 1. For 3 bit ADC. Plot transfer curve and quantization error by shifting entire transfer curve of example 2.
504210 Teaching Scheme: Lectures 4 Hrs/ Week Software Defined Radio ELECTIVE. Transmitter Architectures and their issues. Joint Tactical Radio System. Hybrid DDS-PLL Systems. Key Hardware Elements. 2004 5. Kovarik. References 1. Needs. May 2002 ISBN: 0130811580 2. “Software Radio: A Modern Approach to Radio Engineering”. Parameters of data converters Module IV Smart Antennas: Concept of Smart Antennas. Johnson. Bard. Smart Antenna Algorithms. Timing Recovery in Digital Receivers Using Multirate Digital Filters Module III Signals in SDR: Approaches to Direct Digital Synthesis. John and Kovarik. Band-pass Signal Generation. Vincent.). The Software Communications Architecture”. Jeffrey H. Architectures. Object-oriented representation of radios and network resources. Reed. FPGAs and ASICs Case studies in Radio System: Power Management Issues.A.II Examination Scheme: Theory : 50 Marks (In Semester) 50 Marks (End Semester) Credits : 4 Module I Fundamentals of SDR: Software Radios. Digital hardware choices. Prentice Hall PTR. Generation of Random Sequences. Systems and Functions”. Analysis of Spurious Signals. Sethares. “Software Defined Radio. 2007 35 . Field Programmable Gate Arrays. Wiley 2007 4. and W. Dillinger. Characteristics. Bard. Alonistioti (Eds. Wiley 2003 3. Case studies in software radio design. Structures for Beam-forming Systems. Trade-Offs in Using DSPs. Principal Challenge of Receiver Design Module II RF and SDR: RF Receiver Front-End Topologies. C. Enhanced Flexibility of the RF Chain with Software Radios. Noise and Distortion in the RF Chain. Pearson Prentice Hall. Spurious Components due to Periodic Jitter. “Software Defined Radio: The Software Communications Architecture”. Design Principles of a Software Radio. “Software Defined Radio. Wiley Series in Software Radio. Madani. “Telecommunication Breakdown: Concepts of Communication Transmitted via Software-Defined Radio. Benefits. Radio frequency implementation issues.R. Mobile Application Environments. DSP Processors.
Microwind. RTLinux. 3. LAB VIEW. 4. CAD Feko. find DNL. VxWorks. The student will be study design aspects of software radios. Tanner. NS-II. 3. AWR Microwave office. 4. ANDROID. 36 . 504210 *Software Tools ELECTIVE-II Teaching Scheme: Examination Scheme: Theory 1 Hrs/ Week Credits :1 Introduction to software tools such as Octave. The student will study Needs. 2. Design and simulate PSK module for given specifications.Software Defined Radio Laboratory Assignments/Experiments: 1. IE-3D. & SNR for given specifications. NS-III. Characteristics. The student will study key hardware elements and related Trade-Offs. Design and simulate PLL system for given specifications. The student will understand concept of Smart Antennas. µCOS-II. TCAD Tools. MATLAB. Benefits and Design Principles of a Software Radio. Design and simulate high resolution ADC. calculate performance measures. Course Outcomes: 1. OPNET. INL. *For each Subject under Elective II the student Shall study open source/evaluation versions of at least two software tools mentioned above and should present term paper. 2. Design and simulate OFDM system for given specifications. Tiny OS. Xilinx. OMNET++.
504212 Teaching Scheme: Practical 4 Hrs/ Week Seminar I Examination Scheme: Term Work : 50 Marks Oral/ Presentation: 50 Marks Credits :4 Seminar I : Shall be on state of the art topic of student’s own choice approved by an authority. The student shall submit the duly certified seminar report in standard format. for satisfactory completion of the work by the concerned Guide and head of the department/institute.504211 Teaching Scheme: Practical 4 Hrs/ Week Lab Practice II Examination Scheme: Term Work : 50 Marks Oral/ Presentation: 50 Marks Credits :4 Lab Practice II: The laboratory work will be based on completion of minimum two assignments/experiments confined to the courses of the semester. 37 .
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