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CMOS Analog Design Using All-Region MOSFET

Modeling
1

CMOS Analog Design Using
All-Region MOSFET Modeling

Chapter 6
Current Sources and
Voltage References
CMOS Analog Design Using All-Region MOSFET
Modeling
2
Simple MOS current source
(a) A simple MOS current source (b) Current x voltage
characteristic of the input transistor and load line.
0
1 2 ln 1 1
REF REF
REF DD T t
S S
I I
RI V V n
I I
|
(
| |
~ ÷ ÷ + ÷ + + ÷
( |
|
(
\ .
¸ ¸
I
REF
is, in general, very
sensitive to V
DD
, R,
and M
Low current requires
high R (large silicon
area)

CMOS Analog Design Using All-Region MOSFET
Modeling
3
Widlar current source
Low current can be generated
without large resistances
N is also a design parameter (more
important than R
S
)
Input current I
REF
often high – not
convenient for low-power design
CMOS Analog Design Using All-Region MOSFET
Modeling
4
Self-biased current source - 1
1
1 1
1
1 1
1 1 ln
1 1
OUT
S
S OUT OUT OUT
t S S
OUT
S
I
I
R I I I
I KI
I
KI
|
(
| |
+ ÷
( |
( |
= + ÷ + +
( |
+ ÷ ( |
|
(
\ .
¸ ¸
ln
t
OUT
S
I K
R
|
=
( )
2
2
2
1
2
2
1
1
1
2 1
1
/
t
OUT
S S
S n ox
I
R I K
R C n W L K
|
µ
| |
= ÷ =
|
|
\ .
| |
÷
|
|
'
\ .
weak inversion
strong inversion
1 1
S
WI
S
dR
TC
T R dT
= ÷
1 2
n S
SI
n S
dn dR
TC
n dT R dT
µ
µ
= ÷ ÷
CMOS Analog Design Using All-Region MOSFET
Modeling
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I
1

I
2

I
2
=I
1

Current mirror
M
3
-M
4

Current mirror
M
1
-M
2
-R
S

Point A
Point B
Start-up circuit:
ensures that A is the solution;
“wakes-up” current source
ASAP after power-up
Self-biased current source - 2
CMOS Analog Design Using All-Region MOSFET
Modeling
6
MOSFET-only self-biased current source
1
1
2
1
1
1 1
1 1 ln ln
1 1
f
f
S
f
t
f
i
i
V
i K
K
i
K
|
(
| |
( |
+ ÷
( |
= + ÷ + + ~
( |
+ ÷ ( |
\ .
¸ ¸
5
6 5 1
4
D D D
S
I I I
S
= =
7 7 7 7 1 1 1
( )
D S f r D S f
I I i i I I i = ÷ = =
6
7 6
6
D
f f
S
I
i i
I
= =

7
2
7 7
7
1 1
1 1 ln
1 1
f
S
f r
t
r
i
V
i i
i
|
| |
+ ÷
| = + ÷ + +
|
+ ÷
\ .
5 1
7 1
4 6
f f
S S
i i
S S
=
6 6 5 4 4 1
7 7 1
5 7 5 7 4 6
1 1
r f f
S S S S S S
i i i
S S S S S S
| | | |
= ÷ = ÷
| |
\ . \ .

,

2
7
2 1 2 ( 1)
2
t
OUT n ox
I C n S J J J
|
µ
(
' = ÷ + ÷
¸ ¸
J=S
5
S
7
/S
4
S
6

CMOS Analog Design Using All-Region MOSFET
Modeling
7
Bandgap voltage reference – 1
Choose M such that
0 0
0
out BE
T T
dV dV k
M
dT dT q
= + =
The output voltage for
zero temperature
coefficient is close to the
“extrapolated” band-gap
voltage of Si (1.206 V)
T
V
BE

~ -2 mV/
o
C
T
k/q=+ 86.19
µV/
o
C
|
t

V
CC

|
t
generator
E
|
t

M|
t

+
V
BE

-
M
I
1

out BE t
V V M| = +
CMOS Analog Design Using All-Region MOSFET
Modeling
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0 0
0
out BE
T T
dV dV k
M
dT dT q
= + ~
T
constant
BE
kT
V M
q
+ ~
BE
V
t
M|
Bandgap voltage reference – 2
CMOS Analog Design Using All-Region MOSFET
Modeling
9
1
exp
BE
C sat
t
V
I I I
|
| |
= =
|
\ .
2
i n t
sat
B
qAn
I
G
µ |
=
2 3
exp
G
i
E
n DT
kT
÷
| |
~
|
\ .
( )
0 0
/
m
n n
T T µ µ
÷
=

E
G:
~1.206 eV, silicon bandgap extrapolated to 0 K.
Assume the average mobility of electrons in the base region is
The temperature coefficient of the voltage reference is
0
B
W
B A
G N dx =
}
( )
1 0 0
/
C
I I T T
o
=
( )
(4 )
BE t
G BE
d V M
E V k
m M
dT T q kT
|
o
+
(
= + ÷ ÷ ÷ ÷ +
(
¸ ¸
Assume that
( )
0
0 0
(4 )
/
BE G
V E
M m
kT q kT
o = ÷ + + ÷ ÷
=0 at T=T
0

0
0
2
0
(4 )(1 ln )
(4 )
2
G
OUT
OUT
T T
E T kT
V m
q q T
T T kT
V m
q T
o
o
=
= + ÷ ÷ + ~
÷
| |
÷ ÷ ÷
|
\ .
Bandgap voltage reference – 3
CMOS Analog Design Using All-Region MOSFET
Modeling
10
CMOS-compatible bandgap reference - 1
( )
( )
1
2
1 2
2
1
/
ln
/
O BE BE
I W L
kT
V V V V V n
q I W L
= + ÷ = +
Problem: n=n(T, V
G
)
Minimum supply: V
BE
+V
1
+V
DSsat

(current
source)
Both M
1
and M
2
in weak inversion
CMOS Analog Design Using All-Region MOSFET
Modeling
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CMOS-compatible bandgap reference - 2
PTAT voltage generator. Transistors M
1

and M
3
are biased in weak inversion.
3 2 2 2
1 4 1 4
1 1 ln
O
S R S S kT
V
R S q S S
(
| |
= + +
( |
\ .
¸ ¸
CMOS Analog Design Using All-Region MOSFET
Modeling
12
CMOS-compatible bandgap reference - 3
V
CC

+
V
BE1

-
I
1

V
CC

+
V
BE2

-
I
2

1 1
1
1 1
2 2
2
2 2
1 2
1 2
2 1
ln ln
ln ln
ln
BE t t
S S
BE t t
S S
BE BE BE t
I I
V
I J A
I I
V
I J A
I A
V V V
I A
| |
| |
|
= =
= =
A = ÷ = 1 2 1
ln
R E E
kT
V V V N
q
= ÷ =
2
2
1
1 ln
REF BE
R kT
V V N
R q
(
| |
= ÷ + +
( |
\ .
¸ ¸
CMOS Analog Design Using All-Region MOSFET
Modeling
13
CMOS-compatible bandgap reference - 4
2
2
1
ln
REF EB
R kT
V V N
R q
= +
Problems:
 Op amp offset voltage
 Poor performance of
substrate pnp transistors ??
CMOS Analog Design Using All-Region MOSFET
Modeling
14
Exercise
( )
2
2
3
1
OUT EB EB OS
R
V V V V
R
| |
= + + A +
|
\ .
Band-gap reference in n-well CMOS
Vertical (substrate)
pnp transistors
Exercise: Show that
Source of error
CMOS Analog Design Using All-Region MOSFET
Modeling
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CMOS-compatible bandgap reference - 5
VFCM
VFCM: voltage following
current mirror
2
3
1
ln
REF EB
R kT
V V N
R q
= +
CMOS Analog Design Using All-Region MOSFET
Modeling
16
Eric A. Vittoz, MOS Transistors Operated in the
Lateral Bipolar Mode and Their Application in
CMOS Technology, IEEE JSSC, Vol. 18, no. 3,
pp. 273-279, June 1983
p-well CMOS process
CMOS-compatible bandgap reference - 6
CMOS Analog Design Using All-Region MOSFET
Modeling
17
CMOS bandgap reference with sub-1-V
operation
V
DD

M
3

M
1

M
2

R
1

1
Q
1

N
I
1a

R
2

V
REF

Q
2

+
R
2

R
3

I
2a

I
1b

I
2b

I
1
I
2

I
3

I
1
=I
2
=I
3

-
CMOS Analog Design Using All-Region MOSFET
Modeling
18
Design of a SBCS – 1
2
1 2 2
1
1
1 1
f f f
S
i i i
S N
o
(
| |
= + + =
( |
\ .
¸ ¸
2
2 2
2
1 1
1 1 ln
1 1
f
X
f f
t
f
i
V
i i
i
o
o
|
| |
+ ÷
| = + ÷ + +
|
+ ÷
\ .
2 2
1 1 2
( ) ( 1)
S f x
S f f x
I i NI
I i i N I
=
÷ = +
Applying UICM to both M1 & M2
2 1 f r
i i =
Sat.
Triode
2 x
I NI =
SELF-CASCODE MOSFET (SCM)
2
2 2
2
1 1
1 1 ln
1 1
X
SH
X X X
t SH SH
X
SH
NI
S I
V NI NI
S I S I
NI
S I
o
o
|
| |
+ ÷
|
|
= + ÷ + +
|
+ ÷
|
|
\ .
CMOS Analog Design Using All-Region MOSFET
Modeling
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1
0.01 S =
2
0.01 S =
I
X

I
X

2I
X

3
10 S =
4
1.13 S =
I
X

I
X

2I
X

1 1
1 1 ln
1 1
X
SH
X X X
t SH SH
X
SH
I
SI
V I I
SI SI
I
SI
o
o
|
| |
+ ÷
|
|
= + ÷ + +
|
+ ÷ |
|
\ .
/
X t
V |
/
X SH
I I
SCM
1,2

SCM
3,4

3
0.01 S
o =
=
18.7
1.13 S
o =
=
Design of a SBCS – 2
CMOS Analog Design Using All-Region MOSFET
Modeling
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VOLTAGE FOLLOWING (NMOS) CURRENT MIRROR (PMOS)
1

9
ln( )
ref S t
V V JK | = +
When both M
8
& M
9
operate in WI:
8
9
8 8
8
1 1
1 1 ln
1 1
f
ref S
f f
t
f
JKi
V V
JKi i
i
|
| |
+ ÷
÷
| = + ÷ + +
|
+ ÷
\ .
Design of a SBCS – 3
CMOS Analog Design Using All-Region MOSFET
Modeling
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A self-biased current source
V
x

VFCM
V
x



Design of a SBCS – 4
CMOS Analog Design Using All-Region MOSFET
Modeling
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VFCM
2
1
1
1 1 1 1 1 3
S
S N
o
| |
= + + = + + =
|
\ .
1 30 1
1 30 1 10 ln 2.93
1 10 1
X
t
V
|
| |
+ ÷
= + ÷ + + =
|
|
+ ÷
\ .
M
1
&M
2
in MI: i
f2
= 10 S
2
= S
1
, N = 1
2
2 2
2
1 1
1 1 ln
1 1
f
X
f f
t
f
i
V
i i
i
o
o
|
| |
+ ÷
| = + ÷ + +
|
+ ÷
\ .
Let us choose
M
3
&M
4
in WI: i
f3(4)
<<1
2.93
ln 18.7
X
t
V
e o o
|
~ ¬ = ~
4 4
3 3
1
18.7 1 1 8.85
1
S S
S S
| |
= + + ¬ =
|
\ .
Output current: I
ref
=10 nA
I
SHn-channel
~100 nA, I
SHp-channel
~40 nA
=1
=10 nA
2 2 2 2 1
10 nA 1 nA 0.01
S f S
I i I S S = ÷ = ÷ = =
Let us choose i
f3
=0.187 ÷
| |
4 3 4 3
/ 1 2 / 0.01
f f
i i S S = + = 4 4 4 4
10 nA 1 A 10
S f S
I i I S µ = ÷ = ÷ =
4
3
1.13
8.85
S
S = =
Design of a SBCS – 5
CMOS Analog Design Using All-Region MOSFET
Modeling
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S i
f
i
r

M
1
0.01 10 0
M
2
0.01 30 10
M
3
1.13 0.187 0.01
M
4
10 0.01 0
M
8
, M
8(a)
1 0. 1 0
M
9
, M
9(a)
1 0. 1 0
M
P
(all) 2.5 0.1 0
4
10 S =
VFCM
=1
=10 nA
2
1 0.0 S =
2.93
X t
V | =
2.93
X t
V | =
3
1.13 S =
1
1 0.0 S =
Summary
Design of a SBCS – 6
CMOS Analog Design Using All-Region MOSFET
Modeling
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Design of a SBCS – 7