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AD9850

AD9850

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DDS
DDS

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Published by: Vasi Vali on Jan 21, 2014
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FEATURES 125 MHz Clock Rate On-Chip High Performance DAC and High Speed Comparator DAC SFDR > 50 dB @ 40 MHz A OUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability 3.3 V or 5 V Single-Supply Operation Low Power: 380 mW @ 125 MHz (5 V) Low Power: 155 mW @ 110 MHz (3.3 V) Power-Down Function Ultrasmall 28-Lead SSOP Packaging APPLICATIONS Frequency/Phase—Agile Sine Wave Synthesis Clock Recovery and Locking Circuitry for Digital Communications Digitally Controlled ADC Encode Generator Agile Local Oscillator Applications

CMOS, 125 MHz Complete DDS Synthesizer AD9850
FUNCTIONAL BLOCK DIAGRAM
+VS REF CLOCK IN MASTER RESET GND DAC RSET HIGH SPEED DDS 32-BIT TUNING WORD FREQUENCY UPDATE/ DATA REGISTER RESET WORD LOAD CLOCK PHASE AND CONTROL WORDS 10-BIT DAC ANALOG OUT

ANALOG IN CLOCK OUT CLOCK OUT

FREQUENCY/PHASE DATA REGISTER

DATA INPUT REGISTER SERIAL LOAD 1-BIT 40 LOADS PARALLEL LOAD

COMPARATOR

AD9850

8-BITS 5 LOADS FREQUENCY, PHASE, AND CONTROL DATA INPUT

GENERAL DESCRIPTION

The AD9850 is a highly integrated device that uses advanced DDS technology coupled with an internal high speed, high performance D/A converter and comparator to form a complete, digitally programmable frequency synthesizer and clock generator function. When referenced to an accurate clock source, the AD9850 generates a spectrally pure, frequency/phase programmable, analog output sine wave. This sine wave can be used directly as a frequency source, or it can be converted to a square wave for agile-clock generator applications. The AD9850’s innovative high speed DDS core provides a 32-bit frequency tuning word, which results in an output tuning resolution of 0.0291 Hz for a 125 MHz reference clock input. The AD9850’s circuit architecture allows the generation of output frequencies of up to one-half the reference clock frequency (or 62.5 MHz), and the output frequency can be digitally changed (asynchronously) at a rate of up to 23 million new frequencies per second. The device also provides five bits of digitally controlled phase modulation, which enables phase shifting of its output in increments of 180°, 90°, 45°, 22.5°,

11.25°, and any combination thereof. The AD9850 also contains a high speed comparator that can be configured to accept the (externally) filtered output of the DAC to generate a low jitter square wave output. This facilitates the device’s use as an agile clock generator function. The frequency tuning, control, and phase modulation words are loaded into the AD9850 via a parallel byte or serial loading format. The parallel load format consists of five iterative loads of an 8-bit control word (byte). The first byte controls phase modulation, power-down enable, and loading format; Bytes 2 to 5 comprise the 32-bit frequency tuning word. Serial loading is accomplished via a 40-bit serial data stream on a single pin. The AD9850 Complete DDS uses advanced CMOS technology to provide this breakthrough level of functionality and performance on just 155 mW of power dissipation (3.3 V supply). The AD9850 is available in a space-saving 28-lead SSOP, surface-mount package. It is specified to operate over the extended industrial temperature range of –40°C to +85°C.

REV. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.

AD9850–SPECIFICATIONS (V = 5 V ؎ 5% except as noted, R
S

SET

= 3.9 k⍀)
Min AD9850BRS Typ Max Unit

Parameter CLOCK INPUT CHARACTERISTICS Frequency Range 5 V Supply 3.3 V Supply Pulse Width High/Low 5 V Supply 3.3 V Supply DAC OUTPUT CHARACTERISTICS Full-Scale Output Current RSET = 3.9 kΩ RSET = 1.95 kΩ Gain Error Gain Temperature Coefficient Output Offset Output Offset Temperature Coefficient Differential Nonlinearity Integral Nonlinearity Output Slew Rate (50 Ω, 2 pF Load) Output Impedance Output Capacitance Voltage Compliance Spurious-Free Dynamic Range (SFDR) Wideband (Nyquist Bandwidth) 1 MHz Analog Out 20 MHz Analog Out 40 MHz Analog Out Narrowband 40.13579 MHz ± 50 kHz 40.13579 MHz ± 200 kHz 4.513579 MHz ± 50 kHz/20.5 MHz CLK 4.513579 MHz ± 200 kHz/20.5 MHz CLK COMPARATOR INPUT CHARACTERISTICS Input Capacitance Input Resistance Input Current Input Voltage Range Comparator Offset* COMPARATOR OUTPUT CHARACTERISTICS Logic 1 Voltage 5 V Supply Logic 1 Voltage 3.3 V Supply Logic 0 Voltage Propagation Delay, 5 V Supply (15 pF Load) Propagation Delay, 3.3 V Supply (15 pF Load) Rise/Fall Time, 5 V Supply (15 pF Load) Rise/Fall Time, 3.3 V Supply (15 pF Load) Output Jitter (p-p) CLOCK OUTPUT CHARACTERISTICS Clock Output Duty Cycle (Clk Gen. Config.)

Temp

Test Level

Full Full 25°C 25°C

IV IV IV IV

1 1 3.2 4.1

125 110

MHz MHz ns ns

25°C 25°C 25°C Full 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full Full Full Full 25°C 25°C 25°C 25°C 25°C 25°C

V V I V I V I I V IV IV I

10.24 20.48 –10 150 10 50 0.5 0.5 400 120 0.75 1 +10

50

8 1.5

mA mA % FS ppm/°C µA nA/°C LSB LSB V/µs kΩ pF V

IV IV IV IV IV IV IV V IV I IV VI VI VI VI V V V V V IV

63 50 46

72 58 54 80 77 84 84 3

dBc dBc dBc dBc dBc dBc dBc pF kΩ µA V mV V V V ns ns ns ns ps %

500 –12 0 30 4.8 3.1

+12 VDD 30

0.4 5.5 7 3 3.5 80 50 ± 10

–2–

REV. H

3. Specifications subject to change without notice.8 12 12 3 Unit V V V µA µA pF Full Full Full Full Full Full Full Full Full Full VI VI VI VI VI VI VI VI V V 30 47 44 76 100 155 220 380 30 10 48 60 64 96 160 200 320 480 mA mA mA mA mW mW mW mW mW mW TIMING CHARACTERISTICS*(V = 5 V ؎ 5% except as noted.5 MHz Clock.3 V Supply 62. 5 V Supply PDISS Power-Down Mode 5 V Supply 3. 3. Specifications subject to change without notice.5 7. 3. 5 V Supply 125 MHz Clock.5 MHz Clock. 5 V Supply PDISS @ 62.5 MHz Clock.3 V Supply 62.3 V Supply 110 MHz Clock.9 k⍀) AD9850BRS Min Typ Max 3.5 5 13 2 5 Unit ns ns ns ns ns ns ns ns CLKIN Cycles CLKIN Cycles ns ns ns CLKIN Cycles CLKIN Cycles CLKIN Cycles µs Parameter tDS tDH tWH tWL tWD tCD tFH tFL tCF tFD tRH tRL tRS tOL tRR (Data Setup Time) (Data Hold Time) (W_CLK Minimum Pulse Width High) (W_CLK Minimum Pulse Width Low) (W_CLK Delay after FQ_UD) (CLKIN Delay after FQ_UD) (FQ_UD High) (FQ_UD Low) (Output Latency from FQ_UD) Frequency Change Phase Change (FQ_UD Minimum Delay after W_CLK) (CLKIN Delay after RESET Rising Edge) (RESET Falling Edge after CLKIN) (Minimum RESET Width) (RESET Output Latency) (Recovery from RESET) Wake-Up Time from Power-Down Mode Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C Test Level IV IV IV IV IV IV IV IV IV IV IV IV IV IV IV IV V *Control functions are asynchronous with CLKIN.5 3.5 3.5 2.3 V Supply *Tested by measuring output duty cycle variation.3 V Supply 110 MHz Clock.5 3.4 0. 5 V Supply 125 MHz Clock.5 MHz Clock.0 3.0 3. 5 V Supply Logic 1 Voltage. Temp 25°C 25°C 25°C 25°C 25°C 25°C Test Level I IV IV I I V AD9850BRS Min Typ Max 3.AD9850 Parameter CMOS LOGIC INPUTS (Including CLKIN) Logic 1 Voltage. 3. 3. H –3– .5 7.5 3. REV.0 7.3 V Supply Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance POWER SUPPLY (AOUT = 1/3 CLKIN) +VS Current @ 62. R S SET = 3.0 18 13 7.

WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Model AD9850BRS AD9850BRS-REEL AD9850BRSZ* AD9850BRSZ-REEL* AD9850/CGPCB AD9850/FSPCB *Z = Pb-free part. . . Functional operability under any of these conditions is not necessarily implied. . . . . . . . . . . . . permanent damage may occur on devices subjected to high energy electrostatic discharges. . . . . . . . . . . 300°C SSOP θJA Thermal Impedance . . . IV Parameter is guaranteed by design and characterization testing. . . . 6 V Digital Inputs . . . . . CAUTION ESD (electrostatic discharge) sensitive device. . . . . . . . . . . . Test Level I 100% Production Tested. . . 82°C/W *Absolute maximum ratings are limiting values. . . . . . . . . . . . . . . . . . . . . . Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. . . . . V Parameter is a typical value only. . . to be applied individually. . . . . . . 30 mA Storage Temperature . . . . . . . . . . III Sample Tested Only. VI All devices are 100% production tested at 25°C. . Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. . . . . . . . . . . . . . . guaranteed by design and characterization testing for industrial devices. . H . . . . . . . Application Note: Users are cautioned not to apply digital input signals prior to power-up of this device. . . . . . 100% production tested at temperature extremes for military temperature devices. . . . . . . .7 V to +VS Digital Output Continuous Current . . . . .AD9850 ABSOLUTE MAXIMUM RATINGS * EXPLANATION OF TEST LEVELS Maximum Junction Temperature . Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description Shrink Small Outline Package (SSOP) Shrink Small Outline Package (SSOP) Shrink Small Outline Package (SSOP) Shrink Small Outline Package (SSOP) Evaluation Board Clock Generator Evaluation Board Frequency Synthesizer Package Option RS-28 RS-28 RS-28 RS-28 –4– REV. 5 mA DAC Output Current . . . . Although the AD9850 features proprietary ESD protection circuitry. . . . . –0. . . . –40°C to +85°C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . Doing so may result in a latch-up condition. . and beyond which the serviceability of the circuit may be impaired. Therefore. . . . . . . . . . . . . . . proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 150°C VDD . –65°C to +150°C Operating Temperature . . . . .

PIN FUNCTION DESCRIPTIONS Pin No. 13 14 15 16 17 20 21 22 QOUTB QOUT VINN VINP DACBL (NC) DAC Baseline. This is the comparator’s complement output. IOUTB IOUT RESET Complementary Analog Output of the DAC. Analog Current Output of the DAC. 4 to 1. This clock is used to load the parallel or serial frequency/phase/control words. For normal applications (FS IOUT = 10 mA). Analog Ground. This resistor value sets the DAC full-scale output current. This is the comparator’s negative input. Output Complement.248 V/RSET). it clears all registers (except the input register). This is the comparator’s true output. Word Load Clock. Output True. when set high. The rising edge of this clock initiates operation.AD9850 PIN CONFIGURATION D3 D2 D1 LSB D0 DGND DVDD W CLK FQ UD CLKIN 1 2 3 4 5 6 7 28 D4 27 D5 26 D6 25 D7 MSB/SERIAL LOAD 24 DGND 23 DVDD AD9850 TOP VIEW 22 RESET 8 (Not to Scale) 21 IOUT 9 20 IOUTB 19 AGND 18 AVDD 17 DACBL (NC) 16 VINP 15 VINN AGND 10 AVDD 11 RSET 12 QOUTB 13 QOUT 14 NC = NO CONNECT Table I. This is the 8-bit data port for iteratively loading the 32-bit frequency and the 8-bit phase/ control word. D7 = MSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data-word. The RSET/IOUT relationship is IOUT = 32 (1. Reference Clock Input. These are the ground return leads for the digital circuitry. 23 7 8 9 10. Noninverting Voltage Input. 28 to 25 5. DAC’s External RSET Connection. D0 = LSB. 19 11. Supply Voltage for the Analog Circuitry (DAC and Comparator). Reset. This may be a continuous CMOS-level pulse train or sine input biased at 1/2 V supply. Digital Ground. the value for RSET is 3. This is the DAC baseline voltage reference. REV. Inverting Voltage Input. This is the comparator’s positive input. and the DAC output goes to cosine 0 after additional clock cycles—see Figure 7. it then resets the pointer to Word 0. 24 6.9 kΩ connected to ground. Supply Voltage Leads for Digital Circuitry. These leads are the ground return for the analog circuitry (DAC and comparator). this lead is internally bypassed and should normally be considered a no connect for optimum performance. the DDS updates to the frequency (or phase) loaded in the data input register. 18 12 Mnemonic D0 to D7 DGND DVDD W_CLK FQ_UD CLKIN AGND AVDD RSET Function 8-Bit Data Input. This is the master reset function. H –5– . Frequency Update. On the rising edge of this clock.

AD9850 Configured as Clock Generator with 42 MHz LP Filter (40 MHz AOUT/125 MHz CLKIN) TPC 6. CLKIN = 125 MHz/fOUT = 1 MHz TPC 4.818 dB Fxd CH1 S Spectrum AD9850 12dB/REF 0dBm –85.6 sec STOP 62. SFDR.5MHz RBW # 3Hz VBW 3Hz CENTER 4. SFDR.6dBm 76.AD9850–Typical Performance Characteristics CH1 S Spectrum AD9850 10dB/REF –8. H .58V Runs After TPC 3. SFDR.513579MHz ATN # 20dB SWP 399. CLKIN = 125 MHz/fOUT = 41 MHz TPC 5.0ns D 500ps Ch 1 1.925 dB Fxd CLOCK 125MHz CLOCK 125MHz 0 0 RBW # 100Hz START 0Hz VBW 100Hz ATN # 30dB SWP 762 sec STOP 62.3RD : 300ps @: 25.5MHz TPC 1. SFDR. CLKIN = 20. Output Residual Phase Noise (5 MHz AOUT/125 MHz CLKIN) –6– REV.642 dB Fxd CH1 S Spectrum AD9850 10dB/REF –10dBm 59. Typical Comparator Output Jitter.26ns –110 –115 –120 –125 dBc –130 –135 –140 –145 1 500mV⍀ –150 –155 100 10k 1k OFFSET FROM 5MHz CARRIER – Hz 100k Ch 1 M 20. CLKIN = 125 MHz/fOUT = 20 MHz CH1 S Spectrum AD9850 10dB/REF –10dBm 54.5MHz RBW # 300Hz START 0Hz VBW 300Hz ATN # 30dB SWP 182.5 sec SPAN 400kHz TPC 2.401 dB –23 kHz Mkr CLOCK 125MHz 0 0 RBW # 300Hz START 0Hz VBW 300Hz ATN # 30dB SWP 182.6 sec STOP 62.5 MHz Tek Run: 100GS/s ET Sample –105 PN.5 MHz/fOUT = 4.

Supply Current vs.00ns Ch 1 1. Comparator Output Rise Time (5 V Supply/15 pF Load) TPC 10.AD9850 Tek Run: 50. Supply Current vs. CLKIN Frequency (AOUT = 1/3 of CLKIN) 90 75 80 SUPPLY CURRENT – mA 70 VCC = 5V fOUT = 1MHz 70 SFDR – dB 65 60 60 fOUT = 20MHz 50 VCC = 3.0GS/s ET Average Tek Run: 50.3V VCC = 5V 0 20 40 60 80 CLKIN – MHz 100 120 140 0 20 40 60 80 100 CLOCK FREQUENCY – MHz 120 140 TPC 8. Comparator Output Fall Time (5 V Supply/15 pF Load) 68 90 fOUT = 1/3 OF CLKIN 66 80 62 SFDR – dB 60 58 56 54 52 VCC = 3.00V⍀ M 1.870ns Ch 1 Fall 3. SFDR vs. H –7– .0GS/s ET Average Ch 1 Rise 2. CLKIN Frequency (AOUT = 1/3 of CLKIN) TPC 11.202ns 1 1 Ch1 1.3 V Plot) TPC 12.3V VCC = 5V SUPPLY CURRENT – mA 64 70 60 50 40 30 20 10 VCC = 3. DAC IOUT (AOUT = 1/3 of CLKIN) REV.00V⍀ M 1.74V Ch1 1.3V 55 fOUT = 40MHz 50 40 30 45 0 10 20 30 FREQUENCY OUT – MHz 40 5 10 15 DAC IOUT – mA 20 TPC 9. SFDR vs. AOUT Frequency (CLKIN = 125/110 MHz for 5 V/3.00ns Ch 1 1.74V TPC 7.

470pF PROCESSOR BUS RESET. The phase accumulator is a variable-modulus counter that increments the number stored in it each time it receives a clock pulse. Basic AD9850 Clock Generator Application with Low-Pass Filter TUNING WORD 3b.0291 Hz with a 125 MHz reference clock applied. When the counter overflows. the AD9850 allows an output frequency resolution of 0. The AD9850 uses an innovative and proprietary algorithm that mathematically converts the 14-bit truncated value of the phase accumulator to the appropriate COS value. H . reference clock. The frequency tuning word sets the modulus of the counter. DATA OR 1-b ؋ 40 SERIAL DATA. Frequency/Phase–Agile Reference for PLL REF FREQUENCY PHASE COMPARATOR FILTER LOOP FILTER VCO Rx IF IN I 8 I/Q MIXER AD9059 AND LOW-PASS Q DUAL 8-BIT 8 ADC FILTER VCA ADC CLOCK FREQUENCY LOCKED TO Tx CHIP/ SYMBOL PN RATE 125MHz DIGITAL DEMODULATOR Rx BASEBAND DIGITAL DATA OUT AGC RF FREQUENCY OUT PROGRAMMABLE DIVIDE-BY-N FUNCTION ADC ENCODE AD9850 COMPLETE DDS TUNING WORD REFERENCE CLOCK AD9850 32 CLOCK GENERATOR CHIP/SYMBOL/PN RATE DATA 3c. and tuning word of the AD9850 is determined by the formula fOUT = (∆ Phase × CLKIN)/232 where: ∆ Phase is the value of the 32-bit tuning word. AD9850 Complete DDS Synthesizer in Frequency Up-Conversion Applications Figure 2. Digitally-Programmable Divide-by-N Function in PLL Figure 3. The basic functional block diagram and signal flow of the AD9850 configured as a clock generator is shown in Figure 4. The AD9850’s output waveform is phase continuous when changed. Because the output of the –8– REV. DDS technology is an innovative circuit architecture that allows fast and precise manipulation of its output frequency under full digital control. and an on-board high speed comparator is provided to translate the analog sine wave into a low jitter TTL/CMOS compatible output square wave. AD9850 Clock Generator Application in a Spread-Spectrum Receiver THEORY OF OPERATION AND APPLICATION The AD9850 uses direct digital synthesis (DDS) technology.AD9850 +VS GND IOUT 5-POLE ELLIPTICAL 42MHz LOW-PASS 200⍀ IMPEDANCE LOW-PASS FILTER IF FREQUENCY IN FILTER 125MHz FILTER RF FREQUENCY OUT 200⍀ 100k⍀ 8-b ؋ 5 PARALLEL DATA. in the form of a numerically controlled oscillator. AND 2 CLOCK LINES 100k⍀ 100⍀ AD9850 IOUTB VINN XTAL CLK VINP OSC QOUT CMOS QOUTB CLOCK OUTPUTS RSET COMP AD9850 COMPLETE DDS REFERENCE TUNING WORD 3a. CLKIN is the input reference clock frequency in MHz. it wraps around. which contributes to the small size and low power dissipation of the AD9850. to generate a frequency/ phase-agile sine wave. fOUT is the frequency of the output signal in MHz. which effectively determines the size of the increment (∆ Phase) that is added to the value in the phase accumulator on the next clock pulse. making the phase accumulator’s output contiguous. The DDS circuitry is basically a digital frequency divider function whose incremental resolution is determined by the frequency of the reference clock divided by the 2N number of bits in the tuning word. Frequency/Phase–Agile Local Oscillator 200⍀ 125MHz REFERENCE CLOCK AD9850 COMPLETE DDS FILTER PHASE COMPARATOR DIVIDE-BY-N LOOP FILTER RF FREQUENCY OUT VCO TRUE Figure 1. DDS also enables very high resolution in the incremental selection of output frequency. The larger the added increment. the faster the accumulator overflows. The digital sine wave output of the DDS block drives the internal high speed 10-bit D/A converter that reconstructs the sine wave in analog form. This unique algorithm uses a much reduced ROM look-up table and DSP techniques to perform this function. The digital sine wave is converted to analog form via an internal 10-bit high speed D/A converter. which results in a higher output frequency. This DAC has been optimized for dynamic performance and low glitch energy as manifested in the low jitter performance of the AD9850. The relationship of the output frequency.

A graphical representation of the sampled spectrum. the 5-bit phase modulation word. an FQ_UD pulse is required to update the output frequency (or phase). used for factory test purposes. Basic DDS Block Diagram and Signal Flow of AD9850 AD9850 is a sampled signal. The function assignments of the data and control words are shown in Table III. H –9– . After five loads. The rising edge of FQ_UD loads the (up to) 40-bit control data-word into the device and resets the address pointer to the first register. the device resumes normal operation. a single low-pass filter. The D/A converter output and comparator inputs are available as differential signals that can be flexibly configured in any manner desired to achieve the objectives of the end system. and powering up/down. The user must take deliberate precaution to avoid inputting the codes listed in Table II. Output Spectrum of a Sampled Signal In this example. or close to. and the generation of the comparator reference midpoint from the differential DAC output as shown in Figure 1. The W_CLK and FQ_UD signals are used to address and load the registers. consideration must be given to the relationship of the selected output frequency and the reference clock frequency to avoid unwanted (and unexpected) output anomalies. the detailed timing sequence for updating the output frequency and/or phase. Figure 5. In serial load mode. and thereby avoid generating aliased signals that fall within. subsequent rising edges of W_CLK shift the 1-bit data on Pin 25 (D7) through the 40 bits of programming information. the register is loaded via an 8-bit bus. In fact. the output band of interest (generally dc-selected output frequency). This register can be loaded in a parallel or serial mode. This practice eases the complexity (and cost) of the external filter requirement for the clock generator application. its output spectrum contains the fundamental plus aliased signals (images) that occur at multiples of the reference clock frequency ± the selected output frequency. with aliased images. The typical application of the AD9850 is with single-ended output/ input analog signals. Note: There are specific control codes. In the parallel load mode.AD9850 REF CLOCK DDS CIRCUITRY N PHASE ACCUMULATOR AMPLITUDE/COS CONV. When in this state. Obviously. This shutdown mode prevents excessive current leakage in the dynamic registers of the device. depending on the fo/reference clock relationship. and the power-down function. As can be seen. To apply the AD9850 as a clock generator. the reference clock is 100 MHz and the output frequency is set to 20 MHz. the full 40-bit word requires five iterations of the 8-bit word. is shown in Figure 5. its output spectrum follows the Nyquist sampling theorem. limit the selected output frequency to <33% of reference clock frequency. Subsequent W_CLK rising edges load the 8-bit data on words [7:0] and move the pointer to the next register. After 40 bits are shifted through. resetting the device. The reference clock frequency of the AD9850 has a minimum limitation of 1 MHz. The device has internal circuitry that senses when the minimum clock rate threshold has been exceeded REV. the first aliased image can be on the order of –3 dB below the fundamental. W_CLK edges are ignored until either a reset or an FQ_UD rising edge resets the address pointer to the first register. Programming the AD9850 SIGNAL AMPLITUDE 120MHz 20MHz 80MHz 2ND IMAGE FUNDAMENTAL 1ST IMAGE 100MHz REFERENCE CLOCK FREQUENCY 180MHz 3RD IMAGE 220MHz 4TH IMAGE 280MHz 5TH IMAGE The AD9850 contains a 40-bit register that is used to program the 32-bit frequency control word. if the clock frequency again exceeds the threshold. fOUT sin(x)/x ENVELOPE fc – fo fc + fo fc 2fc – fo 2fc + fo 3fc – fo x=( ␲ )fo/fc and automatically places itself in the power-down mode. the aliased images are very prominent and of a relatively high energy level as determined by the sin(x)/x roll-off of the quantized D/A converter output. Specifically. are shown in the timing diagrams of Figures 6 through 12. that render the AD9850 temporarily inoperable. ALGORITHM D/A CONVERTER LP COMPARATOR CLK OUT TUNING WORD SPECIFIES OUTPUT FREQUENCY AS A FRACTION OF REF CLOCK FREQUENCY IN DIGITAL DOMAIN COS (x) Figure 4. A low-pass filter is generally placed between the output of the D/A converter and the input of the comparator to further suppress the effects of aliased images.

5ns 3.0ns 7. 8-Bit Parallel Load Data/Control Word Functional Assignment Word W0 W1 W2 W3 W4 Data[7] Phase-b4 (MSB) Freq-b31 (MSB) Freq-b23 Freq-b15 Freq-b7 Data[6] Phase-b3 Freq-b30 Freq-b22 Freq-b14 Freq-b6 Data[5] Phase-b2 Freq-b29 Freq-b21 Freq-b13 Freq-b5 Data[4] Phase-b1 Freq-b28 Freq-b20 Freq-b12 Freq-b4 Data[3] Phase-b0 (LSB) Freq-b27 Freq-b19 Freq-b11 Freq-b3 Data[2] Power-Down Freq-b26 Freq-b18 Freq-b10 Freq-b2 Data[1] Control Freq-b25 Freq-b17 Freq-b9 Freq-b1 Data[0] Control Freq-b24 Freq-b16 Freq-b8 Freq-b0 (LSB) –10– REV.0ns 7.AD9850 Table II. W33 = 1 t CD DATA W0* W1 W2 W3 W4 t DS W CLK tDH tWH tWL t FD t FL FQ UD t FH CLKIN tCF COS OUT *OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCK OLD FREQ (PHASE) VALID DATA NEW FREQ (PHASE) SYMBOL tDS tDH tWH tWL tCD tFH tFL tFD tCF DEFINITION DATA SETUP TIME DATA HOLD TIME W CLK HIGH W CLK LOW CLK DELAY AFTER FQ_UD FQ UD HIGH FQ UD LOW FQ UD DELAY AFTER W CLK OUTPUT LATENCY FROM FQ UD FREQUENCY CHANGE PHASE CHANGE MINIMUM 3. W33 = 0 2) W32 = 0. H .5ns 3. Factory Reserved Internal Test Control Codes Loading Format Parallel Serial Factory Reserved Codes 1) W0 = XXXXXX10 2) W0 = XXXXXX01 1) W32 = 1. W33 = 1 3) W32 = 1.0ns 18 CLOCK CYCLES 13 CLOCK CYCLES Figure 6. Parallel Load Frequency/Phase Update Timing Sequence Table III.5ns 3.5ns 3.5ns 7.

5ns 3.5ns 2 CLK CYCLES 5 CLK CYCLES 13 CLK CYCLES RESULTS OF RESET: – FREQUENCY/PHASE REGISTER SET TO 0 – ADDRESS POINTER RESET TO W0 – POWER-DOWN BIT RESET TO 0 – DATA INPUT REGISTER UNEFFECTED Figure 7. H –11– . Parallel Load Power-Down Sequence/Internal Operation DATA (W0) XXXXX000 W CLK FQ UD CLKIN INTERNAL CLOCKS ENABLED Figure 9. Parallel Load Power-Up Sequence/Internal Operation REV.AD9850 CLKIN tRH RESET tRL tRR tRS tOL COS OUT COS (0) NOTE: THE TIMING DIAGRAM ABOVE SHOWS THE MINIMAL AMOUNT OF RESET TIME NEEDED BEFORE WRITING TO THE DEVICE. THE MASTER RESET DOES NOT HAVE TO BE SYNCHRONOUS WITH THE CLKIN IF THE MINIMAL TIME IS NOT REQUIRED. Master Reset Timing Sequence DATA (W0) XXXXX100 W CLK FQ UD CLKIN DAC STROBE INTERNAL CLOCKS DISABLED Figure 8. HOWEVER. SYMBOL tRH tRL tRR tRS tOL DEFINITION CLK DELAY AFTER RESET RISING EDGE RESET FALLING EDGE AFTER CLK RECOVERY FROM RESET MINIMUM RESET WIDTH RESET OUTPUT LATENCY MINIMUM 3.

Serial Load Enable Sequence 2 +V SUPPLY 3 4 AD9850BRS Figure 11. H . Figure 10.AD9850 DATA (W0) (PARALLEL) DATA (SERIAL) REQUIRED TO RESET CONTROL REGISTERS XXXXX011 W32 = 0 W33 = 0 NOTE: W32 AND W33 SHOULD ALWAYS BE SET TO 0. HARDWIRE PIN 2 AT 0. W CLK FQ UD ENABLE SERIAL MODE LOAD 40-BIT SERIAL WORD NOTE: FOR DEVICE START-UP IN SERIAL MODE. PIN 3 AT 1. Pins 2 to 4 Connection for Default Serial Mode Operation DATA – W0 W1 W2 W3 W39 FQ UD W CLK 40 W CLK CYCLES Figure 12. 40-Bit Serial Load Word Function Assignment W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 Freq-b0 (LSB) Freq-b1 Freq-b2 Freq-b3 Freq-b4 Freq-b5 Freq-b6 Freq-b7 Freq-b8 Freq-b9 Freq-b10 Freq-b11 Freq-b12 Freq-b13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 Freq-b14 Freq-b15 Freq-b16 Freq-b17 Freq-b18 Freq-b19 Freq-b20 Freq-b21 Freq-b22 Freq-b23 Freq-b24 Freq-b25 Freq-b26 Freq-b27 W28 W29 W30 W31 W32 W33 W34 W35 W36 W37 W38 W39 Freq-b28 Freq-b29 Freq-b30 Freq-b31 (MSB) Control Control Power-Down Phase-b0 (LSB) Phase-b1 Phase-b2 Phase-b3 Phase-b4 (MSB) –12– REV. AND PIN 4 AT 1 (SEE FIGURE 11). Serial Load Frequency/Phase Update Sequence Table IV.

applications engineering support is available to answer additional questions on grounding and PCB layout. ideally right up against the device. Fast switching signals like clocks should be shielded with ground to avoid radiating noise to other sections of the board. the internal comparator on the AD9850 DUT is not enabled (see Figure 15 for an electrical schematic of AD9850/FSPCB). Evaluation Boards Two versions of evaluation boards are available for the AD9850. It connects the AD9850’s DAC output to the internal comparator input via a single-ended. It is recommended that the top layer of the multilayer board also contain an interspatial ground plane. If separate analog and digital system ground planes exist. REV. Avoid running digital lines under the device because these couple noise onto the die. they should be placed as close as possible to the device. Good decoupling is also an important consideration. remove R2. The AD9850/CGPCB is used in applications using the device in the clock generator mode. The evaluation board can be operated with 3.analog. Use microstrip techniques where possible. which facilitate the implementation of the device for benchtop analysis and serve as a reference for PCB layout. Traces on opposite sides of the board should run at right angles to each other. Both versions of the AD9850 evaluation board are designed to interface to the parallel printer port of a PC. Inc.3 V or 5 V supplies. All analog and digital supplies should be decoupled to AGND and DGND. AD9850 I/O Equivalent Circuits PCB LAYOUT INFORMATION The AD9850/CGPCB and AD9850/FSPCB evaluation boards (Figures 15 through 18) represent typical implementations of the AD9850 and exemplify the use of high frequency/high resolution design and layout practices. The operating software runs under Microsoft® Windows® and provides a userfriendly and intuitive format for controlling the functionality and observing the performance of the device. This reduces the effects of feedthrough through the circuit board. The power and ground planes should be free of etched traces that cause discontinuities in the planes. Call 1-800-ANALOGD or contact us at www. 5-pole elliptical filter. This version facilitates connection of the AD9850’s internal D/A converter output to a 50 Ω spectrum analyzer input. To achieve best performance from the decoupling capacitors. In systems where a common supply is used to drive both the AVDD and DVDD supplies of the AD9850. The evaluation boards are configured at the factory for an external reference clock input. it is recommended that the system’s AVDD supply be used. Avoid crossover of digital and analog signal paths. respectively. which makes ground available for surface-mount devices.com/dds. The power supply lines to the AD9850 should use as large a track as possible to provide a low impedance path and reduce the effects of glitches on the power supply line. The analog (AVDD) and digital (DVDD) supplies to the AD9850 are independent and separately pinned out to minimize coupling between analog and digital sections of the device.5 inch floppy provided with the evaluation board contains an executable file that loads and displays the AD9850 function-selection screen. they should be connected together at the AD9850 for optimum results. if the on-board crystal clock source is used.AD9850 DATA (7) – W32 = 0 W33 = 0 W34 = 1 W35 = X W36 = X W37 = X W38 = X W39 = X FQ UD W CLK Figure 13. The 3. 42 MHz low-pass. The printed circuit board that contains the AD9850 should be a multilayer board that allows dedicated power and ground planes. with high quality ceramic capacitors. Serial Load Power-Down Sequence VCC VCC VCC VCC QOUT/ QOUTB VINP/ VINN DIGITAL IN IOUT IOUTB DAC Output Comparator Output Comparator Input Digital Inputs Figure 14. Analog Devices. This model facilitates the access of the AD9850’s comparator output for evaluation of the device as a frequency. H –13– . The AD9850/FSPCB is used in applications where the device is used primarily as a frequency synthesizer.and phase-agile clock source (see Figure 17 for an electrical schematic of AD9850/CGPCB).

3.EXE and execute that program. and 7 of U3 to 5 V. and E5 to E6 connects the on-board filter and the midpoint switching voltage to the comparator. fifth-order. Locate the file called 9850REV2. Remove R2 for high Z clock input. 4. the AD9850 output should be active and outputting the user's frequency information. The unmarked hole next to each labeled test point is a ground connection. Upon completion of this step. The AD9850/CGPCB provides BNC inputs and outputs associated with the on-chip comparator and the on-board. –14– REV. If they have trouble getting their computer to recognize any printer port. The AD9850 may be powered with 3. Click the LOAD button or press enter on the keyboard. The two active inputs are labeled TP1 and TP2. 5. Other operational modes (frequency sweeping.5 inch floppy drive. Move the cursor to the OUTPUT FREQUENCY box and type in the desired output frequency (in MHz). dc offset the signal to one-half the supply voltage and apply at least 3 V p-p signal across the 50 Ω (R2) input resistor. A message will appear telling users if their choice of output ports is correct. 6. 45 MHz. The BUS MONITOR section of the control panel will show the 32-bit word that was loaded into the AD9850. serial input) are available to the user via keyboard/mouse control. • XTAL clock or signal generator—if using a signal generator. If users choose to use the XTAL socket to supply the clock to the AD9850. Changing the output phase is accomplished by clicking on the down arrow in the OUTPUT PHASE DELAY box to make a selection and then clicking the LOAD button.3 V to 5 V. Connect the printer cable from your computer to the AD9850 evaluation board.AD9850 AD9850 Evaluation Board Instructions Required Hardware/Software • IBM compatible computer operating in a Windows environment. they must remove R2 (a 50 Ω chip resistor). 8. • 5 V voltage supply. H . Monitor should display a control panel to allow operation of the AD9850 evaluation board. If troubles persist. The two active outputs are labeled TP5 and TP6. The output should be a dc voltage equal to the full-scale output of the AD9850. Unmarked ground connections are adjacent to each of these test points. try a different printer cable. sleep. E3 to E4. they should try the following: connect three 2 kΩ pull-up resistors from Pins 9. Point to and click the selection marked LPT1 and then point to the TEST box and click. Copy the contents of the AD9850 disk onto your hard drive (there are three files). Apply power to AD9850 evaluation board. Choose other ports as necessary to achieve a correct setting. locate the box called COMPUTER I/O. The crystal oscillator must be either TTL or CMOS (preferably) compatible. 1. • AD9850 evaluation board software disk and AD9850/FSPCB or AD9850/CGPCB evaluation board. elliptic. Connect external 50 Ω clock or remove R2 and apply a high Z input clock such as a crystal can oscillator. 2. Jumpering (soldering a wire) E1 to E2. • Printer port. 0° phase. Operation On the control panel. This will reset the AD9850 to 0 Hz. The AD9850/FSPCB provides access into and out of the on-chip comparator via test point pairs (each pair has an active input and a ground connection). and Centronics compatible printer cable. This will assist weak printer port outputs in driving the heavy capacitance load of the printer cable. Users may elect to insert their own filter and comparator threshold voltage by removing the jumpers and inserting a filter between J7 and J6 and then providing a threshold voltage at E1. Click the LOAD button or press the enter key. 200 Ω input/output Z. Setup Locate the CLOCK box and place the cursor in the frequency box. Locate the MASTER RESET button with the mouse and click it. low-pass filter. 3. The AD9850 is powered separately from the connector marked DUT +V. Type in the clock frequency (in MHz) that the user will be applying to the AD9850.

2k⍀ R3 2. 6 No.2k⍀ +V 5V RRESET FFQUD WWCLK STROBE Figure 15. R10 R5 R6. J6 REV.1␮F C10 0.1␮F C8 0. R4 R3. J4 J5. 6 D3 1 D3 2 D2 3 D1 4 D0 BANANA J3 JACKS J4 5V GND D4 28 D4 D5 27 D5 D2 D1 D0 MOUNTING HOLES U1 D6 AD9850 26 D6 D7 25 D7 DGND 24 GND DVDD 23 +V RESET 22 RESET IOUT 21 IOUTB 20 AGND 19 GND AVDD 18 DACBL 17 VINP 16 VINN 15 GND GND R6 1k⍀ J5 +V R7 1k⍀ GND TP1 +V R5 25⍀ R4 50⍀ GND 5 DGND +V WCLK 6 DVDD 7 J6 DAC OUT TO 50⍀ W CLK FQ UD CLKIN FQUD 8 CLKIN 9 CLK OE GND 10 AGND +V 11 AVDD 12 RSET 13 QOUTB TP5 14 QOUT TP2 COMPARATOR TP3 INPUTS TP4 COMPARATOR TP6 OUTPUTS TP7 U3 74HCT574 8D 7D 6D 5D 4D 3D 2D 1D CLK 11 STROBE 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE 1 12 13 14 15 16 17 18 19 RESET WCLK FQUD CHECK TP8 GND GND CLKIN REMOVE WHEN USING Y1 +5V 14 R2 50⍀ XTAL OSC VCC Y1 GND 7 OUT 8 5V R10 2. AD9850/FSPCB Electrical Schematic COMPONENT LIST Integrated Circuits U1 U2. U3 Capacitors AD9850BRS (28-Lead SSOP) 74HCT574 H-CMOS Octal Flip-Flop 0.1␮F C5 0.1␮F C4 0.1␮F C3 0. R8. R7 Connectors J1 J2.9k⍀ RRESET 9 8 7 6 5 4 3 2 U2 74HCT574 8D 7D 6D 5D 4D 3D 2D 1D 11 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 1 12 13 14 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 J2 +V H1 H2 H3 H4 No.1␮F C9 0. 6 No. R9.2k⍀ R8 2.AD9850 C36CRPX J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P O R T 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 STROBE +V C6 10␮F 5V C7 10␮F C2 0.2k⍀ R9 2. C8 to C10 C6.9 kΩ Resistor 50 Ω Resistor 2. 6 No. J3.1␮F WWCLK CHECK RRESET WWCLK FFQUD RRESET 9 8 7 6 5 4 3 2 FFQUD STROBE 10mA RSET R1 3.1 µF Ceramic Chip Capacitor 10 µF Tantalum Chip Capacitor 3.2 kΩ Resistor 25 Ω Resistor 1 kΩ Resistor 36-Pin D Connector Banana Jack BNC Connector C2 to C5. H –15– . C7 Resistors R1 R2.

H . AD9850/FSPCB Bottom Layer Figure 16. AD9850/FSPCB Ground Plane 16d. AD9850/FSPCB Evaluation Board Layout –16– REV. AD9850/FSPCB Top Layer 16c. AD9850/FSPCB Power Plane 16b.AD9850 16a.

R11 R4. U3 Capacitors AD9850BRS (28-Lead SSOP) 74HCT574 H-CMOS Octal Flip-Flop 470 pF Ceramic Chip Capacitor 0. J3.1␮F C9 0.1␮F C5 0.2k⍀ R10 2.3 pF Ceramic Chip Capacitor 33 pF Ceramic Chip Capacitor 8.3pF L2 1008CS 680nH 1 2 C14 8. 6 No.2k⍀ REMOVE WHEN USING Y1 5V 14 R2 50⍀ GND +V J6 R8 100⍀ R7 200⍀ U3 74HCT574 8D 7D 6D 5D 4D 3D 2D 1D CLK 11 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE 1 12 13 14 15 16 17 18 19 +V RESET WCLK FQUD CHECK RRESET FFQUD WWCLK STROBE XTAL OSC VCC Y1 GND 7 OUT 8 +V 5V C6 10␮F C7 10␮F C2 0.2k⍀ R11 2. 6 No.1␮F 5V C8 0.1␮F C10 0. R7 R8 Connectors 3.2 kΩ Resistor 100 kΩ Resistor 200 Ω Resistor 100 Ω Resistor Banana Jack BNC Connector 910 nH Surface Mount 680 nH Surface Mount J2. R10.2k⍀ R3 2. C8 to C10 C6.9 kΩ Resistor 50 Ω Resistor 2.9k⍀ +V 11 12 13 14 D3 D2 D1 D0 DGND DVDD U1 D6 AD9850 26 D6 E6 J7 BNC E5 D7 25 D7 DGND 24 GND DVDD 23 +V R4 100k⍀ R5 100k⍀ R6 200⍀ C11 22pF W CLK RESET 22 RESET FQ UD CLKIN AGND AVDD RSET QOUTB QOUT IOUT 21 IOUTB 20 AGND 19 AVDD 18 DACBL 17 VINP 16 VINN 15 C1 470pF E1 E2 E4 E3 J5 5V CLKIN R9 2.AD9850 C36CRPX J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 P O 18 R T 19 20 1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 STROBE STROBE WWCLK CHECK RRESET WWCLK FFQUD RRESET 9 8 7 6 5 4 3 2 FFQUD 10mA RSET BNC J8 BNC J9 STROBE RRESET J2 +V U2 74HCT574 9 8 7 6 5 4 3 2 8D 7D 6D 5D 4D 3D 2D 1D CLK 11 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE 1 12 13 14 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 BANANA J3 JACKS J4 5V GND H1 H2 H3 H4 No.1␮F C4 0.2 pF Ceramic Chip Capacitor 22 pF Ceramic Chip Capacitor C1 C2 to C5.1 µF Ceramic Chip Capacitor 10 µF Tantalum Chip Capacitor 22 pF Ceramic Chip Capacitor 3. 6 MOUNTING HOLES D4 28 D4 D5 27 D5 200⍀ Z 42MHz ELLIPTIC LOW-PASS FILTER L1 1008CS 910nH 1 2 C12 3.1␮F C3 0. AD9850/CGPCB Electrical Schematic COMPONENT LIST Integrated Circuits Resistors U1 U2. C7 C11 C12 C13 C14 C15 R1 R2 R3.1␮F Figure 17. H –17– . 6 No. R5 R6. J4 J5 to J9 Inductors L1 L2 REV.2pF C13 33pF C15 22pF D3 1 D2 2 D1 3 D0 4 GND 5 +V 6 WCLK 7 FQUD 8 CLKIN 9 GND 10 R1 3. R9.

AD9850 18a. AD9850/CGPCB Top Layer 18c. AD9850/CGPCB Bottom Layer Figure 18. AD9850/CGPCB Evaluation Board Layout –18– REV. AD9850/CGPCB Power Plane 18b. H . AD9850/CGPCB Ground Plane 18d.

80 7.65 BSC 0.50 10.75 1. H –19– .95 0.65 0.60 5.25 0.10 COPLANARITY 0.75 0.40 2.00 MAX 1.22 SEATING PLANE 8؇ 4؇ 0؇ 0.20 7.05 MIN 0.85 1.55 COMPLIANT TO JEDEC STANDARDS MO-150AH REV.20 9.00 1 14 8.90 28 15 5.AD9850 OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.09 0.30 5.38 0.

. . . . . . . . . . . . . . . . . . . . H. . . . .Universal Changes to SPECIFICATIONS . . . . . . . . . . . . . H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11/03—Data Sheet changed from REV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 –20– REV. . . . F. . . . . . . . . . . . . . 3 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated ORDERING GUIDE . . . . . . . . . . . Renumbered figures and TPCs . . . . . G to REV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C00632–0–2/04(H) 12/03—Data Sheet changed from REV. . . . . . . . . . . . . . . . . . . . G. . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . Page Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . .AD9850 Revision History Location 2/04—Data Sheet changed from REV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E to REV. . . . F to REV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to Table I . . . . . . . . . . . . . . 4 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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