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**The given nonrecursive signal processing structure is shown as
**

X1(n) D D D D

a1

a2

a3

a4

a5

0

Y(n)

b1

b2

b3

b4

b5

X2(n)

D

D

D

D

There are two critical paths, one from X1(n) to Y(n) and the other from X2(n) to Y(n). The iteration along such a path is given by Tsample = Tm +5 Ta We can reduce this time period by dividing the whole circuit into two parts as below and using transposition on each part. Transposing part 1 yields

X1(n)

a5

a4

a3

a2

a1

0

D

D

D

D

Y(n)

**Thus equivalent broadcast structure is given by
**

X1(n)

a5

a4

a3

a2

a1

0

D

D

D

D

Y(n)

b5

b4

b3

b2

b1

X2(n)

The iteration period for this broadcast circuit is Tsample =Tm + Ta

Number of samples processed per second (throughput) is given by 1/ (Tm + Ta). Block architecture for the circuit 6th-order FIR filter of block size of 3 using parallel processing is given by equations y(3k) = ax(3k) +bx(3k-4)+cx(3k-6) y(3k+1) = ax(3k+1) +bx(3k-3)+cx(3k-5) y(3k+2) = ax(3k+2) +bx(3k-2)+cx(3k-4) .The iteration along critical path is given by Tsample = Tm +2 Ta To limit the clock period by one multiply-add time we use transposition on the circuit above and get the new circuit as x(n) c b a 4D 2D y(n) The new time period of each output sample for the new transposed circuit is given by Tsample = Tm + Ta 7(b) . 7. (a) The 6th-order FIR filter is given by y(n)= ax(n) + bx(n-4) +cx(n-6) This circuit is represented in block diagram by x(n) 4D 2D a b c y(n) There are two critical paths from x(n) to y(n) .

x(3k+2) x(3k+1) x(3k) a c b 2D y(3k) D b 2D c a y(3k+1) D 2D b c a y(3k+1) Given that Tm = 3Ta Rearranging the pipelined parallel filter structure such that the clock period is one-fourth of a multiply-add time is given by .

in which the multiplier has been broken into three parts m1. m2 and m3. . The pipelining latches are placed along the feed forward cutsets shown by dotted lines. Each part has the same computation time as addition computation.x(3k+2) x(3k+1) x(3k) b c a 2D y(3k-9) c b a D D y(3k-8) c b a D D y(3k-7) The above structure shows the pipelined parallel filter structure.

The given recursive filter is x(n) = ax(n-2) + u(n) The circuit above is given by a 2D u(n) x(n) Breaking up the multiply-add operation into 2 components is done by using two Multiply Add Components (MAC) which is given by the figure u(n) MAC Output = u(n) + aZ a Z In our circuit MAC is represented by u(n) MAC x(n-2) a 2D x(n) x(n) = ax(n-2) + u(n) Redistributing the delay elements in the loop is given by 0 u(n) MAC1 D MAC2 x(n) x(n-1) D u(n) .8(a).

These idle cycles are used to operate v(n)... There appears an idle cycle in every two cycles.8(b).. From (1) and (1a) we get β2 <=1/5 => β =√5 =0.u1(n) MAC x1(n).b 4D Time Input Output 1 u1 x1 2 v1 y1 3 u2 x2 4 v2 y2 5 u3 x3 6 v3 y3 7 u4 x4 8 v4 y4 9 v5 x5 …….4 V Initial Voltage supply Vo = 5 V Let the level of pipelining be M Let β is the voltage reduction factor i.u2(n). ……..e.v1(n). The given equation is y(n) = by(n-2) + v(n) First slow down the circuit by replacing the 2-delay with a 4-delay and then interleave the two computations.x2(n). .v2(n). Given that Threshold voltage Vt = 0.… …….. supply voltage can be reduced to βVo for the pipelined system..y1(n).y2(n).447 . a. Pipelining the multiply-add operation by 4 stages we get u(n) MAC1 x(n) D 0 MAC2 MAC3 0 D 0 MAC4 D D 9.x3(n)……….

0.427. Tcritical =4Ta For filter(b).4) 2 ┐ (0.5 V.Vt )2 (βVo . Vt & β and solving for M we get M= ┌ 0.8 ┐ = 3 Therefore.34% 42 .2.4) 2 =┌ 2. we have: 36(Vb)2 .447(5. The supply voltage for pipelined system is βVo = 0.Vt )2 Using the values of Vo. Substitute M=3 into (3.11 Volt-------discarded Compare to filter(a) .14 Volts.447 * 5 -0.85Vb + 9 Vb1 Vb2 =0 =2.9) and solve for β =0.Vt ) k(Vb . Given that As required.25 Volt =0.Suppose that the pipelined system and the original system have the same sample rate. filter (a) and filter (b) have equal clock period.the ratio of power saved by filter (b) is 1.(Vb)2 (Va) = 1. we have M= β (Vo . 10.252 = 68.427* 5 V = 2. Ccharge(a) Ccharge(b) = Propagation delay of circuit A(Tcritical(a)) Propagation delay of circuit B (Tcritical(b)) = Vb * (Va-Vt)2 Va * (Vb-Vt)2 Substitute the values of Va = 4 V and Vt = 0. the system should be pipelined at 3 level.Vt )2 From the filter structure we know Tcritical =9Ta for filter (a). therefore: Ccharge(a)Va = Ccharge(b)Vb 2 k(Va .

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