Circuits VLSI Conception d’un multiplieur de Booth 16× 16 et son int´ egration dans un microprocesseur

5 d´ ecembre 2013

´ S. JOVANOVIC
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Table des mati` eres

Table des mati` eres
1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . Multiplieur de Booth . . . . . . . . . . . . . . . 1.1.1 Introduction . . . . . . . . . . . . . . . . 1.1.2 L’encodage de Booth Radix-4 . . . . . . 1.1.3 Multiplieur de Booth : architecture . . . Processeur MIPS . . . . . . . . . . . . . . . . . 1.2.1 L’encodage d’instruction . . . . . . . . . 1.2.2 Architecture du processeur . . . . . . . . 1.2.3 Exemple de code . . . . . . . . . . . . . 1.2.4 Contenu de la m´ emoire et son d´ ecodage . 1.2.5 Code VHDL [WH10] . . . . . . . . . . . V´ erification du syst` eme . . . . . . . . . . . . . . R´ ef´ erences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 4 5 6 6 8 11 12 13 25 25

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Universit´ e de Lorraine

2

Master 2 I2E2I

on utilisera les outils Cadence et Mentor Graphics dont la prise en main a fait partie du premier TP. Le chemin de donn´ ees est bas´ e sur une architecture de Von Neuman utilisant un bus de donn´ ee d’une taille de 8 bits.DSP (Digital Signal Processor ) sous forme logicielle ou dans des circuits int´ egr´ es (ASIC ou reconfigurables de type FPGA) sous forme mat´ erielle. Dans la premi` ere phase.35µm. L’objectif principal de ce projet est de concevoir un multiplieur 16 × 16 utilisant le codage de Booth de type Radix-4 et de l’int´ egrer dans un microprocesseur. Dans la deuxi` eme phase. Dans le travail demand´ e. valid´ e et test´ e en tant qu’une unit´ e ind´ ependante au niveau comportemental/structurel en utilisant le langage de description VHDL et ensuite int´ egr´ e dans le microprocesseur mis a ` disposition. Ces recherches visent a ` am´ eliorer des performances temporelles des ´ el´ ements a ` int´ egrer ainsi qu’` a diminuer la surface de silicium occup´ ee (pour r´ eduire le coˆ ut de fabrication). Pour pouvoir int´ egrer le multiplieur 16 × 16 dans le chemin de donn´ ees propos´ e. L’´ etudiant aura a ` disposition le code VHDL d´ ecrivant une architecture simplifi´ ee d’un microprocesseur 8 bits de type MIPS. l’addition et la multiplication sont des op´ erateurs indispensables. Ce recodage permet de transformer une s´ erie de 1 par des 0 en se basant sur l’identit´ e suivante : 2i + 2i+1 + 2i+2 + · · · + 2i+k = 2i+k+1 − 2i (1) Universit´ e de Lorraine 3 Master 2 I2E2I . toute la documentation permettant de comprendre son fonctionnement et un exemple de code machine avec son ´ equivalent en assembleur montrant son fonctionnement sur un cas concret. convolutions. plusieurs algorithmes d’addition et de multiplication ont ´ et´ e´ etudi´ es et impl´ ement´ es sous plusieurs formes : dans des processeurs de calcul sp´ ecialis´ e . le multiplieur a ` concevoir devra ˆ etre dans un premier temps d´ ecrit. Les nombres ` a traiter sont cod´ es en compl´ ement a ` 2.1 1. Ce projet est r´ eparti en deux phases. L’´ evolution des technologies de l’int´ egration des circuits ´ electroniques a fait que les recherches dans le domaine architectural se font de plus en plus pouss´ ees. le syst` eme complet (le microprocesseur et le multiplieur ) d´ evelopp´ e et test´ e dans la premi` ere phase devra ˆ etre impl´ ement´ e en tant qu’un ASIC dans la technologie AMS 0.1 Multiplieur de Booth Introduction Le principe du codage de Booth est de r´ eduire de moiti´ e le nombre de produits partiels en analysant des groupes de bits du multiplicande. filtrage ou analyse fr´ equentielle). Ce document concerne une ´ etude architecturale d’un type de multiplieurs et son int´ egration dans un microprocesseur. 1.1 Introduction Dans plusieurs traitement de signaux discrets (corr´ elations.1. l’´ etudiant sera amen´ ea ` faire une adaptation de taille de donn´ ee sans modifier le multiplier. De ce fait.

+2} (3) n −1 2 P =A·B = i=0 (a2i−1 + a2i − 2a2i+1 ) 22i ·B {−2. o` u a− 1 = 0 {−2.+1. 1: La table d’encodage de produits partiels pour l’algorithme Booth Radix-4 n −1 2 A= i=0 (a2i−1 + a2i − 2a2i+1 ) 22i . Les op´ erandes sont cod´ es en compl´ ement ` a 2.−1.0.−1.+2} A n −1 2 = i=0 n −1 2 (a2i−1 + a2i − 2a2i+1 ) · B ·22i {−2B. Universit´ e de Lorraine 4 Master 2 I2E2I .+B.+1.0. 0 et -1 (not´ e 1).2 L’encodage de Booth Radix-4 a2i+1 0 0 0 0 1 1 1 1 a2i 0 0 1 1 0 0 1 1 a2i−1 0 1 0 1 0 1 0 1 Pi 0 +B +B +2B -2B -B -B 0 (2) Tab.1 Multiplieur de Booth En utilisant les chiffres 1.−B.1.+2B } (4) = i=0 Pi · 22i Quelques exemples de multiplication avec l’encodage de Booth sont pr´ esent´ es ci-dessous. on peut remplacer une suite de zero ou de 1 dans un nombre binaire comme suit : 0111110001101011 = 1000010010111101 1.0.1.

1: Sch´ ema synoptique d’un multiplieur de Booth Universit´ e de Lorraine 5 Master 2 I2E2I .1. un n´ egatif 1101 ∗0111(0) 00000011 111010 11101011 multiplicande B multiplicateur A = (a3 a2 a1 a0 ) a1 a0 a−1 = 110 → −B a3 a2 a1 = 011 → +2B R´ esultat S = A · B = (−3)10 · 710 = (−21)10 (6) Example 3 : 2 entiers n´ egatifs 1101 ∗1001(0) 11111101 000110 (1)00010101 1.1.1 Multiplieur de Booth Example 1 : 2 entiers positifs 0111 ∗0011(0) 11111001 0111 (1)00010101 multiplicande B multiplicateur A = (a3 a2 a1 a0 ) a1 a0 a−1 = 110 → −B a3 a2 a1 = 001 → +B R´ esultat S = A · B = 710 · 310 = 2110 (5) Example 2 : un entier positif.3 multiplicande B multiplicateur A = (a3 a2 a1 a0 ) a1 a0 a−1 = 010 → B a3 a2 a1 = 100 → −2B R´ esultat S = A · B = (−3)10 · (−7)10 = (21)10 (7) Multiplieur de Booth : architecture B X X A Encodage de Booth X Matrice/arbre CSA Additionneur CPA Fig.

inversion du B. g´ en` ere des signaux de contrˆ ole d´ efinissant le type d’op´ eration ` a effectuer sur le multiplicande B (pas d’op´ eration sur B. C 4 B 4 A 4 C 3 B 3 A 3 C 2 B 2 A 2 C 1 B 1 A 1 C 0 B 0 A 0 B Cout A B Cout A B Cout A B Cout A B Cout A FA S Cin FA S Cin FA S Cin FA S Cin FA S Cin D B Cout A 4 D B Cout A 3 D B Cout A 2 D B Cout 1 D B Cout A 0 A FA S Cin FA S Cin FA S Cin FA S Cin FA S Cin 0 CPA B Cout A B Cout A B Cout A B Cout A B Cout A FA S Cin FA S Cin FA S Cin FA S Cin FA S Cin 0 S 5 S 4 S 3 S 2 S 1 S 0 Fig.2 1. 2: Un arbre CSA utilis´ e pour l’addition de 4 op´ erandes de 5 bits 1. l’arbre CSA pour la somme des produits partiels et un additionneur a ` propagation de retenue pour calculer le r´ esultat final. d´ ecalage du B. il existe 3 types d’instruction (figure 3)[WH10] : — Les instructions de type R qui sont utilis´ ees pour les op´ erations arithm´ etiques et n’utilisant que des registres internes du processeur (2 registres de source et un de destination) — Les instructions de type I utilisant 2 registres du processeur et un op´ erande (immediate ) de 16 bits stock´ e dans la m´ emoire et Universit´ e de Lorraine 6 Master 2 I2E2I .2. Un arbre CSA avec un additionneur CPA en dernier ´ etage pour une addition de 4 op´ erandes de 5 bits est pr´ esent´ e sur la figure 2. les blocs de calcul de produits partiels. L’arbre CSA (Carry Save Adder) est une architecture couramment utilis´ ee pour additionner plusieurs op´ erandes en mˆ eme temps.1.1 Processeur MIPS L’encodage d’instruction Dans le microprocesseur pr´ esent´ e.2 Processeur MIPS Le sch´ ema synoptique de l’architecture d’un multiplieur de Booth est pr´ esent´ e sur la figure 1. inversion et d´ ecalage du B). en fonction des valeurs de bits du multiplicateur A. Les ´ el´ ements principaux sont : le bloc pour l’encodage de Booth qui.

1. 3: L’encodage d’instruction [WH10] Le jeu d’instruction de ce microprocesseur est pr´ esent´ e dans la figure 4. 4: Jeu d’instruction [WH10] Universit´ e de Lorraine 7 Master 2 I2E2I . Fig.2 Processeur MIPS — Les instructions de type J utilis´ ees pour les instructions de branchement sur une adresse cod´ ee sur 26 bits. Fig.

2 Processeur MIPS 1. 5: Le sch´ ema synoptique du processeur [WH10] Fig.2. La connexion entre le microprocesseur et la m´ emoire est pr´ esent´ ee sur la figure 6 tandis que la machine d’´ etat du microprocesseur est pr´ esent´ ee sur la figure 8. La figure 9 d´ etaille les modes de fonctionnement de l’unit´ e ALU.2 Architecture du processeur Les figures 5 et 7 pr´ esentent respectivement les sch´ emas synoptique et d´ etaill´ e du microprocesseur. Fig.1. 6: Le sch´ ema de liaison entre le microprocesseur et la m´ emoire [WH10] Universit´ e de Lorraine 8 Master 2 I2E2I .

2 Processeur MIPS Fig.1. 7: Le sch´ ema d´ etaill´ e du processeur [WH10] Universit´ e de Lorraine 9 Master 2 I2E2I .

2 Processeur MIPS Fig.1. 8: La machin´ e d’´ etats du processeur [WH10] Universit´ e de Lorraine 10 Master 2 I2E2I .

10: Le code C pour le programme calculant la suite de Fibonacci [WH10] Universit´ e de Lorraine 11 Master 2 I2E2I .1. assembleur et son ´ equivalent en code machine sont pr´ esent´ es dans les figures 10.3 Exemple de code Un exemple de programme en C. 11 et 12.2. 9: Les signaux de contrˆ ole de l’ALU [WH10] 1. Fig.2 Processeur MIPS Fig.

12: Le langage machine pour le programme calculant la suite de Fibonacci [WH10] 1. a ` l’adresse 1 est R1 .2 Processeur MIPS Fig. La figure 14 d´ etaille le d´ ebut de d´ ecodage de la m´ emoire en consid´ erant que le registre a ` l’adresse 0 est R0 .1.2.4 Contenu de la m´ emoire et son d´ ecodage Le contenu de la m´ emoire est pr´ esent´ e dans la figure 13. 11: Le code assembleur pour le programme calculant la suite de Fibonacci [WH10] Fig. A compl´ eter cette liste. etc. Universit´ e de Lorraine 12 Master 2 I2E2I .

all.Top design (testbench) -----------------------------------------------------------------------library IEEE. ← R2 OR R7 = 716 . . .and 3 bit register addresses (8 regs) end. writedata: out integer := 8. .vhd -.2. ← 516 . STD_LOGIC.default 8-bit datapath regbits: integer := 3). 14: D´ ecodage du contenu de la m´ emoire du microprocesseur 1. ← 316 . -. use IEEE. architecture test of top is component mips generic(width: regbits: port(clk. STD_LOGIC_VECTOR(width-1 downto 0)). ← C16 . -.2 Processeur MIPS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 80020044 80070040 80e30045 00e22025 00642824 00a42820 10a70008 0064302a 10c00001 80050000 00e2302a 00c53820 00e23822 0800000f 80070000 a0470047 00000003 00000005 0000000c Fig.1. memwrite: out adr.Model of subset of MIPS processor described in Ch 1 --------------------------------------------------------------------------------------------------------------------------------. entity top is -. Fig.default 8-bit datapath integer := 3).STD_LOGIC_1164. use IEEE. -. R2 R7 R3 R4 R5 .STD_LOGIC_UNSIGNED. reset: in memdata: in memread.David_Harris@hmc.and 3 bit register addresses (8 regs) STD_LOGIC. 13: Contenu de la m´ emoire du microprocesseur 1 2 3 4 5 . STD_LOGIC_VECTOR(width-1 downto 0).mips. ← R3 AND R4 = 416 . -.edu 9/9/03 -.all. Universit´ e de Lorraine 13 Master 2 I2E2I .5 Code VHDL [WH10] ---------------------------------------------------------. .top-level design for testing generic(width: integer := 8.

-. end if. regbits) port map(clk.check that 7 gets written to address 76 at end of program process (clk) begin if (clk’event and clk = ’0’ and memwrite = ’1’) then if (conv_integer(adr) = 76 and conv_integer(writedata) = 7) then report "Simulation completed successfully".Generate reset for first two clock cycles process begin reset <= ’1’. wait for 5 ns. -.2 Processeur MIPS end component. component memory generic(width: integer). wait for 5 ns.all. memdata). use IEEE. end process.STD_LOGIC_ARITH. memwrite.all. memwrite: in STD_LOGIC. port(clk. reset <= ’0’. writedata. Universit´ e de Lorraine 14 Master 2 I2E2I . clk <= ’0’. use IEEE. end. writedata: in STD_LOGIC_VECTOR(width-1 downto 0).". memdata: out STD_LOGIC_VECTOR(width-1 downto 0)). writedata). adr. end process. end component. signal memdata. reset. end. reset.all. memread. else report "Simulation failed.external memory accessed by MIPS generic(width: integer). entity memory is -. memdata.STD_LOGIC_UNSIGNED.TEXTIO. -. memread.1. adr. signal clk.STD_LOGIC_1164. adr. -.Memory ---------------------------------------------------------------------------------------- library IEEE. memwrite. writedata: in STD_LOGIC_VECTOR(width-1 downto 0). wait for 22 ns. ------------------------------------------------------------------------.external memory for code and data exmem: memory generic map(width) port map(clk. begin -.Generate clock with 10 ns period process begin clk <= ’1’.mips being tested dut: mips generic map(width. memdata: out STD_LOGIC_VECTOR(width-1 downto 0)). adr. use STD. memwrite: in STD_LOGIC. writedata: STD_LOGIC_VECTOR(width-1 downto 0).all. use IEEE.End of Top design (testbench) ----------------------------------------------------------------- ------------------------------------------------------------------------. port(clk. end process. memwrite: STD_LOGIC. wait. end if. adr.

End of Memory --------------------------------------------------------------------------------- ------------------------------------------------------------------------. end if. end process. type ramtype is array (255 downto 0) of STD_LOGIC_VECTOR(7 downto 0).set all contents low mem(conv_integer(i)) := "00000000".1. end loop.initialize memory from file -.MIPS ------------------------------------------------------------------------------------------ library IEEE.all. while not endfile(mem_file) loop readline(mem_file.simplified MIPS processor Universit´ e de Lorraine 15 Master 2 I2E2I .STD_LOGIC_1164. ch). end loop. elsif ’a’ <= ch and ch <= ’f’ then result := result*16 + character’pos(ch)-character’pos(’a’)+10. adr. end loop. for j in 0 to 3 loop result := 0. end. variable ch: character. end loop.dat". ------------------------------------------------------------------------.80020044 means mem[3] = 80 and mem[0] = 44 for i in 0 to 255 loop -. end loop. mem(index*4+3-j) := conv_std_logic_vector(result. L). index := 0. variable mem: ramtype. else report "Format error on line " & integer’image(index) severity error.read or write memory loop if clk’event and clk = ’1’ then if (memwrite = ’1’) then mem(conv_integer(adr)) := writedata. end if. index := index + 1. wait on clk. use IEEE. for i in 1 to 2 loop read(L. entity mips is -. result: integer.2 Processeur MIPS architecture synth of memory is begin process is file mem_file: text open read_mode is "memfile. variable L: line. begin -. end if. memdata <= mem(conv_integer(adr)). variable index. -. if ’0’ <= ch and ch <= ’9’ then result := result*16 + character’pos(ch)-character’pos(’0’).memory in little-endian format -. width).

irwrite. port(clk. alusrcb: STD_LOGIC_VECTOR(1 downto 0). regdst: in STD_LOGIC.default 8-bit datapath 3). pcen. reset. pcen. regbits) port map(clk. instr: out STD_LOGIC_VECTOR(31 downto 0). zero. alusrcb. memtoreg. iord. memread. STD_LOGIC. memwrite. regdst: out STD_LOGIC. memtoreg. alucont. memtoreg. pcsrc. alusrca.and 3 bit register addresses (8 regs) STD_LOGIC. memtoreg. writedata: out end. zero: out STD_LOGIC. regbits: integer). signal aluop.2 Processeur MIPS generic(width: integer := regbits: integer := port(clk. irwrite). alucont: out STD_LOGIC_VECTOR(2 downto 0)). end component. pcen. regwrite. writedata). funct: in STD_LOGIC_VECTOR(5 downto 0).controller ------------------------------------------------------------------------------------ Universit´ e de Lorraine 16 Master 2 I2E2I . regdst. alusrcb: in STD_LOGIC_VECTOR(1 downto 0). 8. regdst. ------------------------------------------------------------------------. STD_LOGIC_VECTOR(width-1 downto 0). signal instr: STD_LOGIC_VECTOR(31 downto 0). zero: in STD_LOGIC. iord.1.End of MIPS ----------------------------------------------------------------------------------------------------------------------------------------------------------. reset: in STD_LOGIC. alusrca. alusrca. writedata: out STD_LOGIC_VECTOR(width-1 downto 0)). pcsrc. alusrcb. begin cont: controller port map(clk. end component. adr. alucont: in STD_LOGIC_VECTOR(2 downto 0). alusrca. component alucontrol port(aluop: in STD_LOGIC_VECTOR(1 downto 0). -. memwrite: out adr. reset: in memdata: in memread. iord. memwrite. zero. op: in STD_LOGIC_VECTOR(5 downto 0). alusrcb. memdata. instr(5 downto 0). adr. architecture struct of mips is component controller port(clk. iord. ac: alucontrol port map(aluop. signal irwrite: STD_LOGIC_VECTOR(3 downto 0). regwrite. irwrite: in STD_LOGIC_VECTOR(3 downto 0). alusrca. signal alucont: STD_LOGIC_VECTOR(2 downto 0). pcen. iord. reset. component datapath generic(width. dp: datapath generic map(width. memread. instr. pcsrc. regwrite. pcsrc. signal zero. -. end component. STD_LOGIC_VECTOR(width-1 downto 0)). alucont). regwrite. aluop: out STD_LOGIC_VECTOR(1 downto 0). irwrite: out STD_LOGIC_VECTOR(3 downto 0)). pcsrc. memdata: in STD_LOGIC_VECTOR(width-1 downto 0). reset: in STD_LOGIC. aluop. memtoreg. regwrite. end. instr(31 downto 26). regdst: STD_LOGIC. pcen.

-. end if. when J => nextstate <= JEX. entity controller is -. begin process (clk) begin -. when others => nextstate <= FETCH1. end process. memread. memwrite. nextstate <= FETCH4. RTYPEWR. when others => nextstate <= FETCH1. -. when LBWR => nextstate <= FETCH1. op) case state is when FETCH1 when FETCH2 when FETCH3 when FETCH4 when DECODE begin -.next state logic => => => => => nextstate <= FETCH2. end if. signal pcwrite.STD_LOGIC_1164. Universit´ e de Lorraine 17 Master 2 I2E2I . nextstate: statetype. constant BEQ: STD_LOGIC_VECTOR(5 downto 0) := "000100".should never happen end case. when BEQ => nextstate <= BEQEX. when JEX => nextstate <= FETCH1.should never happen end case. FETCH3. memtoreg. end.state register if clk’event and clk = ’1’ then if reset = ’1’ then state <= FETCH1. case op is when LB | SB => nextstate <= MEMADR.2 Processeur MIPS library IEEE. when BEQEX => nextstate <= FETCH1. end process. regwrite. op: in STD_LOGIC_VECTOR(5 downto 0). constant LB: STD_LOGIC_VECTOR(5 downto 0) := "100000". BEQEX. SBWR. RTYPEEX.1. reset: in STD_LOGIC. when LBRD => nextstate <= LBWR. FETCH2. when MEMADR => case op is when LB => nextstate <= LBRD. when SB => nextstate <= SBWR. alusrca.control FSM port(clk. zero: in STD_LOGIC. pcen. pcsrc. FETCH4. constant RTYPE: STD_LOGIC_VECTOR(5 downto 0) := "000000". aluop: out STD_LOGIC_VECTOR(1 downto 0). MEMADR. when RTYPEWR => nextstate <= FETCH1. constant SB: STD_LOGIC_VECTOR(5 downto 0) := "101000". alusrcb. pcwritecond: STD_LOGIC. LBRD. irwrite: out STD_LOGIC_VECTOR(3 downto 0)). when SBWR => nextstate <= FETCH1. nextstate <= DECODE. signal state. when others => nextstate <= FETCH1. iord. regdst: out STD_LOGIC.should never happen end case. JEX). when RTYPE => nextstate <= RTYPEEX. -. nextstate <= FETCH3. else state <= nextstate. LBWR. process (state.all. use IEEE. signal state_sig:integer range 0 to 15. DECODE. constant J: STD_LOGIC_VECTOR(5 downto 0) := "000010". architecture synth of controller is type statetype is (FETCH1. when RTYPEEX => nextstate <= RTYPEWR.

end case. irwrite <= "0100". irwrite <= "0001". pcwrite <= ’0’. pcwrite <= ’1’. pcwrite <= ’1’. state_sig <= 6. pcwritecond <= ’1’. memtoreg <= ’0’. irwrite <= "1000". memtoreg <= ’1’. aluop <= "01". memread <= ’0’. state_sig <= 4. iord <= ’0’. when FETCH3 => memread <= ’1’. alusrcb <= "00". when BEQEX => alusrca <= ’1’. iord <= ’1’.set all outputs to zero. state_sig <= 2. when RTYPEEX => alusrca <= ’1’. pcwritecond <= ’0’. state_sig <= 1. when LBRD => memread <= ’1’. pcwrite <= ’1’. alusrcb <= "01". when RTYPEWR => regdst <= ’1’. state_sig <= 8. when MEMADR => alusrca <= ’1’. alusrcb <= "01". when FETCH4 => memread <= ’1’. state_sig <= 11. Universit´ e de Lorraine 18 Master 2 I2E2I . irwrite <= "0010".2 Processeur MIPS process (state) begin -. state_sig <= 3. when JEX => pcwrite <= ’1’. regwrite <= ’1’. state_sig <= 5. alusrcb <= "01". alusrcb <= "10". aluop <= "00". when LBWR => regwrite <= ’1’. case state is when FETCH1 => memread <= ’1’. regwrite <= ’0’. alusrca <= ’0’. state_sig <= 9. memwrite <= ’0’. pcwrite <= ’1’. when FETCH2 => memread <= ’1’. aluop <= "10". pcsrc <= "10". when DECODE => alusrcb <= "11". state_sig <= 13.1. alusrcb <= "01". when SBWR => memwrite <= ’1’. state_sig <= 7. pcsrc <= "01". then conditionally assert just the appropriate ones irwrite <= "0000". iord <= ’1’. state_sig <= 12. state_sig <= 10. regdst <= ’0’. pcsrc <= "00".

pcen <= pcwrite or (pcwritecond and zero). -. entity datapath is -.STD_LOGIC_1164. -.subtract (for sub) when "100100" => alucont <= "000". irwrite: in STD_LOGIC_VECTOR(3 downto 0). regbits: integer). Universit´ e de Lorraine 19 Master 2 I2E2I .MIPS datapath generic(width. end process. -.add (for lb/sb/addi) when "01" => alucont <= "110". use IEEE.2 Processeur MIPS end process. entity alucontrol is -.End of alucontrol ----------------------------------------------------------------------------------------------------------------------------------------------------.End of controller ----------------------------------------------------------------------------- ------------------------------------------------------------------------. iord.datapath -------------------------------------------------------------------------------------library IEEE.add (for add) when "100010" => alucont <= "110". -.logical and (for and) when "100101" => alucont <= "001".all. alusrcb: in STD_LOGIC_VECTOR(1 downto 0). -. alucont: out STD_LOGIC_VECTOR(2 downto 0)). -.all. -. funct) begin case aluop is when "00" => alucont <= "010".ALU control decoder port(aluop: in STD_LOGIC_VECTOR(1 downto 0). memdata: in STD_LOGIC_VECTOR(width-1 downto 0).program counter enable end.logical or (for or) when "101010" => alucont <= "111". use IEEE. pcen. port(clk.1. alusrca. regwrite.all. end.sub (for beq) when others => case funct is -. regdst: in STD_LOGIC. memtoreg. architecture synth of alucontrol is begin process(aluop. -. funct: in STD_LOGIC_VECTOR(5 downto 0). use IEEE.alucontrol -----------------------------------------------------------------------------------library IEEE. end.STD_LOGIC_1164.R-type instructions when "100000" => alucont <= "010". -. end case. ------------------------------------------------------------------------.set on less (for slt) when others => alucont <= "---". ------------------------------------------------------------------------.should never happen end case.STD_LOGIC_ARITH. reset: in STD_LOGIC. pcsrc.

q: out STD_LOGIC_VECTOR(width-1 downto 0)). port(d0. component regfile generic(width. signal dp_instr: STD_LOGIC_VECTOR(31 downto 0). y: out STD_LOGIC_VECTOR(width-1 downto 0)). port(clk. end component. port(d0. wa: STD_LOGIC_VECTOR(regbits-1 downto 0). d: in STD_LOGIC_VECTOR(width-1 downto 0). port(clk. STD_LOGIC_VECTOR(31 downto 0). d1. src1. regbits: integer). wd. reset. writedata: end.shift left constant field by 2 constx4 <= dp_instr(width-3 downto 0) & "00". constant CONST_ONE: STD_LOGIC_VECTOR(width-1 downto 0) := conv_std_logic_vector(1. wd: in STD_LOGIC_VECTOR(width-1 downto 0). ra1. aluresult. port(a: in STD_LOGIC_VECTOR(width-1 downto 0). constant CONST_ZERO: STD_LOGIC_VECTOR(width-1 downto 0) := conv_std_logic_vector(0. port(a. d2. in out out out STD_LOGIC_VECTOR(2 downto 0). port(clk: in STD_LOGIC. write: in STD_LOGIC. rd2: out STD_LOGIC_VECTOR(width-1 downto 0)).1. end component. end component. rd1.2 Processeur MIPS alucont: zero: instr: adr. s: in STD_LOGIC_VECTOR(1 downto 0). constx4: STD_LOGIC_VECTOR(width-1 downto 0). a. width). component mux4 generic(width: integer). Universit´ e de Lorraine 20 Master 2 I2E2I . wa: in STD_LOGIC_VECTOR(regbits-1 downto 0). port(clk: in STD_LOGIC. nextpc. q: out STD_LOGIC_VECTOR(width-1 downto 0)). component flopen generic(width: integer). signal ra1. component zerodetect generic(width: integer). signal pc. aluout. y: out STD_LOGIC). -. d3: in STD_LOGIC_VECTOR(width-1 downto 0). y: out STD_LOGIC_VECTOR(width-1 downto 0)). rd2. ra2. src2. STD_LOGIC. architecture struct of datapath is component alu generic(width: integer). b: in STD_LOGIC_VECTOR(width-1 downto 0). STD_LOGIC_VECTOR(width-1 downto 0)). end component. width). end component. en: in STD_LOGIC. d1: in STD_LOGIC_VECTOR(width-1 downto 0). rd1. en: in STD_LOGIC. d: in STD_LOGIC_VECTOR(width-1 downto 0). end component. md. end component. result: out STD_LOGIC_VECTOR(width-1 downto 0)). ra2. component flop generic(width: integer). end component. s: in STD_LOGIC.register file addrss fields ra1 <= dp_instr(regbits+20 downto 21). dp_writedata. d: in STD_LOGIC_VECTOR(width-1 downto 0). q: out STD_LOGIC_VECTOR(width-1 downto 0)). alucont: in STD_LOGIC_VECTOR(2 downto 0). component flopenr generic(width: integer). component mux2 generic(width: integer). begin -.

slt: STD_LOGIC_VECTOR(width-1 downto 0). src1). slt when others. end.STD_LOGIC_UNSIGNED.2 Processeur MIPS ra2 <= dp_instr(regbits+15 downto 16).End of datapath ------------------------------------------------------------------------------------------------------------------------------------------------------. alunit: alu generic map(width) port map(src1. alusrcb. regwrite. areg: flop generic map(width) port map(clk.1. irwrite(2).STD_LOGIC_1164. iord. irwrite(3). b: in STD_LOGIC_VECTOR(width-1 downto 0). wdmux: mux2 generic map(width) port map(aluout. CONST_ZERO. ------------------------------------------------------------------------. dp_instr(23 downto 16)). writedata <= dp_writedata. dp_instr(regbits+10 downto 11). width) when sum(width-1) = ’1’ else conv_std_logic_vector(0. adr). dp_instr(width-1 downto 0). zd: zerodetect generic map(width) port map(aluresult.datapath pcreg: flopenr generic map(width) port map(clk. nextpc. adrmux: mux2 generic map(width) port map(pc.alu ------------------------------------------------------------------------------------------- library IEEE. nextpc). rd2). aluout). begin b2 <= not b when alucont(2) = ’1’ else b. memdata(7 downto 0). alusrca. reset. mdr: flop generic map(width) port map(clk.drive outputs instr <= dp_instr. a. dp_instr(7 downto 0)). rd2. entity alu is -. end. memdata. ir1: flopen generic map(8) port map(clk. regbits) port map(clk.independent of bit width. ra2. wa). ir2: flopen generic map(8) port map(clk. constx4. set less than generic(width: integer).all. use IEEE. src2. Universit´ e de Lorraine 21 Master 2 I2E2I . md). pcen. aluout. with alucont(1 downto 0) select result <= a and b when "00". pcsrc. res: flop generic map(width) port map(clk. src1mux: mux2 generic map(width) port map(pc. dp_instr(31 downto 24)). dp_instr(15 downto 8)). memtoreg. sum <= a + b2 + alucont(2). regdst. sum when "10". ir3: flopen generic map(8) port map(clk. rf: regfile generic map(width. wa. a or b when "01". width). dp_writedata).all. irwrite(1). result: out STD_LOGIC_VECTOR(width-1 downto 0)). wd). zero). memdata(7 downto 0). rd1. -.all. OR. -. -. alucont: in STD_LOGIC_VECTOR(2 downto 0). load dp_instruction into four 8-bit registers over four cycles ir0: flopen generic map(8) port map(clk. pcmux: mux4 generic map(width) port map(aluresult.slt should be 1 if most significant bit of sum is 1 slt <= conv_std_logic_vector(1. architecture synth of alu is signal b2. constx4. md. a). -. memdata(7 downto 0). use IEEE. CONST_ONE. regmux: mux2 generic map(regbits) port map(dp_instr(regbits+15 downto 16). aluout.STD_LOGIC_ARITH. aluresult). wrd: flop generic map(width) port map(clk. src2). alucont. pc). AND. use IEEE. aluresult. irwrite(0). ra1. memdata(7 downto 0). port(a. sum. rd1. src2mux: mux4 generic map(width) port map(dp_writedata. wd.Arithmetic/Logic unit with add/sub.

use IEEE. ------------------------------------------------------------------------.End of regfile -------------------------------------------------------------------------------------------------------------------------------------------------------. entity regfile is -.End of alu -----------------------------------------------------------------------------------------------------------------------------------------------------------. Universit´ e de Lorraine 22 Master 2 I2E2I . rd1.STD_LOGIC_1164.read two ports combinationally -.regfile --------------------------------------------------------------------------------------- library IEEE. end process. end. use IEEE. ------------------------------------------------------------------------. -. y: out STD_LOGIC). else rd2 <= mem(conv_integer(ra2)). port(clk: in STD_LOGIC.all.STD_LOGIC_ARITH.register 0 holds 0 else rd1 <= mem(conv_integer(ra1)). entity zerodetect is -.all.all.2 Processeur MIPS end. use IEEE. ra2. end process. process(ra1.STD_LOGIC_UNSIGNED.write third port on rising edge of clock process(clk) begin if clk’event and clk = ’1’ then if write = ’1’ then mem(conv_integer(wa)) <= wd. end if.true if all input bits are zero generic(width: integer).STD_LOGIC_1164. width). port(a: in STD_LOGIC_VECTOR(width-1 downto 0).zerodetect ------------------------------------------------------------------------------------ library IEEE. architecture synth of regfile is type ramtype is array (2**regbits-1 downto 0) of STD_LOGIC_VECTOR(width-1 downto 0). rd2: out STD_LOGIC_VECTOR(width-1 downto 0)). wa: in STD_LOGIC_VECTOR(regbits-1 downto 0).three-port register file of 2**regbits words x width bits generic(width. ra2) begin if (conv_integer(ra1) = 0) then rd1 <= conv_std_logic_vector(0. regbits: integer). end. width).three-ported register file -. end if. signal mem: ramtype. if (conv_integer(ra2) = 0) then rd2 <= conv_std_logic_vector(0.1. wd: in STD_LOGIC_VECTOR(width-1 downto 0). end if. ra1.all. use IEEE. end if. write: in STD_LOGIC. begin -.

STD_LOGIC_1164. architecture synth of zerodetect is signal i: integer. ------------------------------------------------------------------------. signal x: STD_LOGIC_VECTOR(width-1 downto 1). en: in STD_LOGIC. use IEEE. port(clk: in STD_LOGIC. d: in STD_LOGIC_VECTOR(width-1 downto 0).1. end. end. y <= x(width-1).all.all.flip-flop generic(width: integer). q: out STD_LOGIC_VECTOR(width-1 downto 0)). entity flopen is -.flip-flop with enable generic(width: integer). use IEEE. end if. q: out STD_LOGIC_VECTOR(width-1 downto 0)). port(clk. end generate.flop ------------------------------------------------------------------------------------------ library IEEE. end generate.2 Processeur MIPS end.End of zerodetect ----------------------------------------------------------------------------------------------------------------------------------------------------. begin -. architecture synth of flop is begin process(clk) begin if clk’event and clk = ’1’ then -.N-bit AND of inverted inputs AllBits: for i in width-1 downto 1 generate LowBit: if i = 1 generate A1: x(1) <= not a(0) and not a(1).or use "if RISING_EDGE(clk) then" q <= d. end. Universit´ e de Lorraine 23 Master 2 I2E2I .flopen ---------------------------------------------------------------------------------------- library IEEE. ------------------------------------------------------------------------.End of flop ----------------------------------------------------------------------------------------------------------------------------------------------------------. end generate. end process. entity flop is -. OtherBits: if i /= 1 generate Ai: x(i) <= not a(i) and x(i-1).STD_LOGIC_1164. d: in STD_LOGIC_VECTOR(width-1 downto 0).

produce a vector of all zeros elsif en = ’1’ then q <= d. end. port(d0.2 Processeur MIPS end.all. entity flopenr is -. d1: in STD_LOGIC_VECTOR(width-1 downto 0). end process. s: in STD_LOGIC. use IEEE.two-input multiplexer generic(width: integer). y: out STD_LOGIC_VECTOR(width-1 downto 0)). entity mux2 is -. width).STD_LOGIC_1164.End of flopenr -------------------------------------------------------------------------------------------------------------------------------------------------------. port(clk. en: in STD_LOGIC.STD_LOGIC_1164. use IEEE. end. end if. architecture synth of mux2 is Universit´ e de Lorraine 24 Master 2 I2E2I .flip-flop with enable and synchronous reset generic(width: integer).mux2 ------------------------------------------------------------------------------------------ library IEEE.all. end if. q: out STD_LOGIC_VECTOR(width-1 downto 0)). architecture synchronous of flopenr is begin process(clk) begin if clk’event and clk = ’1’ then if reset = ’1’ then q <= CONV_STD_LOGIC_VECTOR(0. end if.STD_LOGIC_ARITH. d: in STD_LOGIC_VECTOR(width-1 downto 0). end.all.End of flopen --------------------------------------------------------------------------------------------------------------------------------------------------------. ------------------------------------------------------------------------. reset. end.flopenr --------------------------------------------------------------------------------------- library IEEE. -. end process. use IEEE. end if.1. ------------------------------------------------------------------------. architecture synth of flopen is begin process(clk) begin if clk’event and clk = ’1’ then if en = ’1’ then q <= d.

2010. 3 R´ ef´ erences R´ ef´ erences [WH10] Neil Weste and David Harris.End of mux2 ----------------------------------------------------------------------------------------------------------------------------------------------------------. architecture synth of mux4 is begin y <= d0 when s = "00" else d1 when s = "01" else d2 when s = "10" else d3. d1. Universit´ e de Lorraine 25 Master 2 I2E2I . y: out STD_LOGIC_VECTOR(width-1 downto 0)). end. port(d0. s: in STD_LOGIC_VECTOR(1 downto 0). 4th ed. end. entity mux4 is -.all. use IEEE. d2. end.End of mux4 ------------------------------------------------------------------------------- 2 V´ erification du syst` eme La v´ erification du syst` eme se d´ ecompose en deux parties : — en v´ erification du multiplieur 16 × 16 de mani` ere ind´ ependante et — en v´ erification du microprocesseur int´ egrant le multiplieur con¸ cu en l’adaptant a ` son architecture. ------------------------------------------------------------------------.four-input multiplexer generic(width: integer). CMOS VLSI Design : A Circuits and Systems Perspective.. USA. La premi` ere partie consiste ` a appliquer en entr´ ees du multiplieur des valeurs enti` eres en compl´ ement a ` 2 sur 16 bits tandis que la seconde partie consiste ` a´ ecrire un code machine effectuant la fonction 5! (factoriel de 5) permettant d’´ evaluer la fonction de multiplication nouvellement int´ egr´ ee au sein du microprocesseur. ------------------------------------------------------------------------.mux4 ------------------------------------------------------------------------------------------ library IEEE.STD_LOGIC_1164. d3: in STD_LOGIC_VECTOR(width-1 downto 0). Addison-Wesley Publishing Company.begin y <= d0 when s = ’0’ else d1.

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