Preliminary Information

AMD Athlon
Processor Model 4 Data Sheet

TM

Publication # 23792 Rev: K Issue Date: November 2001

Preliminary Information

© 2000, 2001 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.

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Trademarks AMD, the AMD Arrow logo, AMD Athlon, AMD Duron, and combinations thereof, and 3DNow! are trademarks of Advanced Micro Devices, Inc. HyperTransport is a trademark of the HyperTransport Technology Consortium. MMX is a trademark of Intel Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Preliminary Information
23792K—November 2001

AMD Athlon™ Processor Model 4 Data Sheet

Contents
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 AMD Athlon™ Processor Model 4 Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AMD Athlon System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . 6

2

Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 2.3 2.4

3 4

Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Working State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 12 Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2

4.3

5 6 7

Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CPUID Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 24 Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 24 VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 25 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . . 27 SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 28 AMD Athlon System Bus AC and DC Characteristics . . . . . 30 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 32 APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . 34

Contents

iii

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 8
23792K—November 2001

Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 35
8.1 Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Signal Sequence and Timing Description . . . . . . . . . . . . . . . . 35 Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . . . . 37 Serial Initialization Packet (SIP) Protocol . . . . . . . . . . . . . . . 38 Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 38 The AMD Athlon Processor Model 4 and Northbridge Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AMD Athlon Processor Model 4 CPGA Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin Diagram and Pin Name Abbreviations . . . . . . . . . . . . . . 43 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 AMD Athlon System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . 60 Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 APIC Pins, PICCLK, PICD[1:0]# . . . . . . . . . . . . . . . . . . . . . . . 60 CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . . . . 60 CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 61 CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . . . . 63 Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . . . 64 Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SYSCLK and SYSCLK# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8.2

9

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.1 9.2 9.3

10

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.1 10.2 10.3

iv

Contents

. . . . . . . . . . . . . . . 75 Contents v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Appendix A Conventions and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Signals and Bits . . . . . . . . . . 74 Abbreviations and Acronyms. . . . . . 64 VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . VCC_Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . 66 11 Ordering Information . . . . . . . . . .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet SYSVREFMODE Pin. . . . . . . . . . . . 73 Data Terminology . . . . . . . . . . . . . . . . . . . . . 71 Standard AMD Athlon Processor Model 4 Products . . . . . . . . . and VSS_Z Pins . . . . . . . . . . . . . . . . . . . . 66 ZN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 VREFSYS Pin . ZP. . . . . . . . . . . . . . . . . . . . . . . . . . .

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 vi Contents .

. . . . . . . . . . 44 Figure 13. . . 7 AMD Athlon Processor Model 4 Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical AMD Athlon™ Processor Model 4 System Block Diagram . . . . . . . . . . . . . . . . . . . 45 Figure 14. . . . . . . . . . . . . . . . . . . 3 Logic Symbol Diagram . . . . . . . . . . . . . . . . . 28 SYSCLK Waveform . . . . . . . 29 Figure 10. . . . . . . AMD Athlon Processor Model 4 Pin Diagram— Topside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 11. . . . . . . . . . . . . . . Figure 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Processor Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7. . 13 Exiting Stop Grant State/Bus Reconnect Sequence . . . . 9 Example of an AMD Athlon System Bus Disconnect Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet List of Figures Figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Northbridge Connect State Diagram . . . . . . . . . . . . . . . . AMD Athlon Processor Model 4 Pin Diagram— Bottomside View. . . . . . . . . . . Figure 5. . . . . . . . . . . . AMD Athlon Processor Model 4 CPGA Package. 16 SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . . . . . . . . . . Figure 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 List of Figures vii . . . . . . . Figure 8. . . . . . . . 41 Figure 12. . . . . . . . . . . . . . . . Signal Relationship Requirements During Power-Up Sequence . . PGA OPN Example for the AMD Athlon Processor Model 4 . . . . . . Figure 9. . . . Figure 2. Figure 6. . .

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 viii List of Figures .

. . . . . Table 9. . . . Thermal Design Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating Ranges. . . . . . . . . . . . . . . . . . . . . . Table 16. . . . . . . . . . . . . . . . Table 7. . . . Table 18. . 40 Pin Name Abbreviations . . . . . . . . . . . . . . . . . . Table 3. . . . . . . . . Table 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SYSCLK and SYSCLK# DC Characteristics . . . Table 13. . . . . . . . . Table 10. . . . . . . . . . . . . . . . . . . . 62 VID[4:0] Code to Voltage Definition . . Table 11. . . . . . . . . . . . . 23 VID[4:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 General AC and DC Characteristics . 30 AMD Athlon System Bus AC Characteristics . . . . . . . . . . . . Table 19. . . . . . . . . . . . . 25 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 76 List of Tables ix . . . . . . . . . Table 14. . . . . . . . . . . Table 5. . . . . . . . . . . 52 FID[3:0] Clock Multiplier Encodings . . . . . . . . . . . . . Table 21. . . . . . . . . . . . . 24 VCCA AC and DC Characteristics . . . . . . Table 15. . . . . . . . . . . . 19 Interface Signal Groupings . . . . . . . . . . . . . . Table 2. .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet List of Tables Table 1. . . . . . . . . . 75 Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . Table 8. . . . . 46 Cross-Reference by Pin Location . . . . . . . . . . . . Table 6. . . . . . . . . . . . . . . 28 SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . . . . 32 APIC Pins AC and DC Characteristics . . . . 29 AMD Athlon™ System Bus DC Characteristics . . . . 66 Abbreviations . 24 FID[3:0] DC Characteristics . . . . . . . Table 22. . . . . . . . . . Table 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CPGA Mechanical Loading . . . . . . 26 VCC_CORE Voltage and Current. . . . . . . . . . . . . . 39 Dimensions for the AMD Athlon Processor Model 4 CPGA Package . . . . . . . . . . . . . . . Table 4. . . . . . . .

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 x List of Tables .

revised Figure 3. In Chapter 4. “Thermal Design Power.” on page 29. “SYSCLK and SYSCLK# AC Characteristics.” on page 19 In Chapter 7. updated Table 8. revised Table 16. included APIC information in “Halt State” on page 10 and “Stop Grant States” on page 10 In Chapter 5.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Revision History Date Rev Description This revision of the AMD Athlon™ Processor Model 4 Data Sheet covers changes since September 2001 that include the following: November 2001 K ■ ■ ■ In Chapter 5. This revision is for the 1400 MHz AMD Athlon™ Processor Model 4 and covers changes since March 2001 that include the following: ■ June 2001 I ■ ■ ■ In Chapter 4. updated Table 1. and revised Note 1 in Table 11.” on page 34. "PGA OPN Example for the AMD Athlon™ Processor Model 4‚" on page 71 This revision of the 1400 MHz AMD Athlon™ Processor Model 4 covers changes since June 2001 that include the following: September 2001 J In Chapter 9. and revised Figure 11. “AMD Athlon™ System Bus DC Characteristics.” on page 27 In Chapter 11. revised Figure 14. “Pin Name Abbreviations. "AMD Athlon™ Processor Model 4 Power Management States‚" on page 9 In Chapter 5. “Thermal Design Power. revised Table 8. PICCLK. “VCC_CORE Voltage and Current.” on page 27 In Chapter 10. “Thermal Design Power. revised description of “Serial Initialization Packet (SIP) Protocol” on page 38 In Chapter 10. “VCC_CORE Voltage and Current.” on page 19 Table 8.” on page 29 Chapter 11. “VCC_CORE Voltage and Current. added Table 16. added description of “APIC Pins. updated IoL specification to 12 mA in Table 14.” on page 27. updated Table 1.” on page 40.” on page 30. “APIC Pins AC and DC Characteristics. "AMD Athlon™ Processor Model 4 CPGA Package‚" on page 41.” on page 20 In Chapter 7. revised Table 10. “Dimensions for the AMD Athlon™ Processor Model 4 CPGA Package. In Chapter 8.” on page 19 In Chapter 7. PICD[1:0]#” on page 62. revised description on the AMD Athlon™ system bus.” on page 48. “Ordering Information” on page 71 This revision is for the 1333 MHz speed grade and covers changes since October 2000. “SYSCLK and SYSCLK# AC Characteristics. and revised description of “AMD Pin” on page 62 “AMD Athlon™ Processor Model 4 Microarchitecture Summary” on page 2 Table 1. “VCC_CORE Voltage and Current.” on page 27 Table 10. “Thermal Design Power. revised description of “FERR Pin” on page 61 and in Table 18 on page 52 In Chapter 1. Updated Table 8. ■ ■ ■ March 2001 H ■ ■ ■ Added information about the 133 MHz front side bus (FSB) as follows: ■ ■ ■ ■ ■ October 2000 G Revision History xi . revised Table 1.

■ Added SAI#[0] pin in location AJ29 to Figure 15.” on page 25 ■ Table 8. Table 17. “Socket A Pin Cross-Reference by Pin Location. “Overview” on page 3 ■ Table 1. "AMD Athlon™ Processor Model 4 Pin Diagram—Topside View‚" on page 46.” on page 19.” on page 27 ■ Revised OPN to include the new 1200 MHz speed grade in Chapter 10.” on page 47.” on page 55. order# 90009” with new document name of “Socket A Motherboard Design Guide. ● Added information about the 1. ■ Updated “Motherboard PGA Design Guide.1-GHz AMD Athlon™ Processor Model 4 as follows: ■ ■ August 2000 D ■ ■ ■ Chapter 1.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Date October 2000 Rev F Description Revised VID[4:0] information in Table 3 on page 24 and “VID[4:0] Pins” on page 65 Added Information about the 1.” on page 28. xii Revision History . “Thermal Design Power. and Table 9.” on page 55Revised all no connect (NC) pins on the pin grid array (PGA) as follows: ■ October 2000 E ■ Figure 15.” on page 25. “SYSCLK and SYSCLK# DC Characteristics. “Thermal Design Power. “Thermal Design Power. “SYSCLK and SYSCLK# AC Characteristics. “VCC_CORE Voltage and Current. “Operating Ranges.” on page 25 Table 8. Revised KLCKOUT/KCLKOUT# verbiage in Chapter . “VCC_CORE Voltage and Current. See Table 10. “Pin Name Abbreviations. ● Table 16. “Ordering Information” on page 71 ■ Revised Maximum and Typical Thermal Power numbers in Table 1." Table 6. “Operating Ranges. “Pin Name Abbreviations.” on page 47. “Overview” on page 3 Table 1.” on page 21 Table 6. ■ Revised table note 2 as “The Sleep Voltage is used for the S1 sleep state and as the Powerup voltage before PWROK and PWRGD are asserted. “Socket A Pin Cross-Reference by Pin Location.” on page 27.2 GHz AMD Athlon™ Processor Model 4 as follows: Chapter 1. ■ Added note to Table 6 for new Die temperature.” on page 27 Revised and reorganized the AC and DC characteristics for SYSCLK and SYSCLK#. Added the AMD Pin (AH6) to Table 16. ● Table 15.” on page 21 ■ Table 6. “Operating Ranges. "AMD Athlon™ Processor Model 4 Pin Diagram—Topside View‚" on page 46. order# 24363” throughout book. “K7CLKOUT and K7CLKOUT# Pins” on page 65.

” on page 21 to Chapter 5. Revised the timing requirements in Step 4 on page 37.” on page 24. “AMD Athlon™ Processor Model 4 Interface Signal Groupings. “Thermal Design Power.” on page 23. Revised and reorganized Table 11. see Table 1. Added VCROSS symbol to this table. “VCCA AC and DC Characteristics. APIC. “VCC_CORE Voltage and Current. “SYSCLK/SYSCLK# AC and DC Characteristics. Test. “VID[4:0] DC Characteristics. ■ Revised maximum values in Table 7. For thermal information.” on page 27.75V for all speed grades. “Thermal Design”. Made the following changes in Chapter 7: ■ ■ ■ August 2000 C ■ ■ ■ Changed PLL power source signal name from VDDA to VCCA. ■ Changed VCC_CORE to 1. “FID[3:0] DC Characteristics. “SYSCLK and SYSCLK# AC and DC Characteristics.” on page 27.” on page 26. “Electrical Data” on page 23 as follows: Added JTAG. Revised Figure 10.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Date Rev Description Added Table 1. ■ Revised and reorganized information in Table 8. ■ Revised IVCCA information in Table 5. “Absolute Ratings.” on page 21. ■ Added “Conventions” on page 23. ■ Added and revised information in Table 6. Revised Chapter 6. Miscellaneous rows to Table 2.” on page 25. ■ Revised information in Table 4. ■ Revised information in Table 3. Reorganized signals into their correct categories. “Thermal Design Power. “Signal Relationship Requirements during Power-Up Sequence” on page 36.” on page 23. Revision History xiii .” on page 24.

xiv Revision History . AG1 (FERR). N5 (PIC[1]#). “Ordering Information” on page 71. AC7 (VCC_Z). ■ Removed all specific resistor values in “Detailed Pin Descriptions” on page 62. AJ23 (VCCA). AN13 (PLLMON1). AN21 (K7CLKOUT#). AE33 (SADDIN[5]#). “Socket A Pin Cross-Reference by Pin Location. ■ Revised definition of the Reference column in Table 17. AJ21 (CLKFWDRST). AN15 (PLLBYPASSCLK). AE37 (SDATA[9]#).” on page 55 in “Pin List” on page 53. Revised Chapter 9. AN35 (SADINN[13]#). revised information for the following pin locations: ● N1 (PICCLK). ■ In Table 17. AN37 (SADINN[9]#) ■ Revised information in “K7CLKOUT and K7CLKOUT# Pins” on page 65. AN31 (SADINN[14]#). order# 90009. see the Motherboard PGA Design Guide.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Date Rev Description Revised all figures and information in Chapter 8. “Socket A Pin Cross-Reference by Pin Location. N3 (PIC[0]#). “Mechanical Data” on page 41. AN33 (SDATAINVAL#). For specific implementation information. “AMD Athlon™ Processor Model 4 Pin Diagram— Topside View” on page 46.” on page 55. Revised Chapter 10. “Pin Descriptions” on page 45 as follows: Changed FERR# to FERR in Figure 15. AE35 (SDATAOUTCLK[0]#). ■ August 2000 C June 2000 B Initial public release. AN29 (SADINN[12]#). See “FERR Pin” on page 63 for more information.

workstation-class computer-aided design (CAD). T h e A M D A t h l o n p r o c e s s o r m o d e l 4 f e a t u re s t h e seventh-generation microarchitecture with an integrated L2 cache. commercial desktop publishing. The high-speed execution core of the AMD Athlon processor model 4 includes multiple x86 instruction decoders. digital video. digital photo editing. and speech recognition. three address calculation pipelines. t h re e -way floating-point engine. I/O. For cutting-edge software applications. soft DVD. Chapter 1 Overview 1 . a dual-ported 128-Kbyte split level-one (L1) cache. video encoding for streaming over the internet.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 1 Overview The AMD Athlon™ processor model 4 powers the next generation in computing platforms. and a s u p e rs c a l a r. including digital content creation. f u l ly p i p e l i n e d . the A M D A t h l o n p ro c e s s o r m o d e l 4 d e l ive rs c o m p e l l i n g performance. three independent integer pipelines. Delivered in a CPGA package and achieving frequencies of 1. image compression. which supports the growing processor and system bandwidth requirements of emerging software. and memory technologies. a 256-Kbyte on-chip L2 cache. workstations. commercial 3D modeling. floating-point and 3D multimedia performance needed for highly demanding applications running on x86 system platforms. It also offers the scalability and reliability that IT managers and business users require for enterprise computing. delivering compelling performance for cutting-edge applications and an unprecedented computing experience. The AMD Athlon processor model 4 with performance-enhancing cache memory is a member of the AMD Athlon family of processors that are designed to meet the computation-intensive requirements of cutting-edge software applications running on high-performance desktop systems. graphics.4 GHz (1400 MHz). and servers. o u t -o f -o rd e r. the AMD Athlon processor model 4 delivers the integer. The floating-point engine is capable of delivering outstanding performance on numerically complex applications.

s u ch a s point-to-point topology. single-precision floating-point results per clock cycle. 1. Using a data format and single-instruction multiple-data (SIMD) operations based on the MMX instruction model. The AMD Athlon system bus c o m b i n e s t h e l a t e s t t e ch n o l og i c a l a dva n c e s . superpipelined. and low-voltage signaling.1Gigabyte per second system bus.1 AMD Athlon™ Processor Model 4 Microarchitecture Summary The following features summarize the AMD Athlon processor model 4 microarchitecture: ■ ■ ■ ■ ■ ■ ■ ■ An advanced. scalable bus for an x86 processor. 1.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 The AMD Athlon processor model 4 microarchitecture i n c o r p o ra t e s e n h a n c e d 3 D N ow ! ™ t e c h n o l o gy. The enhanced 3DNow! technology implemented in the AMD A thl on process o r mod el 4 inc ludes new integer multimedia instructions and software-directed data movement instructions for optimizing such applications as digital content creation and streaming video for the internet. 2. as well as new instructions for digital signal processing (DSP)/communications applications. MMX and 3DNow! instructions Three out-of-order. the AMD Athlon processor model 4 can produce as many as four. pipelined integer units Three out-of-order. superscalar. and both a 200-MHz. The AMD Athlon processor model 4 is binary-compatible with existing x86 software and backwards compatible with applications optimized for MMX™ and 3DNow! instructions. fully pipelined floating-point execution units. to provide an extremely powerful. pipelined address calculation units A 72-entry instruction control unit Advanced dynamic branch prediction Enhanced 3DNow! technology with new instructions to enable improved integer math calculations for speech or video encoding and improved data movement for internet plug-ins and other streaming applications 2 Overview Chapter 1 . superscalar. 32-bit. and a 266 MHz.6-Gigabyte per second system bus. superscalar x86 processor microarchitecture designed for high clock frequencies Multiple x86 instruction decoders Three out-of-order. a high-performance cache architecture. superscalar. source-synchronous packet-based transfers. which execute all x87 (floating-point).

Typical AMD Athlon™ Processor Model 4 System Block Diagram Chapter 1 Overview 3 .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet ■ ■ 200-MHz and 266 MHz AMD Athlon system bus (scalable beyond 400 MHz) enabling leading-edge system bandwidth for data movement-intensive applications High-performance cache architecture featuring an integrated 128-Kbyte L1 cache and a 16-way. AMD Athlon™ Processor AGP Bus AGP System Controller (Northbridge) Memory Bus DRAM PCI Bus Peripheral Bus Controller (Southbridge) System Management LAN SCSI ISA Bus USB Dual EIDE BIOS Figure 1. The AMD Athlon processor model 4 is compatible with motherboards based on AMD's Socket A. Figure 1 on page 3 shows a typical AMD Athlon processor model 4 system block diagram. industry-standard form factor. on-chip 256-Kbyte L2 cache for a total of 384-Kbytes of on-chip cache The AMD Athlon processor model 4 delivers excellent system performance in a cost-effective.

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 4 Overview Chapter 1 .

The signal inputs use differential receivers. For more information about pins and signals. “Pin Descriptions” on page 43. Termination resistors are not needed because the driver is impedance matched to the motherboard and a high impedance reflection is used at the receiver to bring the signal past the input threshold. “Pin Descriptions” on page 43. The system bus architecture consists of three high-speed channels (a unidirectional processor request channel. Chapter 10. and a packet-based protocol. the system bus supports several control. Chapter 2 Interface Signals 5 .1 Interface Signals Overview The AMD Athlon™ system bus architecture is designed to de liver unprecede nt ed da ta m oveme nt bandw idth fo r next-generation x86 platforms. which has been enhanced to provide larger noise margins. as well as the high performance required by enterprise-class application software. For more information. In addition.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 2 2. 2. see “AMD Athlon™ System Bus Signals” on page 6. clock. and legacy signals. a unidirectional probe channel. reduced ringing. The interface signals use an impedance controlled push-pull low-voltage swing signaling technology contained within the Socket A socket. swing signaling technology. order# 21902. which require a reference voltage (VREF). see Chapter 10. and variable voltage levels. The reference signal is used by the receivers to determine if a signal is asserted or deasserted by the source. and a 72-bit bidirectional data channel). The signals are push-pull and impedance compensated.2 Signaling Technology The AMD Athlon system bus uses a low-voltage. source-synchronous clocking. and the AMD Athlon™ and AMD Duron™ System Bus Specification.

The impedance of the PP drivers is set to match the impedance of the motherboard by two external resistors connected to the ZN and ZP pins. ZP. VCC_Z.4 AMD Athlon™ System Bus Signals T h e A M D A t h l o n s y s t e m b u s i s a c l o ck -f o r wa rd e d . “Electrical Data” on page 23 and the AMD Athlon™ and AMD Duron™ System Bus Specification.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 2. See “ZN. order# 21902. 6 Interface Signals Chapter 2 . and VSS_Z Pins” on page 66 for more information. 2. see Chapter 7. point-to-point interface with the following three point-to-point channels: ■ ■ ■ A 13-bit unidirectional output address/command channel A 13-bit unidirectional input address/command channel A 72-bit bidirectional data channel For more information. The system logic configures the AMD Athlon processor model 4 with the configuration parameter called SysPushPull (1=PP).3 Push-Pull (PP) Drivers The Socket A AMD Athlon processor model 4 supports Push-Pull (PP) drivers.

This diagram shows the logical grouping of the input and output signals. Logic Symbol Diagram Chapter 3 Logic Symbol Diagram 7 . Clock SYSCLK SDATA[63:0]# SDATAINCLK[3:0]# SDATAOUTCLK[3:0]# SDATAINVAL# SDATAOUTVAL# SFILLVAL# SYSCLK# VID[4:0] COREFB COREFB# PWROK Data Voltage Control Frequency Control Probe/SysCMD Request SADDIN[14:2]# SADDINCLK# SADDOUT[14:2]# SADDOUTCLK# PROCRDY CLKFWDRST CONNECT STPCLK# RESET# AMD Athlon™ Processor Model 4 FID[3:0] FERR IGNNE# INIT# INTR NMI A20M# SMI# Legacy Power Management and Initialization PICCLK PICD[1:0]# APIC Figure 2.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 3 Logic Symbol Diagram Figure 2 is the logic symbol diagram of the processor.

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 8 Logic Symbol Diagram Chapter 3 .

NMI. C1 Halt Execute HLT SMI#. The figure includes the ACPI “Cx” naming convention for these states. Figure 3 shows the power management states of the AMD Athlon processor model 4.1 Power Management Power Management States The AMD Athlon™ processor model 4 supports low-power Halt and Stop Grant states.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 4 4. INTR. INIT#. RESET# C0 Working 4 (Read PLVL2 register or throttling) STPCLK# deasserted STPCLK# asserted STP C STP CL ST P Athlon™ System Bus is connected during the following The AMD System Bus is connected during the following states: states: 1) The Probe state state to Stop Grant state 2) During transitions from Halt the Halt state to the Stop Grant state Stop Grant state tofrom the Halt state 3) During transitions Stop Grant state to the Halt state 4) The C0 Working state Figure 3. AMD Athlon™ Processor Model 4 Power Management States Chapter 4 Incoming Probe Probe State1 Probe Serviced de ass LK ert #a ed 3 sse rte d2 K# ST PC CL K# LK # de ass ass ert ed ert ed Incoming Probe Probe Serviced C2 Stop Grant Cache Snoopable C3/S1 S1 Stop Grant Cache Not Snoopable Sleep Legend: Hardware transitions Software transitions Power Management 9 . These states are used by Advanced Configuration and Power Interface (ACPI) enabled operating systems for processor power management.

enabling the processor to monitor bus activity and provide a quick resume from the Halt state. Stop Grant States The AMD Athlon processor model 4 enters the Stop Grant state upon recognition of assertion of STPCLK# input. or an interrupt via the INTR or NMI pins. 10 Power Management Chapter 4 . probes are allowed. There are two mechanisms for asserting STPCLK#—hardware and software. In C2. as shown in Figure 3 on page 9. Note: In all power management states. This task is accomplished by asserting the THERM# input to the Southbridge. If an ACPI Thermal Zone is defined for the processor. The Southbridge can force STPCLK# assertion for throttling to protect the processor from exceeding its maximum case temperature. The processor enters the P ro b e s t a t e t o s e rv i c e c a ch e s n o o p s i n i t i a t e d by t h e Northbridge during Stop Grant for C2 or throttling. the processor issues a Halt special cycle to the system bus. the system must not disable the system clock (SYSCLK/SYSCLK#) to the processor. When the AMD Athlon processor model 4 executes the HLT instruction. or via a local APIC interrupt message. Throttling asserts STPCLK# for a percentage of a predefined throttling period: STPCLK# is repetitively asserted and deasserted until the THERM# pin is deasserted. SMI#. The Halt state is exited when the processor detects the assertion of INIT#. The Phase-Lock Loop (PLL) continues to run. Working State Halt State The Working state refers to the state in which the processor is executing instructions. Software can force the processor into the Stop Grant state by accessing ACPI-defined registers typically located in the Southbridge. The processor enters a lower power state if the system logic (Northbridge) disconnects the AMD Athlon system bus in response to the Halt special cycle. Software places the processor in C2 by reading the PLVL_2 register in the Southbridge. the OS can initiate throttling with STPCLK# using the ACPI defined P_CNT register in the Southbridge. RESET#.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 The following paragraphs descr ibe each of the powe r management states.

After recognizing the assertion of STPCLK#. Probe State The Probe state is entered when the Northbridge initiates an AMD Athlon system bus connect as required to probe the processor. the processor initiates a connection of the AMD Athlon system bus if it is disconnected. the AMD Athlon processor model 4 completes all pending and in-progress bus cycles and acknowledges the STPCLK# assertion by issuing a Stop Grant special bus cycle to the AMD Athlon system bus. The processor responds to a probe cycle in the Probe state in the same way it does during the Working state. When the probe has been serviced. The Stop Grant state is exited upon the deassertion of STPCLK# or the assertion of RESET#. the Northbridge must initiate a system bus connection before it probes the processor to snoop the caches of the processor . INTR. After the processor enters the Working state. When STPCLK# is deasserted. If RESET# is sampled asserted during the Stop Grant state. the processor enters a low-power state dictated by the CLK_Ctl register. During the S1 sleep state. any pending interrupts are recognized and serviced and the processor resumes execution at the instruction boundary where STPCLK# was initially recognized. Once in the Halt or Stop Grant state. and SMI#.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet The Stop Grant state is also entered for the S1 system sleep state based on a write to the SLP_TYP field in the ACPI-defined power management 1 control register. If the processor has been disconnected from the system bus. Chapter 4 Power Management 11 . During the Stop Grant states. system software ensures no bus master or probe activity occurs. the processor returns to the same state as when it entered the Probe state (Halt or Stop Grant state). the processor latches INIT#. NMI. the processor returns to the Working state and the reset process begins. a low-power s t a t e i s o n ly a ch i eve d i f t h e N o r t h b r i d g e i n i t i a t e s a disconnection from the system bus. or a local APIC interrupt message if they are asserted. After the Northbridge disconnects the AMD Athlon system bus in response to the Stop Grant special bus cycle.

PROCRDY. The processor detects the deassertion of CONNECT on a rising edge of SYSCLK. If the Northbridge requires the processor to service a probe after the system bus has been disconnected. The option of disconnecting is controlled by an enable bit in the Northbridge. Reconnect is initiated by the processor in response to an interrupt for Halt. or by the Northbridge to service a probe. the Northbridge asserts CLKFWDRST in anticipation of reestablishing a connection at some later point. if there are no outstanding probes or data movements. Note: The Northbridge must disconnect the processor from the AMD Athlon system bus before issuing the Stop Grant special cycle to the PCI bus. and deasserts PROCRDY to the Northbridge. Connect Protocol In addition to the legacy STPCLK# signal and the Halt and Stop Grant special cycles. When the Northbridge receives the Halt or Stop Grant special cycle from the processor and.2 Connect and Disconnect Protocol Significant power savings of the AMD Athlon processor model 4 only occurs if the processor is disconnected from the system bus by the Northbridge while in the Halt or Stop Grant state. the AMD Athlon system bus connect protocol includes the CONNECT. In return. or passing the Stop Grant special cycle to the Southbridge for systems that connect to the Southbridge with HyperTransport™ technology. it must first initiate a system bus connect. This note applies to current chipset implementation: alternate chipset implementations that do not require this are possible. and CLKFWDRST signals and a Connect special cycle. the Northbridge deasserts CONNECT a minimum of eight SYSCLK periods after the last command sent to the processor. AMD Athlon system bus disconnects are initiated by the Northbridge in response to the receipt of a Halt or Stop Grant special cycle. 12 Power Management Chapter 4 . STPCLK# deassertion. The Northbridge can optionally initiate a bus disconnect upon the receipt of a Halt or Stop Grant special cycle. The Northbridge contains BIOS programmable registers to enable the system bus disconnect in response to Halt and Stop Grant special cycles.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 4.

rather than continuing with the disconnect sequence. the processor enters the Stop Grant State. Figure 4 shows the sequence of events from a Northbridge perspective. see the AMD Athlon™ and AMD Duron™ System Bus Specification . the Northbridge cancels the disconnect request.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Note: In response to Halt special cycles. In response to the Connect special cycle. The system is required to assert the CONNECT signal before returning the C-bit for the connect special cycle (assuming CONNECT has been deasserted). When the processor recognizes STPCLK# asserted. The processor can receive an interrupt after it sends a Halt special cycle. the processor sends the Connect special cycle to the Northbridge. 2. STPCLK# System!Bus CONNECT PROCRDY CLKFWDRST PCI!Bus Stop!Grant Stop!Grant Figure 4. the Northbridge passes the Halt special cycle to the PCI bus or Southbridge immediately. Chapter 4 Power Management 13 . order# 21902 for the definition of the C-bit and the Connect special cycle. which leads to disconnecting the processor from the AMD Athlon system bus and placing the processor in the Stop Grant state. In this case. Example of an AMD Athlon™ System Bus Disconnect Sequence The following sequence of events describes how the processor is placed in the Stop Grant state when bus disconnect is enabled within the Northbridge: 1. The Southbridge asserts STPCLK# to place the processor in the Stop Grant state. then issues a Stop Grant special cycle on the AMD Athlon system bus. For more information. or STPCLK# deassertion after it sends a Stop Grant special cycle to the Northbridge but before the disconnect actually occurs.

The Northbridge asserts CONNECT. After the processor is disconnected from the bus. reconnect the processor to the AMD Athlon system bus. which synchronizes the forwarded clocks between the processor and the Northbridge. it asserts PROCRDY. 5. Figure 5 shows the signal sequence of events that take the processor out of the Stop Grant state. 14 Power Management Chapter 4 . Exiting Stop Grant State/Bus Reconnect Sequence The following sequence of events removes the processor from the Stop Grant state and reconnects it to the AMD Athlon system bus: 1. the Northbridge passes the Stop Grant special cycle to the Southbridge. 3. When the Stop Grant special cycle is received by the Northbridge and no probe traffic is pending. the Northbridge deasserts CONNECT. notifying the Northbridge to reconnect to the bus. STPCLK# PROCRDY CONNECT CLKFWDRST Figure 5. The Northbridge finally deasserts CLKFWDRST. 4. The processor responds to the Northbridge by deasserting PROCRDY. 4. The Southbridge deasserts STPCLK# in response to a resume event. 6. initiating a bus disconnect to the processor. and put the processor into the Working state. 2. The Northbridge asserts CLKFWDRST to complete the bus disconnect sequence. When the processor recognizes STPCLK# deassertion.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 3. acknowledging the bus disconnect request.

Although reconnected to the system interface. respectively. Northbridge Connect State Diagram Chapter 4 Power Management 15 . the 8 Northbridge must not issue any non-NOP SysDC commands for a minimum of four SYSCLK periods after deasserting CLKFWDRST. 4/A 2/A Disconnect Pending 3/C 5/B 8 Connect 1 Disconnect Requested 3 8 Disconnect 7/D.C Reconnect Pending Probe Pending 2 6/C Probe Pending 1 7/D Condition 1 A disconnect is requested and probes are still pending 2 A disconnect is requested and no probes are pending 3 A CONNECT special cycle from the processor 4 No probes are pending 5 PROCRDY is deasserted 6 A probe needs service 7 PROCRDY is asserted Three SYSCLK periods after CLKFWDRST is deasserted.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Connect State Diagram Figu re 6 be low and Figure 7 on pa ge 16 d escrib e t h e Northbridge and processor connect state diagrams. A Action Deassert CONNECT eight SYSCLK periods after last SysDC sent B Assert CLKFWDRST C Assert CONNECT D Deassert CLKFWDRST Figure 6.

6 Forward clocks start three SYSCLK periods after CLKFWDRST is deasserted. Processor wake-up event or CONNECT asserted by 4 Northbridge.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Connect 1 2/B 6/B Connect Pending 2 5 Connect Pending 1 Disconnect Pending 3/A Disconnect 4/C Condition 1 2 CONNECT is deasserted by the Northbridge (for a previously sent Halt or Stop Grant special cycle). Figure 7. Processor receives a wake-up event and must cancel the disconnect request. If the AMD Athlon system bus is connected so the Northbridge can probe the processor a Connect special cycle is not issued at that time (it is only issued after a subsequent processor wake-up event). Action A CLKFWDRST is asserted by the Northbridge. B Issue a CONNECT special cycle.* C Return internal clocks to full speed and assert PROCRDY * The Connect special cycle is only issued after a 3 Deassert PROCRDY and slow down internal clocks. Processor Connect State Diagram 16 Power Management Chapter 4 . processor wake-up event (interrupt or STPCLK# deassertion) occurs. 5 CLKFWDRST is deasserted by the Northbridge.

and Debug Developers Guide.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 4.3 Clock Control The processor implements a Clock Control (CLK_Ctl) MSR (address C001_001Bh) that determines the internal clock divisor when the AMD Athlon system bus is disconnected. Software. order# 21656. for more details on the CLK_Ctl register. Chapter 4 Power Management 17 . Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS.

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 18 Power Management Chapter 4 .

a n d t h e c o o l i n g g u i d e l i n e s o n www.6 W 49.75 V 62.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 5 Thermal Design For information about thermal design for the AMD Athlon™ processor model 4.8 W 72.3 W 69.0 W 53.com.1 W 65. and Chassis Cooling Design G u i d e .1 W 45.1 W 55. including layout and airflow considerations.9 W 60.1 W 61.1 W 55.amd.1 W 60. The thermal design power represents the maximum sustained power dissipated while executing publicly available software or instruction sequences under normal system operation at nominal VCC_CORE.3 W 62.7 W 58.7 W 95ºC 90ºC Frequency (MHz) 900 950 1000 1100 1133 1200 1266 1300 1333 1400 Chapter 5 Thermal Design 19 . see the AMD Thermal. o rd e r # 2 3 7 9 4 .5 W 54. Table 1 shows the thermal design power. Mechanical.6 W 64.8 W 47. Thermal Design Power Nominal Voltage Maximum Thermal Typical Thermal Max Die Power Power Temperature 51.7 W 66. Table 1.3 W 1.9 W 68. Thermal solutions must monitor the processor temperature to prevent the processor from exceeding its maximum die temperature.

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 20 Thermal Design Chapter 5 .

type. Chapter 6 CPUID Support 21 . see the AMD Processor Recognition Application Note .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 6 CPUID Support AMD Athlon™ processor model 4 version and feature set recognition can be performed through the use of the CPUID instruction that provides complete information about the processor—vendor. Software can make use of this information to accurately tune the system for maximum performance and benefit to users. name. and its capabilities. etc. order# 20734. For information on the use of the CPUID instruction..

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 22 CPUID Support Chapter 6 .

Preliminary Information
23792K—November 2001

AMD Athlon™ Processor Model 4 Data Sheet

7
7.1

Electrical Data
Conventions
The conventions used in this chapter are as follows:

Current specified as being sourced by the processor is negative. Current specified as being sunk by the processor is positive.

7.2

Interface Signal Groupings
The electrical data in this chapter is presented separately for each signal group. Table 2 defines each group and the signals contained in each group.

Table 2.

Interface Signal Groupings
Signals VID[4:0], VCC_CORE, VCCA, COREFB, COREFB# Notes See “Voltage Identification (VID[4:0])” on page 24, “VID[4:0] Pins” on page 65, and “VCCA AC and DC Characteristics” on page 25. See “Frequency Identification (FID[3:0])” on page 24 and “FID[3:0] Pins” on page 61. See “SYSCLK and SYSCLK# DC Characteristics” on page 28. See “AMD Athlon™ System Bus AC and DC Characteristics” on page 30. See “General AC and DC Characteristics” on page 32. See “General AC and DC Characteristics” on page 32. See “APIC Pins AC and DC Characteristics” on page 34 and “APIC Pins, PICCLK, PICD[1:0]#” on page 60

Signal Group Power

Frequency System Clocks

FID[3:0] SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and RSTCLK/RSTCLK#), PLLBYPASSCLK#, PLLBYPASSCLK

SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, AMD Athlon™ SADDOUTCLK#, SFILLVAL#, SDATAINVAL#, System Bus SDATAOUTVAL#, SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, CLKFWDRST, PROCRDY, CONNECT Southbridge JTAG APIC RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#, STPCLK#, FLUSH# TMS, TCK, TRST#, TDI, TDO PICD[1:0]#, PICCLK

Chapter 7

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Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet
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Table 2.

Interface Signal Groupings (continued)
Signals PLLTEST#, PLLMON1, PLLMON2, SCANCLK1, SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG Notes See “General AC and DC Characteristics” on page 32. See “General AC and DC Characteristics” on page 32.

Signal Group Test

Miscellaneous DBREQ#, DBRDY, PWROK, PLLBYPASS#

7.3

Voltage Identification (VID[4:0])
Table 3 shows the VID[4:0] DC characteristics. For more information, see “VID[4:0] Pins” on page 65.

Table 3.
Parameter IOL VOH
Note:

VID[4:0] DC Characteristics
Description Output Current Low Output High Voltage Min 16 mA 2.625 V * Max

*

The VID pins must not be pulled above this voltage by an external pullup resistor.

7.4

Frequency Identification (FID[3:0])
Table 4 shows the FID[3:0] DC characteristics. For more information, see “FID[3:0] Pins” on page 61.

Table 4.
IOL VOH
Note:

FID[3:0] DC Characteristics
Description Output Current Low Output High Voltage Min 16 mA 2.625 V * Max

Parameter

*

The FID pins must not be pulled above this voltage by an external pullup resistor.

24

Electrical Data

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AMD Athlon™ Processor Model 4 Data Sheet

7.5

VCCA AC and DC Characteristics
Table 5 shows the AC and DC characteristics for VCCA. For more information, see “VCCA Pin” on page 65.

Table 5.
Symbol VVCCA IVCCA
Notes:

VCCA AC and DC Characteristics
Parameter VCCA Pin Voltage VCCA Pin Current Min 2.25 0 Nominal 2.5 Max 2.75 50 Units V mA/GHz Notes 1 2

1. Minimum and maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted. 2. Measured at 2.5 V.

7.6

Decoupling
See the AMD Athlon™ Processor-Based Motherboard Design Guide , order# 24363, or contact your local AMD office for information about the decoupling required on the motherboard for use with the AMD Athlon™ processor model 4.

7.7

Operating Ranges
The AMD Athlon processor model 4 is designed to provide functional operation if the voltage and temperature parameters are within the limits defined in Table 6.

Table 6.
VCC_CORE

Operating Ranges
Description Processor core supply Temperature of processor die 900-1400 MHz Processor core supply in Sleep state Min 1.65 V 1.2 V Nominal 1.75 V 1.3 V Max 1.85 V 1.4 V 95ºC Notes 1 2 3

Parameter VCC_CORESLEEP TDIE
Notes:

1. For normal operating conditions (nominal VCC_CORE is 1.75 V). 2. Sleep Voltage can be used for the S1 sleep state. For more information see the AMD Athlon™ and AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656. 3. Die temperature is 90ºC for frequencies of 1100 MHz and lower.

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Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet
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7.8

Absolute Ratings
The AMD Athlon processor model 4 should not be subjected to conditions exceeding the absolute ratings listed in Table 7, as such conditions can adversely affect long-term reliability or result in functional damage.

Table 7.
VCC_CORE VCCA VPIN TSTORAGE

Absolute Ratings
Description AMD Athlon™ Processor Model 4 core supply AMD Athlon Processor Model 4 PLL Supply Voltage on any signal pin Storage temperature of processor Min –0.5 V –0.5 V –0.5 V –40ºC Max VCC_CORE Max + 0.5 V VCCA Max + 0.5 V VCC_CORE Max + 0.5 V 100ºC

Parameter

26

Electrical Data

Chapter 7

3 A 39. Measured at Nominal voltage of 1.9 A 41.2 A 30.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 7.5 A 34.5 A 1.0 A 39.75 V 1.75 V.9 VCC_CORE Voltage and Current Table 8 shows the power and current of the processor during normal and reduced power states.2 A 95°C 90°C Die Temperature Frequency (MHz) 900 950 1000 1100 1133 1200 1266 1300 1333 1400 Notes: 1. VCC_CORE Voltage and Current Nominal Voltage Maximum Voltage Stop Grant (Maximum)1 Maximum ICC (Power Supply Current)2 29. Chapter 7 Electrical Data 27 .5 A 37. The BIOS must program the CLK_Ctrl MSR to fff0_d22fh for the AMD Athlon™ Processor Model 4. Measured at 1. 2.85 V 5W 35.3 V for Sleep state operating conditions.5 A 38.3 A 31. Table 8.

Figure 8 shows the waveforms of the SYSCLK and SYSCLK# signals. The SYSCLK signal represents CLKIN and RSTCLK tied together while the SYSCLK# signal represents CLKIN# and RSTCLK# tied together.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 7.10 SYSCLK and SYSCLK# AC and DC Characteristics Table 9 shows the DC characteristics of the SYSCLK and SYSCLK# differential clocks. Table 9. SYSCLK and SYSCLK# Differential Clock Signals 28 Electrical Data Chapter 7 . Symbol SYSCLK and SYSCLK# DC Characteristics Description Min 400 450 —1 1 VCC_CORE/2 +/– 100 4 12 Max Units mV mV mA mA mV pF VThreshold-DC Crossing before transition is detected (DC) VThreshold-AC Crossing before transition is detected (AC) ILEAK_P ILEAK_N VCROSS CPIN Leakage current through P-channel pullup to VCC_CORE Leakage current through N-channel pulldown to VSS (Ground) Differential signal crossover Capacitance VCROSS VThreshold-DC = 400mV VThreshold-AC = 450mV Figure 8.

8 133 30% 7. as measured into a 10 or 20-pF load must be less than 500 kHz.05 2 2 Max @ 100 70% 133 70% Units MHz Notes Period High Time Low Time Fall Time Rise Time Period Stability ns ns ns 2 2 ns ns ps 1.05 1. 2 ± 300 ± 300 1. Circuitry driving the SYSCLK and SYSCLK# inputs can purposely alter the SYSCLK and SYSCLK# period (spread spectrum clock generators).8 1. SYSCLK and SYSCLK# AC Characteristics Symbol Parameter Description Clock Frequency Duty Cycle t1 t2 t3 t4 t5 Notes: Min @ 100 30% 10 1. 2. In no cases can the SYSCLK and SYSCLK# period violate the minimum specification above. t2 VCROSS VThreshold-AC t3 t5 t1 t4 Figure 9. Circuitry driving the SYSCLK and SYSCLK# inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL to track the jitter.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Table 10 shows the SYSCLK/SYSCLK# differential clock AC characteristics of the AMD Athlon processor model 4. Table 10. The –20 dB attenuation point. SYSCLK and SYSCLK# inputs can vary from 100% of the specified period to 99% of the specified period at a maximum rate of 100 kHz. SYSCLK Waveform Chapter 7 Electrical Data 29 .5 1. Figure 9 shows a sample waveform.

SYSCLK connects to CLKIN/RSTCLK.5*VCC_CORE) –50 +50 –100 +100 VCC_CORE + 500 VREF – 200 VCC_CORE+500 400 IVREF_LEAK_P VREF Tristate Leakage Pullup IVREF_LEAK_N VREF Tristate Leakage Pulldown VIH VIL VOH VOL ILEAK_P ILEAK_N CIN Notes: µA µA mV mV mV mV mA mA pF 3 2 2 Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Input Pin Capacitance 1. VREF must be created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the ± 50 mV specification listed above.11 AMD Athlon™ System Bus AC and DC Characteristics Table 11 shows the DC characteristics of the AMD Athlon system bus used by the AMD Athlon processor model 4. Specified at TDIE given in Table 6. For more information. and SYSCLK#. 2. VREF is nominally set to 50% of VCC_CORE with actual values that are specific to motherboard design implementation.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 7. The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK. SYSCLK# connects to CLKIN#/RSTCLK#. see Table 17 on page 46 . Table 11. and VCC_CORE in Table 8.85*VCC_CORE –500 –1 +1 12 Condition Min Max Units Notes mV 1 (0.5*VCC_CORE) (0. AMD Athlon™ System Bus DC Characteristics Symbol VREF Parameter DC Input Reference Voltage VIN = VREF Nominal VIN = VREF Nominal VREF + 200 –500 IOUT = –200µA IOUT = 1 mA VIN = VSS (Ground) VIN = VCC_CORE Nominal 4 0. 30 Electrical Data Chapter 7 . 3.

5 4. Chapter 7 Electrical Data 31 . Test Load is 25 pF. AMD Athlon™ System Bus AC Characteristics Group All Signals Symbol TRISE TFALL TSKEWSAMEEDGE TSKEWForward Clocks DIFFEDGE Parameter Output Rise Slew Rate Output Fall Slew Rate Output skew with respect to the same clock edge Output skew with respect to a different clock edge Input Data Setup Time Input Data Hold Time Capacitance on input Clocks Capacitance on output Clocks RSTCLK to Output Valid Setup to RSTCLK Hold from RSTCLK Min 1 1 Max 3 3 385 770 Units V/ns V/ns ps ps ps ps Notes 1 1 2 2 3 3 TSU THD CIN COUT T VAL 300 300 4 4 250 500 1000 12 12 2000 pF pF ps ps ps 4. The synchronous signals include PROCRDY. TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock. Rise and fall time ranges are guidelines over which the I/O has been characterized. THD is hold of CONNECT/CLKFWDRST from rising edge of RSTCLK. 4. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. and CLKFWDRST. as measured at the package. 6 4. as measured at the package. with respect to different clock edges. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet The AC characteristics of the AMD Athlon system bus are shown in Table 12. Table 12. CONNECT. 2. 3. The parameters are grouped based on the source or destination of the signals involved. 6 Sync Notes: TSU THD 1. 5. TSKEW-SAMEEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock. with respect to the same clock edge. T VAL is RSTCLK rising edge to output valid for PROCRDY. 6.

The approximate value for standard case in normal mode operation. the signal must persist for this time to ensure capture. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins. Scale parameters between VCC_CORE Min and VCC_CORE Max. 13.0 40. divisors.12 General AC and DC Characteristics Table 13 shows the AMD Athlon processor model 4 AC and DC ch a ra c t e r i s t i c s o f t h e S o u t h b r i d g e .Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 7. 32 Electrical Data Chapter 7 . 11. J TAG . 4.1 µA mA mA ns ps ns ns ns 3 3 4. 5. LowPower mode. 3. 5 5 7. Table 13. Reassertions of the signal within this time are not guaranteed to be seen by the core. This value assumes RSTCLK and K7CLKOUT are running at the same frequency.0 0. respectively. 2. 10. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase. a n d miscellaneous pins.0 20.2 1. 6. This value assumes RSTCLK period is 10ns ==> TBIT = 2*fRST. 8. t e s t .2 VIN = VSS (Ground) VIN = VCC_CORE Nominal –1 600 –16 16 2. In asynchronous operation. 9. These are aggregate numbers. 5 4. and core frequency. This value is dependent on RSTCLK frequency. IOL and IOH are measured at VOL max and VOH min. though the processor is capable of other configurations. 12. Characterized across DC supply voltage range.0 0.8 9–13 1. Values specified at nominal VCC_CORE. General AC and DC Characteristics Symbol VIH VIL VOH VOL ILEAK_P ILEAK_N IOH IOL TSU THD TDELAY TBIT TRPT Notes: Parameter Description Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Output High Current Output Low Current Sync Input Setup Time Sync Input Hold Time Output Delay with respect to RSTCLK Input Time to Acquire Input Time to Reacquire Condition Min (VCC_CORE/2) + 200mV –300 VCC_CORE – 400 –300 Max VCC_CORE + 300mV 350 VCC_CORE + 300 400 Units V mV mV mV mA Notes 1. 7.0 6. Edge rates indicate the range over which inputs were characterized.

0 1. 4. Chapter 7 Electrical Data 33 . Values specified at nominal VCC_CORE. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase. In asynchronous operation. 7. 6. divisors. 10. General AC and DC Characteristics (continued) Symbol TRISE TFALL CPIN Notes: Parameter Description Signal Rise Time Signal Fall Time Pin Capacitance Condition Min 1.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Table 13.0 12 Units V/ns V/ns pF Notes 6 6 1. IOL and IOH are measured at VOL max and VOH min. 3. 11. the signal must persist for this time to ensure capture.0 4 Max 3. though the processor is capable of other configurations.0 3. 13. 5. This value assumes RSTCLK and K7CLKOUT are running at the same frequency. 9. 12. Characterized across DC supply voltage range. respectively. Edge rates indicate the range over which inputs were characterized. This value assumes RSTCLK period is 10ns ==> TBIT = 2*fRST. Reassertions of the signal within this time are not guaranteed to be seen by the core. 2. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins. The approximate value for standard case in normal mode operation. 8. and core frequency. Scale parameters between VCC_CORE Min and VCC_CORE Max. LowPower mode. This value is dependent on RSTCLK frequency. These are aggregate numbers.

5 V VOL Max 12 1. APIC Pins AC and DC Characteristics Symbol VIH VIL VOH VOL ILEAK_P ILEAK_N IOL TRISE TFALL CPIN Notes: Parameter Description Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Output Low Current Signal Rise Time Signal Fall Time Pin Capacitance Condition Min 1. 2. Table 14.625 700 2.0 12 mA mA V/ns V/ns pF 4 4 1.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 7. 2 3 –300 VIN = VSS (Ground) VIN = 2.0 1.625 Units V mV V mV mA Notes 1. Characterized across DC supply voltage range. Scale parameters with VDD.7 –300 Max 2. 4.13 APIC Pins AC and DC Characteristics Table 14 shows the AMD Athlon processor model 4 AC and DC characteristics of the APIC pins.0 4 –1 400 1 3. 3. Values specified at nominal VDD (1.5 V). 34 Electrical Data Chapter 7 . 3 1.625 V = 2. 2.0 3.5 V + 5% maximum Edge rates indicate the range over which inputs were characterized.

2. 8. Chapter 8 Signal and Power-Up Requirements 35 . Signal Relationship Requirements During Power-Up Sequence Notes: 1. Figure 10 represents several signals generically by using names not necessarily consistent with any pin lists or schematics.1 Power-Up Requirements Figure 10 shows the relationship between key signals in the system during a power-up sequence. This figure details the requirements of the processor. Requirements 1-6 in Figure 10 are described in “Power-Up Timing Requirements” on page 36. Signal Sequence and Timing Description 3.5V) (for PLL) VCC_CORE (Processor Core) RESET# 1 NB_RESET# 4 2 6 PWROK 5 3 System Clock Figure 10.3V Supply VCCA (2.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 8 Signal and Power-Up Requirements This chapter describes the AMD Athlon™ processor model 4 power-up requirements during system power-up and warm resets.

VCC_CORE. 1. After PWROK is asserted. It is recommended that RESET# be asserted at least 10 ns prior to the assertion of PWROK. The motherboard is required to delay PWROK assertion for a minimum of three milliseconds from the 3. VCC_CORE. In practice VCCA. 36 Signal and Power-Up Requirements Chapter 8 .3 V supply being within specification. RESET# must be asserted before PWROK is asserted. The processor core voltage. All motherboard voltage planes must specification before PWROK is asserted. be within PWROK is an output of the voltage regulation circuit on the motherboard. The AMD Athlon processor PLL is powered by VCCA. PWROK indicates that VCC_CORE and all other voltage planes in the system are within specification. and all other voltage planes must be within specification be for several milliseconds before PWROK is asserted. T h e f o l l o w i n g s i g n a l t i m i n g requirements correspond to numbers 1-6 in Figure 10 on page 35. In practice. VCCA must be within spec at least five microseconds before PWROK is asserted. The AMD Athlon processor model 4 does not set the correct clock multiplier if PWROK is asserted prior to a RESET# assertion. must be within specification as dictated by the VID[4:0] pins driven by the processor before PWROK is asserted. the processor PLL locks to its operational frequency. This ensures that the system clock (SYSCLK/SYSCLK#) is operating within specification when PWROK is asserted. the AMD Athlon processor is clocked by a ring oscillator. Southbridges assert RESET# milliseconds before PWROK is deasserted. The processor PLL does not lock if VCCA is not high enough for the processor logic to switch for some period before PWROK is asserted.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Power-Up Timing Requirements. Before PWROK assertion. 2.

When PWROK is asserted. 5. AMD Southbridges enforce a delay of 1. The SIP is Chapter 8 Signal and Power-Up Requirements 37 .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 3. The PLL lock time may take from hundreds of nanoseconds to tens of microseconds. For more information. The duration of RESET# assertion during cold boots is intended to satisfy the time it takes for the PLL to lock with a less than 1-ns phase error. The chipset uses this FID information and other information sampled at the deassertion of RESET# to determine the correct Serial Initialization Packet (SIP) to send to the processor for configuration of the AMD system bus for the clock multiplier processor frequency indicated by the FID[3:0] code.0 ms. 4.0 milliseconds between PWRGD (Southbridge version of PWROK) assertion and NB_RESET# deassertion.3 V has been within specification for three milliseconds. It is recommended that the minimum time between PWROK assertion to the deassertion of RESET# be at least 1. The processor PLL begins to run after PWROK is asserted and the internal clock grid is switched from the ring oscillator to the PLL. 6. PWROK must be monotonic. If NB_RESET# does not assert until after RESET# has deasserted. see “FID[3:0] Pins” on page 61. The processor should not switch between the ring oscillator and the PLL after the initial assertion of PWROK. the processor misinterprets the CONNECT assertion (due to NB_RESET# being asserted) as the beginning of the SIP transfer (See “Serial Initialization Packet (SIP) Protocol” on page 38). There must be sufficient overlap in the resets to ensure that CONNECT is sampled asserted by the processor before RESET# is deasserted. The reference system clock should be valid at this time. the chipset samples the FID[3:0] frequency ID from the processor in a chipset-specific manner. NB_RESET# must be asserted (causing CONNECT to also assert) before RESET# is deasserted. In practice all Southbridges enforce this requirement. The system clock (SYSCLK/SYSCLK#) must be running within specification before PWROK is asserted. The system clocks are guaranteed to be running after 3.5 to 2. PWROK assertion to deassertion of RESET#. Clock Multiplier Selection (FID[3:0]) When RESET# is deasserted. the processor switches from driving the internal processor clock grid from the ring oscillator to driving from the PLL.

RESET# to the Northbridge is the same in as PCI RESET#.5 to 2.0 milliseconds. This protocol uses the PROCRDY. AMD Southbridges enforce a minimum assertion of RESET# to the processor. or PCI of 1. CONNECT. The AMD Athlon™ Processor Model 4 and Northbridge Reset Pins 38 Signal and Power-Up Requirements Chapter 8 .Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 sent to the processor using the SIP protocol. order# 21902 for details of the SIP protocol. Serial Initialization Packet (SIP) Protocol Refer to AMD Athlon™ and AMD Duron™ System Bus Specification. 8. The minimum assertion for PCI RESET# is one millisecond. and CLKFWDRST signals. Northbridge. which are synchronous to SYSCLK.2 Processor Warm Reset Requirements RESET cannot be asserted to the processor without also being asserted to the Northbridge.

2 Die Loading The processor die on the CPGA package is exposed at the top of the package. order# 24363. 9.Any heat sink design should avoid loads on corners and edges of die. see the AMD Athlon™ Processor-Based Motherboard Design Guide. Chapter 9 Mechanical Data 39 . Load specified for coplanar contact to die surface. This is done to facilitate heat transfer from the die to an approved heat sink. Table 15.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 9 9. It is critical that the mechanical loading of the heat sink does not exceed the limits shown in Table 15. CPGA Mechanical Loading Location Die Surface Die Edge Notes: Dynamic (MAX) 100 10 Static (MAX) 30 10 Units lbf lbf Note 2 3 1. 2. Load defined for a surface at no more than a two degree angle of inclination to die surface.1 Mechanical Data Introduction The AMD Athlon™ processor model 4 connects to the motherboard through a PGA socket named Socket A and utilizes the Ceramic Pin Grid Array (CPGA) package type described in “AMD Athlon™ Processor Model 4 CPGA Package Dimensions” on page 40. Tool-assisted zero-insertion force sockets should be designed such that no load is placed on the ceramic substrate of the package. The CPGA package has compliant pads that serve to bring surfaces in planar contact. For more information.

88 – 1.35 2.50 φP φb φb1 S L M N e e1 * Dimensions are given in millimeters.79 REF – 2.31 4.116 – – 0.33 11.80 14.375 3.25 14.60 0.66 7.24 REF 1.52 3.54 BSC 1. Table 16.27 BSC 2.50 1.78 10.27 9.30 10.25 7.96 49.15 10.43 – 1.80 7.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 9.35 7.27 0.80 0.05 37 453 1.19 6.42 10.05 2.72 BSC Letter or Symbol E11 G/H A A1 A2 A3 A4 Minimum Maximum Dimension* Dimension* 5.90 6.53 0.10 REF 3.60 11. 40 Mechanical Data Chapter 9 .41 14.39 1.63 2.31 REF 3.64 5.64 10.07 3.78 45.65 7. Dimensions for the AMD Athlon™ Processor Model 4 CPGA Package Letter or Symbol D/E D1/E1 D2 D3 D4 D5 D6 D7 D8 E3 E4 E5 E6 E7 E8 E9 E10 Note: Minimum Maximum Dimension* Dimension* 49. Table 16 provides the dimensions in millimeters assigned to the letters and symbols shown in the Figure 11 diagram.84 1.96 15.435 3.19 11.3 AMD Athlon™ Processor Model 4 CPGA Package Dimensions Figure 11 on page 41 shows a diagram and notes for the AMD Athlon processor model 4 CPGA package.

AMD Athlon™ Processor Model 4 CPGA Package Chapter 9 Mechanical Data 41 .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Figure 11.

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 42 Mechanical Data Chapter 9 .

Chapter 10 Pin Descriptions 43 .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 10 10. Table 17 on page 46 lists all the pins in alphabetical order by pin name. Figure 13 on page 45 show s the bottomside view of the array. along with the abbreviation where necessary. Because some of the pin names are too long to fit in the grid.1 Pin Descriptions Pin Diagram and Pin Name Abbreviations Figure 12 on page 44 shows the staggered Ceramic Pin Grid Array (CPGA) for the AMD Athlon™ processor model 4. they are abbreviated.

44 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 A SAO#3 VCC SAO#2 VCC SAO#6 NC KEY NC VID[4] NC VID[3] VCC KEY VSS VCC NC VCC NC VSS NC VCC NC VSS KEY VCC VSS NC VSS VCC_Z NC VSS_Z NC KEY NC NC NC NC NC NC 6 7 8 9 10 11 SAO#12 VSS SD#54 VSS SD#52 VSS NC NC NC NC NC VSS NC VCC SD#24 VSS NC VCC NC VSS NC VCC NC VSS SD#8 VCC NC NC NC NC COREFB VCC NC VCC NC VCC NC NC 12 SAO#5 VCC SDOC#3 VCC SD#50 VCC NC VCC SD#19 VCC SD#26 VSS SD#25 VCC SD#17 VSS SD#7 VCC SD#5 VSS SDIC#0 VCC NC VSS SD#0 VCC SD#10 VSS SAI#5 VCC NC VSS NC VCC PLMN2 VSS PLMN1 13 14 SD#55 VSS NC VSS SD#49 VSS KEY VSS VCC VSS VCC VSS VCC VSS NC NC NC VSS SDIC#1 VCC NC VSS SD#27 VCC SD#16 VSS SD#15 VCC SD#4 VSS SD#2 VCC SD#3 VSS SD#13 VCC SD#14 VSS SDOC#0 VSS NC VCC NC VSS PLBYC# VCC PLBYC 15 16 SD#61 VCC SD#51 VCC SDIC#3 VCC NC NC KEY NC NC NC SD#20 VSS VCC VSS VCC VSS VCC NC VCC VCC SD#23 VSS SD#29 VCC SD#28 VSS SD#18 SD#48 SD#58 SD#36 SD#46 NC SDIC#2 SD#33 SD#32 NC SD#31 VCC SD#21 VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS SD#22 SD#60 SD#59 SD#56 SD#37 SD#47 SD#38 SD#45 SD#43 SD#42 SD#41 SDOC#1 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC SD#53 SD#63 SD#62 NC SD#57 SD#39 SD#35 SD#34 SD#44 NC SDOC#2 SD#40 SD#30 A B C D E F G H J K L M N P Q B VSS VCC VSS C SAO#7 SAO#9 SAO#8 D VCC VCC VSS E SAO#11 SAOC# SAO#4 F VSS VSS VSS G SAO#10 SAO#14 SAO#13 H VCC VCC NC J SAO#0 SAO#1 NC K VSS VSS VSS L VID[0] VID[1] VID[2] M VCC VCC VCC N PICCLK PICD#0 PICD#1 P VSS VSS VSS AMD Athlon™ Processor Model 4 Data Sheet Q TCK TMS SCNSN R VCC VCC VCC VSS SD#6 VCC NC VSS SD#1 VCC SD#12 R S T U V W X Y Z AA VCC SD#11 VSS SD#9 S SCNCK1 SCNINV SCNCK2 T VSS VSS VSS U TDI TRST# TDO V VCC VCC VCC W FID[0] FID[1] VREF_S AMD Athlon™ Processor Model 4 Topside View Preliminary Information Pin Descriptions VSS COREFB# VSS NC VSS NC ANLOG VCC KEY VCC VSS VCC NC VSS NC VCC CLKIN# VSS CLKIN 17 18 X VSS VSS VSS Y FID[2] FID[3] NC Z VCC VCC VCC AA DBRDY DBREQ# SVRFM AB VSS VSS VSS AB AC AD AE VSS NC VCC CLKFR VSS VCC VCCA VSS VSS PLBYP# VCC VCC NC VSS VSS SAI#0 VCC VCC NC KEY NC SFILLV# VSS NC NC VSS SAIC# VCC NC SAI#2 VSS SAI#6 VCC VCC SAI#11 VSS SAI#3 VCC SAI#7 AC STPC# PLTST# ZN AD VCC VCC VCC AE A20M# PWROK ZP AF VSS VSS NC AF AG AH AJ AK RCLK# VCC RCLK 19 20 AG FERR RESET# NC AH VCC VCC AMD AJ IGNNE# INIT# VCC AK VSS VSS CPR# AL INTR FLUSH# VCC K7CO VSS K7CO# 21 22 CNNCT VCC PRCRDY 23 24 NC VSS NC 25 26 NC VCC NC 27 28 SAI#1 VSS SAI#12 29 30 SDOV# VCC SAI#14 31 32 SAI#8 VSS SDINV# 33 34 SAI#4 VCC SAI#13 35 36 SAI#10 VSS SAI#9 37 AL AM AN AM VCC VSS VSS AN NMI SMI# 23792K—November 2001 Chapter 10 1 2 3 4 5 Figure 12. AMD Athlon™ Processor Model 4 Pin Diagram—Topside View .

A B C D E F G H J K L M N P Q R S T U V W X Y Z AA AB AC AD AE AF AG AH AJ AK AL AM AN 1 SAO#10 VCC SAO#14 VCC SAO#13 NC VID[4] NC KEY NC NC VCC NC VSS VCC KEY VCC KEY VSS NC VCC NC VSS VCC NC VSS NC VCC NC VCC KEY VSS NC NC NC NC NC NC SD#20 VSS SD#23 VSS SD#21 G H J K L M SAO#7 VSS SAO#1 VSS NC VSS VID[3] NC NC NC COREFB VSS COREFB# VCC NC VSS VSS NC VCC NC VSS CLKFR VCC VCCA VSS NC VCC VCC NC NC KEY NC NC VCC SD#19 VCC SDIC#1 VCC SD#29 SD#28 VSS SD#18 N P SAO#11 VCC VID[1] VCC VID[2] VCC KEY VCC VSS VCC VSS VCC VSS VCC VSS NC NC NC NC NC VCC NC VSS ANLOG VCC PLBYC# VSS CLKIN# VCC RCLK# VSS K7CO VCC CNNCT VSS PLBYP# VCC NC VSS SAI#0 VSS NC VCC SD#7 VSS SD#17 VCC SD#16 Q R SAO#0 VSS PICD#0 VSS PICD#1 VSS NC NC NC KEY VCC_Z VSS_Z KEY NC VCC VSS VCC VSS VCC VSS VCC NC AMD CPR# NC NC NC VCC NC VSS PLMN2 VCC PLBYC VSS CLKIN VCC RCLK VSS K7CO# VCC PRCRDY VSS NC VCC NC VSS SAI#1 VCC NC VSS SD#5 VCC SD#15 VSS SD#6 S T VID[0] VCC TMS VCC SCNSN SCNCK2 TDO VREF_S NC SVRFM ZN ZP NC VCC VCC VSS NC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS SMI# SCNINV TRST# FID[1] FID[3] DBREQ# PLTST# PWROK RESET# INIT# FLUSH# NMI VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC PICCLK TCK SCNCK1 TDI FID[0] FID[2] DBRDY STPC# A20M# FERR IGNNE# INTR 1 2 3 4 5 6 7 8 9 10 NC VSS PLMN1 2 VSS VCC VSS Chapter 10 VCC 3 SAO#12 SAO#9 SAOC# 4 VCC VCC VSS 5 SAO#5 SAO#8 SAO#4 6 VSS VSS VSS 7 SAO#3 SAO#2 SAO#6 8 VCC VCC NC 9 SD#55 SD#54 SD#52 10 VSS VSS VSS 11 SD#61 SDOC#3 SD#50 11 12 13 14 15 16 17 18 19 20 21 22 23 VSS NC 12 VCC VCC VCC 13 SD#53 NC SD#49 14 VSS VSS VSS AMD Athlon™ Processor Model 4 Data Sheet 15 SD#63 SD#51 SDIC#3 16 VCC VCC VCC 17 SD#62 SD#60 SD#48 18 VSS VSS VSS 19 NC SD#59 SD#58 20 VCC VCC VCC 21 SD#57 SD#56 SD#36 AMD Athlon™ Processor Model 4 Bottomside View Preliminary Information Pin Descriptions VSS NC VSS SD#26 VSS NC SD#27 VCC SD#25 SD#24 VCC VSS NC NC NC VCC VSS VCC VSS NC VCC SDIC#0 VSS SD#4 VCC NC U V 22 VSS VSS VSS 23 SD#39 SD#37 SD#46 24 VCC VCC VCC 24 25 26 27 VSS SAI#12 VCC NC VSS NC VCC VSS SD#8 VCC VCC SD#10 VSS NC VSS SAI#5 VCC NC NC NC SAI#2 VSS NC NC VSS SAIC# VCC NC SFILLV# VSS SAI#8 VCC VCC SDOV# VSS SDINV# VCC SAI#14 25 SD#35 SD#47 NC 26 VSS VSS VSS 27 SD#34 SD#38 SDIC#2 28 VCC VCC VCC 28 29 30 31 32 33 34 SD#2 VSS SD#1 W X 29 SD#44 SD#45 SD#33 30 VSS VSS NC 31 NC SD#43 SD#32 32 VCC VCC VCC 33 SDOC#2 SD#42 NC 34 VSS VSS VCC 35 SD#40 SD#41 SD#31 SD#3 VCC SD#12 Y Z SD#0 VSS SD#13 AA AB SD#14 VCC SD#11 AC AD SDOC#0 VSS SD#9 AE AF SAI#11 VCC SAI#7 AG AH SAI#6 VSS SAI#3 AJ AK SAI#4 VCC SAI#10 AL AM SAI#13 VSS SAI#9 AN 35 36 37 36 VCC VSS VCC 37 SD#30 SDOC#1 SD#22 A B C D E F 23792K—November 2001 45 Figure 13. AMD Athlon™ Processor Model 4 Pin Diagram—Bottomside View .

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Table 17. Pin Name Abbreviations (continued) Abbreviation NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Full Name Pin A19 A31 C13 E25 E33 F8 F30 G11 G13 G19 G21 G27 G29 G31 H6 H8 H10 H28 H30 H32 J5 J31 K8 K30 L31 L35 N31 Q31 S7 S31 U7 U31 U37 W7 W31 Y5 Y31 Y33 AA31 ANLOG CLKFR CNNCT CPR# K7CO K7CO# 46 Pin Descriptions Chapter 10 . Pin Name Abbreviations Abbreviation Full Name A20M# AMD ANALOG CLKFWDRESET CLKIN CLKIN# CONNECT COREFB COREFB# CPU_PRESENCE# DBRDY DBREQ# FERR FID[0] FID[1] FID[2] FID[3] FLUSH# IGNNE# INIT# INTR K7CLKOUT K7CLKOUT# KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY Pin AE1 AH6 AJ13 AJ21 AN17 AL17 AL23 AG11 AG13 AK6 AA1 AA3 AG1 W1 W3 Y1 Y3 AL3 AJ1 AJ3 AL1 AL21 AN21 G7 G9 G15 G17 G23 G25 N7 Q7 Y7 AA7 AG7 AG9 AG15 AG17 AG27 AG29 Table 17.

Pin Name Abbreviations (continued) Abbreviation PICD#0 PICD#1 PLBYP# PLBYC PLBYC# PLMN1 PLMN2 PLTST# PRCRDY Full Name PICD[0]# PICD[1]# PLLBYPASS# PLLBYPASSCLK PLLBYPASSCLK# PLLMON1 PLLMON2 PLLTEST# PROCREADY PWROK RESET# RSTCLK RSTCLK# SADDIN[0]# SADDIN[1]# SADDIN[2]# SADDIN[3]# SADDIN[4]# SADDIN[5]# SADDIN[6]# SADDIN[7]# SADDIN[8]# SADDIN[9]# SADDIN[10]# SADDIN[11]# SADDIN[12]# SADDIN[13]# SADDIN[14]# SADDINCLK# SADDOUT[0]# SADDOUT[1]# SADDOUT[2]# SADDOUT[3]# SADDOUT[4]# SADDOUT[5]# SADDOUT[6]# SADDOUT[7]# SADDOUT[8]# SADDOUT[9]# Pin N3 N5 AJ25 AN15 AL15 AN13 AL13 AC3 AN23 AE3 AG3 AN19 AL19 AJ29 AL29 AG33 AJ37 AL35 AE33 AJ35 AG37 AL33 AN37 AL37 AG35 AN29 AN35 AN31 AJ33 J1 J3 C7 A7 E5 A5 E7 C1 C5 C3 RCLK RCLK# SAI#0 SAI#1 SAI#2 SAI#3 SAI#4 SAI#5 SAI#6 SAI#7 SAI#8 SAI#9 SAI#10 SAI#11 SAI#12 SAI#13 SAI#14 SAIC# SAO#0 SAO#1 SAO#2 SAO#3 SAO#4 SAO#5 SAO#6 SAO#7 SAO#8 SAO#9 Chapter 10 Pin Descriptions 47 .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Table 17. Pin Name Abbreviations (continued) Abbreviation Full Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NMI PICCLK Pin AC31 AD8 AD30 AE31 AF6 AF8 AF10 AF28 AF30 AF32 AG5 AG19 AG21 AG23 AG25 AG31 AH8 AH30 AJ7 AJ9 AJ11 AJ15 AJ17 AJ19 AJ27 AK8 AL7 AL9 AL11 AL25 AL27 AM8 AN7 AN9 AN11 AN25 AN27 AN3 N1 Table 17.

Pin Name Abbreviations (continued) Abbreviation SD#29 SD#30 SD#31 SD#32 SD#33 SD#34 SD#35 SD#36 SD#37 SD#38 SD#39 SD#40 SD#41 SD#42 SD#43 SD#44 SD#45 SD#46 SD#47 SD#48 SD#49 SD#50 SD#51 SD#52 SD#53 SD#54 SD#55 SD#56 SD#57 SD#58 SD#59 SD#60 SD#61 SD#62 SD#63 SDIC#0 SDIC#1 SDIC#2 SDIC#3 Full Name SDATA[29]# SDATA[30]# SDATA[31]# SDATA[32]# SDATA[33]# SDATA[34]# SDATA[35]# SDATA[36]# SDATA[37]# SDATA[38]# SDATA[39]# SDATA[40]# SDATA[41]# SDATA[42]# SDATA[43]# SDATA[44]# SDATA[45]# SDATA[46]# SDATA[47]# SDATA[48]# SDATA[49]# SDATA[50]# SDATA[51]# SDATA[52]# SDATA[53]# SDATA[54]# SDATA[55]# SDATA[56]# SDATA[57]# SDATA[58]# SDATA[59]# SDATA[60]# SDATA[61]# SDATA[62]# SDATA[63]# SDATAINCLK[0]# SDATAINCLK[1]# SDATAINCLK[2]# SDATAINCLK[3]# Pin J37 A37 E35 E31 E29 A27 A25 E21 C23 C27 A23 A35 C35 C33 C31 A29 C29 E23 C25 E17 E13 E11 C15 E9 A13 C9 A9 C21 A21 E19 C19 C17 A11 A17 A15 W33 J35 E27 E15 48 Pin Descriptions Chapter 10 .Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Table 17. Pin Name Abbreviations (continued) Abbreviation SAO#10 SAO#11 SAO#12 SAO#13 SAO#14 SAOC# SCNCK1 SCNCK2 SCNINV SCNSN SD#0 SD#1 SD#2 SD#3 SD#4 SD#5 SD#6 SD#7 SD#8 SD#9 SD#10 SD#11 SD#12 SD#13 SD#14 SD#15 SD#16 SD#17 SD#18 SD#19 SD#20 SD#21 SD#22 SD#23 SD#24 SD#25 SD#26 SD#27 SD#28 Full Name SADDOUT[10]# SADDOUT[11]# SADDOUT[12]# SADDOUT[13]# SADDOUT[14]# SADDOUTCLK# SCANCLK1 SCANCLK2 SCANINTEVAL SCANSHIFTEN SDATA[0]# SDATA[1]# SDATA[2]# SDATA[3]# SDATA[4]# SDATA[5]# SDATA[6]# SDATA[7]# SDATA[8]# SDATA[9]# SDATA[10]# SDATA[11]# SDATA[12]# SDATA[13]# SDATA[14]# SDATA[15]# SDATA[16]# SDATA[17]# SDATA[18]# SDATA[19]# SDATA[20]# SDATA[21]# SDATA[22]# SDATA[23]# SDATA[24]# SDATA[25]# SDATA[26]# SDATA[27]# SDATA[28]# Pin G1 E1 A3 G5 G3 E3 S1 S5 S3 Q5 AA35 W37 W35 Y35 U35 U33 S37 S33 AA33 AE37 AC33 AC37 Y37 AA37 AC35 S35 Q37 Q35 N37 J33 G33 G37 E37 G35 Q33 N33 L33 N35 L37 Table 17.

Pin Name Abbreviations (continued) Abbreviation VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Full Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Pin F34 F36 H2 H4 H12 H16 H20 H24 K32 K34 K36 M2 M4 M6 M8 P30 P32 P34 P36 R2 R4 R6 R8 T30 T32 T34 T36 V2 V4 V6 V8 X30 X32 X34 X36 Z2 Z4 Z6 Z8 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Chapter 10 Pin Descriptions 49 . Pin Name Abbreviations (continued) Abbreviation SDINV# SDOC#0 SDOC#1 SDOC#2 SDOC#3 SDOV# SFILLV# STPC# SVRFM Full Name SDATAINVALID# SDATAOUTCLK[0]# SDATAOUTCLK[1]# SDATAOUTCLK[2]# SDATAOUTCLK[3]# SDATAOUTVALID# SFILLVALID# SMI# STPCLK# SYSVREFMODE TCK TDI TDO TMS TRST# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Pin AN33 AE35 C37 A33 C11 AL31 AJ31 AN5 AC1 AA5 Q1 U1 U5 Q3 U3 B4 B8 B12 B16 B20 B24 B28 B32 B36 D2 D4 D8 D12 D16 D20 D24 D28 D32 F12 F16 F20 F24 F28 F32 Table 17.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Table 17.

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Table 17. Pin Name Abbreviations (continued) Abbreviation VCC Full Name VCC_CORE VCCA VCC_Z VID[0] VID[1] VID[2] VID[3] VID[4] VREF_SYS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin AM34 AJ23 AC7 L1 L3 L5 L7 J7 W5 B2 B6 B10 B14 B18 B22 B26 B30 B34 D6 D10 D14 D18 D22 D26 D30 D34 D36 F2 F4 F6 F10 F14 F18 F22 F26 H14 H18 H22 H26 VREF_S 50 Pin Descriptions Chapter 10 . Pin Name Abbreviations (continued) Abbreviation VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Full Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Pin AB30 AB32 AB34 AB36 AD2 AD4 AD6 AF14 AF18 AF22 AF26 AF34 AF36 AH2 AH4 AH10 AH14 AH18 AH22 AH26 AK10 AK14 AK18 AK22 AK26 AK30 AK34 AK36 AJ5 AL5 AM2 AM10 AM14 AM18 AM22 AM26 AM22 AM26 AM30 Table 17.

Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Table 17. Pin Name Abbreviations (continued) Abbreviation VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Full Name Pin H34 H36 K2 K4 K6 M30 M32 M34 M36 P2 P4 P6 P8 R30 R32 R34 R36 T2 T4 T6 T8 V30 V32 V34 V36 X2 X4 X6 X8 Z30 Z32 Z34 Z36 AB2 AB8 AB4 AB6 AD32 AD34 Table 17. Pin Name Abbreviations (continued) Abbreviation VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_Z ZN ZP Full Name Pin AD36 AF2 AF4 AF12 AF16 AH12 AH16 AH20 AH24 AH28 AH32 AH34 AH36 AK2 AK4 AK12 AK16 AK20 AK24 AK28 AK32 AM4 AM6 AM12 AM16 AM20 AM24 AM28 AM32 AM36 AE7 AC5 AE5 Chapter 10 Pin Descriptions 51 .

Cross-Reference by Pin Location Pin A1 A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 A31 A33 A35 A37 No Pin SADDOUT[12]# SADDOUT[5]# SADDOUT[3]# SDATA[55]# SDATA[61]# SDATA[53]# SDATA[63]# SDATA[62]# NC Pin SDATA[57]# SDATA[39]# SDATA[35]# SDATA[34]# SDATA[44]# NC Pin SDATAOUTCLK[2]# SDATA[40]# SDATA[30]# page 63 page 63 Name Description page 63 L P P P P P P P P P P P P P P P P P O O O B B B B B B B B B B O B B R G G G P P G G G G G P P G P G P Table 18. “O” indicates open-drain mode that allows devices to share the pin. Note: The Socket A AMD Duron Processor supports push-pull drivers. Cross-Reference by Pin Location Pin B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 B30 B32 B34 B36 C1 VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE SADDOUT[7]# Name Description L P P O R G 52 Pin Descriptions Chapter 10 . Table 18. see “Push-Pull (PP) Drivers” on page 6.2 Pin List Table 18 cross-references Socket A pin location to signal name. “P” indicates a push-pull mode driven by a single source. The “R” (Reference) column indicates if this signal should be referenced to VSS (G) or VCC_CORE (P) planes for the purpose of signal routing with respect to the current return paths. For more information.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 10. The “P” (Port) column indicates if this signal is an input (I). The “L” (Level) column shows the electrical specification for this pin. or bidirectional (B) signal. output (O).

Cross-Reference by Pin Location Pin C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 Name SADDOUT[9]# SADDOUT[8]# SADDOUT[2]# SDATA[54]# SDATAOUTCLK[3]# NC Pin SDATA[51]# SDATA[60]# SDATA[59]# SDATA[56]# SDATA[37]# SDATA[47]# SDATA[38]# SDATA[45]# SDATA[43]# SDATA[42]# SDATA[41]# SDATAOUTCLK[1]# VCC_CORE VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE page 63 Description L P P P P P P P P P P P P P P P P P P O O O B O B B B B B B B B B B B O R G G G P G P G G G P G G G G G G G Pin D34 D36 E1 E3 E5 E7 E9 E11 E13 E15 E17 E19 E21 E23 E25 E27 E29 E31 E33 E35 E37 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 VSS VSS SADDOUT[11]# SADDOUTCLK# SADDOUT[4]# SADDOUT[6]# SDATA[52]# SDATA[50]# SDATA[49]# SDATAINCLK[3]# SDATA[48]# SDATA[58]# SDATA[36]# SDATA[46]# NC Pin SDATAINCLK[2]# SDATA[33]# SDATA[32]# NC Pin SDATA[31]# SDATA[22]# VSS VSS VSS NC Pin VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS page 63 page 63 page 63 Name Description L P P P P P P P P P P P P P P P P P P O O O O B B B I B B B B I B B B B R P G P G P P G G P G P P G P P P G - Chapter 10 Pin Descriptions 53 .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Table 18. Cross-Reference by Pin Location (continued) Table 18.

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Table 18. Cross-Reference by Pin Location (continued) Table 18. Cross-Reference by Pin Location Pin F28 F30 F32 F34 F36 G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 G33 G35 G37 H2 H4 H6 H8 H10 H12 H14 H16 H18 H20 NC Pin VCC_CORE VCC_CORE VCC_CORE SADDOUT[10]# SADDOUT[14]# SADDOUT[13]# Key Pin Key Pin NC Pin NC Pin Key Pin Key Pin NC Pin NC Pin Key Pin Key Pin NC Pin NC Pin NC Pin SDATA[20]# SDATA[23]# SDATA[21]# VCC_CORE VCC_CORE NC Pin NC Pin NC Pin VCC_CORE VSS VCC_CORE VSS VCC_CORE page 63 page 63 page 63 page 63 page 63 page 63 page 63 page 63 page 63 page 63 page 63 page 63 page 63 page 63 page 63 page 63 Name VCC_CORE page 63 Description L P P P P P P P O O O B B B R P G G G G G Pin H22 H24 H26 H28 H30 H32 H34 H36 J1 J3 J5 J7 J31 J33 J35 J37 K2 K4 K6 K8 K30 K32 K34 K36 L1 L3 L5 L7 L31 L33 L35 L37 M2 M4 VSS VCC_CORE VSS NC Pin NC Pin NC Pin VSS VSS SADDOUT[0]# SADDOUT[1]# NC Pin VID[4] NC Pin SDATA[19]# SDATAINCLK[1]# SDATA[29]# VSS VSS VSS NC Pin NC Pin VCC_CORE VCC_CORE VCC_CORE VID[0] VID[1] VID[2] VID[3] NC Pin SDATA[26]# NC Pin SDATA[28]# VCC_CORE VCC_CORE page 63 page 65 page 65 page 65 page 65 page 63 page 63 page 63 page 64 page 64 page 63 page 65 page 63 page 63 page 63 page 63 Name Description L P P O P P P O O O O P P P O O O B I B O O O O B B R G P P P P - 54 Pin Descriptions Chapter 10 .

Cross-Reference by Pin Location Pin M6 M8 M30 M32 M34 M36 N1 N3 N5 N7 N31 N33 N35 N37 P2 P4 P6 P8 P30 P32 P34 P36 Q1 Q3 Q5 Q7 Q31 Q33 Q35 Q37 R2 R4 R6 R8 Name VCC_CORE VCC_CORE VSS VSS VSS VSS PICCLK PICD#[0] PICD#[1] Key Pin NC Pin SDATA[25]# SDATA[27]# SDATA[18]# VSS VSS VSS VSS VCC_CORE VCC_CORE VCC_CORE VCC_CORE TCK TMS SCANSHIFTEN Key Pin NC Pin SDATA[24]# SDATA[17]# SDATA[16]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE page 63 page 63 page 64 page 63 page 63 page 60 page 60 page 60 page 63 page 63 Description L O O O P P P P P P P P P P I B B B B B I I I B B B R P P G P G G Pin R30 R32 R34 R36 S1 S3 S5 S7 S31 S33 S35 S37 T2 T4 T6 T8 T30 T32 T34 T36 U1 U3 U5 U7 U31 U33 U35 U37 V2 V4 V6 V8 V30 V32 VSS VSS VSS VSS SCANCLK1 SCANINTEVAL SCANCLK2 NC Pin NC Pin SDATA[7]# SDATA[15]# SDATA[6]# VSS VSS VSS VSS VCC_CORE VCC_CORE VCC_CORE VCC_CORE TDI TRST# TDO NC Pin NC Pin SDATA[5]# SDATA[4]# NC Pin VCC_CORE VCC_CORE VCC_CORE VCC_CORE VSS VSS page 63 page 63 page 63 page 63 page 63 page 63 page 64 page 64 page 64 page 63 page 63 Name Description L P P P P P P P P P P P P I I I B B B I I O B B R G P G G G - Chapter 10 Pin Descriptions 55 . Cross-Reference by Pin Location (continued) Table 18.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Table 18.

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Table 18. Cross-Reference by Pin Location (continued) Table 18. Cross-Reference by Pin Location Pin V34 V36 W1 W3 W5 W7 W31 W33 W35 W37 X2 X4 X6 X8 X30 X32 X34 X36 Y1 Y3 Y5 Y7 Y31 Y33 Y35 Y37 Z2 Z4 Z6 Z8 Z30 Z32 Z34 Z36 VSS VSS FID[0] FID[1] VREFSYS NC Pin NC Pin SDATAINCLK[0]# SDATA[2]# SDATA[1]# VSS VSS VSS VSS VCC_CORE VCC_CORE VCC_CORE VCC_CORE FID[2] FID[3] NC Pin Key Pin NC Pin NC Pin SDATA[3]# SDATA[12]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VSS VSS VSS VSS page 62 page 62 page 63 page 63 page 63 page 63 page 62 page 62 page 66 page 63 page 63 Name Description L O O P P P P O O P P P I B B B B R G G P G P Pin AA1 AA3 AA5 AA7 AA31 AA33 AA35 AA37 AB2 AB4 AB6 AB8 AB30 AB32 AB34 AB36 AC1 AC3 AC5 AC7 AC31 AC33 AC35 AC37 AD2 AD4 AD6 AD8 AD30 AD32 AD34 AD36 AE1 AE3 Name DBRDY DBREQ# SYSVREFMODE Key Pin NC Pin SDATA[8]# SDATA[0]# SDATA[13]# VSS VSS VSS VSS VCC_CORE VCC_CORE VCC_CORE VCC_CORE STPCLK# PLLTEST# ZN VCC_Z NC Pin SDATA[10]# SDATA[14]# SDATA[11]# VCC_CORE VCC_CORE VCC_CORE NC Pin NC Pin VSS VSS VSS A20M# PWROK page 63 page 63 page 64 page 64 page 66 page 66 page 63 Description page 61 page 61 page 64 page 63 page 63 L P P P P P P P P P P P P P P P O I I B B B I I B B B I I R P G G P G G - 56 Pin Descriptions Chapter 10 .

Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Table 18. Cross-Reference by Pin Location (continued) Table 18. Cross-Reference by Pin Location Pin AE5 AE7 AE31 AE33 AE35 AE37 AF2 AF4 AF6 AF8 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AF30 AF32 AF34 AF36 AG1 AG3 AG5 AG7 AG9 AG11 AG13 AG15 AG17 AG19 ZP VSS_Z NC Pin SADDIN[5]# SDATAOUTCLK[0]# SDATA[9]# VSS VSS NC Pin NC Pin NC Pin VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE NC Pin NC Pin NC Pin VCC_CORE VCC_CORE FERR RESET# NC Pin Key Pin Key Pin COREFB COREFB# Key Pin Key Pin NC Pin page 63 page 63 page 63 page 61 page 61 page 63 page 63 page 63 page 61 page 63 page 63 page 63 page 63 page 63 page 63 Name Description page 66 page 66 page 63 L P P P P P P I O B O I R G P G Pin AG21 AG23 AG25 AG27 AG29 AG31 AG33 AG35 AG37 AH2 AH4 AH6 AH8 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AH32 AH34 AH36 AJ1 AJ3 AJ5 AJ7 AJ9 AJ11 AJ13 NC Pin NC Pin NC Pin Key Pin Key Pin NC Pin SADDIN[2]# SADDIN[11]# SADDIN[7]# VCC_CORE VCC_CORE AMD Pin NC Pin VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS NC Pin VSS VSS VSS IGNNE# INIT# VCC_CORE NC Pin NC Pin NC Pin Analog page 63 page 63 page 63 page 60 page 63 page 63 page 63 page 60 page 63 Name Description page 63 page 63 page 63 page 63 page 63 page 63 L P P P P P P I I I I I R G G P - Chapter 10 Pin Descriptions 57 .

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Table 18. Cross-Reference by Pin Location Pin AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AJ33 AJ35 AJ37 AK2 AK4 AK6 AK8 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK30 AK32 AK34 AK36 AL1 AL3 AL5 AL7 NC Pin NC Pin NC Pin CLKFWDRST VCCA PLLBYPASS# NC Pin SADDIN[0]# SFILLVALID# SADDINCLK# SADDIN[6]# SADDIN[3]# VSS VSS CPU_PRESENCE# NC Pin VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VCC_CORE INTR FLUSH# VCC_CORE NC Pin page 63 page 63 page 63 page 61 page 63 Name Description page 63 page 63 page 63 page 60 page 65 page 64 page 63 page 64 L P P P P P P P P P P I I I I I I I I I R P G G P G Pin AL9 AL11 AL13 AL15 AL17 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL35 AL37 AM2 AM4 AM6 AM8 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AM32 AM34 AM36 AN1 NC Pin NC Pin PLLMON2 PLLBYPASSCLK# CLKIN# RSTCLK# K7CLKOUT CONNECT NC Pin NC Pin SADDIN[1]# SDATAOUTVALID# SADDIN[8]# SADDIN[4]# SADDIN[10]# VCC_CORE VSS VSS NC Pin VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE VSS No Pin page 63 page 63 Name Description page 63 page 63 page 64 page 64 page 60 page 60 page 63 page 60 page 63 page 63 page 64 L O P P P P P P P P P P P O I I I O I I O I I I R P P P P P G G - 58 Pin Descriptions Chapter 10 . Cross-Reference by Pin Location (continued) Table 18.

Cross-Reference by Pin Location (continued) Pin AN3 AN5 AN7 AN9 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN31 AN33 AN35 AN37 NMI SMI# NC Pin NC Pin NC Pin PLLMON1 PLLBYPASSCLK CLKIN RSTCLK K7CLKOUT# PROCRDY NC Pin NC Pin SADDIN[12]# SADDIN[14]# SDATAINVALID# SADDIN[13]# SADDIN[9]# page 63 page 63 page 63 page 63 page 63 page 64 page 64 page 60 page 60 page 63 Name Description L P P O P P P P P P P P P P P I I B I I I O O I I I I I R P P P G G P G G Chapter 10 Pin Descriptions 59 .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Table 18.

RESET#. See the AMD Athlon™ and AMD Duron™ System Bus Specification. SDATA[63:0]#. SDATAINCLK[3:0]#. Pin Descriptions Chapter 10 AMD Athlon™ System Bus Pins Analog Pin APIC Pins. AMD Socket A processors do not implement a pin at location AH6. Connect CLKIN# (AL17) with RSTCLK# (AL19) and name it SYSCLK#. CLKFWDRST resets clock-forward circuitry for both the system and processor. PICCLK. are the bi-directional message-passing signals used for the APIC and are driven to the Southbridge or a dedicated I/O APIC. socket manufacturers are allowed to have a contact loaded in the AH6 position. must be driven with a valid clock input. SADDOUT[14:2]#. CONNECT is an input from the system used for power management and clock-forward initialization at reset. All Socket A designs must have a top plate or cover that blocks this pin location. The pin.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 10. The pins. Connect CLKIN (AN17) with RSTCLK (AN19) and name it SYSCLK. The Advanced Programmable Interrupt Controller (APIC) is a feature that provides a flexible and expandable means of delivering interrupts in a system using an AMD processor. SDATAINVALID#. a non-AMD part (e. order# 21902 for information about the system bus pins — PROCRDY. PICD[1:0]# CLKFWDRST Pin CLKIN.g. PWROK. SDATAOUTVALID#. motherboard socket design should account for the possibility that a contact could be loaded in this position. SADDOUTCLK#. For more information. When the cover plate blocks this location. See “SYSCLK and SYSCLK# Pins” on page 64 for more information. SADDINCLK#. Therefore.. PGA370) does not fit into the socket. see Table 14. PICCLK. Treat this pin as a NC. SFILLVALID#. Length match the clocks from the clock generator to the Northbridge and processor. RSTCLK (SYSCLK) Pins CONNECT Pin 60 .” on page 34. SDATAOUTCLK[3:0]#.3 A20M# Pin AMD Pin Detailed Pin Descriptions The information in this section pertains to Table 18 on page 52. “APIC Pins AC and DC Characteristics. SADDIN[14:2]#. A20M# is an input from the system used to simulate address wrap-around in the 20-bit 8086. However. PICD[1:0].

DBRDY and DBREQ# Pins FERR Pin FID[3:0] Pins Chapter 10 Pin Descriptions 61 . FERR is an output to the system that is asserted for any unmasked numerical exception independent of the NE bit in CR0. CPU_PRESENCE# is connected to VSS on the processor package. CPU_PRESENCE# can be used to detect the presence or absence of a processor in the Socket A–style socket. Table 19 on page 62 describes the encodings of the clock multipliers on FID[3:0]. FID[1] (W3). FID[2] (Y1). FERR is a push-pull active High signal that must be inverted and level shifted to an active Low signal. FID[3] (Y3). DBRDY (AA1) and DBREQ# (AA3) are routed to the debug connector.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet COREFB and COREFB# Pins CPU_PRESENCE# Pin COREFB and COREFB# are outputs to the system that provide processor core voltage feedback to the system. see the “Required Circuits” chapter of the AMD Athlon™ Processor-Based Motherboard Design Guide order# 24363. For more information about FERR and FERR#. and FID[0] (W1) are the 4-bit processor clock-to-SYSCLK ratio. See “Frequency Identification (FID[3:0])” on page 24 for the AC and DC characteristics for FID[3:0]. If pulled-up on the motherboard. DBREQ# is tied to VCC_CORE with a pullup resistor.

5 9 9.5 10 10.5 6 6.5 V.5* 5 5. See the AMD Athlon™ and AMD Duron™ System Bus Specification .5V tolerant. which causes the SIP configuration for all ratios of 12. order#21902 for more information about the Serialization Initialization Packets and SIP protocol. if these signals are pulled High to above 2. To prevent damage to the processor.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Table 19. order# 24363.5x or greater to be the same.5x have the same FID[3:0] code of 0011. they must be electrically isolated from the processor.5 *All ratios greater than or equal to 12. The FID[3:0] signals are open drain processor outputs that are pulled High on the motherboard and sampled by the chipset at the deassertion of RESET# to determine the SIP (Serialization Initialization Packet) that gets sent to the processor. FID[3:0] Clock Multiplier Encodings FID[3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Note: FID[2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FID[1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FID[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Processor Clock to SYSCLK Frequency Ratio 11 11.5 8 8. For information about the FID[3:0] isolation circuit. 62 Pin Descriptions Chapter 10 .5 12 ≥ 12. The processor FID[3:0] outputs are open drain and 2.5 7 7. see the AMD Athlon™ Processor-Based Motherboard Design Guide.

TRST# (U3). AG15. A socket designer has the option of creating a top mold piece that allows PGA key pins only where designated. If a debug connector is implemented. AG27. AG7. INTR is an input from the system that causes the processor to start an interrupt acknowledge transaction that fetches the 8-bit interrupt vector and starts execution at that location. N7. TCK. Motherboard designers should treat key pins like NC (no connect) pins. NMI is an input from the system that causes a non-maskable interrupt. Pin Descriptions 63 IGNNE# Pin INIT# Pin INTR Pin JTAG Pins K7CLKOUT and K7CLKOUT# Pins Key Pins NC Pins NMI Pin PGA Orientation Pins Chapter 10 . Execution starts at 0_FFFF_FFF0h. IGNNE# is an input from the system that tells the processor to ignore numeric errors. TMS. G17. G15. AG9. and TRST# to VCC_CORE with pullup resistors. sockets that populate all 16 key pins must be allowed. TMS (Q3). See “NC Pins” on page 63 for more information. AA7. 100 ohms to VCC_CORE and 100 ohms to VSS. The effective termination resistance and voltage are 50 ohms and VCC_CORE/2. FLUSH# is routed to the debug connector. TCK (Q1). No pin is present at pin locations A1 and AN1. However.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet FLUSH# Pin FLUSH# must be tied to VCC_CORE with a pullup resistor. INIT# is an input from the system that resets the integer registers without affecting the floating-point registers or the internal caches. G23. and TDO (U5) are the JTAG interface. Motherboard designers should not allow for a PGA socket pin at these locations. K7CLKOUT (AL21) and K7CLKOUT# (AN21) are each run for 2 to 3 inches and then terminated with a resistor pair. G25. so the motherboard must always provide for pins at all key pin locations. These 16 locations are for processor type keying for forwards and backwards compatibility (G7. The pin hole should not be electrically connected to anything. TDI (U1). AG17. Pullup TDI. Q7. Y7. Connect these pins directly to the motherboard debug connector. The motherboard should provide a plated hole for an NC pin. and AG29). G9.

a n d PLLBYPASSCLK# (AL15) are the PLL bypass and test interface. SCANINTEVAL (S3). and PLLMON2) are tied to VCC_CORE with pullup resistors. Fo r m o re i n f o r m a t i o n . SCANSHIFTEN (Q5). SADDOUT[1:0]# are tied to VCC with pullup resistors if these pins are supported by the Northbridge.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 For more information. order# 24363. For more information. RSTCLK (SYSCLK) Pins” on page 60 for more information. All four processor inputs (PLLTEST#. if this bit is not supported by the Northbridge (future models can support SADDIN[1]#). PLLBYPASS#. See “CLKIN. SADDIN[1:0]# and SADDOUT[1:0]# Pins The AMD A thlon processor mo del 4 does not support SADDIN[1:0]# or SADDOUT[1:0]#. All six pin signals are routed to the debug connector. PLLBYPASS# (AJ25). P L L M O N 2 ( A L 1 3 ) . S e e “ S i g n a l a n d Po w e r -U p Requirements” on page 35. This interface is tied disabled on the motherboard. PLLMON1 (AN13). The PWROK input to the processor must not be asserted until all voltage planes in the system are within specification and all system clocks are running within specification. SMI# is an input that causes the processor to enter the system management mode. P L L B Y PA S S C L K ( A N 1 5 ) . SADDIN[1]# is tied to VCC with pullup resistors. order# 21902. This interface is AMD internal and is tied disabled with pulldown resistors to ground on the motherboard. SYSVREFMODE (AA5) is Low to ensure that the external VREFSYS voltage is the actual voltage used by the input buffers and that no scaling occurs internally between the Pin Descriptions Chapter 10 PWROK Pin Scan Pins SMI# Pin STPCLK# Pin SYSCLK and SYSCLK# Pins SYSVREFMODE Pin 64 . PLL Bypass and Test Pins PLLTEST# (AC3). see the AMD Athlon™ and AMD Duron™ System Bus Specification. see the AMD Athlon™ Processor-Based Motherboard Design Guide. PLLMON1. STPCLK# is an input that causes the processor to enter a lower power mode and issue a Stop Grant special cycle. and SCANCLK2 (S5) are the scan interface. SYSCLK and SYSCLK# are differential input clock signals provided to the processor’s PLL from a system-clock generator. SCANCLK1 (S1).

This pin is tied Low with a pulldown resistor.” on page 25 and the AMD Athlon™ Processor-Based Motherboard Design Guide. For information about the VCCA pin. VID[4:0] Pins Chapter 10 Pin Descriptions 65 . VCCA Pin VCCA is the processor PLL supply.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet VREFSYS voltage and the input threshold. see Table 5. The VID[4:0] pins are pulled-up on the motherboard and used by the VCC_CORE DC/DC converter. These voltage ID values are defined Table 20 on page 66. The VID[4:0] (Voltage Identification) outputs are used to dictate the VCC_CORE voltage level. order# 24363. “VCCA AC and DC Characteristics. The VID[4:0] pins are strapped to ground or left unconnected on the processor’s package.

Fo r m o re information. VREFSYS Pin VREFSYS (W5) drives the threshold voltage for the system bus input receivers.825 1. In addition.600 1. i n c l u d e d e c o u p l i n g c a p a c i t o rs .850 1. In Push-Pull mode (selected by the SIP parameter SysPushPull asserted).200 1.250 1. ZN (AC5).425 1. see the AMD Athlon™ Processor-Based Motherboard Design Guide.575 1.325 1.150 1. VID[4:0] Code to Voltage Definition VID[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 VCC_CORE (V) 1. ZP. VSS_Z is tied to VSS.650 1.800 1.225 1. to minimize VCC_CORE noise rejection from V R E F S Y S .675 1.625 1. ZP (AE5). order# 24363. VCC_Z.700 1.450 1. VCC_ Z is tied to VCC_CORE.525 1.400 1.300 1.125 1.550 1. and VSS_Z(AE7) are the push-pull compensation circuit pins.375 1.175 1. The value of VREFSYS is system specific. see the “Required Circuits” chapter of the AMD Athlon™ Processor-Based Motherboard Design Guide.500 1. order# 24363. ZN.725 1.350 1.775 1. ZP is tied to VSS with a resistor that has a resistance matching the impedance Z0 of the transmission line.750 1. ZN is tied to VCC_CORE with a resistor that has a resistance matching the impedance Z0 of the transmission line.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Table 20. VCC_Z (AC7). and VSS_Z Pins 66 Pin Descriptions Chapter 10 .275 1.100 No CPU For more information.475 VID[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 VCC_CORE (V) 1.

1266 = 1266 MHz. Figure 14. 1300=1300 MHz. T = 90ºC Operating Voltage: M = 1. 1200=1200 MHz. 1400=1400 MHz Family/Architecture: A = AMD Athlon™ Processor Model 4 Architecture Note: Spaces are added to the number shown above for viewing clarity only.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet 11 Ordering Information Standard AMD Athlon™ Processor Model 4 Products AMD standard products are available in several operating ranges. The ordering part numbers (OPN) are formed by a combination of the elements. C = 266 MHz Size of L2 Cache: 3 = 256 Kbytes Die Temperature: S = 95ºC. 1100=1100 MHz. PGA OPN Example for the AMD Athlon™ Processor Model 4 Chapter 11 Ordering Information 71 . PGA OPN A 1400 A M S 3 C Max FSB: B = 200 MHz. 1333= 1333 MHz. 1133= 1133 MHz.75V Package Type: A = PGA Speed: 0900=900 MHz. 1000=1000 MHz. as shown in Figure 14.

Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 72 Ordering Information Chapter 11 .

These bits and signals are reserved by AMD for future implementations. They are asserted in their Low-voltage state and negated in their High-voltage state. When used in this context. When software reads registers with reserved bits. Reserved Bits and Signals—Signals or bus bits marked reserved must be driven inactive or left unconnected. Signal Ranges—In a range of signals. Signals and Bits ■ Active-Low Signals—Signal names containing a pound sign. such as SFILL#. it must first read the register and change only the non-reserved bits before writing back to the register. When software writes such registers.Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Appendix A Conventions and Abbreviations This section contains information about the conventions and abbreviations used in this document. as indicated in the signal descriptions. indicate active-Low signals. High and Low are written with an initial upper case letter. ■ ■ ■ Appendix A 73 . D[63:0]). the reserved bits must be masked. Three-State—In timing diagrams. signal ranges that are high impedance are shown as a straight horizontal line half-way between the high and low levels. the highest and lowest signal numbers are contained in brackets and separated by a colon (for example.

signal ranges that are invalid or don't-care are filled with a screen pattern. bit positions are numbered from right to left—the little end is on the right and the big end is on the left. AD[31:0]). In byte diagrams.xx00 is in the least-significant byte position (little end). the highest and lowest bit numbers are contained in brackets and separated by a colon (for example. Abbreviations—The following notation is used for bits and bytes: ï Kilo (K. Because byte addresses increase from right to left. Data Terminology The following list defines data terminology: ■ ■ Quantities ï A word is two bytes (16 bits) ï A doubleword is four bytes (32 bits) ï A quadword is eight bytes (64 bits) Addressing—Memory is addressed as a series of bytes on eight-byte (64-bit) boundaries in which each byte can be separately enabled.. Little-Endian Convention—The byte with the address xx. When data items are aligned. bit ranges are shown with a dash (for example. When accompanied by a signal or bus name. bit notation on a 64-bit data bus maps directly to bit notation in 64-bit-wide memory. ■ ■ ■ ■ ■ 74 Appendix A . Bit Values—Bits can either be set to 1 or cleared to 0. as in 4 Gbytes of memory space) See Table 21 on page 75 for more abbreviations. as in 4 Mbits/sec) ï Giga (G. Bit Ranges—In text. as in 4-Kbyte page) ï Mega (M. hexadecimal numbers are followed by an h and binary numbers are followed by a b.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 ■ Invalid and Don’t-Care—In timing diagrams. strings appear in reverse order when illustrated. Hexadecimal and Binary Numbers—Unless the context makes interpretation clear. bits 9–1). Data structure diagrams in memory show low addresses at the bottom and high addresses at the top..

Abbreviations Abbreviation A F G Gbit Gbyte H h K Kbyte M Mbit Mbyte MHz m ms mW Meaning Ampere Farad GigaGigabit Gigabyte Henry Hexadecimal KiloKilobyte MegaMegabit Megabyte Megahertz MilliMillisecond Milliwatt MicroMicroampere Microfarad Microhenry Microsecond Microvolt nanonanoampere nanofarad nanohenry nanosecond Ohm picopicoampere µ µA µF µH µs µV n nA nF nH ns ohm p pA Appendix A 75 .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Abbreviations and Acronyms Table 21 contains the definitions of abbreviations used in this document. Table 21.

Acronyms Abbreviation ACPI AGP APCI API APIC BIOS BIST BIU DDR DIMM DMA DRAM EIDE EISA EPROM FIFO GART HSTL IDE ISA JEDEC JTAG Meaning Advanced Configuration and Power Interface Accelerated Graphics Port AGP Peripheral Component Interconnect Application Programming Interface Advanced Programmable Interrupt Controller Basic Input/Output System Built-In Self-Test Bus Interface Unit Double-Data Rate Dual Inline Memory Module Direct Memory Access Direct Random Access Memory Enhanced Integrated Device Electronics Extended Industry Standard Architecture Enhanced Programmable Read Only Memory First In. Abbreviations (continued) Abbreviation pF pH ps s V W Meaning picofarad picohenry picosecond Second Volt Watt Table 22 contains the definitions of acronyms used in this document.Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Table 21. First Out Graphics Address Remapping Table High-Speed Transistor Logic Integrated Device Electronics Industry Standard Architecture Joint Electron Device Engineering Council Joint Test Action Group 76 Appendix A . Table 22.

Acronyms (continued) Abbreviation LAN LRU LVTTL MSB MTRR MUX NMI OD PBGA PA PCI PDE PDT PLL PMSM POS POST RAM ROM RXA SDI SDRAM SIP SMbus SPD SRAM SROM TLB TOM TTL VAS VPA VGA USB Meaning Large Area Network Least-Recently Used Low Voltage Transistor Transistor Logic Most Significant Bit Memory Type and Range Registers Multiplexer Non-Maskable Interrupt Open-Drain Plastic Ball Grid Array Physical Address Peripheral Component Interconnect Page Directory Entry Page Directory Table Phase Locked Loop Power Management State Machine Power-On Suspend Power-On Self-Test Random Access Memory Read Only Memory Read Acknowledge Queue System DRAM Interface Synchronous Direct Random Access Memory Serial Initialization Packet System Management Bus Serial Presence Detect Synchronous Random Access Memory Serial Read Only Memory Translation Lookaside Buffer Top of Memory Transistor Transistor Logic Virtual Address Space Virtual Page Address Video Graphics Adapter Universal Serial Bus Appendix A 77 .Preliminary Information 23792K—November 2001 AMD Athlon™ Processor Model 4 Data Sheet Table 22.

Acronyms (continued) Abbreviation ZDB Meaning Zero Delay Buffer 78 Appendix A .Preliminary Information AMD Athlon™ Processor Model 4 Data Sheet 23792K—November 2001 Table 22.

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