NTDCTV05

TECHNICAL TRAINING MANUAL N5SS (TG-1, C) CHASSIS

COLOR TELEVISION
CN27E90, CX32E70 CN32E90, CN35E15 CF35E50, CX35E60 CX35E70, CX35E81 CN35E90, CN35E95

PRINTED IN JAPAN Aug. 1995 So

Contents
SECTION I OUTLINE ...................................................................... 6
1. OUTLINE OF N5SS CHASSIS (CN32E90, CN35E90) .................................................................... 7 2. PC BOARD CONFIGURATION ........................................................................................................ 7 3. MAJOR SPECIFICATIONS (NEW FUNCTIONS IN ADDITION TO THOSE OF N5SS) ........ 7 4. MODIFICATIONS ON CHASSIS ..................................................................................................... 7 5. CONSTRUCTION OF CHASSIS ...................................................................................................... 8 6. LOCATION OF CONTROLS ............................................................................................................ 9 7. CN32D90 BLOCK DIAGRAM ......................................................................................................... 13 8. [US, CANADA] SPECIFICATION FOR MODEL's 1995 ............................................................ 14

SECTION II TUNER, IF/MTS/S.PRO MODULE ......................... 16
1. CIRCUIT BLOCK ............................................................................................................................. 17 2. TUNER ................................................................................................................................................ 18 3. IF/MTS/S.PRO MODULE ................................................................................................................. 19 4. PIP TUNER ......................................................................................................................................... 23

SECTION III CHANNEL SELECTION CIRCUIT ........................ 24
1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM .................................................... 25 2. OPERATION OF CHANNEL SELECTION CIRCUIT ................................................................ 25 3. MICROCOMPUTER ......................................................................................................................... 26 4. MICROCOMPUTER TERMINAL FUNCTION ........................................................................... 27 5. EEPROM (QA02) ............................................................................................................................... 29 6. ON SCREEN FUNCTION ................................................................................................................. 29 7. SYSTEM BLOCK DIAGRAM ......................................................................................................... 30 8. LOCAL KEY DETECTION METHOD .......................................................................................... 31 9. REMOTE CONTROL CODE ASSIGNMENT ............................................................................... 32 10. ENTERING TO SERVICE MODE ................................................................................................ 35 11. TEST SIGNAL SELECTION ......................................................................................................... 35 12. SERVICE ADJUSTMENT .............................................................................................................. 35 13. FAILURE DIAGNOSIS PROCEDURE ......................................................................................... 36 14. TROUBLE SHOOTING CHART .................................................................................................. 38

SECTION IV AUDIO OUTPUT CIRCUIT ..................................... 41
1. OUTLINE ............................................................................................................................................ 42 2. AUDIO OUT IC .................................................................................................................................. 43 2

SECTION V A/V SWITCHING CIRCUIT .................................... 44
1. OUTLINE ............................................................................................................................................ 45 2. IN / OUT TERMINALS ..................................................................................................................... 45 3. CIRCUIT OPERATION .................................................................................................................... 45

SECTION VI VIDEO PROCESSING CIRCUIT ............................ 47
1. OUTLINE ............................................................................................................................................ 48 2. SIGNAL FLOW .................................................................................................................................. 48 3. CIRCUIT OPERATION .................................................................................................................... 48

SECTION VII V/C/D/IC ...................................................................... 52
1. OUTLINE ............................................................................................................................................ 53 2. LARGE SCALE EMPLOYMENT OF BUS CONTROL OF PARAMETER FOR PICTURE CONTROLS ...................................................................................................................................... 53 3. EMPLOYMENT OF CONTAINING EACH VIDEO BAND FILTER INSIDE.......................... 53 4. EMPLOYMENT OF CONTAINING EACH FILTER (FOR S/H) INSIDE................................. 53 5. LOW COST OF IC ............................................................................................................................ 53

SECTION VIII PIP MODULE ............................................................. 55 SECTION IX SYNC SEPARATION, H-AFC, H-OSCILLATOR CIRCUITS .............................. 58
1. SYNC SEPARATION CIRCUIT ...................................................................................................... 59 2. H AFC (Automatic Frequency Control) CIRCUIT ......................................................................... 60 3. H OSCILLATOR CIRCUIT ............................................................................................................. 61

SECTION X VERTICAL OUTPUT CIRCUIT ............................. 63
1. OUTLINE ............................................................................................................................................ 64 2. V OUTPUT CIRCUIT ....................................................................................................................... 65

3

SECTION XI HORIZONTAL DEFLECTION CIRCUIT.............. 69
1. OUTLINE ............................................................................................................................................ 70 2. HORIZONTAL DRIVE CIRCUIT ................................................................................................... 70 3. BASIC OPERATION OF HORIZONTAL DRIVE ........................................................................ 71 4. HORIZONTAL OUTPUT CIRCUIT ............................................................................................... 74 5. HIGH VOLTAGE GENERATION CIRCUIT ................................................................................. 79 6. X-RAY PROTECTION CIRCUIT ................................................................................................... 82 7. OVER CURRENT PROTECTION CIRCUIT................................................................................ 83 8. KINK CORRECTION CIRCUIT ..................................................................................................... 84

SECTION XII DEFLECTION DISTORTION CORRECTION CIRCUIT (Side DPC Circuit) .............................. 85
1. DEFLECTION DISTORTION CORRECTION IC (TA8859P) .................................................... 86 2. SIDE DPC ............................................................................................................................................ 87 3. DIODE MODULATOR CIRCUIT ................................................................................................... 88 4. ACTUAL CIRCUIT ........................................................................................................................... 89

SECTION XIII CLOSED CAPTION/EDS CIRCUIT ....................... 92
1. OUTLINE ............................................................................................................................................ 93 2. DATA TRANSMISSION FORMAT ................................................................................................ 93 3. DISPLAY FORMAT ........................................................................................................................... 94 4. CIRCUIT OPERATION .................................................................................................................... 95

SECTION XIV POWER CIRCUIT ..................................................... 98
1. OUTLINE ............................................................................................................................................ 99 2. RECTIFYING CIRCUIT AND STANDBY POWER SUPPLY ................................................... 100 3. MAIN SUPPLY CIRCUIT............................................................................................................... 100 4. OUTLINE OF CURRENT RESONANT TYPE SUPPLY ........................................................... 101 5. FUNDAMENTAL THEORY ........................................................................................................... 101 6. ACTUAL CIRCUIT ......................................................................................................................... 102 7. OTHER POWER CIRCUIT ........................................................................................................... 105 8. PROTECTOR MODULE (Z801) .................................................................................................... 106

4

SECTION XV DSP CIRCUIT .......................................................... 109
1. ORIGINS OF DOLBY SURROUND ............................................................................................. 110 2. THE DOLBY MP MATRIX ............................................................................................................ 110 3. THE DOLBY SURROUND DECODER ......................................................................................... 111 4. DSP CIRCUIT ................................................................................................................................... 111 5. DSP (Digital Surround Processor) IC ............................................................................................. 114 6. SURROUND CIRCUIT ................................................................................................................... 116 7. INPUT BALANCE CIRCUIT ......................................................................................................... 116 8. MATRIX CIRCUIT ......................................................................................................................... 117 9. FILTER CIRCUIT (ANTI-ALIAS FILTER)................................................................................. 117 10. DSP CIRCUIT (DELAY) ............................................................................................................... 118 11. 7 kHz LOW PASS FILTER ........................................................................................................... 119 12. DOLBY NR CIRCUIT ................................................................................................................... 120 13. DSP FRONT ADDITION CIRCUIT ............................................................................................ 121 14. BUS CONVERTER ........................................................................................................................ 122 15. NEUTRAL BIAS ............................................................................................................................ 122 16. AUDIO OUTPUT AMPLIFIER (For Rear SP) .......................................................................... 123 17. TROUBLESHOOTING CHART ................................................................................................. 124

SECTION XVI FAILURE DIAGNOSIS PROCEDURES ............... 125
1. H STARTING CIRCUIT FAILURE DIAGNOSIS PROCEDURES........................................... 126 2. DEFLECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES ......................................... 127 3. LEFT-RIGHT PIN-CUSHION DISTORTION CORRECTION CIRCUIT .............................. 128 4. X-RAY PROTECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES ........................... 129 5. PROTECTION CIRCUIT DIAGNOSIS PROCEDURE ............................................................. 130 6. VIDEO CIRCUIT DIAGNOSIS PROCEDURES ......................................................................... 131

5

SECTION I OUTLINE

6

1. OUTLINE OF N5SS CHASSIS (CN32E90, CN35E90)
The N5SS chassis is a complete bus control type chassis where the deflection circuit is controlled by a newly developed I2C-bus line control system.

3. MAJOR SPECIFICATIONS (NEW FUNCTIONS IN ADDITION TO THOSE OF N5SS)
(1) EOS (Extended-Data-Service) (2) Center-Ch-Audio-Input provided

2. PC BOARD CONFIGURATION
(1) (2) (3) (4) Signal unit Power/def unit A/V, CRT-D, SP-TERM CCD, comb (CN32E90) Digital comb (CN35E90) (5) D.S.P unit (6) C.C, EDS/R.G.B SW

4. MODIFICATIONS ON CHASSIS
(1) Serviceability improved with direct, front access system employed. (2) One touch cabinet securing (CN32E90) to the chassis. (3) Improved serviceability with the bus control system employed for the defection circuits. (4) Improved serviceability with the white balance bus control system employed. (5) Digital comb/CCD miniaturized into a socketable size.

7

5. CONSTRUCTION OF CHASSIS
DPC circuit

CCD circuit PIP circuit SIGNAL circuit IF/MTS/A-PRO module AUDIO OUT EDS, RGB SW circuit

CRT circuit

REAR AMP circuit

CONVERTER trans A/V circuit

8

Fig. 1-1
POWER/DEF circuit V. OUT DPC circuit H.OUT H.OUT trans

RF SW

6. LOCATION OF CONTROLS
6-1. TV Set For specific use of each control, consult the corresponding page numbers in brackets.

Front View

POWER indicator

POWER

POWER button Remote sensor

Press to open the door

Behind the door

VIDEO/AUDIO IN jacks <VIDEO 3>

CHANNEL

buttons

DEMO button

VOLUME -/+buttons

buttons

MENU button

ANT/VIDEO button ADV button

Fig. 1-2 9

Rear view

S-VIDEO IN jack <VIDEO 1>

ANTenna terminals

VARiable AUDIO OUT jacks

EXTernal SPEAKER terminals

MAIN SPEAKER switch REAR SPEAKER terminals

VIDEO AUDIO OUT jacks PIP AUDIO OUT jacks VIDEO/AUDIO IN jacks <VIDEO 2> VIDEO/AUDIO IN jacks <VIDEO 1>

Fig. 1-3 10

6-2 Location of Controls (Remote Control) Only the buttons that are used to operate the TV set are described here. For details on the use of each control, refer to pages in brackets.

Aim at the remote sensor on the TV

Learn/Transmit indicator

TIMER button

EDS button TV/CABLE/VCR/AUX switch Set to "TV" to control the TV.

RECALL button POWER button MUTE button

TV/VIDEO

Channel Number buttons

CHANNEL VOLUME

buttons buttons

RTN buttons PIP function buttons

AUDio button PICture button RESET button ANT 1/2 button C.CAPT button CYS/SBS button Learning buttons You can use these eight buttons only as Learning function buttons. They are not affected by Mode selection (TV/CABLE/ VCR/AUX).

SET UP button OPTION button EXIT button

-\+ buttons FAV -/+ buttons
DSP/SUR button DSP F/R button

LEAR/USE switch

To operate buttons inside the cover, slide the cover down and toward you.

Fig. 1-4 11

6-3 Monitor Panel This TV set is equipped with S-VIDEO INPUT jacks, VIDEO/AUDIO INPUT jacks, VIDEO/AUDIO OUTPUT jacks, VARIABLE AUDIO OUTPUT jacks, PIP AUDIO OUTPUT jacks and EXTERNAL SPEAKER terminals for connecting your desired video/audio equipment.

5

3

9 TV Rear TV Front

4

7

10

11

1

2

8

6

Fig. 1-5

,

,

VIDEO 1/VIDEO 2/VIDEO 3 IN Jacks — provide for direct connection of video devices (VCR, video disc player, camcorder, etc.) with video/audio outputs. S-VIDEO IN Jacks —provide for direct S-video VCR or a video disc connection from an player. The TV's VIDEO 1/3 audio jacks can also be used to connect the VCR's audio cables. VIDEO/AUDIO OUT Jacks --- provide fixedlevel audio and video outputs from whatever is displayed on the screen. VARIABLE AUDIO OUT Jacks --- feed volume-controlled stereo audio out from whatever is displayed on the screen, allows connection of audio amplifier and lets you adjust sound level with TV's remote. 12

PIP AUDIO OUT Jacks — provide fixed-level audio outputs from whatever is displayed on the PIP window screen. EXTERNAL SPEAKER Terminals — provide for direct connection of external speakers. MAIN SPEAKER Switch — lets you turn off TV's built-in speakers so that sound will instead come through speakers connected to EXTERNAL SPEAKER terminals. REAR SPEAKER Terminals — provide for direct connection of the supplied Surround Speakers.

,

CRT DRIVE PCB

U/V
SYNC SIGNAL DET.
12
SYNC G 42 B 41 R 43

SIGNAL UNIT
SPEED MOD RED OUTPUT 143 144 144 145 BLUE OUTPUT 145 143 GREEN OUTPUT

HY01(CHILD) TUNER IF EL922L
58 Y 38 I 37 O 35 34 Ys 1 4 34 G 33 B SDA SCL 27 28 13
C H 23

SDA

SCL

4

3

CRT

Q501 TA1222N
V 31

+200V

V

H

H001(MOTHER) 9 TUNER IF EL466L
32 Ys 35 R 83 84 35 83

2

SDA
B 6

SCREEN FOCUS HIGH VOLTAGE

7. CN32D90 BLOCK DIAGRAM

11

12

8

PIP
V MODULE G 5

R

SCL

H002 S(L) V/SIF/MTS 18 MVUS34S 16 6 22 S(R) V

301 V OUTPUT 2 TA8427K Q302 E/W CORRECTION TA8859AP Q402 H DRIVE 2SC1569FA-5 Q404 H OTUTPUT 2SD2253(FA)

R370 +27V

Q370 2SA933SQ Q462 DPC 2SC1740S-Q

32

31

30

29

I2C-BUS LINE

KEY CONTROL I 2C Bus line

SDA

SCL

STOP SYNC

T461

QA01 MICROCOMPUTER TMP87CS38N-3152

EDS/C.C
TB40 D840

-27V
D371

FBT

CONVERTER TRANS

Q670 AUDIO OUT
AI AT VAR-R VAR-L

VIDEO OUTPUT

L R W
9V-2 Q832

4 2 1

11

TA8256H

8 12 R L W 40

R883 Q862 PHOTO-COUPLER TLP621GR-L

A/V PCB
VAR AUDIO
5V-3 5V-2

L

R

L

R

PIP AUDIO

Q831 R Q830 L WOOFER

VOLTAGE REG. OVER VOLTAGE } PROTECTOR OVER HEAT STR-

13
CCD UNIT PB5419
V
DG 5A DC DD

5

6

VIDEO INPUT 3 Y C
F801 TB01

SDA SCL ICA02 MEMORY 24LCO4BI/P ST24C04CB6

KEY CONTROL

HEATER

TFB 4132AD 4132BD
SR801 D801 T862 D883 Q801 F470 2A +125V 33V D471 D885 F883 5A

Fig. 1-6
V-AV EA EH 43 45 30 32 Y-COMB C-COMB AB AA EJ EI AJ

Z801 PROTECTOR L78MR05 D847 Q840
RESET

+24.5V +12V

38 V

Q420

9V-1

VIDEO INPUT 2

VIDEO INPUT 1

36 V L R Y R L QV01 SIGNAL SW TA1218N Y V SDA SCL C C 42 25 24 1 2 34

POWER/DEF UNIT

STBY 5V

2SC1B15Y QE06 SW

8. [US, CANADA] SPECIFICATION FOR MODEL's 1995
CHASSIS MODEL Nbr SPECIFICATION * G E N E R A L CRT C CN27E90 HITACHI *FST-D/T 181ch q q q q *A-Univ (42k) q (2TN) q (Power) 8key — — q q — *10Wx2 & 13W *80x120x2 & 100R (Hon) *q (GLS) — q q q *q *q q 650 q q q *q/q *q *q — q (1+1) 1+2/— *q q q q — — -— NEW — 14 C CX32E70 TDD NF-D/T 181ch q q q q *A-Univ (42k) q (2TN) q (Power) 8key — — q — q 10Wx2 70x130x2 q (CCD) — q q q q q q 700 q q q q/q *q *q — q (1+1) 1+2/1 q q q q *— *q — — CX32D70 — C CN32E90 TDD NF-D/T 181ch q q q q *Intelig+EZ q (2TN) q (Power) 8key q q (DSP4ch) — q — 10Wx2 & 13W & 5Wx2 80x120x2 100R & REAR q (CCD) — q q q q q q 700 q q q q/q *q *q — q (1+1) 1+2/1 q q q q *q *— q SS-SR94 — CN32D90 — C CE35E15 DERIV *TDD *FST-D/T 181ch q q q q *Unive (36k) *q (1TN) *q (Power) 8key — — q — — 10Wx2 70x130x2 q (CCD) — q q q q q q 800 q q q q/q *q *q — q (1) *3/1 — q — q — — — — *CE35D10 — C CF35E50 *TDD FST-D/T 181ch q q q q *Unive (36k) q (1TN) q (Power) 8key — — q — — 10Wx2 70x30x2 q (GLS) — q q q q q q 800 q q q q/q *q *q — q (1) 3/1 — q — q — — — — CF35D50 —

1 Picture Tube 2 Channel Capacity 3 C. Caption 4 MTS with dbx 5 Bass, Tre, Balance 6 Sub-Audio-Program 7 Remote band unit 8 Picture-in-Picture 9 LED Indicators (RED) 10 Local Keys 11 Dolby Surround 12 Dig-Sound Processor 13 Front Surround 14 Cyclone ABX 15 Sub-Bass-System 16 Audio Output 17 Speaker Size & Nbr 18 Comb Filter 19 Dy-Quadruple Focus 20 Scan Velocity Modu 21 Vert Contour Corre 22 Black Level Expand 23 Flesh Tone Correct 24 Dynamic Noise Reduc 25 Picture Preference 26 Horiz Resolution 27 Parental-Ch Lock 28 Channel Label (32ch) 29 3-Language Display 30 Clock/Off-Timer 31 Favorite Channel 32 Extended-Data-Servi 33 Star-Sight-decoder 34 S-Video In-Term 35 Audio, Video-In/Out 36 Front AV Jack 37 Variable Audio Out 38 2-RF Input 39 Ext Speaker Term 40 PIP Audio Out Jack 41 Center-Ch-Aud-Input 42 Speaker-Box 43 Others *Cabinet PARTS SUPPLY (ISO)

* S O U N D

* P I C T U R E

* O T H E R

* T E R M S

* AC

CHASSIS MODEL Nbr SPECIFICATION * G E N E R A L CRT

C CX35E60 TDD FST-D/T 181ch q q q q *A-Univ (42k) q (2TN) q (Power) 8key — — q — q 10Wx2 70x130x2 q (DIG) q q q q q q q 800 q q q q/q *q *q — q (1+1) 1+2/1 q q q q — — — C35D60 — 15

C CX35E70 TDD NF-D/T 181ch q q q q *A-Univ (42k) q (2TN) q (Power) 8key — — q — q 10Wx2 70x130x2 q (DIG) q q q q q q q 800 q q q q/q *q *q — q (1+1) 1+2/1 q q q q *— *q — — CX35D70 —

C CX35E81 CONSOLE TDD NF-D/T 181ch q q q q *A-Univ (42k) q (2TN) q (Power) 8key — — q — q 10Wx2 70x130x2 q (DIG) q q q q q q q 800 q q q q/q *q *q — q (1+1) 1+2/1 q q q q *— *q — *VCR-Storate NEW (DAX) —

C CN35E90 TDD NF-D/T 181ch q q q q *Intelig+EZ q (2TN) q (Power) *8key q q (DSP4ch) — q — 10Wx2 & 13W, 5Wx2 80x120x2 & *100R, REAR q (DIG) q q q q q q q 800 q q q q/q *q *q — q (1+1) 1+2/1 q q q q *q *— q SS-SR94 — CN35D90 —

C CN35E95 CINEMA TDD NF-D/T 181ch q q q *q *Intelig+EZ q (2TN) q (Power) *8key q q (DSP4ch) — q — 10Wx2 & 13W, 5Wx2 80x120x2 & *120R, REAR q (DIG) q q q q q q q 800 q q q q/q *q *q — q (1+1) 1+2/1 q q q q *q *— q SS-SR94 *VCR-Stora NEW (BLK) —

1 Picture Tube 2 Channel Capacity 3 C. Caption 4 MTS with dbx 5 Bass, Tre, Balance 6 Sub-Audio-Program 7 Remote band unit 8 Picture-in-Picture 9 LED Indicators (RED) 10 Local Keys 11 Dolby Surround 12 Dig-Sound Processor 13 Front Surround 14 Cyclone ABX 15 Sub-Bass-System 16 Audio Output 17 Speaker Size & Nbr 18 Comb Filter 19 Dy-Quadruple Focus 20 Scan Velocity Modu 21 Vert Contour Corre 22 Black Level Expand 23 Flesh Tone Correct 24 Dynamic Noise Reduc 25 Picture Preference 26 Horiz Resolution 27 Parental-Ch Lock 28 Channel Label (32ch) 29 3-Language Display 30 Clock/Off-Timer 31 Favorite Channel 32 Extended-Data-Servi 33 Star-Sight-decoder 34 S-Video In-Term 35 Audio, Video-In/Out 36 Front AV Jack 37 Variable Audio Out 38 2-RF Input 39 Ext Speaker Term 40 PIP Audio Out Jack 41 Center-Ch-Aud-Input 42 Speaker-Box 43 Others *Cabinet PARTS SUPPLY (ISO)

* S O U N D

* P I C T U R E

* O T H E R

* T E R M S

* AC

SECTION II TUNER, IF/MTS/S.PRO MODULE

16

1. CIRCUIT BLOCK
IF/MTS/S.PRO Module MVUS34S EL466L Tuner RF AGC
C-IN R-IN L-IN TP12 Video output TV R-OUT TV L-OUT C-OUT R-OUT L-OUT (L+R) -OUT

SAW Filter

VIF/SIF Circuit

SIF output

Sound Multiplex Circuit

S.PRO Circuit

AFT output

To A/V switch circuit

Fig. 2-1 Block diagram

1-1. Outline (1) RF signals sent from an antenna are converted into intermediate frequency band signals (video: 45.75 MHz, audio: 41.25 MHz) in the tuner. (Hereafter, these signals are called IF signals.) (2) The IF signals are band-limited in passing through a SAW filter. (3) The IF signals band-limited are detected in the VIF circuit to develop video and AFT signals. (4) The band-limited IF signals are detected in the SIF circuit and the detected output is demodulated by the audio multiplexer, developing R and L channel outputs. These outputs are fed to the A/V switch circuit. (5) A sound processor (S.PRO.) is provided. 1-2. Major Features (1) The VIF/SIF circuit is fabricated into a small module by using chip parts considerably. (2) As the tuner, EL466L that which contains an integrated PLL circuit is employed. (3) Wide band double SAW filter F1802R used. (4) FS (frequency synthesizer) type channel selection system employed. (5) VIF/SIF circuit uses PLL sync detection system to improve performances shown below: • Telop buzz in video over modulation • DP, DG characteristics (video high-fidelity reproduction) • Cross color characteristic (coloring phenomenon at color less high frequency signal objects) (6) HIC SBX1637A-22 is used in the audio multiplexer circuit to minimize the size with increased performance. (7) As a sound control processor, TA1217N is used. I2Cbus data control the DAC inside the IC to perform switching of the audio multiplexer modes.

17

2. TUNER
2-1. Outline (1) Type name: EL466L (2) Applicable 181CH (3) I2C-bus version (4) PLL-integrated

2-2-2. Terminals (Tuner section) Name IF OUT BM RF AGC VT
EL466L

Function IF outputs (P=45.75 MHz, C=42.17 MHz, S=41.25 MHz) Tuner power supply (9V) Gain control terminal to obtain constant IF output Control voltage to select channels

PLL Selection Tuner Section

2-2-3. Tuner VT Voltage (unit: V) (1) VHF (2) UHF CH MM QQ WW 14 20 26 32 38 44 50 56 62 69 VT voltage (TYP) 1.1 2.2 4.0 5.8 7.8 9.2 10.8 12.5 13.9 15.0 17.2 19.4 23.6

1 2

3

4 5

6

7

8

9

CH 2 6 A-2 B C I 10 J N R W FF LL

VT voltage (TYP) 1.4 6.4 12.8 20.0 1.4 3.5 5.6 7.6 9.7 11.8 14.2 17.9 24.2

Terminal No. 1 2 3 4 5 6 7 8 9

Name 32V 5V S-CLOCK S-DATA ADDRESS IF OUT BM (9V) RF AGC VT

Fig. 2-2 Tuner terminal layout * VT voltage not indicated for a channel falls between those values for channels just upper and lower the channel.

2-2. Operation of the Tuner
2-2-1. Receiver Channels VHF 2~13CH UHF 14~69CH 181CH in total CATV A-6~, J~W, AA~BBB, 65~92, 100~127CH

18

3. IF/MTS/S.PRO MODULE
The IF/MTS/S.PRO module (MVUS34S) limits bandwidth of IF signals and detects video and audio signals. The module consists of IF amplifiers, SAW (surface acoustic wave) filter, and PIF IC. The SAW filter has a wideband response to improve picture quality and audio buzz characteristic and, develops separate outputs of video and audio signals. The PIF IC employs a PLL complete sync detection + audio split carrier system. 3-1. IF/MTS/S.PRO Module (MVUS34S) 3-1-1. Module Terminal Layout

3-1-2 Video PIF Circuit A PIF detector switching carrier is oscillating at a frequency adjusted to 45.75 MHz with L051 (VCO CW coil) under no RF signal input. When an RF signal enters, an IF video carrier is fed to APC section from IF AMP inside the IC, and the detector switching carrier is adjusted by the APC, VCO, etc. in the PLL circuit so that its frequency and phase are matched to those of the IF video carrier to perform precise sync detection. Thus processed video output is developed at pin 21. PLL lock speed is automatically controlled by adding the video signal at pin 21 to pin 1. That is, since the video signal is not output at operations of power on, CH switching, etc., the APC filter between pin 16 and GND consists of C022 and C053, and R018, and the filter effect decreases, thus increasing PLL lock speed. Next, when a video out exists, the internal resistance is shortcircuited and the APC filter consists of C022 and C053, internal resistance, and R018. As a result, the filter effect increases and the PLL lock speed decreases. Consequently, under normal signal reception, phase of the detector switching carrier is locked in a stable condition if an IF video carrier is lost for a short time due to over modulation, etc. By combining such a PLL complete sync detection system and a wideband SAW filter shown in Fig. 2-4, a wideband (4.2 MHz) video detection output with less beat interference will be obtained.

27

12

9

1

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14

Name GND IF-IN NC +9V RF AGC AFC VIDEO OUT ADR SW MPX OUT ----TV R-OUT DAC-OUT1 TV L-OUT

Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27

Name DAC-OUT2 R-IN C-IN L-IN GND SCL SDA W-OUT C-OUT L-OUT GND R-OUT +9V

3-1-3. Audio PIF Circuit The IF signal fed through Q003 (Fig. 2-4) enters an audio section of the SAW filter (Z001) which has an IF bandwidth for dedicated audio signals, and only the audio signal of 41.25 MHz is fed to pin 7. The signal is sync-detected with the detection carrier completely synchronized with the IF video carrier and pin 14 develops a 4.5 MHz SIF signal. By using the PLL split carrier system just stated, audio signals with less buzz by the video signal will be reproduced. The 4.5 MHz SIF enters pin 15 through a 4.5 MHz filter, Z003 and pin 9 develops a FM-detected audio signal.

Fig. 2-3 IF/MTS/S.PRO module terminal layout

19

4.5MHz SIF SIGNAL Z003 FM DET. COIL L053 SIF BANDWIDTH
15 11 12

SIF LIMIT
14.

FM DET.

9

17.

R151 L051 VCO CW COIL
C106

TO SOUND MPX IC

Q002

S

SIF DET

APC VCD
18 23

Q003 IF AMP GAIN – 14dB
Z001 SAW FILTER
7

L502 AFT COIL
IF AMP VIDEO DET.
21

5 4 22

F1802R

R021
LOCK CONTROL

TP12 Q004

-6dB

Z002
1

AGC
2 13 16

-15dB

20

R022
R018
RF AGC R051

S C

P

C022 C053

41.25M 45.75M VIDEO IF BANDWIDTH

1 GND

2 IF-IN

3

4 N.C

5 +B(9V)

6 RF AGC

7

8 AFC

9 VIDEO OUT ADR SW M

Fig. 2-4 IF/MTS/S. PRO circuit diagram

20

3-1-4. Audio Multiplex Demodulation Circuit The sound multiplex composite signal FM-detected in the PIF circuit enters pin 12 of HIC (hybrid IC) in passing through the separation adjustment VR RV2 and amplified. After the amplification, the signal is split into two: one enters a de-emphasis circuit, and only the main signal with the LR signal and a SAP signal removed enters the matrix circuit. At the same time, the other passes through various filters and trap circuits, and the L-R signal is AM-demodulated, and the SAP is FM-demodulated.

Then, both are fed to the matrix circuit. At the same time, each of the stereo pilot signal fH and the SAP pilot signal 5fH is also demodulated to obtain an identification voltage. With the identification voltage thus obtained and the user control voltage are used to control the matrix. The audio signals obtained by demodulating the sound multiplex signal develop at pin 10 and 11 of HIC and develop the terminals of 12 and 14 of the module.

MVUS32S

MPX Out
9 10 11

DAC-out1 TV TV R-Out (SURR OFF) L-Out
12 13 14

DAC-out2 (RFSW)
14

Monitor the input pin for multiplex sound IC

Stereo 0V Other 0V

SAP 0V Other 0V

OFF ON

0V 9V

RF1 0V RF1 9V

Not used for CN32E90.

TV waveform detection output (R)

TV waveform detection output (L)

To AV select circuit

Fig. 2-5 Block diagram of MVUS32S

Table 2-1 Matrix for broadcasting conditions and reception mode Output OSD display Broad- Switching 12 pin 14 pin casted mode Stereo SAP (R) (L) Stereo STE SAP MONO Mono STE SAP MONO Stereo STE + SAP SAP MONO Mono + SAP STE SAP MONO R R L+R L+R L+R L+R R SAP L+R L+R SAP L+R L L L+R L+R L+R L+R L SAP L+R L+R SAP L+R O O O X X X O O O X X X X X X X X X O O O O O O

Note: Of the mode selection voltages, switching voltages for STE, SAP, MONO do not output outside the module. They are used inside the module to control the BUS.

21

3-1-5. A.PRO Section (Audio Processor) The S.PRO section has following functions. (1) Woofer processing (L+R output) (2) High band, low band, balance control (3) Sound volume control, cyclone level control (4) Cyclone ON/OFF

All these processing are carried out according to the BUS signals sent from a microcomputer. Fig. 2-6 shows a block diagram of the A.PRO IC.

TA1217N

1

27 29 22 32 33

30

9

8

28

Lin Rin Cin

30 BALANCE 34 2 TONE CONTROL Center LEVEL

26 Lout 25 Rout VOLUME 18 10 Woofer LEVEL 17 16 I/O 15 14 Cout Wout

Win

3

LPF

SDA 20 I C SGL 21
2

13 D/A CONV 12 11 SAP det. STE det.

4

5

6

7

31

24

23

22

19

16

17

18

19

20

21

22

23

24

25

26

27

R-in

C-in

L-in

SCL

SDA

W-out O-out

L-out

R-out 9V

From From A/V Dolby

From A/V

Q670 Q640

Q670

Q670

Via QS101

Fig. 2-6 A.PRO block diagram

22

4. PIP TUNER

Lable Name Lot No.
TUNER SECTION SAW FILTER VIF/SIF CIRCUIT

RF AGC
1 15

VIDEO AUDIO AFT OUTPUT OUTPUT OUTPUT

Fig. 2-7

Terminal No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Name NC 32V S-CLOCK S-DATA NC ADDRESS 5V RF AGC 9V AUDIO GND AFT NC GND VIDEO

4-1. Outline The PIP tuner (EL922L) consists of a tuner and an IF block integrated into one unit. The tuner receives RF signals induced on an antenna and develops an AFT output, video output, and audio output. The tuner has receive channels of 181 as in the tuner for the main screen and it is also controlled through the I2C-bus. As the IC for the IF, a PLL complete sync detection plus audio inter carrier system are employed.

Fig. 2-8 Tuner terminal layout

23

SECTION III CHANNEL SELECTION CIRCUIT

24

1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM
The channel selection circuit in the N5SS chassis employs a bus system which performs a central control by connecting a channel selection microcomputer to a control IC in each circuit block through control lines called a bus. In the bus system which controls each IC, the I2C bus system (two line bus system) developed by Philips Co. Ltd. in the Netherlands has been employed. The ICs controlled by the I2C bus system are : IC for audio signal processing (QN06), IC for V/C/D signal processing (Q501), IC for A/V switching (QV01), IC for non volatile memory (QA02), Main and sub U/V tuners (H001, HY01), IC for deflection distortion correction (Q302), IC for PIP signal processing (QY04), IC for DSP (QM01), IC for closed caption control (Q701). Differences from N4SS chassis are as follows; 1. On-screen function inside microcomputer is used. Separate IC is not used for on-screen. 2. The microcomputer does not have the closed caption function, but controls separate IC for closed caption. 3. The system uses two channels of I2C bus. One is only for non-volatile memory.

• Setting of memory values for video parameters such as white balance (RGB cutoff, GB drive) and gcorrection, etc. • Setting of video parameters of video modes (Standard, Movie, Memory) (3) CONTROL OF A/V SWITCH IC (QV01 Toshiba TA1219N) • Preforms source switching for main screen and sub screen • Performs source switching for TV and three video inputs (4) CONTROL OF NON-VOLATILE MEMORY IC (QA02 Microchip 24LC04BI/P) • Memorizes data for video and audio signal adjustment values, volume and woofer adjustment values, external input status, etc. • Memorizes adjustment data for white balance (RGB cutoff, GB drive), sub-brightness, sub color, sub tint, etc. • Memorizes deflection distortion correction value data adjusted for each unit. (5) CONTROL OF U/V TUNER UNIT (H001 Matsushita EL466L, HY01 Toshiba EL922L) • A desired channel can be tuned by transferring a channel selection frequency data (divided ratio data) to the I2C bus type frequency synthesizer equipped in the tuner, and by setting a band switch data which selects the UHF or VHF band. (6) CONTROL OF DEFLECTION DISTORTION CORRECTION IC (Q302 Toshiba TA8859P) • Sets adjustment memory value for vertical amplitude, linearity, horizontal amplitude, parabola, corner, trapezoid distortion. (7) CONTROL OF PIP SIGNAL PROCESS IC (QY04 Toshiba TC9083F) • Controls ON/OFF and position shift of PIP. (8) CONTROL OF DIGITAL SOUND PROCESSOR IC (QM04 Yamaha YSS238-D) • Performs mode switching of DSP. (9) CONTROL OF CLOSED CAPTION/EDS (QM01 Motorola XC144144P) • Controls Closed Caption/EDS.

2. OPERATION OF CHANNEL SELECTION CIRCUIT
Toshiba made 8 bit microcomputer TLCS-870 series for TV receiver, TMP87CS38N-3152 is employed for QA01. With this microcomputer, each IC and circuit shown below are controlled. (1) CONTROL OF AUDIO SIGNAL PROCESS IC (QN06 Toshiba TA1217N) • Adjustments for volume, treble, bass and balance • Selection between surround mode and DSP mode, and level adjustment • Level adjustment of BAZOOKA system • Audio muting during channel selection or no signal reception. (2) CONTROL OF VIDEO/CHROMA/DEF SIGNAL PROCESS IC (Q501 Toshiba TA1222N) • Adjustments for uni-color, brightness, tint, color gain, sharpness and PIP uni-color • Setting of adjustment memory values for subbrightness, sub-color and sub-tint, etc.

25

3. MICROCOMPUTER
Microcomputer TMP87CS38N-3152 has 60k byte of ROM capacity and equipped with OSD function inside. The specification is as follow. • Type name : TMP87CS38N-3152 • ROM : 60k byte • RAM : 2k byte • Processing speed : 0.5m s (at 8MHz with Shortest command) • Package : 42 pin shrink DIP • I2C-BUS : two channels • PWM : 14 bit x 1, 7 bit x 9 • ADC : 8 bit x 6 (Successive comparison system, Conversion time 20ms) • OSD Character kinds : 256 Character display : 24 characters x 12 lines Character dot : 14 x 18 dots Character size : 3 kinds (Selected by line) Character color : 8 colors (Selected by character) Display position : Horizontal 128 steps, Vertical 256 steps This microcomputer performs functions of AD converter, reception of U/V TV and OSD display in one chip. IIC device controls through I2C bus. (Timing chart : See fig. 3-1) • LED uses big current port for output only. • For clock oscillation, 8MHz ceramic oscillator is used. • I2C has two channels. One is for EPROM only. • Self diagnosis function which utilizes ACK function of I2C is equipped • Function indication is added to service mode. • Remote control operation is equipped, and the control by set no touch is possible. (Bus connector in the conventional bus chassis is deleted.) • Substantial self diagnosis function (1) B/W composite video signal generating function (micom inside, green crossbar added) (2) Generating function of audio signal equivalent to 1kHz (micom inside) (3) Detecting function of power protection circuit operation (4) Detecting function of abnormality in IIC bus line (5) Functions of LED blink indication and OSD indication (6) Block diagnosis function which uses new VCD and AV SW

SDA SCL START CONDITION

1-7 ADDRESS

8 R/W

9 Ack

1-7

8 DATA

9 Ack

1-7 DATA

8

9 Ack STOP CONDITION

Approx.180mS

Some device may have no data, or may have data with several bytes continuing.

Fig. 3-1

26

4. MICROCOMPUTER TERMINAL FUNCTION

TMP87CS38N3152 (QA01)

GND BAL REM OUT MUTE SP MUTE NC POWER LED NC NC IIC -BUS SCL0 SDA0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 I O O O O O O O I O IO I I I I I I O O

GND P40 (PWM0) P41 (PWM1) P42 (PWM2) P43 (PWM3) P44 (PWM4) P45 (PWM5) P46 (PWM6) P47 (PWM7) P50 (PWM8/TC2) P51 (SCL1) P52 (SDA1) P53 (AINO/TC1) P54 (AIN1) P55 (AIN2) P56 (AIN3) P60 (AIN4) P61 (AIN5) P62 P63 VSS

VDD P57 P32 P57 SDA0 SCL0 (TC3)P31 (RXIN)P30 P20 RESET XOUT XIN TEST 0SC2 0SC1 VD HD Y/BL B G R IO O I I I I O I I O I I I O O O O I

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

VDD ACP NC GND SDA1 SCL1 IICBUS

SYNC AV1 RMT IN SW IN RESET XOUT XIN TEST 0SC1 0SC2 VSYNC HSYNC Ys BOUT GOUT ROUT

SYNC VCD NC AFT2 AFT1 KEY-A KEY-B SGV SGA GND

Fig. 3-2

27

<< MICROCOMPUTER TERMINAL NAME AND OPERATION LOGIC >> No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Terminal Name Function GND BAL REM OUT MUTE SP MUTE DEF POW POWER LED POWER LNB LNB DET SCL() SDA() SYNC VCD AFT2 IN AFT1 KEY A KEY B SGV SGA VSS R G B Y/BL HSYNC VSYNC OSC1 OSC2 TEST XIN XOUT RESET SW IN RMT IN SYNC AV1 SCL1 SDA1 GND NC ACP VDD NSYNC INPUT POWER In — AC pulse input 5V 5V REMOTE CONTROL SIGNAL INPUT HSYNC INPUT IIC BUS CLOCK OUT IN In Out In remote control pulse input=L External H. sync signal input IIC bus clock output 1 IIC bus data input/output 1 In reception of remote pulse Pulse Pulse Pulse 0V DISPLAY CLOCK DISPLAY CLOCK TEST MODE SYSTEM CLOCK SYSTEM CLOCK SYSTEM RESET UV MAIN S-CURVE SIGNAL LOCAL KEY INPUT LOCAL KEY INPUT TEST SIGNAL OUT TEST AUDIO OUT POWER GROUNDING R G B BL IIC BUS CLOCK OUT INPUT BALANCE REMOTE CONTROL SIGNAL OUT SOUND MUTE OUT SPEAKER MUTE POWER ON/OFF OUT POWER LED OUTPUT In/Out Out Out Out Out Out Out Out Out In Out IIC bus clock output 0 IIC bus data input/output 0 Main picture H. sync signal input Sub tuner AFT S-curve input Main tuner AFT S-curve signal input Local key detection: 0 to 5V Local key detection: 0 to 5V Test signal output In normal=L Test audio output In normal=L 0V: Gounding voltage 0V 0V 0V At display on:Pulse At dispaly on:Pulse At dispaly on:Pulse HSYNC for OSD display VSYNC for OSD display 4.5MHz GND fixed System clock input System clock output 8MHz System reset input (In reset=L) At dispaly on:Pulse Pulse Pulse Pulse Pulse 0V 8MHz pulse 8MHz pulse 5V IIC BUS DATA IN/OUT In/Out H SYNC INPUT In In In In In Out Out — Out Out Out Out In In Out In In In Out In Logic PWM out Remote control output Sound mute output In muting = H Power control In ON=H Power LED on-control LED lighting=L 0V 0V Remarks 0V

IIC BUS DATA IN/OUT In/Out

28

5. EEPROM (QA02)
EEPROM (Non volatile memory) has function which, in spite of power-off, memorizes the such condition as channel selecting data, last memory status, user control and digital processor data. The capacity of EEPROM is 8k bits. Type name is 24LC04BI/ P or ST24C04CB6, and those are the same in pin allocation and function, and are exchangeable each other. This IC controls through I2C bus. The power supply of EEPROM and MICOM is common. Pin function of EEPROM is shown in Figure 3-3.

EEPROM(QA02)

A0 Device adress GND A1 A2 Vss

1 2 3 4

8 7 6 5

Vcc + 5V NC SCL I2C-BUS line SDA

Fig. 3-3

6. ON SCREEN FUNCTION
ON SCREEN FUNCTION indicates data like channel, volume. Formerly, exclusive use of OSD IC was used, but in N5SS, OSD function is involved in microcomputer. Pin function concerning on-screen is shown in figure 3-4. Oscillation clock of OSD is approx. 4.5MHz. 9MHz which becomes twice in microcomputer is dot clock. For oscillation coil, TRF1160D (LA02) is used.

QA01 OSC2 OSC1 VD HD Y/BL B G R O I I I O O O O 29 28 27 26 25 24 23 22 OSC2 OSC1 VSYNC HSYNC Ys/Ym BOUT GOUT ROUT COLOR SIGNAL VG OSC OUT OSC IN H. SYNC SIGNAL V. SYNC SIGNAL HALF TONE SIGNAL

Fig. 3-4

29

7. SYSTEM BLOCK DIAGRAM
QA01 TMP87CS38N-3152

QA02 MEMORY 24LC04B1/P SDA 5 SCL 6

SDA 1 SCL 1

38 37
REMOTE SENSOR UNIT

H001 MAIN U/V TUNER EL446L SDA SCL

RMT

35

11 12

SCL 0 SDA 0 KEY-A 17 18 33 42 1 21 7 41 8 H002 31 32 8MHz CLOCK SDA SDA 27
POWER SUPPLY CIRCUIT

HY01 SUB U/V TUNER EL922L KEY SWITCH SDA SCL

H. SYNC PULSE VSYNC PULSE

26 27

HSYNC VSYNC

KEY-B

RST
VIDEO SIGNAL PROCESS CIRCUIT

22 23 24 25

R G B YS/TM RMT OUT

VDD GND VSS POWER ACP

Q501 VCD TA1222 SCL 28

REMOTE CONTROL OUTPUT

3

LED XIN XOUT

SOUND MUTE SPEAKER MUTE

4 5

MUTE SP MUTE

IF/MPX MVUS345 SCL 20

Q701 C/C, EDS XC144144P DATA CLK

OSCI OSCO

28 29

6.1MHz CLOCK

21

SGV SGA

19 20

SIGNAL OUTPUT

MAIN SCREEN SYNC-AV1 AFT1 IN DPC UNIT SUB SCREEN DATA CLK SYCN-AV2 AFT2 IN QY04 13 2 SYNC DET. AFT DET. QM01 DSP SDA SCL 36 16 SYNC DET. AFT DET. AV SW TA1219N SDA 26 SCL 27 QV01

PIP CONTROL DATA CLK 6 5

Fig. 3-5 30

8. LOCAL KEY DETECTION METHOD
Local key detection in the N5SS chassis is carried out by using analog like method which detects a voltage appears at local key input terminals (pins 17, 18) of the microcomputer when a key is pushed. With this method using two local key input terminals ( pins 17,18), key detection up to maximum 14 keys will be carried out. The circuit diagram shown left is the local key circuit. As can be seen from the diagram, when one of key among SA-01 to SA-08 is pressed, each of two input terminal (pins 17, 18) developes a voltage Vin corresponding to the key pressed. (The voltage measurement and key identification are carried out by an A/D converter inside the microcomputer and the software.

15 S15-1

16

S16-1

S15-2

S16-2

S15-3

S16-3

S15-4

S16-4

S15-5

S16-5

S15-6

S16-6

S15-7

S16-7

Fig. 3-6. Local key assignment

Key No. SA-02 SA-03 SA-04 SA-05 SA-06 SA-07 SA-08

Function POWER CH UP CH DN VOL UP VOL DN ANT/VIDEO, ADV MENU

Key No. SA-01

Function DEMO START/STOP

Table 3-1. Local key assinment

31

9. REMOTE CONTROL CODE ASSIGNMENT
Custom codes are 40-BFH Applicable Function to remote Applicable Contito TV set nuty control 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 6 Channel 8 Channel 8 Channel 100 Channel ANT 1/2 RESET AUDIO PICTURE/FUNC TV/VIDEO MUTE CHANNEL SEARCH POWER MTS ADD/ERASE TIMER/CLOCK AUTO PROGRAM CHANNEL RETURN DSP/SUR (TV/CATV) CONTROL UP VOLUME UP CHANNEL UP RECALL CONTROL DOWN VOLUME DOWN CHANNEL DOWN PIP LOCATE PIP LOCATE PIP LOCATE PIP LOCATE CARVER SURROUND UP SURROUND DOWN VOCAL ZOOM CHANNEL LOCK PIP CHANNEL UP PIP CHANNEL DOWN PIP STILL/RELEASE PIP ZOOM, ZOOM SIZE PIP LOCATE PIP SOURCE Custom codes are 40-BFH Applicable Function to remote Applicable Contito TV set nuty control PIP STILL PIP ON/OFF Do not use. Old type core power ON PIP SWAP PIC SIZE DSP F/R WIDE/SCROLL CAPTION EXIT CYCLONE, SBS SER UP OPTION SUB WOOFER UP SUB WOOFER DOWN

Code 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH

Code 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH

MENU EDS ADV UP ADV DWN

PIP CONTROL

Do not use. Old type core power ON

NOISE CLEAN

PIP VOLUME UP PIP CONTROL PIP VOLUME DOWN

32

Code C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH DFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH

Custom codes are 40-BFH Applicable Applicable ContiFunction to remote to TV set nuty control

Custom codes are 40-BFH Code A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH Function SUB-BRIGHT ADJUSTMENT G. DRIVE ADJUSTMENT B. DRIVE ADJUSTMENT
CUTOFF DRIVE 40H INITIALIZING, HORIZONTAL ONE LINE

Applicable Contito TV set nuty

PIP LOCATE PIP LOCATE PIP LOCATE PIP LOCATE PIP STROBE PIP STROBE SPEED PIP CHANNEL SEARCH

R. CUTOFF ADJUSTMENT G. CUTOFF ADJUSTMENT B. CUTOFF ADJUSTMENT MEMORY ALL AREA INITIALIZE PIP BRIGHT ADJUSTMENT SUB CONTRAST ADJUSTMENT HOR, VER PICTURE POSITON ADJUSTMENT SUB COLOR ADJUSTMENT SUB TINT ADJUSTMNET ADJUSTMENT-UP ADJUSTMENT-DOWN HORIZONTAL ONE LINE: SERVICE DSP ON/OFF TEXT-1 TV/PIP VIDEO CHANGE-OVER CAPTION-1

Do not use. Old type core power ON

PIP VIDEO ADJ. STILL, FRAME ADVANCE SPEED ZOOM

TV/CABLE CHANGE-OVER IN SAME TIME ON MAN AND SUB

HOTEL SETTING MENU DATA 4 TIMES SPEED UP DATA 4 TIMES SPEED DOWN CHANGE-OVER OF HOTEL/NORMAL PIP CENTER M MODE CAPTON OFF ALL CHANNEL PRESET

33

Custom codes are 40-BFH Code E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH E0H E1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH Function PINCUTION/EW CORER (PARA/CNR)
VERTICAL S-CUVE CORRECTION/VERTICAL M-CURVE CORRECTION (VSC/FVC)

Applicable Contito TV set nuty

HORIZONTAL WIDTH (WID/PARA) TRAPEZOIDE CORRECTION (TRAP) TEST TONE DOLBY 3 DIMENTIONAL Y/C SEPARATION DPC STANDARD (HEIGHT LINEARITY) (VLIN/HIT) WIDE (HEIGHT LINEARITY) (VLIN) SCROOL WIDE 1, 2, 3

34

10. ENTERING TO SERVICE MODE
1. PROCEDURE (1) Press once MUTE key of remote hand unit to indicate MUTE on screen. (2) Press again MUTE key of remote hand unit to keep pressing until the next procedure. (3) In the status of above (2), wait for disappearing of indication on screen. (4) In the status of above (3), press MENU (Channel setting) key on TV set. 2. Service mode is not memorized as the last-memory. 3. During service mode, indication S is displayed at upper right corner on screen.

12. SERVICE ADJUSTMENT
1. ADJUSTMENT MENU INDICATION ON/OFF : MENU key ( on TV set) 2. During display of adjustment menu, the followings are effective. a) Selection of adjustment item : POS UP/DN key (on TV/remote unit) b) Adjustment of each item : VOL UP/ DN key (on TV / remote unit) c) Direct selection of adjustment item R CUTOFF : 1 POS (remote unit) G CUTOFF : 2 POS (remote unit) B CUTOFF : 3 POS (remote unit) d) Data setting for PC unit adjustment SUB CONTRAST : 4 POS (remote unit) SUB COLOR : 5 POS (remote unit) SUB TINT : 6 POS (remote unit) e) Horizontal line ON/OFF : VIDEO (TV) f) Test signal selection : VIDEO (remote unit) * In service mode, serviceable items are limited. 3. Test audio signal ON / OFF : 8 POS (remote unit) * Test audio signal : 1kHz 4. Self check display : 9 POS (remote unit) * Cyclic display (including ON/OFF) 5. Initialization of memory : CALL (remote unit) + POS UP (TV) 6. Initialization of self check data : CALL (remote unit) + POS DN (TV) 7. BUS OFF : CALL (remote unit) + VOL UP (TV)

11. TEST SIGNAL SELECTION
1. In OFF state of test signal, SGA terminal (Pin 20) and SGV terminal (Pin 21) are kept “L” condition. 2. The function of VIDEO test signal selection is cyclically changed with VIDEO key (remote unit). Test Signal No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name of Pattern Signal OFF All black signal + R single color (OSD) All black signal + G single color (OSD) All black signal + B single color (OSD) All black signal All white signal W/B Black cross bar White cross bar Black cross hatch White cross hatch White cross dot Black cross dot H signal (bright area) H signal (dark area) Black cross + G

(3) SGA (audio test signal) output should be square wave of 1kHz.

35

13. FAILURE DIAGNOSIS PROCEDURE
Model of N5SS chassis is equipped with self diagnosis function inside for trouble shooting. 1. CONTENTS TO BE CONFIRMED BY CUSTOMER

Contents of self diagnosis A. DISPLAY OF FAILURE INFORMATION IN NO PICTURE (Condition of display) 1. When power protection circuit operates; 2. When I2C-BUS line is shorted;

Display items and actual operation Power indicator lamp blinks and picture does not come.

1. Power indicator red lamp blinks. (0.5 seconds interval) 2. Power indicator red lamp blinks. (1 seconds interval) If these indication appears, repairing work is required.

2. CONTENTS TO BE CONFIRMED IN SERVICE WORK (Check in self diagnosis mode)

Contents of self diagnosis Contents of self diagnosis <Countermeasure in case that phenomenon always arises.> B. Detection of shortage in BUS line C. Check of comunication status in BUS line D.Check of signal line by sync signal detection E. Indication of part code of microcom.(QA01) F. Number of operation of power protection circuit

Display items and actual operation Display items and actual operation

(Example of screen display) SELF CHECK No. 2390XXXX Part code of QA01 POWER : 000000 Number of operation of power protection circuit BUS LINE : OK Short check of bus line BUS CONT : OK Comunication check of busline BLOCK : UV V1 V2 QV01, QV01S
Fig. 2-4

E F B C D

3. EXECUTING SELF DIAGNOSIS FUNCTION [CAUTION] (1) When executing block diagnosis, get the desired input mode (U/V BS VIDEO1,2,3) screen, and then enter the self diagnosis mode. (2) When diagnos other input mode, do again diagnosis operation. (PROCEDURE) (1) Set to service mode. (2) Pressing “9” key on remote unit displays self diagnosis result on screen. Every pressing changes mode as below. SERVICE mode SELF DIAGNOSIS mode

(3) To exit from service mode, turn power off.

36

4. UNDERSTANDING SELF DIAGNOSIS INDICATION In case that phenomenon always arises. See figure 3-4 .

Item BUS LINE

Contents Detection of bus line short

BUS CONT

Communication state of bus line

BLOCK:BS UV1 UV2 V1 V2

The sync signal part in each video signal supplied from each block is detected. Then by checking the existence or non of sync part, the result of self diagnosis is displayed on screen. Besides, when “9” key on remote unit is pressed,diagnosis operation is first executed once.

Instruction of results Indication of OK for normal result, NG for abnormal Indication of OK for normal result Indication of failure place in abnormality (Failure place to be indicated) QA02 NG, H001 NG, Q501 NG, H002 NG QV01 NG, Q302 NG, QY02 NG, HY01 NG QD04 NG, QM01 NG, Q701 NG Note 1. The indication of failure place is only one place though failure places are plural. When repair of a failure place finishes, the next failure place is indi cated. (The order of priority of indication is left side.) *Indication by color • Normal block : Green • Non diagnosis block : Cyan

<Clearing method of self diagnosis result> In the error count state of screen, press “CHANNEL DOWN” button on TV set pressing “DISPLAY” button on remote unit. [CAUTION] All ways keep the following caution, in the state of service mode screen.
• Do not press “CHANNEL UP” button. This will cause initialization of memory IC. (Replacement of memory IC is required. • Do not initialize self diagnosis result. This will change user adjusting contents to factory setting value. ( Adjustment is required.)
White Yellow Cyan Green Magenta Red Blue

( COLOR BAR SIGNAL) Color elements are positioned in sequence of high brightness.

<Method utilizing inner signal> (VIDEO INPUT 1 terminal should be open.)
(1) With service mode screen, press VIDEO button on remote unit. If inner video signal can be received, QV01 and after are normal. (2) With service mode screen, press “8” button on remote unit. If sound of 1kHz can be heard, QV01 and after are normal.

* By utilizing signal of VIDEO input terminal, each circuit can be checked. (Composite video signal, audio signal)

37

14. TROUBLE SHOOTING CHART
(1) TV DOES NOT TURNED ON

TV does not turned on. YES Relay sound NO Check of voltage at pin 7 of QA01 (DC 5V). OK Check power circuit. NG NG

8MHz oscillation waveform at pin 32 of QA01. OK

Check OSC circuit. Replace QA01. NG Pulse output at pins 37 and 38 of QA01. OK Voltage check at pin 32 of QA01 (DC 5V) NG

Check reset circuit. OK

Check relay driving circuit.

Replace QA01.

38

(2) NO ACCEPTION OF KEY-IN

Key on TV

Voltage change at pins 17, 18 of QA01 (5V to 0V). OK Replace QA01.

NG

Check key-in circuit.

Remote unit key

Pulse input at pin 35 of QA01, When remote unit key is pressed. OK

NG

Replace QA01

Check tuner power circuit.

(3) NO PICTURE (SNOW NOISE)

No picture

Voltage at pins of +5V, and 32V. OK

NG

Check H001.

Check tuner power circuit.

39

(4) MEMORY CIRCUIT CHECK

Memory circuit check NG Voltage check at pin 8 of QA02 (5V).

OK

Check power circuit.

NG Pulse input at pins 5 and 6 of QA02 in memorizing operation. OK Check QA01. Replace QA02. Note: Use replacement parts for QA02.

Adjust items of TV set adjustment.

(5) NO INDICATION ON SCREEN

No indication on screen. NG

Check of character signal at pin 23 of QA01. (5VP-P ) OK

Check V/C/D circuit. Input of OSC waveform at pin 29 of QA01 with indication key pressed. OK Check OSC circuit. NG

Check of sync signal at pins 26, 27 of QA01. OK Check sync circuit.

Replace QA01.

40

SECTION IV AUDIO OUTPUT CIRCUIT

41

1. OUTLINE
Configuration of the audio circuit and signal flow are given in Fig 4-1.

A/V PCB VIF+MTS+S.PRO MODULE R 12 L 14 R
VIDEO 1

ICV01
EQ ER 6 R 7 L
MOTHER TV CHILD TV

FOR PIP IF MODULE L 29 R 31 L 2 L R
VIDEO OUTPUT TERMINAL

AUDIO PIP OUT (AUDIO)

L L

VIDEO 2

R

11 L 13 R 3 L 9 R 15 L 17 R

VIDEO 1 VIDEO 2

R 1

R
VIDEO 3 (FRONT INPUT)

L

VIF+MTS+A.PRO MODULE
R out

Q670 R L W

VIDEO 3

25 24 22

2 4 1

12 2 11

R 35 L 37

AS AR

DSP CIRCUIT

16 R
L out

R L W

18 L

W out

R L
VARIABLE AUDIO OUTPUT TERMINAL

PIP OUTPUT AI AJ

Fig. 4-1

42

2. AUDIO OUT IC
2-1. OUTLINE In the model, CN32E90, the main amplifiers and woofer output amplifiers use bipolar IC TA8256H and develop out powers of 10W x 2+13W. 2-2. THORY OF OPERATION 2-2-1. Operatin of TA8256H The TA8256H is a modified version of TA8128AH used in the N4SS chassis as an audio ouput IC. In the TA8256H, one channel is added and a total of 3 channels can be used, but performance for each channel is the same as that of the TA8218H. Fig. 4-2 shows a block diagram of the IC.

Vcc 25.5V 47m F

6 1m F L L 4 RIPPLE FILTER 4k 30k

9 Vcc OUTPUT-2 AMP-2 8 2.2W RL (L) 470mF

350W 3 47m F F 1m R R 2 4k 30k MUTING PRE GND 350W (R) AMP-3 OUTPUT-3 5 12 POW 10 GND

0.12mF

0.12mF RL (R) 2.2W 470m F (mute) (mute Tc)

1m F W W 1

30k 4k OUTPUT-3 350W AMP-1

7

11 (S) or (W)

1000m F 2.2W 0.12m F

RL (W)

20kW

Fig. 4-2

43

SECTION V A/V SWITCHING CIRCUIT

44

1. OUTLINE
A/V switching circuit performs change-over of video and audio signals from tuner and external input. The selecting operation is controlled by microcomputer through IIC bus.

2. IN / OUT TERMINALS

INNER INPUT EXTERNAL INPUT

OUTPUT

U/V Tuner (Main) U/V Tuner (Sub) .................................. For sub picture (PIP) VIDEO1 With S-terminal VIDEO2 VIDEO3 (Front) With S-terminal ........ Excepting CF35E50, CL37E56, CE35E15 VIDEO3 (Back) .................................. Only for CF35E50, CL37E56, CE35E15 VIDEO OUTPUT (V, L, R) .................... Excepting CN27E90 AUDIO ON SUB-PICTURE ................... Only for CN32E90, CN35E90, CN35E95

3. CIRCUIT OPERATION
This circuit consists of A/V SW IC; TA1218N (QV01), and selects signals from U/V tuner (Main), U/V tuner (Sub), E1, E2 and E3. 3-1 COMPOSITE VIDEO SIGNAL The selected video signal is output to pin 38 of QV01, and separated by comb filter into Y and C. The resulted signal is input to pins 30 and 32 of QV01, and is output to pins 36 and 34 to be supplied to Q501 (V/C/D). Video signal for sub picture is output to pin 42 of QV01, and is supplied to PIP unit (ZY01). 3-2 S-VIDEO SIGNAL When a cable is connected to S-VIDEO terminal, inner switch of S-VIDEO terminal is shorted to ground to turn off the transistor (QV05 for VIDEO1 input) for S-VIDEO terminal detection. Then chroma input terminal (Pin 14 for VIDEO1 input) of QV01 turns open. From pins 36 and 34 (Y/C output) of QV01, Y/C signal of selected source is output.

45

AV SW CIRCUIT

TUNR/IMA L/R V out

TIF V Aout

EQ QV01 TA1218N

DSP L/R in

18 17 VIDEO 3 16 15 14 13 VIDEO 1 12 11 10 9 VIDEO 2 8 7 6 5

C in R in S in L in C in R in S in L in V in R in L in V in R in L in C out R out Y out L out H out 34 35 36 37 38 C in Q501 Y in PIP TV in PIP L in Y in PIP R in C in 28 29 30 31 32 COMB FILTER Y out V in C out SYNC OUT 26 QA01 SYNC in

PIP AUDIO OUT

2 1

PIP R out PIP L out PIP V out 42

PIP V in

MONITOR OUT

Fig. 5-1

46

SECTION VI VIDEO PROCESSING CIRCUIT

47

1. OUTLINE
This circuit converts and amplifies video signal (Luminance and chroma signals) separated into Y/C, to original color signal, and is supplied to CRT Drive circuit.

2. SIGNAL FLOW
Signal flow chart is shown in fig. 6-2 Block diagram. (1) Luminance signal is input to pin 15 of Q501, and enters into delayline inside Q501 to be output to pin 4. (2) Chroma signal is input to pin 13, and I/Q signal which is demodulated in color, is output to pins 5 and 6, and next supplied to pins 51 and 52. (3) The signal is processed on luminance and chroma

signals, and is converted to original color signal (R,G,B) by RGB matrix. Next the signal is superimposed with OSD signal to be output to pins 41, 42 and 43, and is supplied to CRT Drive circuit. (4) The signal for Scan Modulation is processed with differential in Q501 to be output to pin 48 Besides, at terminal for adjustment TP501, luminance and chroma signals are automatically output according to the selected items of service mode.

3. CIRCUIT OPERATION
All processing operation of video signal are done inside Q501. The outline of Q501 (TA1222N) is explained in the next section. Here, major terminals excepting input/output terminals of Q501 are described.

48

Terminals concerning Video / Chroma circuit of Q501 are explained here. #1 #2 #3 #4 #5 #6 #7 #8 #9 # 10 # 11 # 12 # 13 # 14 # 15 # 32 # 33 # 34 # 35 # 36 # 37 # 38 # 39 # 40 # 41 # 42 # 43 # 44 # 45 # 46 # 47 # 48 # 49 # 50 # 51 # 52 # 53 # 54 # 55 # 56 CW OUTPUT SCP OUTPUT SECAM CONTROL Y1 OUTPUT Q OUTPUT I OUTPUT 1H DL CONTROL XTAL 3 XTAL 2 XTAL 1 APC FILTER Vcc 1 C INPUT GND Y1 INPUT PIP Ys PIP B PIP G PIP R OSD Ys OSD B OSD G OSD R Vcc 2 B OUTPUT G OUTPUT R OUTPUT GND ABL Vcc 3 Ym microcomputer VSM APL DET BLACK DET I INPUT Q INPUT Y2 INPUT COL DAC 1 DAC 2 3.58MHz which is synchronized to burst signal is output, and is used for clock of comb filter. The signal which is superimposed with burst gate pulse and blanking pulse is output. It is not used in this time. When receiving SECAM (Color system of East Europe) signal, it produces DC output. It is not used in this time. Luminance signal of Y1 input (# 15) is output through delay line. Chroma signal of #13 is demodulated in IQ, and Q signal is output. I signal of those of IQ demodulated is output. Color demodulation control signal of PAL, SECAM system (European color system) is output. It is not used in this time. Crystal oscillator terminal. Not used. Ditto 3.58MHz crystal oscillation terminal. Color sync. phase detecting terminal. 5V source (chroma line) terminal Color signal input terminal Grounding terminal of chroma circuit Luminance signal input terminal Input terminal for switching pulse signal of PIP signal Input terminal of PIP RGB signal Ditto Ditto Input terminal for switching pulse signal of OSD signal Input terminal for OSD RGB signal Ditto Ditto +9V source terminal RGB output terminal Ditto Ditto Ground terminal of Y, color difference, RGB circuits Input terminal for ABL control +9V source terminal Input terminal for half tone control pulse which is supplied from Output terminal of velocity modulation signal Detects average level of video signal for correcting DC transmission Detects black area in video signal for black expanding circuit Input signal for I signal of IQ demodulation signal Input signal for Q signal of IQ demodulation signal Input terminal for Y-picture control circuit Terminal for peak hold of color limiter Test point (TP501) output terminal External circuit control terminal (Not used)

49

0.6V(P)

TO COMB 300mV(P) 1V(P) 1V(P) +B <SDA> <SCL> <5V

CW OUTPUT COLOR IDENT. OUTPUT SCP OUTPUT SECAM CONTROL Y1 OUTPUT Q OUTPUT I OUTPUT 1H DL CONTROL XTAL 3 XTAL 2

DAC 2 (2bit) DAC 1 (1bit) MONITOR OUTPUT COLOR LIMITER Y2 INPUT Q INPUT I INPUT

56

1 2 3

55 54

1V(P-P) 4.43 or N M 3.58 pull or R 7.5V
7.5V(AFC) 1.0V(DIR)

53

Fig. 6-1 TA1222N VCD IC PIN LAYOUT CHART 50

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

1V(P) 300mV (P)

52 51 50 49 48

BLACK PEAK HOLD APL DET. VSM OUTPUT Ym INPUT POWER OFF INPUT Vcc 3 ABL INPUT Y, COLOR DIFFERENCE, RGB GND R OUTPUT G OUTPUT B OUTPUT Vcc 2 (+9V) R ANALOG OSD INPUT G ANALOG OSD INPUT B ANALOG OSD INPUT Ys ANALOG OSD INPUT R INPUT G INPUT B INPUT Ys INPUT VP OUTPUT HD OUTPUT EXTERNAL BPP INPUT DAC GND

XTAL 1 APC FILTER Vcc 1 (+5V) CHROMA INPUT CHROMA GND Y1 INPUT V. SEP. SYNC INPUT SYNC OUTPUT DEF GND AFC 1 32 x FH DEF Vcc (+9V) H. OUT BENDING CORRECT AFC PULSE INPUT BLK INPUT DIGITAL GND SDA SCL

47 46 45 44 43 2.5V(P)(typ) 2.8V(P)(typ) 42 41 40 39 from OSD mCom 0.5V(P)(typ) 38 37 36 35 34 33 32 31 30 1yb 29 8H from PIP/TEXT 0.5V (P)(typ)

V(P) denotes value of peak to peak.

5 53 Y I/Q VM 51 Q I Y

6 4 52 48

VELOCITY MODULATION

C COLOR DEMOD.
COLOR SIGNAL PROCESSING

From A/V Board C RGB MATRIX RGB SW Y DELAY LINE
LUMINANCE SIGNAL PROCESSING

13

43 42 41 CRT DRIVE

Y

15

Fig. 6-2 Block diagram of Video Processing circuit
SYNC/DEF PROCESSING OSD R 23 31 55 39 G 38 B 37 Ys 36 Ym 47 TP501 H.OUT VP Microcomputer OSD or EDS or C.C

51

Sync

17

Q501 V/C/D

SECTION VII V/C/D/IC

52

1. OUTLINE
This IC enables more precise picture setting than that of former IC (TA8845N) by means of large scale employment of IIC bus, and reduces many peripheral components by containing filters inside. The main features (comparing TA8845) are as follows.

2. LARGE SCALE EMPLOYMENT OF BUS CONTROL OF PARAMETER FOR PICTURE CONTROLS
(Soft method of picture making) * Black expanding start point * DC transmission correction quantity point * Black level correction quantity * Each ABCL characteristic (Former/TA8845N) External constant External constant External constant External constant TA1222N BUS control BUS control BUS control BUS control

3. EMPLOYMENT OF CONTAINING EACH VIDEO BAND FILTER INSIDE
(Employment of automatic adjustment circuit by Fsc to absorb deviation / Employment of deviation aborbing method by high S/N filter and mask triming using fixed CR) (Former/TA8845N) TA1222N * Y-DL Apa-con DL inside Inside * Chroma TOF/BPF External Inside *Velocity modulation processing circuit External Inside * Fsc trap for chroma demodulation output External Inside

4. EMPLOYMENT OF CONTAINING EACH FILTER (FOR S/H) INSIDE
(Circuit operation by extremely low current / Employment of leak current cancel circuit / Employment of detection circuit which does not suffer from influence of stray capacity) (Former/TA8845N) TA1222N * Chroma ACC / killer filter External Inside * Y / color difference clamp filter External Inside * Filter for filter automatic adjustment External Inside * AFC 2 filter External Inside

5. LOW COST OF IC
* Involving peripheral components inside ——> Down sizing of chip ——> Newly employment (NPN Tr area ratio to former : -25%) of miniature process (PLAS-1 S process) * Involving peripheral components inside——>Increasing of power consumption——>2 power supply system (5V / 9V used) * Involving peripheral components inside ——> Reducing of number of elements ——> Employment of new circuit (1) Reducing of gate (change of preset method) of register for IIC decoder (2) Reducing of DAC elements (employment of rudder type DAC + temperature compensation circuit) (3) Deletion of chroma CW, ACC (employment of 90 degree shift phase circuit with automatic adjustment)

53

BENDING CORRECTION

VCD BLOCK DIAGRAM (TA1222N)
BLK/AFC IN 3'5" VCD SYNC IN AFC1

Daf vCC

17

20

21

25

24 PHASE DET <APC-2>

19

22

GND (DEF) VCC (DEF) H. V. SYNC SEP PHASE DET <APC-1> 32 FM VCO H. BLK H. PHASE SHIFT H. DRIVE H. DUTY SW

V. Sep 16

V. SEP

H. H. COUNT DOWN PARABOLA

Y. Y.P OUT COUNT DOWN SYNC OUT D/A CONVERTER I2C BUS DECODER

H. out 23

31 VER OUT

V. SYNC SEP

18 SYNC OUT 27 SDA

Y IN 15

SYNC CHIP CLAMP

DELAY LINE

FDC TRAP

SW

REGISTER

26 GND 19 SCL

BPF CHROMA IN 13 GND GND 34 VCC 9V 12 (88) ACC DET SUB COLOR P/N IDENT BET CW MATRIX FILTER AUTO ADJ CHROMA BLK CHROMA DEMOD. LPH FSC TRAP B.C RESTORE SHARPNESS DELAY LINE SHARPNESS CONTROL ACC AMP TOF SW SW

DELAY LINE

DELAY LINE

S W TOK

4

Y1 OUT

29 GND GAMMA BLACK CORRECTION LEVEL COR. BLACK STRETON Y. CLAMP 53 Y2 OUT

A.P.L DET

BLACK PEAK DET

WHITE PEAK DET

30 BLACK PEAK HOLD 39 APL DET

APC FILTER 11

APC DET

X tal-1 (3.58MHz)

10

CHROMA VCO

S R T

HPF

TM AMP

VM MUTE

28 VM OUT

T. NR AMP

SUB CONT

UNI COLOR
VCC (98)

26 5 6 Q OUT Y OUT

X tal-2 (PAL) 9 X tal-3 (PAL) 8 I IN 51 IQ/UV CLAMP

WPS

HALF TONE

CLAMP

33 B IN FRESH COLOR IQ UV CONVERT SW RGB BRIGHT CLAMP CONTRAST 34 G IN 35 R IN UNI COLOR COLOR TINF DELAY TIME HALF TONE COLOR GAMMA RGB MATRIX PEAK ACL DET YS SW 36 OSD Ys IN 37 OSD B IN AXIS G-Y MATRIX COLOR PEAK DET HI BRIGHT COLOR CLAMP CLAMP OSD AMP 38 OSD G IN 39 OSD R IN

Q IN 52

COLOR LIMITER 54 DAC 2 55 DAC 2 56

CDE

YS SW

22 Ys IN

SW

ABCL AMP

25 ABL IN

SECAM CONTROL 3 (FOR SECAM)

SECAM CONTROL

COLOR SYS IDENT 1H DL CONTROL

DAC 1/2

DRIVE

CLAMP

BLK

CW OUT

S.C.P OUT

HD OUT EXT EFP IN

POWER OFF IN YM SW VCC (98) GND 47 YM IN 46 44

CUT OFF

RGB OUT

HD OUT/BLACK EXPAND MATRIX

1 CW OUT/ COLOR IDENT.

7 1H DL CONTROL (FOR PAL)

2 SCP OUT (SAND CASTLE)

30

41 42 43 B OUT G OUT R OUT

54

SECTION VIII PIP MODULE

55

PMUS 02H (SN:23148232)

B-Y OFFSET R-Y OFFSET TINT

RY54 RY55

RY50

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

PIN 1 2 3 4 5 6 7 8

I/O 0 I O O O I I YS NC GND
4.8V

NAME
4V 0V

PIN 9 10 11 12

I/O I I I I I/O I/O 5V GND VD HD
3.0V

NAME

350µS 0V 4.2V
1µS 10µS 4.2V 6V Or -0.9V 0V C CHASSIS

R OUT 4.1V
4.8V

G OUT 4.1V
4.8V

13 14 15
4.8V

SCL SCL NC
B CHASSIS

B OUT GND

4.1V

PIP VIDEO

2.8V

56

PMUS02H <BLOCK DIAGRAM OF PIP MODULE> RY55 RY54

PIP VIDEO 8 36 VIDEO IN B-Y 14 OUT R-Y 13 OUT Y-OUT 12 HD 10 VD 11 QY01 PC m 1832GT (PIP V/C/D) SLICE
WAVE FORM MODULATION

R OUT 51 BI 49 RI 47 YI BO 67 RO 65 YO 64 19 B-Y IN 18 R-Y IN 16 YIN R OUT23 G OUT24 B OUT25 4 G OUT 5 B OUT 6

78 HDCN HDPN18 76 VDCN VDPN16 QY03 TC9083F (PIP PROCESSOR) QY01 PC1832GT m (PIP V/C/D)

57
VD 11 HD 12

SECTION IX SYNC SEPARATION, H-AFC, H-OSCILLATOR CIRCUITS

58

1. SYNC SEPARATION CIRCUIT
The sync separation circuit separates a sync signal from a video signal and feeds it to an H and V deflection circuits. The separation circuit consists of an amplitude separation (H and V sync separation circuit) and a frequency separation circuit (V sync separation circuit) which performs the separation by using a frequency difference between H and V. In the N5SS chassis, all these sync separation circuits are contained in a V/C/D IC (TA1222N). Fig. 9-1 shows a block diagram of the sync separation circuit.

Sync input Composite video signal 17

H sync siganl Q501 H. V SYNC SEPARATION CIRCUIT V SYNC SEPARATION CIRCUIT WAVEFORM SHAPEING CIRCUIT V sync signal (Reset pulse)

Fig. 9-1 Sync separation circuit block diagram

1-1. Theory of Operation 1-1-1. Auto slicer type synchronous separation circuit When a synchronizing signal is separated, synchronous separation is made from the beginning with constant voltage in the conventional synchronous separation circuit. The auto slider type circuit employed in this time makes synchronous separation at a constant rate against the synchronizing signal amplitude. (See Fig. 9-2) In this method, even if an abnormal signal with small amplitude is applied, stable synchronizing performance can be obtained without separating pedestal.

Pedestal Level D B B

A a: Corect Sync. Signal

Sync Separation Level A:B=C:D b: Small Amplitude Sync. Signal

Fig. 9-2 Synchronous separation by auto slider system 59

1-1-2. V Sync Separation Circuit To separate a V sync signal from the composite sync signal consisting of V and H sync signals mixed, two stages of integration circuits are provided inside the IC. The circuit consists of a differential circuit and a Miller integration circuit, and has following functions. (1) Removes H sync signal component. (2) Maintain stable V sync performance for a tape recorded with a copy guard. (3) Stabilized V sync performance under special field conditions (poor field, ghost, sync depressed, adjacent channel best). The V sync signal separated in this stage is processed in a waveform shape circuit and then used as a reset pulse in the V division circuit as stated later.

2. H AFC (Automatic Frequency Control) CIRCUIT
A sync system which performs synchronization with each waveform of the sync signal as performed in a sync system in the V circuit is called a direct type sync system. However, if the synchronization for the H oscillator is carried out with this method, the H oscillator synchronizes with external noises and the H synchronization will be disturbed. To prevent this, an output of the H oscillator is compared with a reference H sync signal to detect deviations of frequency and phase. The H oscillator is automatically controlled with the detected output averaged. This circuit is called an AFC circuit. In the N4SS chassis, a conventional AFC circuit is not employed but a new double AFC circuit built-in the TA1222N is used. Fig. 9-3 shows the AFC circuit and the block diagram of the circuit.

First, phases of a 32 fH counted-down signal and a H sync signal contained in broadcasting signal are compared in the AFCI loop and the loop develops an H pulse signal for the AFCII loop. That is, when a phase deference 01 exists in comparison of the phase of fH signal developed by counting down the 32 fH signal and the phase of H sync signal of the broadcasting signal, an error signal corresponding to the phase different is detected and a correction voltage ???1 corresponding to the error output is generated. With this correction voltage, the 32 fH oscillator circuit is controlled. The correction (control) voltage for the oscillator varies in direction of positive or negative corresponding to phase lead or lag of the fH pulse (developed by counting down) from the H sync signal. As the H oscillator (32 x fH), a voltage controlled oscillator (VCO), oscillation frequency and phase of which can be controlled with the control voltage is used. Next, an H pulse signal is created from the fH signal counted down, and the pulse is used instead of the H sync signal in the AFCII circuit. The AFCII circuit differs in the loop of the count down circuit and H output circuit. The AFCII circuit compares phase of a H BLK pulse created by waveform shaping a AFC pulse from the FBT and a phase of the H pulse, and detects an error component corresponding to the phase difference 02 (if exist) and develops a correction voltage V2 corresponding to the error, thereby controlling the phase of Q501 H out. The H output control voltage varies in a positive or negative direction corresponding to the phase lead or lag of the H BLK pulse from that of the H pulse. The phase of H out is varied with the control voltage to make synchronization with the H pulse phase. The purpose of the double AFC circuit employed this time is to improve horizontal jitter under signal reception in a poor electrical field. The jitter in the poor field strength and

SYNC SEPARATION CIRCUIT

PHASE DETECTION CIRCUIT

32 x fH VCO

AFC II LOOP H DRIVE H OUTPUT CIRCUIT

H COUNT DOWN (DIVIDING) AFC I LOOP

PHASE DETECTION CIRCUIT

FBT PULSE (AFC PULSE)

Fig. 9-3 H AFC circuit block diagram 60

distortion due to phase difference are incompatible. That is,to improve the jitter under poor field strength, response speed must be slowed by lowering the AFC sensitivity. On the other hand, to improve distortion due to the phase difference, the response must be increased by increasing the AFC sensitivity. In a conventional AFC circuit, setting of the sensitivity is carried out at one part only, so an compromise point for both characteristics must be found. However, with the double AFC circuit employed this time, for the jitter the AFCI loop works best with decreasing the sensitivity and for the phase distortion the AFCII loop works with increasing the sensitivity.

H Vcc

SYNC IN

2VP-P 17 20 H AFC I CIRCUIT 21 32 x fH VCO

3. H OSCILLATOR CIRCUIT
3-1. Outline A 503 kHz (32 x fH) voltage controlled type oscillator with a ceramic oscillation element is used to generate a clock pulse and the clock is counted down, thereby obviating the need of adjustments for both the H and V deflection process circuit. 3-2. Theory of Operation (1) The H sync signal used as a reference signal enters from the sync separation circuit to the AFCI circuit. At the same time, the fH pulse created by counting down the 32 x fH pulse generated in the ceramic oscillator enters the H AFCI circuit. Phase difference between these two signals enters an integration circuit (low pas filter) connected to pin 4 and converted into a DC voltage (AFC voltage).

SYNC SEPARATION CIRCUIT

H COUNT DOWN

H AFC II CIRCUIT TA1222N

Fig. 9-4

61

(2) The AFC voltage controls frequency (32 x fH) of the oscillator (VCO). Fig. 9-5 shows the control characteristics of the VCO. (3) The H output is obtained by dividing the 32 x fH (503 kHz) of the oscillator with flip-flops. Fig. 9-6 shows the block diagram of this count down circuit. (4) The V output is created by dividing the 32 x fH oscillator output into 1/8, and then by counting the 4 x fH pulse with a vertical counter which is reset with a V reset pulse (V sync output signal stated under sync separation). (5) That is, the V output is not created by simply counting down the H by performing V synchronization with a V reset pulse entering within a window provided for V synchronization --- called direct type sync system, thus, the circuit can work for non standard signals.

High

Low

Low AFC voltage (V)

High

Fig. 9-5

32 x fH VCO

32fH

X 1/8

4fH

fH X 1/4 H OUTPUT

V sync signal

V WAVEFORM SHAPE CIRCUIT

Reset pulse

V COUNTER

V OUTPUT

Fig. 9-6 Block diagram of H, V count down circuits

62

SECTION X VERTICAL OUTPUT CIRCUIT

63

1. OUTLINE
As can be seen from the block diagram, the sync circuit and the V trigger circuit are contained in Q501 (TA1222N), and the sawtooth generation circuit and amplifier (V drive circuit) contained in Q302 (TA8859AP). The output circuit and pump-up circuit circuits are included in Q301 (TA8427K).
D309 C322 +9V R309 C308

R329

15

3

+27V 7 Q301 2 1 5 R301 6 3

D301 R303 L301

C313

Q501 31 C321 R320

14

Q302

6

4

R336 C307

R307 R306 Q311 R313 C306

L462

13

8 C314 R330 Q312

R344 C319 C305 R304 +27V R305

Fig. 10-1 Block diagram of V deflection circuit 1-1. Theory of Operation The purpose of the V output circuit is to provide a sawtooth wave signal with good linearity in V period to the deflection yoke. When a switch S is opened, an electric charge charged up to a reference voltage VP discharges in an constant current rate, and a reference sawtooth voltage generates at point a. This voltage is applied to (+) input (non-inverted input) of an differential amplifier, A. As the amplification factor of A is sufficiently high, a deflection current flows so that the voltage V2 at point C becomes equal to the voltage at point a.

Vp

S: Switch

Differential amplifier L C2 c V2 R3

a R1 C2 R2

V1

Fig. 10-2 64

2. V OUTPUT CIRCUIT
2-1. Actual Circuit
D309 C322 +9V R309 C308

R329

15

3

+27V 7 Q301 2 1 5 R301 6 3

D301 R303 L301

C313

Q501 31 C321 R320

14

Q302

6

4

R336 C307

R307 R306 Q311 R313 C306

L462

13

8 C314 R330 Q312

R344 C319 C305 R304 +27V R305

Fig. 10- 3 2-2. Sawtooth Waveform Generation 2-2-1. Circuit Operation The sawtooth waveform generation circuit consists of as shown in Fig. 10-4. When a trigger pulse enters pin 13, it is differentiated in the waveform shape circuit and only the falling part is detected by the trigger detection circuit, to the waveform generation circuit is not susceptible to variations of input pulse width. The pulse generation circuit also works to fix the V ramp voltage at a reference voltage when the trigger pulse enters, so it can prevent the sawtooth wave start voltage from variations by horizontal components, thus improving interlacing characteristics.

5Vp DC=0V

13

WAVEFORM SHAPE

TRIGGER DET.

PULSE GAIN

V. LAMP

AGC

14 R329 C321

15 C322

16 C323

Fig. 10-4

65

2-3. V Output
2-3-1. Circuit Operation The V output circuit consists of a V driver circuit Q302, Pump-up circuit and output circuit Q301, and external circuit components. (1) Q2 amplifies its input fed from pin 4 of Q301, Q3, Q4 output stage connected in a SEPP amplifies the current and supplies a sawtooth waveform current to a deflection
+27V D301 D308 Q301 6 3 D309 Q3 7 R309
V7

yoke. Q3 turns on for first half of the scanning period and allows a positive current to flow into the deflection yoke (Q3 1DY C306 R305 GND), and Q4 turns on for last half of the scanning period and allows a negative current to flow into the deflection yoke (R305 C306 DY Q4). These operations are shown in Fig. 10-5.
C308
V3

50V 27V GND 27V GND

BIAS CIRCUIT Q2 4 Q4

V2

2 DY C306 R305 Q3 ON

50V

GND

GND 1 Q4 ON

Fig. 10-5 V output circuit (2) In Fig. 10-6 (a), the power Vcc is expressed as a fixed level, and the positive and negative current flowing into the deflection yoke is a current (d) = current (b) + (c) in Fig. 10-6, and the emitter voltage of Q3 and Q4 is expressed as (e). (3) Q3 collector loss is i1 x Vce1 and the value is equal to multiplication of Fig. 10-6 (b) and slanted section of Fig. 10-6 (e), and Q4 collector loss is equal to multiplication of Fig. 10-6 (c) and dotted section of Fig. 10-6 (e). Power Vcc
GND (b) Q3 Collector current i1 Q3 GND (c) Q4 Collector current i2 i1 Vce 1

Q4 GND (d) Deflection yoke current i1+i2 Q2 i2 Vp Vcc 1/2 Vcc GND (a) Basic circuit (e)

Fig. 10-6 Output stage operation waveform 66

(4) To decrease the collector loss of Q3, the power supply voltage is decreased during scanning period as shown in Fig. 10-7, and VCE1 decreases and the collector loss of Q3 also decreases.
Q3 Collector loss decreases by amount of this area Power supply for flyback period (Vp) Power supply for scanning period (Vcc)

Scanning period

Flyback period

Fig. 10-7 Output stage power supply voltage

(6) Since pin 7 of a transistor switch inside Q301 is connected to the ground for the scanning period, the power supply (pin 3) of the output stage shows a voltage of (VCCVF), and C308 is charged up to a voltage of (VCC-VF-VR) for this period. (7) First half of flyback period Current flows into L462 D1 C308 D308 VCC (+27V) GND R305 C306 L462 in this order, and the voltage across these is: VP=VCC+VF+(VCC-VF-VR)+VF about 50V is applied to pin 3. In this case, D301 is cut off. (8) Last half of flyback period Current flows into VCC switch D309 C308 Q301 (pin 3) Q3 L462 C306 R305 in this order, and a voltage of VP=VCC-VCE (sat)-VF+(VCC-VF-VR)-VCE (sat), about 40V is applied to pin 3. (9) In this way, a power supply voltage of about 27V is applied to the output stage for the scanning period and about 50V for flyback period.

(5) In this way, the circuit which switches power supply circuit during scanning period and flyback period is called a pump-up circuit. The purpose of the pump-up circuit is to return the deflection yoke current rapidly for a short period (within the flyback period) by applying a high voltage for the flyback period. The basic operation is shown in Fig. 10-8.

D301

C308

D301

C308

D308 Q301 6 3 D309 Switch Q3 D1 7 Q3 D1 R309 Switch 7 Q301 6 3 D309 R309 VR

First half

L462 2 Q4 C306 R305 Q4 2

L462 C306 R305

Last half (a) Scanning period (b) Flyback period

Fig. 10-8 67

2-4. V Linearity Characteristic Correction
2-4-1. S-character Correction (Up-and Down-ward Extension Correction) A parabola component developed across C306 is integrated by R306 and C305, and the voltage is applied to pin 6 of Q302 to perform S-character correction. 2-4-2. Up-and Down-ward Linearity Balance A voltage developed at pin 2 of Q301 is divided with resistors R307 and R303, and the voltage is applied to pin 6 of Q301 to improve the linearity balance characteristic. Moreover, the S-character correction, up- and down-ward balance correction, and M-character correction are also performed through the bus control.

68

SECTION XI HORIZONTAL DEFLECTION CIRCUIT

69

1. OUTLINE
The H deflection circuit works to deflect a beam from left to right by flowing a sawtooth waveform of 15.734 kHz into the DY H deflection coil.

2. HORIZONTAL DRIVE CIRCUIT
The H drive circuit works to start the H output circuit by applying HVCC (Q501 DEF power source) to pin 22 of Q501 (TA1222N) and a bias to the H drive transistor Q402 at the main power on. 2-1. Theory of Operation (1) When the power switch is on, the main power supply of 125V starts to rise. At the same time, AF power supply 25V also rises. (2) With 25V line risen, Q430 base voltage which is created by dividing the audio power with R433 and D430 also rises. Then, the transistor Q430 turns on and the HVCC is applied from the audio power line through R432 and D431 to pin 22 of Q501.

R432

Q430

D431 Q501

R433

D430

BB81 81 BB80 81 22 H Vcc

L400

SIGNAL

C431

C430

D490

Fig. 11-1 H drive circuit block diagram

70

3. BASIC OPERATION OF HORIZONTAL DRIVE
A sufficient current must flow into base of the horizontal output transistor to rapidly make it into a saturated (ON) condition or a cut off (OFF) condition. For this purpose, a drive amplifier is provided between the oscillator circuit and the output circuit to amplify and to waveshape the pulse voltage. 3-1. Theory of Operation (1) The horizontal drive circuit works as a so called switching circuit which applies a pulse voltage to the output transistor base and makes the transistor on when the voltage swings in forward direction and off in reverse direction. (2) To turn on the output transistor completely and to make the internal impedance low, a sufficiently high, forward drive voltage must be applied to the base and heavy base current ib must be flown. On the contrary, to completely turn off the transistor, a sufficiently high, reverse voltage must be applied to the base. (3) When the transistor is on (collector current is maximum) condition with the sufficiently high forward voltage applied to the base, the transistor can not be turned off immediately, if a reverse base bias is applied to the base because minority carriers storaged in the base can not be reduced to zero instantly. That is, a reverse current flows through an external circuit and gradually reduces to zero. The time lag required for the base current to disappear is called a storage time and falling time. (4) To shorten the storage time and the falling time, a sufficiently high reverse bias voltage must be applied to allow a heavy reverse current to flow. This operation also stabilizes operation of the horizontal output transistor.

On period

OFF period

+ 0 t Input waveform (b)

+ ib 0 V (a) Storage time Reverse current Falling time

Forward current t Base current (c)

Fig. 11-2

71

3-2. Drive System 3-2-1. ON drive system When the drive transistor is on, the horizontal output transistor also turns on. Merit: • The base current can be precisely controlled without being affected by variation of pulse width which is caused by the horizontal oscillator circuit and the drive circuit. Demerit: • It is difficult to flow a reverse bias current to the horizontal output transistor to eliminate its storage carrier for transient period of on to off period for the horizontal output transistor.

3-2-2. OFF drive system When the drive transistor is on, the horizontal output transistor is off. Merit: • Energy balance between on and off periods of the drive circuit is better, and the circuit can be simplified. • Reverse base current of the horizontal output transistor can be controlled easily. Demerit: • Base-emitter forward current flowing into the horizontal output transistor is susceptible to on-period variation of the drive transistor.

H output H driver H OSC H OSC H driver

H output

ON (OFF)

+B

ON (OFF)

ON (OFF)

+B

ON (OFF)

Fig. 11-3

Fig. 11-4

72

3-3. Circuit Description
In the N5SS chassis, the off drive system is employed. (1) When Q1 inside Q501 is turned on, Q402 base is forward biased through 9 V pin 22 of Q501 (H. VCC) pin 23 of Q501 (H. Out) R411/R410 resistor divider, and then, Q402 collector current flows through 125V R416 T401. In this case, the H output transistor Q404 turns on with the base-emitter reverse biased because of the off drive system employed. (2) On the contrary, when Q1 inside IC501 is off (pin 8 is 0V), base-emitter bias of Q402 becomes 0V and Q402 turns off, and a collector pulse as shown in Fig. 11-5 develops at the collector. The voltage is stepped down and Q404 is forward biased with this voltage, thus turning on Q404. (3) In this way, by stepping down the voltage developed at primary winding of the drive transformer and by applying it to Q404, a sufficient base current flows into Q404 base, thereby switching the Q404.

Q501 H. Vcc T401 H drive transistor D490 C431 Q1 23 R410 Q402 H drive transistor 2 C43 4 R411 C417 R415 Q404 H output transistor 1 3

22

+

V1 R416 V2 0V

C416 9V +125V

VCP 0V Q402 OFF Q402 ON

Fig. 11-5

73

4. HORIZONTAL OUTPUT CIRCUIT
The horizontal output circuit applies a 15.734 kHz sawtooth wave current to the deflection coil with mutual action of the horizontal output transistor and the damper diode, and deflects the electron beam from left to right in horizontal direction.

10

HV

5 2 T461 FBT S-charactor capacitor L462 Deflection yoke (H coil)

3 Q404 H output (With damper diode) IC501 R415 H. out TP-33 Q402 H drive BB31 Q1 23 33 R411 R410 C417 C463 C467 D461 C442 T401 H drive transformer C444 8 C440

1

R441

C423 L442 L441

C413 + C416 R416 Resonat capacitor C464 + To DPC output SIGNAL DEF/POWER PCB

L461

M-charactor correction

H linearity coil

125V Diode modulator circuit

Fig. 11-6

74

4-1. Theory of Operation 4-1-1. Operation of Basic Circuit (1) To perform the horizontal scanning, a 15.734 kHz sawtooth wave current must be flown into the horizontal deflection coil. Theoretically speaking, this operation can be made with the circuit shown in Fig. 11-7 a and b. (2) As the switching operation of the circuit can be replaced with switching operation of a transistor and a diode, the basic circuit of the horizontal output can be expressed by the circuit shown in Fig. 11-7 a. That is, the transistor can be turned on or off by applying a pulse across the base emitter. A forward switching current flows for onperiod, and a reverse switching current flows through the diode for off-period. This switching is automatically carried out. The diode used for this purpose is called a damper diode.

Description of the basic circuit 1. t1~t2: A positive pulse is applied to base of the output transistor from the drive circuit, and a forward base current is flowing. The output transistor is turned on in sufficient saturation area. As a result, the collector voltage is almost equal to the ground voltage and the deflection current increases from zero to a value in proportionally. (The current reaches maximum at t2, and a right half of picture is scanned up to this period.) 2. t2: The base drive voltage rapidly changes to negative at t2 and the base current becomes zero. The output transistor turns off, collector current reduces to zero, and the deflection current stops to increase. 3. t2~t3: The drive voltage turns off at t2, but the deflection current can not reduce to zero immediately because of inherent nature of the coil and continues to flow, gradually decreasing by charging the resonant capacitor C0. At the same time, the capacitor voltage or the collector voltage is gradually increases, and reaches maximum voltage when the deflection current reaches zero at t3. Under this condition, all electromagnetic energy in the deflection coil at t2 is transferred to the resonant capacitor in a form of electrostatic energy.

a

H output basic circuit H output transistor

D Damper diode

Co

L Deflection yoke

Resonant capacitor

Vcc b H output equivalent circuit

4. t3~t4: Since the charged energy in the resonant capacitor discharges through the deflection coil, the deflection current increases in reverse direction, and voltage at the capacitor gradually reduces. That is, the electrostatic energy in the resonant capacitor is converted into a electromagnetic energy in this process. 5. t4: When the discharge is completed, the voltage reduces to zero, and the deflection current reaches maximum value in reverse direction. The t2~t4 is the horizontal flyback period, and the electron beam is returned from right end to the left end on the screen by the deflection current stated above. The operation for this period is equivalent to a half cycle of the resonant phenomenon with L and C0, and the flyback period is determined by L and C0.

SW1

SW2

Co

L

Vcc

Fig. 11-7

75

6. t4~t6: For this period. C0 is charged with the deflection current having opposite polarity to that of the deflection current stated in "3.", and when the resonant capacitor voltage exceeds VCC, the damper diode D conducts. The deflection current decreases along to an exponential function (approximately linear) curve and reaches zero at t6. Here, operation returns to the state described under "1.", and the one period of the horizontal scanning completes. For this period a left half of the screen is scanned. In this way, in the horizontal deflection scanning, a current flowing through the damper diode scans the left half of the screen; the current developed by the horizontal output transistor scans the right half of the screen; and for the flyback period, both the damper diode and the output transistor are cut off and the oscillation current of the circuit is used. Using the oscillation current improves efficiency of the circuit. That is, about a half of deflection current (one fourth in terms of power) is sufficient for the horizontal output transistor.

t1 A TR base voltage 0

t2 t3 t4 t5

t6

B

TR base current TR collector current D damper current (SW2) Switch current (TR, SW1) Resonant capacitor current (Co)

0

C

0 0

D

E

0

F

0

G

Deflection current (Lo)

0

H

TR collector voltage

0

Fig. 11-8

76

4-1-2. Linearity Correction (LIN) (1) S-curve Correction (S Capacitor) Pictures are expanded at left and right ends of the screen even if a sawtooth current with good linearity flows in the deflection coil when deflection angle of a picture tube increases. This is because projected image sizes on the screen are different at screen center area and the circumference area as shown in Fig. 11-9. To suppress this expansion at the screen circumference, it is necessary to set the deflection angle @ to a large value (rapidly deflecting the electron beam) at the screen center area, and to set the deflection angle @ to a small value (scanning the electron beam slowly) at the circumference area as shown in Fig. 11-9. In the horizontal output circuit shown in Fig. 11-10, capacitor CS connected in series with the deflection coil LH is to block DC current. By properly selecting the value of CS and by generating a parabolic voltage developed by integrating the deflection coild current across the S capacitor, and by varying the deflection yoke voltage with the voltage, the scanning speed is decreased at beginning and end of the scanning, and increased at center area of the screen. The S curve correction is carried out in this way, thereby obtaining pictures with good linearity.

t2 q2

t1 q1 t2 = t1 q 2 < q1

t2 q2

t1 q1 t2 > t1 q2 = q 1

(a) S-character correction

(b)

Fig. 11-9
Cs

TR

D

Co LH Deflection coil Vcc

(a) H output circuit

(b) Sawtooth wave current

(c) Voltage across LH Fast deflection

Slow deflection (d) Synthesized current

Fig. 11-10

77

total are obtained. (2) Left-right Asymmetrical Correction (LIN coil) In the circuit shown in Fig. 11-11 a, the deflection coil current iH does not flow straight as shown by a dotted line in the figure b if the linearity coil does not exist, by flows as shown by the solid line because of effect of the diode for a first scanning (screen left side) and effect of resistance of the deflection coil for later half period of scanning (screen right side). That is, the deflection current becomes a sawtooth current with bad linearity, resulting in reproducing of asymmetrical pictures at left and right sides of the screen (left side expanded, right side compressed). When a horizontal linearity oil L1 with a current characteristic as shown in figure c is used, left side picture will be compressed and right side picture will be expanded because the inductance is high at the left side on the screen and low at the right side. The left-right asymmetrical correction is carried out in this way, and pictures with good linearity in 4-1-3. Horizontal Linearity, M-character Correction Circuit Since deflection angle increases with size of picture tube increases, a M character trend which compresses a picture image at beginning and end of the scanning will occur. A M character linearity correction circuit is provided in the N5SS as shown in Fig. 11-12. The M character linearity correction is carried out by connecting a series resonant circuit in parallel with the S capacitor and flowing a resonant current

(a) TR LH Deflection coil FBT

D

Co

LH TR D Co LI

iH

Li

Vcc

L Cs C

Cs S-character capacitor (b) Deflection coil current Deflection coil current (iH) Resistance of LH 0 (Left) Characteristic of D (Right)

(b) Sawtooth wave current

(c) Linearity coil characteristic Linearity coil characteristic Inductance (mH)

Fast Slow Fast

Slow Fast

(c) Synthesized current
(Left) (Right) Current (A)

Fig. 11-12 Fig. 11-11 Linearity coil

78

which has two times the H oscillator frequency.

5. HIGH VOLTAGE GENERATION CIRCUIT
The high voltage generation circuit develops an anode voltage for the picture tube, focus, screen, CRT heater, video output (210V) and so on by stepping up the pulse voltage developed for flyback period of the horizontal output circuit with the FBT, and supplies the power to various circuit.

AFC blanking Heater C303 Auxiliary winding

10 9 4

CRT anode

+27V C310 D302 R327 6 C460 -27.5V D406 +210V 3 C446 +125V C448 1 D404 T401 ABL Screen 2 D460 R469 5 Focus 7

Primary winding

C463

H deflection coil L462

L441 1000VP-P 0

R441 C442

1H (15.75KHz)

Fig. 11-13

79

5-1. Theory of Operation 5-1-1. +210V For the flyback period, pulses are stacked up to DC +125V with FBT, and the voltage is rectified by D406 and filtered by C446. 5-1-2. +27V Pin 4 of the FBT is grounded and the shaded area of negative pulse developed for opposite period of the flyback period is rectified, thus developing better regulation power supply. 5-1-3. -27V As a power for the DPC circuit, a negative pulse signal is rectified by D460 and filtered with C460, thus developing the -27V. 5-1-4. High voltage Singular rectification system which uses a harmonics nonresonant type FBT is employed and a better high voltage regulation is obtained, so amplitude variation of pictures becomes low.

+115V

0

Fig. 11-14

10 4 7 8 2 1

0

0 For +27V

0

Fig. 11-15

G

F E Picture tube anode Primary D C Picture tube capacitor EH D C

Pulse

G

E

F

Stacked pulse of 4 block

EO B Auxiliary A A

B

ABL

1H 15.735KHz

Fig. 11-16 80

5-2.

Operation Theory of the Harmonic Non-Resonant System and Tuned Waveforms

The high voltage coil is of film multi-layer winding type and the coils are isolated into seven blocks. Each block is connected through a diode. The basic operation is described in the case of 4 blocks construction for simplification. Positive or negative pulse determined by stray capacitance of each coil develops at F terminal points ( , , , , , G , G ) of each coil as shown in Fig. 11-16, and these pulses are stacked as shown, thus developing the high voltage. Moreover, a capacitance between the internal and external coatings of the picture tube works as a smoothing capacitor. Focus voltage is obtained at point EO. The FBT is turned to a harmonic of 15 times the fundamental

Flyback pulse

Reference wave 45 KHz

11m s 20m s

1 1 = = 45KHz 22m s 22x10

63.5m s

AC 0 AC 0

Harmonics 15 times 675 KHz

Becomes 45 KHz x 15 = 675KHz this is determined by coil inductance capacitance and stray of FBT.

Tuned waveform (In case of 3X) Hight voltage (In case of 15X) E E

Focus current

Picture tube current

In case of 15 times the harmonics as compared with 3 times the harmonics, average conduction peiod of the high voltage diode is wider. As a result, high voltage variations are suppressed. AC 0

Fig. 11-17 Tuned waveforms

81

frequency, and the turned waveform is shown in Fig. 11-17.

6. X-RAY PROTECTION CIRCUIT
1. Outline In case picture tube using high voltage, when high voltage rises abnormally due to components failure and circuit malfunction, there is possible danger that X-RAY leakage increases to affect human body. To prevent it, X-RAY protection circuit is equipped. 2. Operation Figure 10-18 shows the circuit diagram. Supposing high voltage rises abnormally due to some reason, pulse at pin 9 of T461 also rises, and detection voltage Eb rectified by D471 and C471 in X-RAY protection circuit rises. When Eb rises, emitter voltage of Tr10 divided by R25 and R26 in protector module becomes higher than [zener voltage (6.2V) of ZD6 + Tr10 VBE ]. This causes Tr10 turns on to supply base current to Tr9. Then Tr9 turns on. By this Tr6 and Tr6 turn on to make ON/OFF pulse at pin 7of QA01 in low level, QB30 and Q843 turns off, then relay SR81 turns off. Tr6 and Tr7 are in thyristor-connection, and 5V of power holds protection operation until main power switch is turned off. During circuit operation, power LED near main power switch blinks in red. Caution : To restart TV set, repair failure

5V 15 MICOM QA01#7 R10 Tr10 Tr7 RB30 R21 RELAY SR81 16 Q843 QB30 R11 Tr6 D3 Tr5 R12 C1 R20 R22 ZD6 C471 Tr9 R26 12V R9 R25 13 D471 R472 T461 9

ED

12 + C474

Figure 11-18 X-RAY protection circuit

82

first.

7. OVER CURRENT PROTECTION CIRCUIT 1. Outline
If main power (125V) current increases abnormally due to components failure, there is possible danger of the secondary damage like failure getting involved in other part failure, and abnormal heating. To prevent this, over current protection circuit is equipped, which detects current of main B line to turn off power relay in abnormal situation.

2. Operation
Fig. 11-19 shows over current protection circuit. When the current of main B line increases abnormally due to the shortage in load of main B line, voltage drop arises across R470. By this voltage drop, when base-emitter voltage of Tr 8 in protector module (Z801) becomes appprox. 0.7V or more, Tr 8 turns on, and the voltage by divided ratio of R15 and R16 is applied to cathode of ZD4. When this voltage becomes higher than zener voltage of ZD4, ZD4 turns on to supply base current to base of Tr 6 via R14. This causes Tr 5 ON and voltage at pin 16 of Z801 becomes Low. Therefore, QB30 and Q843 turns off to set SR81 OFF. Tr 6 and Tr 7 in Z801 are in thyristor- connection, and power 5V-1 supplied at pin 15 keeps protection operation for standby power until main power switch is turned off. During circuit operation, power LED near main power switch blinks in red. Caution :
R470 MAIN B R479 5V C472 15 MICON QA01#7 R830 RELAY SR81 16 Q843 Q830 Tr5 R11
Z801 PROTECTOR MODULE

F470 To T461 R472

2

1

R9 ZD4 R10 Tr7 R14 Tr6 R12 C1 R15

R16 Tr8

Z801 PROTECTION MODULE 17

Fig. 11-19 Over current protection circuit 83

To restart TV set, repair failure first.

the reverse operation will occur. 2. Circuit Description To correct the kink damping circuit is added between the main B power line and the S character capacitor as shown in Fig. 11-23. In Fig. 11-24, a capacitor C441 is charged with a DC current iB through Q442 connected to MAIN B during the flyback period. When the voltage across C441 and S character correction capacitor increases during the scan period, the diode D442 conducts and reduces the voltage across C442 to the original voltage level, thereby suppressing shift of the raster.

8. KINK CORRECTION CIRCUIT
1. Outline In the N5SS chassis, a kink correction circuit is employed to correct a kink generating when receiving a black and white pattern. In the black and white pattern cross hatch shown in Fig. 1120, when the picture changes from black to white during field scan period, a current Is flows rapidly in secondary of the FBT and a current IP flows in reverse direction during scan period (due to transformer coupling) in the primary winding. This current works to increase the voltage across S character correction capacitor CS. As a result, the deflection current decreases by I1 as shown in Fig. 11-21 and the raster moves toward left, thus causing the kink as shown in Fig. 11-22. On the contrary, when the picture changes from black to white,

Kink Correction Circuit Q404

T461

C444 C440 L642

D442

R442

C442
+ Cs FBT lp ls

C441

L461 D461 C467 SIDE DPC C464 C448

Fig. 11-20

Fig. 11-23
T461

L462 l1 D442 Vcs R442 C442 C441 Vcs C448 iB MAIN B

Fig. 11-21

Kink in the cross bar pattern

Fig. 11-24

Fig. 11-22 84

SECTION XII DEFLECTION DISTORTION CORRECTION CIRCUIT (Side DPC Circuit)

85

1. DEFLECTION DISTORTION CORRECTION IC (TA8859P)
1-1. Outline The deflection distortion correction IC (TA8859AP), in combination with a V/C/D IC (TA8859AP) which has a V pulse output, performs correction for various deflection distortions and V output through the I2C bus control. All the I2C bus controls are carried out by a microcomputer and can be controlled with the remote control. 1-2. Functions and Features The IC has functions of V RAMP voltage generation, V amplitude automatic switching (50/60 Hz), V linearity correction, V amplification, EHT correction, side pincushion correction, I2C bus interface, etc. and controls following items through the I2C bus lines. (1) V amplitude (2) V linearity (3) (4) (5) (6) (7) (8) (9) V S-character correction V picture position (neutral voltage setting) V M-character correction V EHT correction H amplitude L and R pin-cushion distortion correction I (entire area) L and R pin-cushion distortion correction II (corner portions at top and bottom) (10) H trapezoid distortion correction (11) H EHT correction (12) V AGC time constant switching 1-3. Block Diagram Fig. 12-1 shows a block diagram of the basic circuit.

+12V

14 V. Trigger-in 13 Waveform Shape Trigger Det Puise Gen.

15 V. Rame

16 AGC

5 V. AGC Time Constant SW

3

V. M-Character Correction (Bus Control Signal) SDA SCL

V. Linearity Correction

V. S-Character Correction

H. Trapezoid Distortion Correction L-R Pincushion Distortion Correction I L-R Pincushion Distortion Correction II (Top & Bottom Comer Section)

Control Through Bus

10 9 12 Logic V. Screen Position

V. Amplitude Adj.

V. EHT Correction

H.EHT Input

H.EHT Corrction H. Amplitude Adj. 2 EW-Drive 4 EW Feedback

8

6

1 EHT INPUT

V Drive V. Feedback

Fig. 12-1

86

2. SIDE DPC
2-1. Outline Since the deflection coil used in 29 and 34" type of N5SS chassis is not a DPC free type left and right pin-cushion distortion must be corrected with a circuit. If the distortion is not corrected, pin-cushion distortion as shown in Fig. 12-2 (a) will occur. To correct this distortion, a H deflection current must be modulated in a form of parabola for V sync period. The compensation circuit using a diode modulator system which has a large amount of compensation ability is used in N4SS chassis. The correction circuit in N5SS chassis is of a negative type and the diode modulator develops a negative voltage. Accordingly, a negative power supply is used in the amplifier and the output circuit. The circuit can be controlled through the I2C bus. That is, the parabola waveform and DC voltage obtained by controlling E/W output (pin 2) of Q302 (TA8859P) through the bus is shifted in their levels by zener diodes (D464, D465, D466) to use them as a negative power source. The voltage is added to the amplifier and the output circuit (Q462, Q460) and modulates the voltage at CD11 in the diode modulator circuit. Thus developed parabola voltage is a negative voltage and the sum with the main B voltage (VB) is applied across the S character capacitor. This voltage works as a power supply for the H deflection yoke and the H deflection current is modulated as shown in Fig. 12-2 (b), thus correcting the left and right pin-cushion distortion.

V. Sync H. Sync

(a) Left and right pin-cushion distortion Fig. 12-2

(b) H deflection current

9V Q501 V/C/DIC TA1222N Q302 E/W IC TA8859P PARABORA VOLTAGE GEN.

AMP output circuit R465 -B R341

Diode mdulator circuit H. out H. DY FBT

3

13

R343 D464 D466 Q462

S character capacitor L461

9 Bus control 10 (From microcomputer)

WAVEFORM PROCESS 4 2

D465 C464 Q460 +VB

Q461

Fig. 12-3 Diode modulator type side DPC circuit 87

3. DIODE MODULATOR CIRCUIT
Fig. 12-4 shows a basic circuit of the diode modulator used in the N5SS. A key point in the N5SS chassis shown in Fig. 12-4 is to develop a negative pulse at point B. In this circuit, a current loop of the resonant circuit for flyback period is shown by an arrow, and the energy stored in LDY is transferred to resonant capacitors Cr, Crm in passing through Cr, Crm, Cs when the scanning completes. As a result, a positive, horizontal pulse as shown in Fig. 125 (a) will appear at Cr, and the current flows into Crm with the direction as shown. Then a pulse as shown in Fig. 12-5 (b) develops at the point B. On the other hand, since constant amplitude pulses across Cr, as shown in Fig. 12-5, are applied to the primary winding, the high voltage of FBT also develops a constant voltage. When the negative pulse developed at the point B is integrated with Lm and Csm, its average value appears at Csm as a negative voltage. By modulating this voltage to have the parabolic curve with Q460, a waveform of Vm is obtained as shown in Fig. 12-6. As a result, the voltage Vs which is the sum of the power supply voltage VB and the Vm is applied across the S-curve capacitor Cs. The Vs becomes as a power source for the deflection yoke, and the waveform modulated in the parabolic form, as shown in Fig. 12-2 (b), is applied to the horizontal deflection yoke and corrects the left-right pin-cushion distortion.

A FBT LDY H OUT DD Cr Cs Vs B Lm DM Crm Csm Q460 Vm VB

a) Waveform at point A

b) Waveform at point B

Fig. 12-4

Fig. 12-5

VB

VS

0 Vm

Fig. 12-6

88

4. ACTUAL CIRCUIT
In the actual circuit, the resonant capacitor is split into two as shown in Fig. 12-7. One, C440, is inserted between the collector of the H. OUT transistor and ground and another C444 inserted between the collector and emitter. In Fig. 167, C440 is expressed as C1 and C444 as C2, and the resonant current path for the flyback period is shown by arrows. In a conventional circuit, when brightness of a picture tube varies, high voltage current varies and the high voltage also varies. As a result, horizontal amplitude also varies. However, in this circuit, the horizontal amplitude variation can be suppressed to near zero if the high voltage current varies with variation of the high voltage. When the scanning period completes, the energy stored in the deflection yoke LDY is transferred to the resonant capacitor in a form of current Iy. In this case, the current is split into two; Iy1 passing through C1, C3 and Iy2 passing through C2. In the same way, the energy stored in the primary winding of the FBT is transferred to the resonant capacitor in the form of Ip. In this case, the current (path) is also split into two; Ip1 passing through C1 and Ip2 passing through C2, C3. Concequently, the current differences between Iy1 and Ip2 (Iy1-Ip2) passes through C3. When the high voltage current IH reduces with a dark picture, the current Ip in the primary circuit decreases, so Ip1 and Ip2 also decrease. However, a current flowing into (Iy1Ip2) increases as Ip2 decreases. As a result, the pulse developing at the point B increases and the voltage Vm at Csm also increases as shown in Fig. 12-8. That is, when a dark picture appears, the voltage across S-curve capacitor Cs increases as shown in Fig. 12-8, the high voltage rises, and the horizontal amplitude is going to decrease. But, as Vs increases, the deflection yoke current increases and this works to increase the horizontal amplitude. Accordingly, if the brightness of picture changes, the horizontal amplitude is maintained at a constant value. This is one of the fine features the circuit has.
IP1 C1 IH H. OUT IY1 IY C2 VB Lm IP2 IY1 C3 Csm Vm LDY CS IP IP2 FBT

VS

Fig. 12-7

VB

VS

0 Vm

Fig. 12-8

89

4-1. Basic Operation and Current Path 4-1-1. Later Half Scanning Period When the power is turned on, the power supply voltage VB is applied to Cs and Csm, and the Cs acts as a power source for a later half of the scanning period for which the H. OUT transistor is turned on, and the deflection current Iy flows in the path as shown below

4-1-2. First Half Scanning Period When the base drive current decreases and the H. OUT transistor is turned off, each energy stored in LDY, Lm, Lp of FTB is transferred to C1, C2 and C3, respectively, and the resonant current becomes zero at a center of the flyback period. Then, VA and VB pulses show a maximum amplitude.

VA FBT LDY H.OUT IY + Cs VB VB IM DM + LM IDC CSM
IM

VA FBT LDY lP

lP

IP1

C1 IP2

C2 IY2

IY

Cs

VB LM IDC CSM

VB

Fig. 12-9

Fig. 12-11

Voltage & current waveform in H period.
IY 0

IY

0

VA

0

VA

IM

0 0 IDC

0 IDC

IM

VB

0

VB

0
C1 C2 0

C1: IY1+IP1 C2: IY2+IP2

Fig. 12-10
C3 0

C3: I P2-IY1-IM

Fig. 12-12 90

4-1-3. Later Half of Flyback Period All energy in the coil has been transferred to the resonant capacitors at the center of the flyback period, and the voltage shows the maximum value. However, during next half of the flyback period, the energy of the resonat capacitor is discharged as a reverse current through respective coil. When the discharge has been completed, VA and VB becomes zero, and the deflection current in reverse direction becomes the maximum.
VA L.O.P.T IP2 IP1 C1 C2 CS IY1 IY2 VB C3 IM LM IDC CSM VB LDY IY IP

4-1-4. First Half of Scanning Period When the flyback period completes, the damper diode DD and the modulation diode DM turn on, and the Iy and Im proportionally decrease from the maximum value to zero. The H. OUT transistor is turned on just preceding at the center of the scanning period, and repeats the steps 4-1-1 through 4-1-4 stated above.

VA FBT LDY DD IY CS

VB DM IM LM IM CSM

VB

Fig. 12-13

Fig. 12-15
Voltage & current waveform in H period.

Iy

0

IY

0

VA

0

VA

0

IM

0 IDC

IM

0 IDC

VB

0

VB

0

C1 C2

0

C1: I Y1+IP1 C2: I Y2+IP2

Fig. 12-16

C3

0

C3: I P2-Iy1-IM.

Fig. 12-14 91

SECTION XIII CLOSED CAPTION/EDS CIRCUIT

92

1. OUTLINE
CC / EDS circuit extracts data of CC (Closed Caption) and EDS (Extended Data Services) from input video signal, and decode them to generate display signal. Major feature of CC/EDS circuit of TG1-C chassis is as follow. (1) Employing 1 chip decoder of stand alone type (2) Acceptable of field 2 data ( CAPTION 3, 4 TEXT 1, 2 EDS) as well as field 1 data ( CAPTION 1, 2 TEXT 1, 2) (3) Display of text mode extends from 8 rows to 15 rows. (4) Extended character display of 64 kinds standing for Spanish and the like. (5) Representing Background attributes (8 colors + transparent)

2. DATA TRANSMISSION FORMAT
CC/EDS data is transmitted being superimposed on line 21, field 1 (21H) and field 2 (284H). Waveform of line 21 is shown in fig. 13-1. Line 21 signal is composed of data of 7 cycle clock-run-in, start bit and 16 bit (8bits x 2 bytes).

10_50±0.5ms 12_910ms

4.15±0.1ms

33.764ms 0.12ms
b1 b3 b2 b4 b5 b6 P b7 A R I T Y b1 b2 b3 b4 P b5 A b7 b6 R I T Y

10.076ms

20ms

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Fig. 13-1 Line 21 waveform

93

3. DISPLAY FORMAT
Character display area of caption mode and text mode consists of 32 characters x 15 rows as shown in fig. 13-2. On front and back of each row, 1 character blank area is respectively added. In caption mode, up to 8 rows among 15 rows can be displayed at the same time. Characters in text mode are displayed in black box of 34 characters x 15 rows. EDS display format is shown in fig. 13-3. The item can be displayed only when data of the item is transmitted.

SCREEN LINE 43

ROW1

LINE 237

ROW15

1 CHARACTER BLANK AREA

32 CHARACTERS

1 CHARACTER BLANK AREA

Fig. 13-2 Caption / Text display area

(Green) (White, Slant, Unerline) (Cyan)

Network Name Program Name Prog. Length Prog. Type (Cyan)

Call Letters

(Green)

Time In Show

(Cyan)

(Yellow) Program Description (4rows)

(Character background: black)

Fig. 13-3 EDS display format 94

4. CIRCUIT OPERATION
Block diagram of CC / EDS circuit is shown in figure 13-4, and block diagram of QM01 is shown in figure 13-5. Video signal which is input to pin 9 of UM01 is changed to 1 Vp-p signal which is band-limited to 600kHz by the input circuit, and it is supplied to pin 7 of QM01. Inside QA01, line 21 signal is extracted from input video signal, and is recovered on clock and data. Recovered data is decoded by command processor and converted to display signal of R, G, B, Ys in Output Logic section. The display signal is output at pins 18, 2, 3 and 17 in the CMOS level of positive polarity. The display output and OSD are switched by QR01 in UM01, and the selected signal is sent to V/C/D IC. When the display of CC/EDS and OSD are superimposed, OSD is the first priority. H. sync signal with negative CMOS level is input to pin 5 of QM01. This signal becomes the standard signal of PLL circuit in IC. Loop filter for PLL circuit is connected to pin 9. QM01 is controlled by I2C bus connected to pins 14 and 15.

95

UM01 EDS/CC/RGB SW.

QM01 CC/EDS DECODER Q501 V/C/D Video in
9

UV01 A/V MODULE

V-AV EH ATT INVERTER 7 VIDEO 5

LPF HIN

HD

11

30 HD OUT VD

VIN 13

12

31 VP OUT

QA01 uCOM Q89- I2 C BUFFER 2 SCL1
13

QR01 RGB SWITCH BOX 17 15 SCK 14 SDA G B 3 2 R 18 2 5 3 14 1A 2A 3A 4A 1Y 2Y 1 A/B OSD-YS
18 19 20 21

Fig. 13-4 CC /EDS circuit block diagram
SCL2 SDA2
14

96
6 5 SDA SCK 3 SDA1 OSD-R OSD-G OSD-B

SCL1 37

SDA1 38

Ys OUT 4 7 3Y 0 4Y 12 3 1B 6 2B 10 3B 13 4B
6

R OUT
1

36 G OUT
5

OSD YS 37 38 B OUT
2

OSD R OSD G 39 OSD B

R 22

G 23

B 24

+5V 12 VDD Sllced Data Data Sllcer DLCK COMP Video V 7 Clamp Data CLK Recovery Display RAM Command Processor and Vertical CTR And Control 13 VIN Horizontal Counter DOT CLK
SMS SDO SEN SCK SDA

Data Recovery

Data MOD & XFR BUF

8

Sllce Level

SYNC Sllcer

Fig. 13-5 QM01 block diagram

CSYNC COMP SYNC Timing Logic

CHAR ROM

97

Decoder Control

R Output Logic G B Box

18 2 3 17

Phase/ Freq DET PFD HIN 5

Loop Filter Loop FIL 9 LPF

VCO

Vss 1

AVSS 11

6

4

15 14 16

SECTION XIV POWER CIRCUIT

98

1. OUTLINE
Block diagram of power circuit is shown in fig. 14-1. Power circuit consists of stand-by power supply (power transformer) which supplies power to microcomputer, and main power supply which supplies power to H. OUT, AUDIO OUT and signal process circuits. Power for V. OUT, VIDEO OUT and the like is supplied from flyback transformer of H. deflection circuit. Power (+12V from converter transformer) for signal process circuit are supplied from 9V-2, 9V-1, 5V-2 and 5V-3 lines by 3 terminal regulator and 4 terminal regulator with switch which are equipped in latter stage. The characteristics of this system are that main supply newly employs current resonant type which is smaller and more highly effective than conventional type of RCC switching type, and employs protector module (Z801) which includes protection circuit and error amp. for secondary output detection in one package.

T461

+200V +27V R370 T840 POWER TRANS TPW 1459AZ
Q370 OVER VOLTAGE PROTECTOR

+27V 4132 AD BE

F801 T801

+12V Q840 D840 Q420 +5V-1 MICOM PERIPHERALS

(Q462) -27V

9V-1 (TUNER, IMA, E/W, VCD) 9V-2 (COMB, DSP) 5V-2 (TUNER, COMB, VCD) (POP, RGBSW) F470 +B(+125V) R472 2 R472 HEATER C471 D471 VELOCITY MOD.

L901

R808 SR81 D801 F860 R861

T862
CONVERTER TRANS.

+26V

Q832

AUDIO OUT Q830 AND H.V CC +12V R101 1 Q831 R470 R479

Q801 VOLTAGE REGU. OVER VOLTAGE PROTECT Q843 SW QB30 SW PHOTO COUPLER TLP621 (GRL)

TPW 3335A8

R883

QA01 (25)

Z801 16 +32V (H001 PROTECTOR 14 HIC1013 HY01. HF01) 16 3

Fig. 14-1 Power block diagram 99

2. RECTIFYING CIRCUIT AND STANDBY POWER SUPPLY
Rectifying circuit is a circuit to generate dc from ac 120V. D899 is a varistor to absorb surge (ex. lightning) arose on ac line. When surge arises, the circuit let surge by-pass via route shown in figure 13-2 to protect the following circuit. C801 and T801 are a filter circuit to suppress abnormal radiation. Degaussing circuit using thermistor is equipped at after SR81 relay. R811 is a damping resistor to remove light regulator noise. D801 is a bridge rectifier diode and performs rectification and smoothing together with C810. R801 is a resistor to regulate inrush current and to suppress rush current in switch-on. T840 is standby power transformer. D840 and C840 performs rectifying and smoothing to make approx. 12V for relay driving, and Q840 regulator makes +5V to supply to microcomputer and also to output the reset signal of microcomputer.

L901 R811 Rectified output D801
THERMISTOR

F801 D899

C801

C810 R810

Surge

T801 +3V-1 Q863 QB30 MICOM POWER

SR81 Q840 1 C840 2 T840 D340 C843 3 4 C842 5 +5V (to MICOM) Reset

Fig. 14-2 Rectifying circuit and standby power supply

3. MAIN SUPPLY CIRCUIT
This circuit is a current resonant switching power circuit using hybrid IC Q801 (STR-Z3201). The current resonant power supply realizes small, highly effective and low noise power. Output of main supply are for H. deflection circuit (+125V), for audio output circuit( +25V) and for signal processing circuit (Low B, +12V). The supply (Low B, +12V) for signal processing circuit is equipped with 3 terminal regulator and 4 terminal regulator with switch in the following stage, to supply 9V-1, 9V-2, 5V-2 and 5V-3 to signal processing circuit. Audio output supply and signal processing circuit supply lines are equipped with protecting fuses F899 (for audio output line), F890 (for signal processing circuit line) which breaks in circuit failure like short of load. And F860 breaks to protect the circuit in the failure of primary circuit (break of Q801). 100

4. OUTLINE OF CURRENT RESONANT TYPE SUPPLY
Basic configuration of current resonant type power supply used in CN32E90 is shown on figure 14-3. Basic operation is as follow. Primary winding of converter trans and resonant capacitor are connected in series to consist of LC series resonant circuit. And this is drived by push-pull of two power MOS FET’s. Converter transformer operates in forward mode. Just when primary switching device turns ON, converter trans produces the secondary output. Automatic voltage control operation is done in such way that +B voltage is detected by error amp. to be fed back to the primary OSC circuit via photo coupler, then controls frequency.

O S C

D R I V E

+B

ERROR AMP PHOTO COUPLER

Fig. 14-3. Basic diagram

5. FUNDAMENTAL THEORY
Voltage generating on L of LC series resonant circuit has characteristic which varies with frequency peaking at resonant point f= 1/ (2p LC ) [Hz] as shown in figure 14-4. The circuit utilizes this characteristic to control output voltage. Actual operation is done at higher frequency than resonant point. By this operation, variable range of voltage across L ranges from maximum voltage of resonant point to power line voltage.

VL (v)

e
VL e

Resonant point f=

Frequency 1 2p LC

Fig. 14-4. LC series resonating circuit

Fig. 14-5. Characteristic

101

6. ACTUAL CIRCUIT
Two MOS FET’s, driver which drives FET’s and frequency control IC are combined inside HIC (Q801 ). Converter transformer T862 is designed to have loose coupling between the primary and the secondary, and to have some extent of leakage inductance. This is the reason why L and C (leakage inductance and resonant capacitor) are resonated during period that rectifying circuit (diode) connected to the secondary winding conducts. Rectifying circuit of the secondary winding uses double wave rectifier considering current balance of switching device, because converter transformer is driven in push-pull. The function of STR-Z3201 is explained below. Fig. 14-6 shows block diagram and figure 14-7 shows waveforms at main terminals. <<FUNCTION OF HIC>> (1) Output switching element Uses two power MOS FET’s, and operates in push-pull. Voltage across the switching element does not increase more than power line voltage basically, and therefore, element of low rating voltage (enduring 200V) is used. (2) Driving circuit Drives output switching element. MOS FET is specially used for driving element of high side, and to drive this, bootstrap circuit is equipped. (3) Dead time To avoid that two switching element turns ON at the same time in push-pull operation, dead time is arranged. (4) CT terminal (Pin 5) About basic oscillation Variable frequency oscillator is equipped inside frequency control IC, charge and discharge of the capacitor C862 connected to this terminal decide oscillation frequency and dead time. This oscillator generates triangle wave signal with low level of 2.5V(TYP) and with high level of 4V(TYP). Charging time of oscillator becomes output-on period, and discharging time becomes dead time. (5) RT terminal (Pin 5) About lowest oscillation frequency Lowest oscillation frequency is decided by capacitor C862 connected to pin 4 and resistor R867 connected to this terminal. (6) CONT terminal (Pin 6) About frequency control Current flowing out of this terminal varies charging current of oscillating capacitor C862. Therefore, flowing of CONT terminal current corresponding to feedback quantity from photo coupler (Q862) varies charging time of C862 and controls oscillation frequency. Maximum oscillation frequency is decided by R864 connected to CONT terminal. (7) Css terminal (Pin 8) About soft start Capacitor (C866) and resistor (R863) for soft start are connected to make TV start at high frequency in the time of power on and gradually make frequency lower. This function suppresses rush current in POWER MOS FET output and provides stable starting of TV. (8) CD terminal (Pin 9) Latch circuit detects abnormal operation to hold the status of operation seizing, and if following condition as a result of detecting abnormal operation comes, the latch circuit begins to start. *In operation of over voltage protection (OVP) circuit *In operation of thermal shock detection (TSD) circuit *In operation of over current protection (OCP) circuit *In going down and no recovery of Main +B output voltage Until latch function begins to operate, the charging time of capacitor C869 connected to CD terminal (Pin 9) is utilized to produce delay time. To release the latch function after operating once, turn off power and turn on again. (9) OC terminal (Pin 12) About over current protection (OCP) function This is to detect current in LC series resonant circuit, and to suppress over current to stop operation. (10) Over voltage protection (OVP) circuit This is to make latch circuit operate when voltage at Vcc terminal (Pin 10) exceeds 22V (TYP). (11) Thermal shock detection (TSD) circuit This is to make latch circuit operate when temperature inside IC exceeds 150°C.

102

<< BLOCK DIAGRAM AND PIN FUNCTION >>
Vcc 10 VB 16 HO G(H) 3 2

TSD

OVP

START

1

VIN

R1 CD 9 DELAY LATCH REF Logic 15 OUT

OC

12

OC

OSC CONTROL

R2 OSC 14 COM

R4 8 Css 6 CONT 5 CT

R3 7 RT 4 GND 11 LO 13 G(L)

Fig. 14-6. STR-Z3201 block diagram

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Symbol VIN G(H) HO GND CT CONT RT Css CD Vcc LO OC G(L) COM OUT VB Half bridge power input High side MOS FET gate High side gate drive output Control section ground

Function

Capacitor connection terminal for oscillation Oscillator control terminal Resistor connecting terminal for oscillation Capacitor connecting terminal for soft start Capacitor connecting terminal for delay latch, ON-OFF terminal Control section power terminal Low side gate drive output Over current detecting terminal Low side MOS FET gate Half bridge ground Half bridge output High side gate drive power input

Table 14-1. STR-Z3201 pin function

103

DATE TIME =4V CT PIN VOLTAGE =2.5V

OSC OUT SIGNAL

(PIN11) LOW SIDE GATE VOLTAGE (PIN2) HIGH SIDE GATE VOLTAGE

ON

OFF

OFF

ON

(PIN 15) PUSH-PULL OUT VOLTAGE

=VIN PIN VOLTAGE (PIN 1)

OV

(PIN 15) PUSH-PULL OUT CURRENT OA

Fig. 14-7 Waveform at each pin

104

7. OTHER POWER CIRCUIT
Power supply circuits excepting main and standby supply circuits are explained here. Power supplied from T461 (Flyback transformer) of H. deflection circuit is shown in figure 13-8. Flyback transformer supplies 200V for video output from pin 3, 27V for V. out circuit from pin 6, and -27V for side DPC circuit from 5 pin respectively. Resistors (R327, R462) inserted in each line are protecting resistor which fuses in abnormal situation like load short.

-27V AFC BLANKING FBT 10 ANODE

HEATER R642

9 5

C461

D460

4

FOCUS

C3\7 R327 +27V C310 200V D302 D406

7 6

3 SCREEN +B C448 Q404 Collector 1 8 ABL 2

Fig. 14-8. Other power circuit

105

8. PROTECTOR MODULE (Z801)
CN32E90 employs protector module which combines in one package protection circuits for X-RAY protection and over current protection, and error amplifier for +B voltage detection. This is for the purpose of small size and standardization of protection circuit, and what were discrete circuits in conventional chassis are arranged into module. Equivalent circuit is shown in figure 14-9. A section is error amplifier for +B voltage detection, B section is over current protection circuit and C section is X-RAY protection circuit. D section forces power signal from microcomputer to set in low level by the signal from protection circuits, and to turn OFF the power relay and keep it. Actually in case of over current protection circuit, when over current flows in +B line, Tr8 turns on to supply base current into Tr6 through ZD4. In case of X-RAY protection circuit, when high voltage increases abnormally, Tr10 and Tr9 turns on to supply base current into Tr6 through D3, then this causes Tr6 and Tr5 turn on to make power signal from microcomputer in low level. Besides, by the positive feedback that turning on of Tr6 causes Tr7 turn on to make base current flow to Tr6, as long as 5V is supplied to pin15, Tr5, Tr6 and Tr7 continues to be on to keep safety. Therefore the operation is not released by remote control, but continues until AC cord is pulled and inserted. When this module operates, red blinking of power LED shows the operation of protection circuit.

R470 POWER Q862 R890 C470 5V-1 5 3 16 15 6 2 1 14 12 R472 R479 C474 13 +25V 11 +B X-RAY

+25V over voltage protection +27V over current protection

Tr9 A R2 R10 D Tr1 Tr6 R3 ZD1 R12 R11 C1 ZD4 Tr7 R14 R15 Tr8 B R21 D3 R9 R19 R16 D1 R20

Tr10

R25

R23

R22 C R26

Tr5

7

17 Pins 4, 8, 9,10: No connection Pin14: Gate terminal Protection circuit begins to operate with 1.5V or more of this termianl voltage.

Fig. 14-9 Protector module equivalent circuit

106

TROUBLESHOOTING CHART OF POWER CIRCUIT
No raster 17 9 Fuse F801 breaks No 10 Fuse F860 breaks No No YES YES Check/Repair AC circuit Replace F801

23

18 Is the following point short? #1-#14, #1-#15, #14-#15 of Q801 YES

24 Replace Q801, F860 25 Replace F860 26 NG Check/Repair D801, R810 C810 27 Does pin 15 of Q801 operate in switching? NG Voltage across C868 28 OK Check/Replace Instantly switching Q801, C870, T862 and then stops immediately 30 Check/Repair Q801, C862, Q862 Z801, D883, D884, R864 31 Check/Repair C868, D864, R871, D876, R861

Instantly turns ON and 11 then turns OFF immediately

19 OK Check relay SR81 Voltage across C810 20

1 Check/Repair T840, D840 2 No Check/Repair T840 or 5V-1 using circuit 3 Check QA01 (pin 7), QB30 NG

12 Check voltage across C840 OK 13 Voltage at pins 4 and 5 5V? 14 No Is base voltage of Q843 high level? (4.3V) YES YES

NG

21 NG Voltage across C889 OK 22 NG Voltage across C897

32 Check/Repair F899, D885, D886, audio power line 33 Check/Repair F890, D891, D892

4 Power LED blinks in red.

15 Check/Repair Q843, SR81

OK 34 YES 5 Voltage across C884 jumps instantly to 140V or more No 6 Z801 makes over current protection circuit, X-RAY protection circuit and +27V over voltage protection circuit operate Check peripherals of start circuit Q430 and audio Vcc Check/Repair Q801, D883, D884, Z801, R883, R884, Q862, R864 35 16 NG Is voltage at pin 22 (H-Vcc) of Q501 9V? OK

36 7 NG Check deflection circuit Check R920 and CRT Drive board

37

Does heater light? OK

38

107

Check peripherals of Q501 and video out circuit

(No RASTER)

8 No RASTER

1 Check/Replace F470, Q404 NG

4 Red lights Check F470 OK 5 NG Is voltage at pin 22 (H-Vcc) of Q501 9V? OK Check peripherals of start circuit Q430 and audio Vcc

10 Is the status of power LED? Red blinks

2

13 Short R370 and turn power on again (See note below.) 6

21 LED Red blinks Check peripherals of V.out circuit Q301 and +27V line 22

3 Check R920 CRT Drive board NG

15 Does heater light? OK Check peripherals of Q501 and video out circuit 17 Short R470 and turn power on again (See note below.) Red blinks 19 Check protector module Z801 and power circuit F470 blinks Open R472 and turn power on again (See note below.) Red blinks 23 Check main B line and H. out circuit (Q404, 4T461) LED Red blinks Check H. out circuit; C440, C444 and X-RAY protection circuit (including Z801)

7

Note: Do not take time, check within short time.

108

SECTION XV DSP CIRCUIT

109

1. ORIGINS OF DOLBY SURROUND
Dolby Stereo movies and Dolby Surround video and television programs include an additional sonic dimension over conventional stereo productions. They are made using a Dolby MP (Motion Picture) Matrix encoder, which combines four channels of audio into a standard two-channel format, suitable for recording or transmitting the same as regular stereo programs. To recapture the dimensional properties brought by the additional channels, a Dolby Surround decoder is used. In the theatre, a professional decoder is part of the Dolby Stereo cinema processor used to play 35 mm stereo optical prints. The decoder recovers the left, center, and right signals for playback over three front speakers, and extracts the surround signal for distribution over an array of speakers wrapped around the sides and back of the theater. (These same speakers may also be driven from four of the six discrete tracks on 70 mm Dolby Stereo magnetic prints, but in this case no decoder is needed.) Home viewing of movies on video has become extremely popular, and with the advent of stereo VCR's, stereo television and digital video discs, the audio side of the video presentation has improved considerably, inviting the use of full-range sound reproduction. The ability to deliver high quality audio in these formats made it easy to bring MP Matrix-encoded soundtracks into the home as well, thus establishing the foundation for Dolby Surround.

into left, center equally into left and right, and right into right-playing a Dolby Stereo soundtrack over two speakers reproduces the entire encoded soundtrack. There is but one exception: the surround signal, though audible, is not reproduced in its proper spatial perspective. When the first home decoder was developed in 1982, its goal was to restore this lone missing dimension. Before we discuss decoders, it is necessary to see how the MP Matrix encoder works. Referring to the conceptual diagram in Fig. 15-1, the encoder accepts four separate input signals; left, center, right, and surround (L, C, R, S), and creates two final outputs, left-total and right-total (Lt and Rt). The L and R inputs go straight to the Lt and Rt outputs without modification, and the C input is divided equally to Lt and Rt with a 3 dB level reduction (to maintain constant acoustic power). The S input is also divided equally between Lt and Rt, but it first undergoes three additional processing steps: a. Frequency bandlimiting from 100 Hz to 7 kHz. b. Encoding with a modified from of Dolby B-type noise reduction. c. Plus and minus 90-degree phase shifting is applied to create a 180-degree phase differential between the components feeding Lt and Rt. It is clear there is no loss of separation between the left and right signals; they remain completely independent. Not so obvious is that there is also no theoretical loss of separation between the center and surround signals. Since the surround signal is recovered by taking the difference between Lt and Rt, the identical center channel components in Lt and Rt will exactly cancel each other in the surround output. Likewise, since the center channel is derived from the sum of Lt and Rt, the equal and opposite surround channel components will cancel each other in the center output. The ability for this cancellation technique to maintain high separation between center and surround signals requires the amplitude and phase characteristics of the two transmission channels to be as close as possible. For instance, if the center

2. THE DOLBY MP MATRIX
One of the original goals of the MP Matrix was to enable Dolby Stereo soundtracks to be successfully played in theaters equiped for mono or two-channel stereo sound. This allows movies to be distributed in a single optical format, and furtheremore results in complete compativility with home video media without requiring separate soundtrack mixes. Since the three front channels of the MP Matrix are assembled in virtually the same way as a conventional stereo mix --- left

Left

+ + DOLBY NR ENCORDER

+ + +90 DEG -90 DEG + +

Lt

Center

-3dB

Surround

-3dB

B.P.F

Right

+

+

Rt

Fig. 15-1 Conceptual Dolby Stereo/Dolby Surround encoder 110

channel components in Lt are not identical to the ones in Rt as a result of a channel balance error, center information will come out of the surround channel in the form of unwanted crosstalk.

4. DSP CIRCUIT
A surround component (L-R) is extracted from L, R audio signals coming through the AV SW in the matrix circuit as shown in Fig. 15-3. The surround component enters the DSP circuit through the LPF. The signal is A/D converted, delayed by an arbitrary time of 0~100 msec (every 3.2 msec) by digital process and then D/ A converted and outputs from the DSP IC. The DSP IC develops two outputs; (LO) for FRONT (LO) and (RO) for REAR and each output is controlled by the microcomputer for each surround mode. The output signal (LO) for FRONT is added and subtracted with the input signal in a matrix circuit and output from the front speaker in passing through the audio processor and main amplifiers. At the same time, the output signal (RO) for REAR is fe?? to the Dolby NR circuit, but switched to "Dolby surround" mode, and then output from the rear speaker in passing through audio processors and rear main amplifiers. In this case, the DSP stands for not only a simple digital surround processor but also a digital surround field processor. That is, it works to give a simple surround effect but to give effect as if the listener can feel reality suitable for the programs. For example, it aims to give the listeners a reality matching to each program they are enjoying in their home listening room so that they can obtain reality of big concert hall or feel as if they are watching a move at a reserved seat in a movie theater.

3. THE DOLBY SURROUND DECODER
This leads us to the original Dolby Surround decoder. The block diagram in Fig.1 5-2 shows how the decoder works. Except for level and channel balance corrections, the Lt input signal passes unmodified and becomes the left output. The Rt input signal likewise becomes the right output. Lt and Rt also carry the center signal, so it will be heard as a "phantom" image between the left and right speakers, and sounds mixed anywhere across the stereo soundstage will be presented in their proper perspective. The center speaker is thus shown as optional since it is not needed to reproduce the center signal. The L-R stage in the decoder will detect the surround signal by taking the difference of Lt and Rt, then passing it through a 7 kHz low-pass filter, a delay line, and complementary Dolby noise reduction. The surround signal will also be reproduced by the left and right speakers, but it will be heard out-of-phase which will diffuse the image. Since the heart of the decoding process is a simple L-R difference amplifier, it is referred to generically as a "passive" decoder. This is to distinguish it from decoders using active processes to enhance separation which are known as "active" decoders.

INPUTS L Lt INPUT BALANCE CONTROL Rt LEVEL CONTROL L+R Optical passive center siganal R L R C C S MASTER LEVEL CONTROL

OUTPUTS Left Right Center Surround

S L+R

ANTIALIAS FILTER

MODIFIED B-TYPE NR DECODER

DELAY SET

AUDIO DELAY

7 kHz LOW PASS FILTER

Fig. 15-2 Passive surround decoder block diagram 111

From A/V SW QD01 Input Buffer Q670 Front amp L L R R-S L+R L+S 12 10 R L 10 9 5 LPF QD01 QD02 1 LPF 3 1 R 6 7 3 MATRIX (L-R CIRCUIT) (L-R) QD01 4 QD03 DSP IC YM7128 B 8 8 14 L 5 7

QD08 Input Balance

QD02 DSP Front Addition Circuit

L

IN

Speaker R

R

Sycrone (Super woofer)

VC TO A/D DIGITAL DELAY Audio Processor (H002)

Fig. 15-3 Block diagram of DSP circuit
CONT D/A
LO

112
VL Buffer
3 1 5

7

LPF 7 QD05

LO QD05

QD04

BUS CONVERT

From Micro computer

VR D/A
RO

Buffer
3 7 3

DQ06 LPF 8 QD06
1 6

Dolby NR
9
12

14

Q640 Rear Amp +S L-R L Speaker QD07 DQ02 R

As shown in Fig.1 5-4, a sound emitted in a sound field can be classified as a direct sound which directly reaches ears of a listener, and reflected sound which comes after collision with a wall as shown by dotted line or comes after several times of collision as shown by double dotted lines. The listeners are determining that they are listing in what type of location by perceiving time difference and volume level

difference between the direct sound and the reflected sound. For more detail, this situation can be expressed with the direct sound, initial reflection sound coming after one time of reflection, and trains of reverberation sound in later period as shown in Fig. 15-5. The DSP circuit develops these initial reflection sound and the reverberation sound artificially and add them to the original sounds, thereby creating rhe effect that allows the listeners in the home listening room to feel as if they are listening in an original location. The DSP IC YM7128B has eight separate output taps and their delay time and the output levels can be specified separately, so, various sound fields can be selected by varying the initial reflection sound. Moreover, the IC has an internal feedback loop which controls the delay time and the output level in considering the later time reverberation sound.

Direct Sound Sound Level Direct Sound Initial Reflection Sound

Reverberation Sound

Initial Reflection Sound Reverberation Sound Time

Fig. 5-4

Fig. 5-5

113

5. DSP (Digital Surround Processor) IC
Input signal entered into analog input pin 4 of DSP IC QD03 (YM7128B) is converted to 14 bit digital signal with the sampling frequency 23.6 kHz by A/D converter of 14 bit floating system, and enters digital delay circuit through digital attenuator VM and doubler. The digital delay circuit has nine output taps, and the delay time of each tap can be controlled independently, also each tap position can be switched by T0 to T8 register. In a minute, the T0 output passes through the primary FIR (Finite Impulse Response) type low pass filter, and reduction

processing is performed by VC, then it feed-backed to the delay input after it is added to the doubler described above. The output of eight taps T1 to T8 is added after performing reduction processing by GL1~GL8, GR1~GR8, and reduction processing is performed by the digital attenuator VL or VR, and an analog output is created by D/A converter after passing through digital filter, comes out from pin 7 or 8. The digital attenuated value, delay time and the coefficient of FIR type low pass filter are set by writing the data on the register. This process is performed by loading three data from sub microcomputer to microcomputer interface. This unit has four modes as surround mode. The setting values are described in Table 15-1.

Table 15-1 DSP control factor Mode -VM (IN) VL (LO) VR (RO) VC (Echo) GL1 2 3 4 5 6 7 8 GR1 2 3 4 5 6 7 8 T0 (Delay) 1 2 3 4 5 6 7 8 C0 (Filter) 1 114 0 0 19.4 0 P-2 M-2 P-8 P-10 0 12.9 38.7 71.0 87.1 29.0 45.2 83.9 100.0 0 0.71875 0.28125 100.0 93.6 100.0 100.0 0 P0 -¥ P0 P-18 -¥ P-6 M-6 M-10 P-12 19.4 12.9 19.4 22.6 29.0 6.5 9.7 25.3 35.5 0.59375 0.40625 P-4 P-8 P-8 P-14 51.6 71.0 83.9 100.0 0 64.5 80.7 90.4 100.0 0.875 0.125 — — msec OFF Control -¥ DOLBY SURROUND P-0 -¥ P0 -¥ THEATER P0 P0~ -¥ P0 -¥ P-4 M-6 P-12 P-12 -¥ STADIUM NIGHT CLUB CONCERT HALL HALL P0 P0~ -¥ P0 M-6 M-2 -¥ P0 P0~ --¥ P0 M-10 M-2 P-4 P-6 M-10 -¥ P0 P0~ --¥ P0 M-8 P-2 P-10 P-16 -¥ UNIT dB

XD01 CD27 RD32 D01 QD03
1 1 1 2

CD29 CD28

RD33
1 6

XO C1 CV
5

XI

/IC

Vss
1

CD22 RD26 From Input LPF CD15 CH
3 4

REFERENCE VOLTAGE GENERATION VM
A/D CONVERTER

VC C2
T0

D

TIMING GENERATION AVDD
2

LD01 +B (5V)
CD21 CD20

AIN

DIGITAL DELAY
T8 T7 T6 T5 T4 T3 T2T1

GL1 GL2 GL3

Fig. 15-6

CD23 /TI
6

115

GL4 GL5 GL6 GL7 GL8 GL1 GL2 GL3 GL4

VL 2fs
D/A CONVERTER

LO
7

DC26

To LPF Output (For FRONT ch)

VR 2fs

RO
D/A CONVERTER
8

MICROCOMPUTER INTERFACE

GL5 GL6 GL7

To LPF Output (For REAR ch) DC25

DIN AO VDD
1 5 1 4 1 3

SCI

GL8

VSS
1 0 9

AVSS

From

Bus convert (ICD04)

6. SURROUND CIRCUIT
The surround circuit used in this model has the modes shown in Table 15-2 of the modes, description will be given for 5 mode. The description will be made according to items shown below.

7. INPUT BALANCE CIRCUIT
Fig. 15-8 shows the input balance circuit. The input balance circuit is to adjust gain of Lch and Rch so that (L-R) component in the matrix circuit becomes zero. Adjustment by the input balance volume control on the remote hand unit.

Surround Mode CONCERT HALL THEATER NIGHT CLUB STADIUM Dolby Surround OFF

Assumed sound field Front Rear Concert hall Movie theater Disco, Night club Baseball stadium Dolby surround soft Off Table 15-2 O O O O X X O O O O O X

[dB] 0
Response

Lch

Rch

-8 Min Center Control

Fig. 15-7

+9V A/V SW L OUT + 2 CD04 1m50V RD23 15K 4 6 7 8 RD24 56K CD05 22m 4V 9 10 11 12 R 14 CD06 1m 50V 13 Reh Input buffer L 3 5 Leh Input buffer CD09 22m 16V QD08 1

R OUT

Input balance control

Fig. 15-8

116

8. MATRIX CIRCUIT
Fig.15-9 shows the matrix circuit. The matrix circuit is to create a surround signal of (L-R) from the Lch and Rch signals. According, if a monaural signal enters, L-R=0, showing no surround effect exists.

9. FILTER CIRCUIT (ANTI-ALIAS FILTER)
Fig. 15-10 shows the filter circuit. The filter circuit is to cut frequencies higher than 7 kHz in considering processing capacity of the DSP circuit (delay) connected to next stage, and two stages of the filters are employed in this unit.

CD02 1m50V (NP) 12 Lch IN 13

QD01 Buffer 14 Lch OUT RD13 39K CD15 39K QD01 5 6 7 Surround OUT (L-R)

CD02 39K REF

CD03 39K CD16 33K Rch OUT QD01 Buffer

CD03 1m50V (NP) Rch IN

9 8 10

RD14 39K

Fig. 15-9

RD17 10K

RD18 10K

RD19 10K

QD01 3 2

RD20 10K

RD21 10K

RD22 10K

3 2

QD02

CD11 M2700P

CD12 M6800P

CD10 390P

CD13 M2700P

CD14 M6800P

CD16 390P

Fig. 15-10

117

10. DSP CIRCUIT (DELAY)
Fig.1 5-11 shows the DSP circuit. The DSP circuit delays the surround signal entered by a time of digital delay determined for each mode and then outputs the signal. The DSP circuit is controlled with 3 line-bus data from the sub-microcomputer. The DSP circuit develops two type of outputs; one for front addition and the other for rear output. Details of the outputs are shown in Table 15-2.

Bus data

16

15 DIN

14 AD

13 SCI

12 XI

11 XO

10

9

Ycc 1 2

CH 3

DSP QD YM7128B IN CY 4 5 6

Lo 7

Ro 8

LPF Rear OUT Surround IN (L-R) LPF Front OUT

Fig. 15-11

118

11. 7 kHz LOW PASS FILTER
The DSP outputs are received at inputs of high impedance voltage followers and then fed to 7 kHz LPFs. Since L and R components of the DSP output are processed in time sharing by the D/A converter, the LO and RO outputs must be received at the high impedance input circuits. The LPFs which receives the signals consist of OP amplifiers.

QD03 DSP LO

CD39 M5600P CD32 1m 50V 7 CD26 33P RD31 1M REF RD34 1M CD17 M6800P 5 8 CD34 1m50V CD25 33P 6 CD19 M2700P CD18 390P QD06 7 RD47 10K RD46 10K RD45 10K QD06 3 2 1 Rear (Dolby NR circuit) QD05 3 2 1 RD30 10K RD29 10K RD28 10K QD05 5 6 CD31 M3300P CD30 820P 7 Front (Addition circuit)

DSP RO

Fig. 15-12

119

12. DOLBY NR CIRCUIT
Fig. 15-13 shows the Dolby NR circuit. The Dolby NR circuit used in this unit is a modified B type for Dolby surround and the operation characteristics are shown in Fig. 15-14.

RD61 47K

CD43 M4700P

CD44 M0.027

CD45 M5600P

RD60 47K 16 15 Dolby N.R 14 13 12 11 10 9

RD66 18K QD02 14

RD65 150

12 QD07 TA7629P REF 13 6 7 8

Rear OUT CD46 4.7m16V (NP)

1

2 RD48 5.6K

3

4

5

Rear IN RD49 2.2K CD35 10m 16V

CD38 1m50V

RD25 47K

RD27 33K

ENCODE [dB] Response

Fig. 15-13

f

[Hz]

DECODE (Dolby NR) [dB] Response

f

[Hz]

Fig. 15-14 120

13. DSP FRONT ADDITION CIRCUIT
Fig. 15-15 shows the front addition circuit for the surround signal. In the DSP operation of this model, the surround signal is added to the front channel to provide the surround effect if rear speakers are not used. In practice, the front addition surround signal output from the DSP circuit is added to Lch with the phase non-inverted and to Rch with the phase inverted.

RD01 20K Lch IN

QD02 7 Lch OUT 5 6

Lch OUT

RD09 16K Surround (L-R) RD10 15K

RD04 15K

RD06 27K

REF RD08 24K

RD05 16K Rch IN

RD07 15K

9 Rch OUT 10 8 Rch OUT

QD02

Fig. 15-15

121

14. BUS CONVERTER
The bus converter receives I2C-bus data sent from the main microcomputer and converts them into DSP control data. The data are transferred to the data input of the DSP.

15. NEUTRAL BIAS
To develop a neutral bias voltage for the OP amplifier, +B (12V) is divided with resistors.

To DSP (QD03)

+B RD12 1K REF RD11 1K GND CD01 100m 16V

RD42 1K

RD43 1K

RD44 1K

5 DIN Vcc

6 AD

7 SCI SCL

8

QD04 RESET SDA

Fig. 15-17

+5V

4

3

2

1

RD39 100

RD38 100

ICD03 16 pin From main microcomputer

Fig. 15-16

122

16. AUDIO OUTPUT AMPLIFIER (For Rear SP)
The audio amplifier develops 5.0W two circuit.

Vcc C646 100m 25V 4 Ripple Filter 2 6 R641 1.8K 1 R647 22K Mute Q641 2SC2878A C645 47m25V 3 Pre GND PW-GND 5 C655 0.12m R685 2.2W SURROUND SPEAKER TERMINAL 7 Vcc C652 R660 470m 35V 1.5W(5W) C650 1000m35V

R640 6.8K Rear INPUT

C647 1000P

C641 2.2m 50V

C649 2.2m50V

Q640 TA8213K

R644 100K

Fig. 15-18

123

17. TROUBLESHOOTING CHART

No sound.

NG Is power supplied +5V, +12V lines? OK Check Power supply circuit.

NG Are input signals applied to 13 , 14 terminals? OK NG Are inputs applied to pins 14 , 8 of QD01? OK NG Do output pins L 10 , R 11 develop outputs? OK

Check A/V SW output.

Check Input Buffer (QD01).

Check DSP front addition circuit (QD02).

Check Sound volume control circuit (H002) and Front power amplifier circuit (Q670).

No rear sound.

NG Is rear sound component contained in the input signal? OK NG Is input applied to pin 4 of QD03? OK NG Do pin 7 and 8 of QD03 develop outputs? OK NG Does Sout 6 develop the output? OK

Rear sound is not developed as Adaptive matrix circuit is actuated. Use an effective source.

Check L-R matrix circuit (QD01) and Anti-alias Filter (QD01 & 02).

Check DSP (QD03) and DSP control data.

Check LPF (QD06) and Dolby NR circuit (QD07 & 02).

Check Sound volume control circuit (H002) and Rear power amplifier circuit (Q640).

124

SECTION XVI FAILURE DIAGNOSIS PROCEDURES

125

1. H STARTING CIRCUIT FAILURE DIAGNOSIS PROCEDURES
No raster.

Check main power voltage. (125V?)

Check X-Ray circuit, protection circuit.

Check voltage at pin 32 of 0501.

To "Start circuit diagnosis".

Check wafeform at pin 23 of IC501.

Check and repair H drive circuit, H output circuit, FBT circuit, etc.

Check and repair C403 D490, Q501 (TA1222N)

Start circuit diagnosis Start circuit diagnosis.

Check D431 cathode voltage. OK

NG

NG Check voltage of Audio + B line. OK

Check and repair power supply circuit.

Check and repair R432, Q430, D431 and D430.

Check voltage at pin 22 of Q501. OK Check and repair Q501 (TA1222N).

NG

Check and repair C430, C431, D490 and L400. OK

126

2. DEFLECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES

No vertical scanning Horizontal one line.

NG Check +27V power supply. OK

Check, repair and replace C310, D302, Q301, R327.

Check voltage at Normal: + leed of C306 15V

More than 20V

Check and repair L462 R313, R304, R305, R306, R307 in vertical ourput circuit.

Check pin 13 input of Q302 with synchronous scope. 5Vp

NG

Check pin 31 output of Q501 with synchronous scope. 5Vp

OK

Check and repair Q302.

OK

Check pin 15 of Q302 with synchronous scope. 1.5V

Check DEF + Vcc pin 22 of Q501 is 9.0V. V/C + Vcc, pin 40 and 46 of Q501 is 9.0V. OK

NG

Check output circuit.

Replace Q501.

Check pin 3 of Q302 is +9V. OK

NG

Check and repair 910V D420, Q421, Q420 and R424.

Replace Q302

127

3. LEFT-RIGHT PIN-CUSHION DISTORTION CORRECTION CIRCUIT

Left-Right pin-cushion distortion correction is not carried out.

Check voltage across C460 on DPC circuit. (-27V) -27V OK

-27V:NG

Check and repair R469 output circuit.

Check waveform at Q461 collector. Parabora OK waveform

Parabola waveform is not observed

Check and repair around Q461.

Check waveform at Q462 collector. Parabora OK waveform

Parabola waveform is not observed

Check and repair D464, D465, D466, R343, R341, R465.

Check waveforms at Q462 emitter Q460 collector. Parabora OK waveform

Parabola waveform is not observed

Check and repair around Q460, Q462

Check, replace or repair C467, C464, D461, L461

128

4. X-RAY PROTECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES

X-ray protection circuit does not work (When X - R terminals are connected).

Check voltage at D471 cathode. (20 - 22V?) OK

NG

Check and repair D471, R472. Check and repair around pin 9 of FBT.

Check and repair Z801.

129

5. PROTECTION CIRCUIT DIAGNOSIS PROCEDURE
Operation of protection circuit for Thyrister D862. (SR81 Relay turns on but immediately turns off.)

Power on with D870 opened. (Do not turn on for a long period.)

SR81 turns on for a short time but immediately turns off.

Check over-current protection circuit, H output and repair D870, Q870, R870 - R873, R876, R881.

With SW turned on, check 125V line voltage with oscilloscope. Less than 130V

Higher than 130V.

Check over-voltage protection circuit (125V) and D846, D878, Q801, Q841, Q845, Q862 and repair. Check broken pattern in feedback loop.

With SW turned on, check 24.5V line voltage with oscilloscope. Less than 35V

Higher than 35V.

Check over voltage protection circuit (24,5V) (125V rectification line opened, or 24.5V line leaded light.) Check rectification line (T862 -C889), Q610, pattern connectors connected to Q610, and repair.

With SW turned on, check voltage across C471 with oscilloscope. Less than 24.1V

Higher than 24.1V.

Check X-ray protection circuit, H output circuit, X-ray protection detector circuit, and repair.

Check C867, D862, D878, Q863, R874, R875, R877, and repair.

• 125V line becomes over voltage, thyristor D862 comes in to failure, and when Q863 does not turn on, D888 is short-circuited and intermittent oscillation occurs. To protect the circuit a double protection system is employed. • When the overvoltage protection circuit is working. never turn on the power with the protection circuit disabled. High voltage will be stepped up and secondary breakdown may occur.

130

6. VIDEO CIRCUIT DIAGNOSIS PROCEDURES
Failure Phenomena No picture OSD and picture do not appear. OSD is OK, picture does not appear. OSD is OK, picture does not appear. (A/V circuit is defective.) Picture of only VHF/UHF of main screen does not appear. Picture of only VHF/UHF of sub screen does not appear. No color After Q501, no color A/V, comb, etc. Reference Item (A) (B) (C) (D) (E) (F) (G)

* Diagnosis of video signal through VIDEO input is done by inner video signal SGV as well. In this time, do not connect any cable to VIDEO 1.

131

(A) OSD AND PICTURE DO NOT APPEAR
NG Check that heater or CRT lights.

Check R920 (heater resistor) and power/def circuit.

OK

Power supply of CRT Drive board. 9V, 200V

NG Check power/def circuit.

OK NG Check waveform of TP-47R, G, B.

Check CRT and power/def circuit.

OK

NG Check waveform of TP-46R, G, B.

Check Q907, Q910 and blanking circuit. (pow/def board)

OK

Check Q501 power. Pins 22, 40, 46---------- 9V Pin 12---------------------- 5V

NG

Check power line and power/ def circuit.

OK

NG Check waveform of I2C bus line.

Check I2C bus line and QA01 (MICOM).

OK

Check Q501 and peripherals.

Check QA01 and periheral circuit.

132

(B) OSD IS OK, PICTURE DOES NOT APPEAR

Check waveform at pin 53 (Y2 input) of Q510. Approx. 0.7VP-P

OK

Check I2C bus line waveform at pins 27, 28 of Q501.

OK Check Q501.

NG

NG

Check waveform at pin 4 (Y1 output) of Q510. Approx 0.7VP-P

OK Check C203. Check I2C bus line and QA01.

NG

Check waveform at pin 15 (Y1 output) of Q501. Approx 1VP-P

OK Check Q501.

NG

Check waveform of comb Y output. 2VP-P

NG

Check waveform of comb Y input. 2VP-P

NG

Check A/V circuit. Go to (C).

OK Check A/V circuit. Go to (C).

OK

Check waveform of comb Y input. 0.4 VP-P (3.58MHz)

NG Check Q501.

OK

Check Comb Board.

133

(B) OSD IS OK, PICTURE DOES NOT APPEAR (A/V CIRCUIT IS DEFECTIVE)

Check waveform at pin 36 (Y-AV) or QV01. 2VP-P

OK Check Q501. Go to (B).

NG

OK Check waveform at pin 30 (Y-Comb) or QV01. Check QV01.

NG

OK Check waveform at pin 38 (V-AV) or QV01. Check Comb filter. Go to (B).

NG

Check input waveform. 1VP-P Video1 Pin 12 of QV01 Video2 Pin 10 of QV01 Video3 Pin 16 of QV01

OK Check QV01.

NG

Go to (D), (E)

134

(D) PICTURE OF ONLY VHF/UHF OF MAIN SCREEN

Picture of only VHF/UHF of main screen does not appear

Check waveform at pin 7 of H002. NG

OK

Check waveform at pin 7 of QV01.

OK Replace QV01

NG

Check/Replace QV40, QV41, QV42, QV43.

Check power voltage at pin 4 of H002. 9V

NG Check power circuit

OK

Check waveform at pin 2 of H002.

OK Replace H002

NG

Check power voltage of H001. Pin3 9V Pin8 5V Pin9 32V

NG Check power circuit

OK

Replace H001.

135

(E) PICTURE ONLY VHF/UHF OF SUB SCREEN DOES NOT APPEAR(B) OSD IS OK, PICTURE DOES NOT APPEAR

Picture of only VHF/UHF of main screen does not appear

Check waveform at pin 15 of HY01. NG

OK Check waveform at pin 28 of QV01.

OK Replace QV01.

NG Check power voltage of HY01. Pin9 9V Pin7 5V Pin2 32V NG Check power circuit.

Check CV09, RV12.

OK

Replace HY01.

136

(F) NO COLOR (AFTER Q501)

Check waveform at pin 13 of Q501. Burst: 0.3 to 0.6 VP-P

NG Check Q503 and A/V circuit.

OK

Check power supply of Q501. Pin 1=5V, Pins 22, 40, 46=9V

NG Check power/def circuit.

OK

Check waveform at pins 5, 6 of Q501. Color bar: approx. 0.6VP-P

NG

Check Q501 and pins 10, 11 peripherals.

OK

Check waveform at pins 51, 52 of Q501. Color bar: approx. 0.6VP-P

NG

Check C514, C515.

OK NG Check waveform of I2C bus line.

Check I2C bus line, and check bus data, micom memory, etc.

OK

Check Q501.

NG

137

(G) NO COLOR (A/V, COMB)

Check waveform of video output. (or check monitor picture.)

OK

Check waveform at pin 32 of QV01. Burst: 0.3 to 0.6 VP-P

OK NG Check waveform at pin 34 of QV01.

NG

Check comb filter.

Check input waveform as noted below. VIDEO 1 pin 14 of QV01 VIDEO 2 pin 10 of QV01 VIDEO 3 pin 18 of QV01

NG Check QV01. OK

Check Q501.

NG OK

Check QV01.

Check U/V tuner, IMA module, etc.

138

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