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Color Television

Chassis

Q552.2L
LA

19111_000_110519.eps 110711

Contents
1. 2. 3. 4. 5. 6. 7. 8. 9.

Page
11. Styling Sheets Blockbuster/Emmy 32" Blockbuster/Emmy 40" - 46" Sundance 42" - 47" 177 178 179

Revision List 2 Technical Specifications, Diversity, and Connections2 Precautions, Notes, and Abbreviation List 5 Mechanical Instructions 9 Service Modes, Error Codes, and Fault Finding 22 Alignments 41 Circuit Descriptions 48 IC Data Sheets 54 Block Diagrams Wiring diagram Blockbuster/Emmy 32" 65 Wiring diagram Blockbuster/Emmy 40" - 46" 66 Wiring diagram Sundance 42" - 47" 67 Block Diagram Video 68 Block Diagram Audio 69 Block Diagram Control & Clock Signals 70 Block Diagram I2C 71 Supply Lines Overview 72 10. Circuit Diagrams and PWB Layouts Drawing B01 313912365213 73 B02 313912365213 84 B03 313912365213 93 B04 313912365213 101 B05 313912365213 106 B06 313912365213 107 B09 313912365213 111 313912365213 SSB Layout 112 B01 313912365214 114 B02 313912365214 126 B03 313912365214 135 B04 313912365214 143 B05 313912365214 148 B06 313912365214 149 B09 313912365214 153 313912365214 SSB Layout 154
Copyright 2011 Koninklijke Philips Electronics N.V. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips.

Published by ER/TY 1167 BU TV Consumer Care, the Netherlands

Subject to modification

EN 3122 785 19112 2011-Jul-15

EN 2

1.

Q552.2L LA

Revision List

1. Revision List
Manual xxxx xxx xxxx.0 First release. Manual xxxx xxx xxxx.1 Chapter 2: Table 2-1 updated (added CTNs). Chapter 4: added wiring diagrams; see section 4.1. Chapter 7: updated power supply connector overview; see Table 7-1. Chapter 7: added Ambilight; see section 7.8. Manual xxxx xxx xxxx.2 Chapter 2: Table 2-1 updated (added CTNs). Chapter 4: added wiring diagrams; see section 4.1. Chapter 6: added white tone values; see section 6.3.1.

2. Technical Specifications, Diversity, and Connections


Index of this chapter: 2.1 Technical Specifications 2.2 Directions for Use 2.3 Connections 2.4 Chassis Overview Notes: Figures can deviate due to the different set executions. Specifications are indicative (subject to change). Table 2-1 Described Model Numbers and Diversity
SSB Ambilight 2 4 Mechanics Connection Overview Assembly Removal 7 Descriptions 9 10 Schematics B06 (non-DVBS-LVDS) B09 (non-DVBS-conn.) B03 (DC/DC / Class D) E (IR/LED/Keyboard)

2.1

Technical Specifications
For on-line product support please use the CTN links in Table 2-1. Here is product information available, as well as getting started, user manuals, frequently asked questions and software & drivers.

B02 (PNX85500)

AL1 (Ambilight)

AL3 (Ambilight)

Wiring Diagram

3139 123 xxxxx

3104 313 xxxxx

Wire Dressing Dressing

LCD Removal

B01 (Tuner)

CTN

Styling

32PFL6606D/77 Blockbuster 65213 11-1 65214 32PFL7606D/78 Emmy 11-1 65213 65214

64833 64853 64853 64853 64853 64873 64873 64812

2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3

4-1 4-2 4-3 4-3 4-4 4-4 4-5 4-5 4-6 4-6 4-7

4.3 4.3 4.3 4.3 4.3 4.3 4.4 4.4 4.3 4.3 4.4

4.3.7 4.3.7 4.3.7 4.3.7 4.3.7 4.3.7 4.4.8 4.4.8 4.3.7 4.3.7 4.4.8

7.2 7.2 7.2 7.2 7.2 7.2 7.2 7.2 7.2 7.2 7.2

7.4.1 7.4.1 7.4.1 7.4.1 7.4.1 7.4.1 7.4.1 7.4.1 7.4.1 7.4.1 7.4.1

9-1 9-1 9-2 9-2 9-2 9-2 9-3 9-3 9-2 9-2 9-3

10-1 10-9

10-2 10-3 10-4 10-5 10-6 10-7 10-17 10-10 10-11 10-12 10-13 10-14 10-15 10-2 10-3 10-4 10-5 10-6 10-7 10-18 10-10 10-11 10-12 10-13 10-14 10-15 10-2 10-3 10-4 10-5 10-6 10-7 10-17 10-10 10-11 10-12 10-13 10-14 10-15 10-2 10-3 10-4 10-5 10-6 10-7 10-17 10-10 10-11 10-12 10-13 10-14 10-15 10-2 10-3 10-4 10-5 10-6 10-7 10-18 10-10 10-11 10-12 10-13 10-14 10-15 10-10 10-11 10-12 10-13 10-14 10-15 10-18 10-10 10-11 10-12 10-13 10-14 10-15 10-20 10-10 10-11 10-12 10-13 10-14 10-15 10-20 10-10 10-11 10-12 10-13 10-14 10-15 10-19 10-2 10-3 10-4 10-5 10-6 10-7 10-19 10-10 10-11 10-12 10-13 10-14 10-15 10-10 10-11 10-12 10-13 10-14 10-15 10-20

10-21 10-23 10-1 10-9 10-1 10-9 10-1 10-9

40PFL6606D/77 Blockbuster 65213 11-2 65214 40PFL6606D/78 Blockbuster 65213 11-2 65214 40PFL7606D/77 Emmy 11-2 40PFL7606D/78 Emmy 11-2 42PFL8606D/77 Sundance 11-3 42PFL8606D/78 Sundance 11-3 46PFL7606D/77 Emmy 11-2 46PFL7606D/78 Emmy 11-2 47PFL8606D/78 Sundance 11-3 65213 65214 65214 65214 65214 65214 65213 65214 65214

10-21 10-24 10-1 10-9 10-21 10-24 10-9 10-22 10-26 10-9 10-22 10-26 10-9 10-21 10-25 10-9 10-21 10-25 10-1 10-9 10-22 10-27 10-9

2.2

Directions for Use


You can download this information from the following websites: http://www.philips.com/support http://www.p4c.philips.com

2011-Jul-15

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B05 (DDR)

B04 (I/O)

Tuner

PSU

Technical Specifications, Diversity, and Connections 2.3 Connections

Q552.2L LA

2.

EN 3

REAR CONNECTORS
1 2 13 3 3 4
(optional)

SIDE CONNECTORS

10

11 11

BOTTOM REAR CONNECTORS


5 6 7 7 7 8 9

(optional)

12

(3)
(optional)

(2)
HDMI

(1) ARC
19110_051_110421.eps 110716

Figure 2-1 Connection overview Note: The following connector colour abbreviations are used (acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= Grey, Rd= Red, Wh= White, Ye= Yellow. 2.3.1 Rear Connections 1 - CVI: Cinch: Video YPbPr - In, Audio - In Gn - Video Y 1 VPP / 75 ohm Bu - Video Pb 0.7 VPP / 75 ohm Rd - Video Pr 0.7 VPP / 75 ohm Rd - Audio - R 0.5 VRMS / 10 kohm Wh - Audio - L 0.5 VRMS / 10 kohm 2 - Service Connector (UART) 1 - Ground Gnd 2 - UART_TX Transmit 3 - UART_RX Receive 3 - Cinch: Audio - In (VGA/DVI) Rd - Audio R 0.5 VRMS / 10 kohm Wh - Audio L 0.5 VRMS / 10 kohm 4 - AV IN: Cinch: Video CVBS - In, Audio - In Rd - Audio R 0.5 VRMS / 10 kohm Wh - Audio L 0.5 VRMS / 10 kohm Ye - Video CVBS 1 VPP / 75 ohm 13 - Head phone (Output) (optional) Bk - Head phone 32 - 600 ohm / 10 mW 2.3.2 Rear Connections - Bottom 5 - RJ45: Ethernet
12345678

jq jq jq jq jq

10000_025_090121.eps 090121

Figure 2-2 Ethernet connector 1 2 3 4 5 6 7 8 - TD+ - TD- RD+ - CT - CT - RD- GND - GND Transmit signal Transmit signal Receive signal Centre Tap: DC level fixation Centre Tap: DC level fixation Receive signal Gnd Gnd k k j j H H

H k j

jq jq

6 - Cinch: S/PDIF - Out Bk - Coaxial 0.4 - 0.6VPP / 75 ohm 7 - HDMI 2: Digital Video, Digital Audio - In
19 18 1 2

kq

jq jq jq

ot

10000_017_090121.eps 090428

Figure 2-3 HDMI (type A) connector 1 2 3 4 5 6 7 8


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- D2+ - Shield - D2- D1+ - Shield - D1- D0+ - Shield

Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd

j H j j H j j H
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EN 4
9 10 11 12 13 14 15 16 17 18 19 20

2.
- D0- CLK+ - Shield - CLK- Easylink/CEC - n.c. - DDC_SCL - DDC_SDA - Ground - +5V - HPD - Ground

Q552.2L LA
Data channel Data channel Gnd Data channel Control channel DDC clock DDC data Gnd Hot Plug Detect Gnd

Technical Specifications, Diversity, and Connections


j j H j jk j jk H j j H 10 11 12 13 14 15 2.3.3 - Ground Sync - n.c. - DDC_SDA - H-sync - V-sync - DDC_SCL Gnd DDC data 0-5V 0-5V DDC clock H j j j j

Side Connections 10 - SD-Card: Secure Digital Card - In/Out (optional)


14 GND WP 12 11 10

7 - HDMI 1: Digital Video - In, Digital Audio with ARC - In/ Out
19 18 1 2

GND CD 8 7 6 5 4 3 DAT1/IRQ DAT0/D0 GND2 CLOCK VDD GND1 CMD/DI DAT3/CS DAT2/NC

10000_017_090121.eps 090428

Figure 2-4 HDMI (type A) connector 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 - D2+ - Shield - D2- D1+ - Shield - D1- D0+ - Shield - D0- CLK+ - Shield - CLK- Easylink/CEC - ARC - DDC_SCL - DDC_SDA - Ground - +5V - HPD - Ground Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Control channel Audio Return Channel DDC clock DDC data Gnd Hot Plug Detect Gnd j H j j H j j H j j H j jk k j jk H j j H

2 1 9 GND 13

10000_049_100210.eps 100210

Figure 2-6 SD-Card connector 1 2 3 4 5 6 7 8 9 10 11 12 13 14 - DAT3/CS - CMD/DI - GND1 - Vdd - CLOCK - GND2 - DAT0/D0 - DAT1/IRQ - DAT2/NC - CD - GND - WP - GND - GND Signal Signal Gnd Supply Signal Gnd Signal Signal Signal Signal Gnd Signal Gnd Gnd jk k H k k H jk jk jk j H j H H

8 - Aerial - In - - F-type

Coax, 75 ohm

9 - VGA: Video RGB - In


1 6 11 5 10 15

11 - USB2.0

10000_002_090121.eps 090127

10000_022_090121.eps 090121

Figure 2-5 VGA Connector 1 2 3 4 5 6 7 8 9 - Video Red - Video Green - Video Blue - n.c. - Ground - Ground Red - Ground Green - Ground Blue - +5VDC 0.7 VPP / 75 ohm 0.7 VPP / 75 ohm 0.7 VPP / 75 ohm Gnd Gnd Gnd Gnd +5 V j j j H H H H j 1 2 3 4 - +5V - Data (-) - Data (+) - Ground

Figure 2-7 USB (type A) k jk jk H

Gnd

12- HDMI : Digital Video, Digital Audio - In See 7 - HDMI 2: Digital Video, Digital Audio - In

2.4

Chassis Overview
Refer to chapter Block Diagrams for PWB/CBA locations.

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Precautions, Notes, and Abbreviation List

Q552.2L LA

3.

EN 5

3. Precautions, Notes, and Abbreviation List


Index of this chapter: 3.1 Safety Instructions 3.2 Warnings 3.3 Notes 3.4 Abbreviation List Where necessary, measure the waveforms and voltages with (D) and without (E) aerial signal. Measure the voltages in the power supply section both in normal operation (G) and in stand-by (F). These values are indicated by means of the appropriate symbols.

3.1

Safety Instructions
Safety regulations require the following during a repair: Connect the set to the Mains/AC Power via an isolation transformer (> 800 VA). Replace safety components, indicated by the symbol h, only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard. Safety regulations require that after a repair, the set must be returned in its original condition. Pay in particular attention to the following points: Route the wire trees correctly and fix them with the mounted cable clamps. Check the insulation of the Mains/AC Power lead for external damage. Check the strain relief of the Mains/AC Power cord for proper function. Check the electrical DC resistance between the Mains/AC Power plug and the secondary side (only for sets that have a Mains/AC Power isolated power supply): 1. Unplug the Mains/AC Power cord and connect a wire between the two pins of the Mains/AC Power plug. 2. Set the Mains/AC Power switch to the on position (keep the Mains/AC Power cord unplugged!). 3. Measure the resistance value between the pins of the Mains/AC Power plug and the metal shielding of the tuner or the aerial connection on the set. The reading should be between 4.5 M and 12 M. 4. Switch off the set, and remove the wire between the two pins of the Mains/AC Power plug. Check the cabinet for defects, to prevent touching of any inner parts by the customer.

3.3.2

Schematic Notes All resistor values are in ohms, and the value multiplier is often used to indicate the decimal point location (e.g. 2K2 indicates 2.2 k). Resistor values with no multiplier may be indicated with either an E or an R (e.g. 220E or 220R indicates 220 ). All capacitor values are given in micro-farads ( 10-6), nano-farads (n 10-9), or pico-farads (p 10-12). Capacitor values may also use the value multiplier as the decimal point indication (e.g. 2p2 indicates 2.2 pF). An asterisk (*) indicates component usage varies. Refer to the diversity tables for the correct values. The correct component values are listed on the Philips Spare Parts Web Portal.

3.3.3

Spare Parts For the latest spare part overview, consult your Philips Spare Part web portal.

3.3.4

BGA (Ball Grid Array) ICs Introduction For more information on how to handle BGA devices, visit this URL: http://www.atyourservice-magazine.com. Select Magazine, then go to Repair downloads. Here you will find Information on how to deal with BGA-ICs. BGA Temperature Profiles For BGA-ICs, you must use the correct temperature-profile. Where applicable and available, this profile is added to the IC Data Sheet information section in this manual.

3.3.5

Lead-free Soldering Due to lead-free technology some rules have to be respected by the workshop during a repair: Use only lead-free soldering tin. If lead-free solder paste is required, please contact the manufacturer of your soldering equipment. In general, use of solder paste within workshops should be avoided because paste is not easy to store and to handle. Use only adequate solder tools applicable for lead-free soldering tin. The solder tool must be able: To reach a solder-tip temperature of at least 400C. To stabilize the adjusted temperature at the solder-tip. To exchange solder-tips for different applications. Adjust your solder tool so that a temperature of around 360C - 380C is reached and stabilized at the solder joint. Heating time of the solder-joint should not exceed ~ 4 sec. Avoid temperatures above 400C, otherwise wear-out of tips will increase drastically and flux-fluid will be destroyed. To avoid wear-out of tips, switch off unused equipment or reduce heat. Mix of lead-free soldering tin/parts with leaded soldering tin/parts is possible but PHILIPS recommends strongly to avoid mixed regimes. If this cannot be avoided, carefully clear the solder-joint from old tin and re-solder with new tin.

3.2

Warnings
All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD w). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are connected with the same potential as the mass of the set by a wristband with resistance. Keep components and tools also at this same potential. Be careful during measurements in the high voltage section. Never replace modules or other components while the unit is switched on. When you align the set, use plastic rather than metal tools. This will prevent any short circuits and the danger of a circuit becoming unstable.

3.3
3.3.1

Notes
General Measure the voltages and waveforms with regard to the chassis (= tuner) ground (H), or hot ground (I), depending on the tested area of circuitry. The voltages and waveforms shown in the diagrams are indicative. Measure them in the Service Default Mode with a colour bar signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and picture carrier at 475.25 MHz for PAL, or 61.25 MHz for NTSC (channel 3).
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3.3.6

Alternative BOM identification It should be noted that on the European Service website, Alternative BOM is referred to as Design variant.
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EN 6

3.

Q552.2L LA

Precautions, Notes, and Abbreviation List 3.4 Abbreviation List


0/6/12 SCART switch control signal on A/V board. 0 = loop through (AUX to TV), 6 = play 16 : 9 format, 12 = play 4 : 3 format Automatic Aspect Ratio Adaptation: algorithm that adapts aspect ratio to remove horizontal black bars; keeps the original aspect ratio Automatic Channel Installation: algorithm that installs TV channels directly from a cable network by means of a predefined TXT page Analogue to Digital Converter Automatic Frequency Control: control signal used to tune to the correct frequency Automatic Gain Control: algorithm that controls the video input of the feature box Amplitude Modulation Asia Pacific Aspect Ratio: 4 by 3 or 16 by 9 Auto Screen Fit: algorithm that adapts aspect ratio to remove horizontal black bars without discarding video information Advanced Television Systems Committee, the digital TV standard in the USA See Auto TV A hardware and software control system that measures picture content, and adapts image parameters in a dynamic way External Audio Video Audio Video Controller Audio Video Input Processor Monochrome TV system. Sound carrier distance is 5.5 MHz Business Display Solutions (iTV) Board-Level Repair Broadcast Television Standard Committee. Multiplex FM stereo sound system, originating from the USA and used e.g. in LATAM and AP-NTSC countries Blue TeleteXT Centre channel (audio) Consumer Electronics Control bus: remote control bus on HDMI connections Constant Level: audio output to connect with an external amplifier Component Level Repair Computer aided rePair Connected Planet / Copy Protection Customer Service Mode Color Transient Improvement: manipulates steepness of chroma transients Composite Video Blanking and Synchronization Digital to Analogue Converter Dynamic Bass Enhancement: extra low frequency amplification Data Communication Module. Also referred to as System Card or Smartcard (for iTV). See E-DDC Monochrome TV system. Sound carrier distance is 6.5 MHz Dynamic Frame Insertion

The third digit in the serial number (example: AG2B0335000001) indicates the number of the alternative B.O.M. (Bill Of Materials) that has been used for producing the specific TV set. In general, it is possible that the same TV model on the market is produced with e.g. two different types of displays, coming from two different suppliers. This will then result in sets which have the same CTN (Commercial Type Number; e.g. 28PW9515/12) but which have a different B.O.M. number. By looking at the third digit of the serial number, one can identify which B.O.M. is used for the TV set he is working with. If the third digit of the serial number contains the number 1 (example: AG1B033500001), then the TV set has been manufactured according to B.O.M. number 1. If the third digit is a 2 (example: AG2B0335000001), then the set has been produced according to B.O.M. no. 2. This is important for ordering the correct spare parts! For the third digit, the numbers 1...9 and the characters A...Z can be used, so in total: 9 plus 26= 35 different B.O.M.s can be indicated by the third digit of the serial number. Identification: The bottom line of a type plate gives a 14-digit serial number. Digits 1 and 2 refer to the production centre (e.g. SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M. code, digit 4 refers to the Service version change code, digits 5 and 6 refer to the production year, and digits 7 and 8 refer to production week (in example below it is 2010 week 10 / 2010 week 17). The 6 last digits contain the serial number.

AARA

ACI

ADC AFC

AGC

AM AP AR ASF

ATSC

ATV Auto TV

AV AVC AVIP B/G BDS BLR BTSC

10000_053_110228.eps 110228

B-TXT C CEC

Figure 3-1 Serial number (example) 3.3.7 Board Level Repair (BLR) or Component Level Repair (CLR) If a board is defective, consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level. If your repair procedure says the board should be exchanged completely, do not solder on the defective board. Otherwise, it cannot be returned to the O.E.M. supplier for back charging! 3.3.8 Practical Service Precautions It makes sense to avoid exposure to electrical shock. While some sources are expected to have a possible dangerous impact, others of quite high potential are of limited current and are sometimes held in less regard. Always respect voltages. While some may not be dangerous in themselves, they can cause unexpected reactions that are best avoided. Before reaching into a powered TV set, it is best to test the high voltage insulation. It is easy to do, and is a good service precaution.
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CL CLR ComPair CP CSM CTI

CVBS DAC DBE DCM

DDC D/K DFI

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Precautions, Notes, and Abbreviation List


DFU DMR DMSD DNM DNR DRAM DRM DSP DST Directions For Use: owner's manual Digital Media Reader: card reader Digital Multi Standard Decoding Digital Natural Motion Digital Noise Reduction: noise reduction feature of the set Dynamic RAM Digital Rights Management Digital Signal Processing Dealer Service Tool: special remote control designed for service technicians Digital Transmission Content Protection; A protocol for protecting digital audio/video content that is traversing a high speed serial bus, such as IEEE-1394 Digital Video Broadcast - Cable Digital Video Broadcast - Terrestrial Digital Versatile Disc Digital Visual Interface (d= digital only) Enhanced Display Data Channel (VESA standard for communication channel and display). Using E-DDC, the video source can read the EDID information form the display. Extended Display Identification Data (VESA standard) Electrically Erasable and Programmable Read Only Memory Electro Magnetic Interference Electronic Program Guide Erasable Programmable Logic Device Europe EXTernal (source), entering the set by SCART or by cinches (jacks) Full Dual Screen (same as FDW) Full Dual Window (same as FDS) FLASH memory Field Memory or Frequency Modulation Field-Programmable Gate Array Flat TeleVision Giga bits per second Green TeleteXT H_sync to the module High Definition Hard Disk Drive High-bandwidth Digital Content Protection: A key encoded into the HDMI/DVI signal that prevents video data piracy. If a source is HDCP coded and connected via HDMI/DVI without the proper HDCP decoding, the picture is put into a snow vision mode or changed to a low resolution. For normal content distribution the source and the display device must be enabled for HDCP software key decoding. High Definition Multimedia Interface HeadPhone Monochrome TV system. Sound carrier distance is 6.0 MHz Inter IC bus Inter IC Data bus Inter IC Sound bus Intermediate Frequency Infra Red Interrupt Request The ITU Radio communication Sector (ITU-R) is a standards body subcommittee of the International Telecommunication Union relating to radio communication. ITU-656 (a.k.a.
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Q552.2L LA

3.

EN 7

iTV LS

DTCP

DVB-C DVB-T DVD DVI(-d) E-DDC

LATAM LCD LED L/L'

EDID EEPROM EMI EPG EPLD EU EXT FDS FDW FLASH FM FPGA FTV Gb/s G-TXT H HD HDD HDCP

LPL LS LVDS Mbps M/N MHEG

MIPS

MOP MOSFET MPEG MPIF MUTE MTV NC NICAM

NTC NTSC

NVM O/C OSD OAD

HDMI HP I I2 C I2 D I2 S IF IR IRQ ITU-656

OTC P50 PAL

SDI), is a digitized video format used for broadcast grade video. Uncompressed digital component or digital composite signals can be used. The SDI signal is self-synchronizing, uses 8 bit or 10 bit data words, and has a maximum data rate of 270 Mbit/s, with a minimum bandwidth of 135 MHz. Institutional TeleVision; TV sets for hotels, hospitals etc. Last Status; The settings last chosen by the customer and read and stored in RAM or in the NVM. They are called at start-up of the set to configure it according to the customer's preferences Latin America Liquid Crystal Display Light Emitting Diode Monochrome TV system. Sound carrier distance is 6.5 MHz. L' is Band I, L is all bands except for Band I LG.Philips LCD (supplier) Loudspeaker Low Voltage Differential Signalling Mega bits per second Monochrome TV system. Sound carrier distance is 4.5 MHz Part of a set of international standards related to the presentation of multimedia information, standardised by the Multimedia and Hypermedia Experts Group. It is commonly used as a language to describe interactive television services Microprocessor without Interlocked Pipeline-Stages; A RISC-based microprocessor Matrix Output Processor Metal Oxide Silicon Field Effect Transistor, switching device Motion Pictures Experts Group Multi Platform InterFace MUTE Line Mainstream TV: TV-mode with Consumer TV features enabled (iTV) Not Connected Near Instantaneous Compounded Audio Multiplexing. This is a digital sound system, mainly used in Europe. Negative Temperature Coefficient, non-linear resistor National Television Standard Committee. Color system mainly used in North America and Japan. Color carrier NTSC M/N= 3.579545 MHz, NTSC 4.43= 4.433619 MHz (this is a VCR norm, it is not transmitted off-air) Non-Volatile Memory: IC containing TV related data such as alignments Open Circuit On Screen Display Over the Air Download. Method of software upgrade via RF transmission. Upgrade software is broadcasted in TS with TV channels. On screen display Teletext and Control; also called Artistic (SAA5800) Project 50: communication protocol between TV and peripherals Phase Alternating Line. Color system mainly used in West Europe (colour carrier = 4.433619 MHz) and South America (colour carrier
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EN 8

3.

Q552.2L LA

Precautions, Notes, and Abbreviation List


SVGA SVHS SW SWAN SXGA TFT THD TMDS TS TXT TXT-DW UI uP UXGA V VESA VGA VL VSB WYSIWYR 800 600 (4:3) Super Video Home System Software Spatial temporal Weighted Averaging Noise reduction 1280 1024 Thin Film Transistor Total Harmonic Distortion Transmission Minimized Differential Signalling Transport Stream TeleteXT Dual Window with TeleteXT User Interface Microprocessor 1600 1200 (4:3) V-sync to the module Video Electronics Standards Association 640 480 (4:3) Variable Level out: processed audio output toward external amplifier Vestigial Side Band; modulation method What You See Is What You Record: record selection that follows main picture and sound 1280 768 (15:9) Quartz crystal 1024 768 (4:3) Luminance signal Luminance (Y) and Chrominance (C) signal Component video. Luminance and scaled color difference signals (B-Y and R-Y) Component video

PCB PCM PDP PFC PIP PLL

POD

POR PSDL PSL PSLS

PTC PWB PWM QRC QTNR QVCP RAM RGB

RC RC5 / RC6 RESET ROM RSDS R-TXT SAM S/C SCART

SCL SCL-F SD SDA SDA-F SDI SDRAM SECAM

SIF SMPS SoC SOG SOPS SPI

S/PDIF SRAM SRP SSB SSC STB STBY


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PAL M = 3.575612 MHz and PAL N = 3.582056 MHz) Printed Circuit Board (same as PWB) Pulse Code Modulation Plasma Display Panel Power Factor Corrector (or Preconditioner) Picture In Picture Phase Locked Loop. Used for e.g. FST tuning systems. The customer can give directly the desired frequency Point Of Deployment: a removable CAM module, implementing the CA system for a host (e.g. a TV-set) Power On Reset, signal to reset the uP Power Supply for Direct view LED backlight with 2D-dimming Power Supply with integrated LED drivers Power Supply with integrated LED drivers with added Scanning functionality Positive Temperature Coefficient, non-linear resistor Printed Wiring Board (same as PCB) Pulse Width Modulation Quasi Resonant Converter Quality Temporal Noise Reduction Quality Video Composition Processor Random Access Memory Red, Green, and Blue. The primary color signals for TV. By mixing levels of R, G, and B, all colors (Y/C) are reproduced. Remote Control Signal protocol from the remote control receiver RESET signal Read Only Memory Reduced Swing Differential Signalling data interface Red TeleteXT Service Alignment Mode Short Circuit Syndicat des Constructeurs d'Appareils Radiorcepteurs et Tlviseurs Serial Clock I2C CLock Signal on Fast I2C bus Standard Definition Serial Data I2C DAta Signal on Fast I2C bus Serial Digital Interface, see ITU-656 Synchronous DRAM SEequence Couleur Avec Mmoire. Colour system mainly used in France and East Europe. Colour carriers = 4.406250 MHz and 4.250000 MHz Sound Intermediate Frequency Switched Mode Power Supply System on Chip Sync On Green Self Oscillating Power Supply Serial Peripheral Interface bus; a 4wire synchronous serial data link standard Sony Philips Digital InterFace Static RAM Service Reference Protocol Small Signal Board Spread Spectrum Clocking, used to reduce the effects of EMI Set Top Box STand-BY
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WXGA XTAL XGA Y Y/C YPbPr

YUV

Mechanical Instructions

Q552.2L LA

4.

EN 9

4. Mechanical Instructions
Index of this chapter: 4.1 Cable Dressing 4.2 Service Positions 4.3 Assy/Panel Removal Blockbuster/Emmy Styling (xxPFL6/ 7xxx/xx series) 4.4 Assy/Panel Removal Sundance Styling (xxPFL8xxx/xx series) 4.5 Set Re-assembly Notes: Figures below can deviate slightly from the actual situation, due to the different set executions.

4.1

Cable Dressing

Tape (150 m.m.) 2 Tape (80 m.m.) 9 Clamp (11 m.m.) 2


19111_012_110519.eps 110519

Figure 4-1 Cable dressing 32PFL6606D/7x (Blockbuster)

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Mechanical Instructions

Tape (150 m.m.) 4 Tape (80 m.m.) 15 Clamp (11 m.m.) 2


19111_016_110520.eps 110520

Figure 4-2 Cable dressing 32PFL7606D/7x (Emmy)

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Mechanical Instructions

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Tape (150 m.m.) 1 Tape (80 m.m.) 6 Tape (50 m.m.) 2 Clamp (11 m.m.) 2 Stick-on Clamp 1
19111_013_110519.eps 110519

Figure 4-3 Cable dressing 40PFL6606D/7x (Blockbuster)

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Mechanical Instructions

Tape (150 m.m.) 3 Tape (80 m.m.) 16 Tape (50 m.m.) 2 Clamp (11 m.m.) 2 Stick-on Clamp 1
19111_014_110519.eps 110519

Figure 4-4 Cable dressing 40PFL7606D/7x (Emmy)

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19112_100_110712.eps 110712

Figure 4-5 Cable dressing 42PFL8606D/7x (Sundance)

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Mechanical Instructions

Tape (150 m.m.) 5 Tape (80 m.m.) 16 Clamp (11 m.m.) 2 Stick-on Clamp 1
19111_015_110519.eps 110519

Figure 4-6 Cable dressing 46PFL7606D/7x (Emmy)

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19112_101_110712.eps 110712

Figure 4-7 Cable dressing 47PFL8606D/7x (Sundance)

4.2

Service Positions
For easy servicing of a TV set, the set should be put face down on a soft flat surface, foam buffers or other specific workshop tools. Ensure that a stable situation is created to perform measurements and alignments. When using foam bars take care that these always support the cabinet and never only the display. Caution: Failure to follow these guidelines can seriously damage the display! Ensure that ESD safe measures are taken.

Note: it is not necessary to remove the stand while removing the rear cover. 1. Remove all screws of the rear cover. 2. Lift the rear cover from the TV. Make sure that wires and flat coils are not damaged while lifting the rear cover from the set. Additional instructions 40" and 46" sets 40"and 46" sets have a dedicated method to open the bottom catches when removing the rear cover. Refer to Figure 4-8 and Figure 4-9 for details.

4.3

Assy/Panel Removal Blockbuster/Emmy Styling (xxPFL6/7xxx/xx series)


For the 40" and 46" sets, additional instructions (rear cover removal) apply. Refer to subsection Additional instructions 40" and 46" sets. The instructions apply to the 37PFL6606H/12 (Blockbuster European model) - without Ambilight. At time of publishing of this manual, no data was available for the Ambilight models (series xxPFL7606D/xx - Emmy).

1
19100_048_110216.eps 110216

4.3.1

Rear Cover Figure 4-8 Bottom catches 40" and 46" sets -1Warning: Disconnect the mains power cord before you remove the rear cover.

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1
2
19100_049_110216.eps 110216

Figure 4-9 Bottom catches 40" and 46" sets -2It is advised to lay the set with front facing down before executing this operation. 1. Remove all screws from the rear cover. 2. Use a round rod (diameter 2 mm) and insert it in one of the holes [1]. 3. Push the catch located inside the rear cover away by inserting the rod [2] through the hole and lifting the rear cover at the same time. 4. Repeat the same procedure on the other hole. 4.3.2 Speakers Tweeters Each tweeter unit is mounted with two screws. When defective, replace the whole unit. Subwoofer The central subwoofer is located in the centre of the set and is secured by two bosses. When defective, replace the whole unit. 4.3.3 Mains Switch Refer to Figure 4-10 for details. 4.3.5

2
19101_008_110407.eps 110407

Figure 4-11 Main Power Supply 1. Unplug all connectors [1]. 2. Remove the fixation screws [2]. 3. Take the board out. When defective, replace the whole unit. Small Signal Board (SSB) Refer to Figure 4-12 for details.

19101_007_110407.eps 110407

19100_047_110216.eps 110216

Figure 4-12 SSB 1. Unplug all connectors [1]. 2. Remove the fixation screws [2]. 3. Take the board out. When remounting, ensure that the side shielding is positioned correctly. 4.3.6 Keyboard Control, IR & LED Board Refer to Figure 4-13 and Figure 4-14 for details.

Figure 4-10 Mains switch The mains switch is mounted on a plastic subframe and can be removed without removing the subframe. 1. Use a screwdriver and push the switch out of its casing [1]. 2. Unplug the connectors. When defective, replace the whole unit. 4.3.4 Main Power Supply Refer to Figure 4-11 for details.
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1 1

1 1
19101_009_110407.eps 110407

1. Remove the stand [1]. 2. Remove the stand subframe [2]. 3. Remove the screws [3], unplug the connector and take the board out. When defective, replace the whole unit. 4.3.7 LCD Panel Refer to Figure 4-15 to Figure 4-17 for details. 1. Remove the SSB as described earlier. 2. Remove the PSU as described earlier. 3. Remove the tweeters with their subframes and subwoofer as described earlier. 4. Remove the stand and -subframe as described earlier. 5. Remove the cables [1]. 6. Remove the mains switch subframe [2]. 7. Remove the keyboard control-, and IR & LED board as described earlier. 8. Remove all remaining cables and subframes. 9. Use a screwdriver to release the catches [3] that secure the panel. 10. Use a screwdriver to release the catches and remove the sidewings [4] that secure the panel. 11. Take the panel out. Remove the clamps from the panel before sending the panel in for Service.

Figure 4-13 Keyboard control, IR & LED board [1/2]

19101_006_110407.eps 110407

Figure 4-14 Keyboard control, IR & LED board [2/2]

19101_005_110407.eps 110407

Figure 4-15 LCD panel [1/3]

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Mechanical Instructions
When defective, replace the whole unit. Subwoofer The central subwoofer is located in the centre of the set and is secured by two bosses. When defective, replace the whole unit. 4.4.3 Mains Switch Refer to Figure 4-18 for details.

19101_004_110407.eps 110407

Figure 4-16 LCD panel [2/3]

19100_047_110216.eps 110216

Figure 4-18 Mains switch The mains switch is mounted on a plastic subframe and can be removed without removing the subframe. 1. Use a screwdriver and push the switch out of its casing [1]. 2. Unplug the connectors. When defective, replace the whole unit.

4
4.4.4 Main Power Supply Refer to Figure 4-19 for details.

19101_003_110407.eps 110407

Figure 4-17 LCD panel [3/3]

4.4

Assy/Panel Removal Sundance Styling (xxPFL8xxx/xx series)


The instructions apply to the 32PFL7406K/02 - European model.

2 1

4.4.1

Rear Cover Warning: Disconnect the mains power cord before you remove the rear cover. Note: it is not necessary to remove the stand while removing the rear cover. 1. Remove all screws of the rear cover. 2. Lift the rear cover from the TV. Make sure that wires and flat coils are not damaged while lifting the rear cover from the set.

19100_050_110216.eps 110216

Figure 4-19 Main Power Supply 1. Unplug all connectors [1]. 2. Remove the fixation screws [2]. 3. Take the board out. When defective, replace the whole unit. 4.4.5 Small Signal Board (SSB) Refer to Figure 4-20 for details.

4.4.2

Speakers Tweeters Each tweeter unit is mounted with one screw.

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Mechanical Instructions

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3. Remove the screws [3] and take the board out. When defective, replace the whole unit. 4.4.7 Ambilight Units The Ambilight units can be lifted from the subframes without the use of tools. Refer to Figure 4-23 for details.

2
2 2
19100_051_110216.eps 110216

Figure 4-20 SSB 1. Unplug all connectors [1]. 2. Remove the fixation screws [2]. 3. Take the board out. When remounting, ensure that the side shielding is positioned correctly. 4.4.6 Keyboard Control, IR & LED Board Refer to Figure 4-21 and Figure 4-22 for details.
19100_054_110216.eps 110216

Figure 4-23 Ambilight units 1. Unplug the connector [1]. 2. Carefully lift the board [2] and take the board out. When defective, replace the whole unit.

1 1

1 1 1

19100_052_110216.eps 110216

Figure 4-21 Keyboard control, IR & LED board [1/2]

19100_053_110216.eps 110216

Figure 4-22 Keyboard control, IR & LED board [2/2] 1. Remove the stand and the plastic support [1]. 2. Unplug the connector [2].
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4.4.8

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Mechanical Instructions

LCD Panel Refer to Figure 4-24 and Figure 4-25 for details.

2 2 2

1 4 4 2 2 4 4

19100_055_110216.eps 110216

Figure 4-24 LCD panel [1/2] 1. Remove the SSB as described earlier. 2. Remove the PSU as described earlier. 3. Remove the tweeters with their subframes and subwoofer as described earlier. 4. Remove the stand and -support as described earlier. 5. Remove the cables [1]. 6. Remove the stand subframe [2]. 7. Remove the mains switch subframe [3]. 8. Remove the Ambilight units together with their subframes as described earlier. 9. Unplug the connector from the keyboard control-, and IR & LED board as described earlier. 10. Remove all remaining cables and subframes. 11. Use a screwdriver to release the clamps [4] that secure the panel and take the panel out. Remove the clamps from the panel before sending the panel in for Service.

4
19100_056_110217.eps 110217

Figure 4-25 LCD panel [2/2]

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Mechanical Instructions 4.5 Set Re-assembly


To re-assemble the whole set, execute all processes in reverse order. Notes: While re-assembling, make sure that all cables are placed and connected in their original position. Pay special attention not to damage the EMC foams in the set. Ensure that EMC foams are mounted correctly.

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Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding


Index of this chapter: 5.1 Test Points 5.2 Service Modes 5.3 Stepwise Start-up 5.4 Service Tools 5.5 Error Codes 5.6 The Blinking LED Procedure 5.7 Protections 5.8 Fault Finding and Repair Tips 5.9 Software Upgrading All service-unfriendly modes (if present) are disabled, like: (Sleep) timer. Child/parental lock. Picture mute (blue mute or black mute). Automatic volume levelling (AVL). Skip/blank of non-favorite pre-sets.

5.1

Test Points
As most signals are digital, it will be difficult to measure waveforms with a standard oscilloscope. However, several key ICs are capable of generating test patterns, which can be controlled via ComPair. In this way it is possible to determine which part is defective. Perform measurements under the following conditions: Service Default Mode. Video: Color bar signal. Audio: 3 kHz left, 1 kHz right.

How to Activate SDM For this chassis there are two kinds of SDM: an analogue SDM and a digital SDM. Tuning will happen according Table 5-1. Analogue SDM: use the standard RC-transmitter and key in the code 062596, directly followed by the MENU (or HOME) button. Note: It is possible that, together with the SDM, the main menu will appear. To switch it off, push the MENU (or "HOME") button again. Analogue SDM can also be activated by grounding for a moment the solder path on the SSB, with the indication SDM (see Service mode pad). Digital SDM: use the standard RC-transmitter and key in the code 062593, directly followed by the MENU (or "HOME") button. Note: It is possible that, together with the SDM, the main menu will appear. To switch it off, push the MENU (or "HOME") button again.

5.2

Service Modes
Service Default mode (SDM) and Service Alignment Mode (SAM) offers several features for the service technician, while the Customer Service Mode (CSM) is used for communication between the call centre and the customer.

SDM
This chassis also offers the option of using ComPair, a hardware interface between a computer and the TV chassis. It offers the abilities of structured troubleshooting, error code reading, and software version read-out for all chassis. (see also section 5.4.1 ComPair). Note: For the new model range, a new remote control (RC) is used with some renamed buttons. This has an impact on the activation of the Service modes. For instance the old MENU button is now called HOME (or is indicated by a house icon). 5.2.1 Service Default Mode (SDM) Purpose To create a pre-defined setting, to get the same measurement results as given in this manual. To override SW protections detected by stand-by processor and make the TV start up to the step just before protection (a sort of automatic stepwise start-up). See section 5.3 Stepwise Start-up. To start the blinking LED procedure where only LAYER 2 errors are displayed. (see also section 5.5 Error Codes). Specifications 5.2.2 Table 5-1 SDM default settings Default system PAL B/G Purpose To perform (software) alignments. To change option settings. To easily identify the used software version. To view operation hours. To display (or clear) the error code buffer. How to Activate SAM Via a standard RC transmitter: Key in the code 062596 directly followed by the INFO or OK button. After activating SAM with this method a service warning will appear on the screen, continue by pressing the OK button on the RC.
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19100_057_110217.eps 110217

Figure 5-1 Service mode pad After activating this mode, SDM will appear in the upper right corner of the screen (when a picture is available). How to Navigate When the MENU (or HOME) button is pressed on the RC transmitter, the TV set will toggle between the SDM and the normal user menu. How to Exit SDM Use one of the following methods: Switch the set to STAND-BY via the RC-transmitter. Via a standard customer RC-transmitter: key in 00sequence. Service Alignment Mode (SAM)

Region Europe, AP(PAL/Multi) Europe, AP DVB-T

Freq. (MHz) 475.25

DVB-T 546.00 PID Video: 0B 06 PID PCR: 0B 06 PID Audio: 0B 07


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Service Modes, Error Codes, and Fault Finding


Contents of SAM Hardware Info. A. SW Version. Displays the software version of the main software (example: Q555X-1.2.3.4 = AAAAB_X.Y.W.Z). AAAA= the chassis name. B= the SW branch version. This is a sequential number (this is no longer the region indication, as the software is now multi-region). X.Y.W.Z= the software version, where X is the main version number (different numbers are not compatible with one another) and Y.W.Z is the sub version number (a higher number is always compatible with a lower number). B. STBY PROC Version. Displays the software version of the stand-by processor. C. Production Code. Displays the production code of the TV, this is the serial number as printed on the back of the TV set. Note that if an NVM is replaced or is initialized after corruption, this production code has to be re-written to NVM. ComPair will foresee in a possibility to do this. Operation Hours. Displays the accumulated total of operation hours (not the stand-by hours). Every time the TV is switched on/off, 0.5 hours is added to this number. Errors (followed by maximum 10 errors). The most recent error is displayed at the upper left (for an error explanation see section 5.5 Error Codes). Reset Error Buffer. When cursor right (or OK button) pressed here, followed by the OK button, the error buffer is reset. Alignments. This will activate the ALIGNMENTS submenu. See Chapter 6. Alignments. Dealer Options. Extra features for the dealers. Options. Extra features for Service. For more info regarding option codes, see chapter 6. Alignments. Note that if the option code numbers are changed, these have to be confirmed with pressing the OK button before the options are stored, otherwise changes will be lost. Initialize NVM. The moment the processor recognizes a corrupted NVM, the initialize NVM line will be highlighted. Now, two things can be done (dependent of the service instructions at that moment): Save the content of the NVM via ComPair for development analysis, before initializing. This will give the Service department an extra possibility for diagnosis (e.g. when Development asks for this). Initialize the NVM. Note: When the NVM is corrupted, or replaced, there is a high possibility that no picture appears because the display code is not correct. So, before initializing the NVM via the SAM, a picture is necessary and therefore the correct display option has to be entered. Refer to Chapter 6. Alignments for details. To adapt this option, its advised to use ComPair (the correct values for the options can be found in Chapter 6. Alignments) or a method via a standard RC (described below). Changing the display option via a standard RC: Key in the code 062598 directly followed by the MENU (or "HOME") button and XXX (where XXX is the 3 digit decimal display code as mentioned on the sticker in the set). Make sure to key in all three digits, also the leading zeros. If the above action is successful, the front LED will go out as an indication that the RC sequence was correct. After the display option is changed in the NVM, the TV will go to the Stand-by mode. If the NVM was corrupted or empty before this action, it will be initialized first (loaded with default values). This initializing can take up to 20 seconds.

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Display Option Code

39mm

PHILIPS
27mm

040

MODEL: 32PF9968/10
PROD.SERIAL NO: AG 1A0620 000001

(CTN Sticker)

10000_038_090121.eps 090819

Figure 5-2 Location of Display Option Code sticker Store - go right. All options and alignments are stored when pressing cursor right (or the OK button) and then the OK-button. Operation hours display. Displays the accumulated total of operation hours of the screen itself. In case of a display replacement, reset to 0 or to the consumed operation hours of the spare display. SW Maintenance. SW Events. In case of specific software problems, the development department can ask for this info. HW Events. In case of specific software problems, the development department can ask for this info : - Event 26: refers to a power dip, this is logged after the TV set reboots due to a power dip. - Event 17: refers to the power OK status, sensed even before the 3 x retry to generate the error code. Test settings. For development purposes only. Development file versions. Not useful for Service purposes, this information is only used by the development department. Upload to USB. To upload several settings from the TV to an USB stick, which is connected to the SSB. The items are Channel list, Personal settings, Option codes, Alignments, Identification data (includes the set type and prod code + all 12NC like SSB, display, boards), History list. The All item supports to upload all several items at once. First a directory repair\ has to be created in the root of the USB stick. To upload the settings, select each item separately, press cursor right (or the OK button), confirm with OK and wait until the message Done appears. In case the download to the USB stick was not successful, Failure will be displayed. In this case, check if the USB stick is connected properly and if the directory repair is present in the root of the USB stick. Now the settings are stored onto the USB stick and can be used to download into another TV or other SSB. Uploading is of course only possible if the software is running and preferably a picture is available. This method is created to be able to save the customers TV settings and to store them into another SSB. Download from USB. To download several settings from the USB stick to the TV, same way of working needs to be followed as described in Upload to USB. To make sure that the download of the channel list from USB to the TV is executed properly, it is necessary to restart the TV and tune to a valid preset if necessary. The All item supports to download all several items at once. NVM editor. For NET TV the set type number must be entered correctly. Also the production code (AG code) can be entered here via the RC-transmitter. Correct data can be found on the side/rear sticker.

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Service Modes, Error Codes, and Fault Finding


How to Navigate By means of the CURSOR-DOWN/UP knob on the RCtransmitter, can be navigated through the menus. Contents of CSM The contents are reduced to 3 pages: General, Software versions and Quality items. The group names itself are not shown anywhere in the CSM menu. General Set Type. This information is very helpful for a helpdesk/ workshop as reference for further diagnosis. In this way, it is not necessary for the customer to look at the rear of the TV-set. Note that if an NVM is replaced or is initialized after corruption, this set type has to be re-written to NVM. ComPair will foresee in a possibility to do this. The update can also be done via the NVM editor available in SAM. Production Code. Displays the production code (the serial number) of the TV. Note that if an NVM is replaced or is initialized after corruption, this production code has to be re-written to NVM. ComPair will foresee in a possibility to do this. The update can also be done via the NVM editor available in SAM. Installed date. Indicates the date of the first installation of the TV. This date is acquired via time extraction. Options 1. Gives the option codes of option group 1 as set in SAM (Service Alignment Mode). Options 2. Gives the option codes of option group 2 as set in SAM (Service Alignment Mode). 12NC SSB. Gives an identification of the SSB as stored in NVM. Note that if an NVM is replaced or is initialized after corruption, this identification number has to be re-written to NVM. ComPair will foresee in a possibility to do this. This identification number is the 12nc number of the SSB. 12NC display. Shows the 12NC of the display. 12NC supply. Shows the 12NC of the power supply. 12NC 200Hz board. Shows the 12NC of the 200Hz Panel (when present). 12NC AV PIP. Shows the 12NC of the AV PIP board (when present). Software versions Current main SW. Displays the build-in main software version. In case of field problems related to software, software can be upgraded. As this software is consumer upgradeable, it will also be published on the Internet. Example: Q55xx1.2.3.4 Stand-by SW. Displays the build-in stand-by processor software version. Upgrading this software will be possible via ComPair or via USB (see section 5.9 Software Upgrading). Example: STDBY_83.84.0.0. e-UM version. Displays the electronic user manual SWversion (12NC version number). Most significant number here is the last digit. AV PIP software. 3D dongle software version. Quality items Signal quality. Bad / average /good (not for DVB-S). Ethernet MAC address. Displays the MAC address present in the SSB. Wireless MAC address. Displays the wireless MAC address to support the Wi-Fi functionality. BDS key. Indicates if the set is in the BDS status. CI module. Displays status if the common interface module is detected. CI + protected service. Yes/No. Event counter : S : 000X 0000(number of software recoveries : SW EVENT-LOG #(reboots) S : 0000 000X (number of software events : SW EVENTLOG #(events) H : 000X 0000(number of hardware errors)
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How to Navigate In SAM, the menu items can be selected with the CURSOR UP/DOWN key on the RC-transmitter. The selected item will be highlighted. When not all menu items fit on the screen, move the CURSOR UP/DOWN key to display the next/previous menu items. With the CURSOR LEFT/RIGHT keys, it is possible to: (De) activate the selected menu item. (De) activate the selected sub menu. With the OK key, it is possible to activate the selected action. How to Exit SAM Use one of the following methods: Switch the TV set to STAND-BY via the RC-transmitter. Via a standard RC-transmitter, key in 00 sequence, or select the BACK key. 5.2.3 Customer Service Mode (CSM) Purpose When a customer is having problems with his TV-set, he can call his dealer or the Customer Helpdesk. The service technician can then ask the customer to activate the CSM, in order to identify the status of the set. Now, the service technician can judge the severity of the complaint. In many cases, he can advise the customer how to solve the problem, or he can decide if it is necessary to visit the customer. The CSM is a read only mode; therefore, modifications in this mode are not possible. When in this chassis CSM is activated, a test pattern will be displayed during 5 seconds (1 second Blue, 1 second Green and 1 second Red, then again 1 second Blue and 1 second Green). This test pattern is generated by the PNX51X0 (located on the 200Hz board as part of the display). So if this test pattern is shown, it could be determined that the back end video chain (PNX51X0 and display) is working.For TV sets without the PNX51X0 inside, every menu from CSM will be used as check for the back end chain video. When CSM is activated and there is a USB stick connected to the TV set, the software will dump the CSM content to the USB stick. The file (CSM_model number_serial number.txt) will be saved in the root of the USB stick. This info can be handy if no information is displayed. When in CSM mode (and a USB stick connected), pressing OK will create an extended CSM dump file on the USB stick. This file (Extended_CSM_model number_serial number.txt) contains: The normal CSM dump information, All items (from SAM load to USB, but in readable format), Operating hours, Error codes, SW/HW event logs. To have fast feedback from the field, a flashdump can be requested by development. When in CSM, push the red button and key in serial digits 2679 (same keys to form the word COPY with a cellphone). A file Dump_model number_serial number.bin will be written on the connected USB device. This can take 1/2 minute, depending on the quantity of data that needs to be dumped. Also when CSM is activated, the LAYER 1 error is displayed via blinking LED. Only the latest error is displayed (see also section 5.5 Error Codes). How to Activate CSM Key in the code 123654 via the standard RC transmitter. Note: Activation of the CSM is only possible if there is no (user) menu on the screen!
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Service Modes, Error Codes, and Fault Finding


H : 0000 000X (number of hardware events : SW EVENTLOG #(events). How to Exit CSM Press MENU (or "HOME") / Back key on the RC-transmitter.

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EN 25

in this mode with a faulty FET 7U0X is done, you can destroy all ICs supplied by the +1V8 and +1v1, due to overvoltage (12V on XVX-line). It is recommended to measure first the FET 7U0X or others FETs on shortcircuit before activating SDM via the service pads.

5.3

Stepwise Start-up
When the TV is in a protection state due to an error detected by stand-by software (error blinking is displayed) and SDM is activated via shortcutting the SDM solder path on the SSB, the TV starts up until it reaches the situation just before protection. So, this is a kind of automatic stepwise start-up. In combination with the start-up diagrams below, you can see which supplies are present at a certain moment. Caution: in case the start-up The abbreviations SP and MP in the figures stand for: SP: protection or error detected by the Stand-by Processor. MP: protection or error detected by the MIPS Main Processor.

Mains off

Mains on

- WakeUp requested - Acquisition needed - Tact switch pushed

WakeUp requested

St by

- stby requested and no data Acquisition required

Semi St by

Active
- St by requested - tact SW pushed

Tact switch pushed WakeUp requested (SDM) GoToProtection GoToProtection

Hibernate

- Tact switch pushed - last status is hibernate after mains ON

Protection

18770_250_100216.eps 100402

Figure 5-3 Transition diagram

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5.

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Service Modes, Error Codes, and Fault Finding

Off
Mains is applied

Stand by or Protection

Standby Supply starts running. All standby supply voltages become available.

st-by P resets

Initialise I/O pins of the st-by P: - Switch reset-AVC LOW (reset state) - Switch reset-system LOW (reset state) - Switch reset-Ethernet LOW (reset state) - Switch reset-USB LOW (reset state) - Switch reset-DVBs LOW (reset state) - keep Audio-reset and Audio-Mute-Up HIGH

If the protection state was left by short circuiting the SDM pins, detection of a protection condition during startup will stall the startup. Protection conditions in a playing set will be ignored. The protection mode will not be entered.

start keyboard scanning, RC detection. Wake up reasons are off.

- Switch Audio-Reset high. It is low in the standby mode if the standby mode lasted longer than 10s.

Switch ON Platform and display supply by switching LOW the Standby line.

+12V, +24Vs, AL and Bolt-on power is switched on, followed by the +1V2 DCDC converter Detect2 is moved to an interrupt. To be checked if the detection on interrupt base is feasible or not or if we should stick to the standard 40ms interval.

Detect2 high received within 2 seconds?

No

12V error: Layer1: 3 Layer2: 16

Yes

Enter protection

Enable the DCDC converters (ENABLE-3V3n LOW)

Wait 50ms

Enable the supply detection algorithm

Set IC slave address of Standby P to (A0h)

Detect EJTAG debug probe (pulling pin of the probe interface to ground by inserting EJTAG probe)

An EJTAG probe (e.g. WindPower ICE probe) can be connected for Linux Kernel debugging purposes.

EJTAG probe connected ?

Yes

No No

No

Cold boot?

Yes Release AVC system reset Feed warm boot script Release AVC system reset Feed cold boot script Release AVC system reset Feed initializing boot script disable alive mechanism

18770_251_100216.eps 100216

Figure 5-4 Off to Semi Stand-by flowchart (part 1)

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Service Modes, Error Codes, and Fault Finding

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EN 27

Reset-system is switched HIGH by the AVC at the end of the bootscript No AVC releases Reset-Ethernet, Reset-USB and Reset-DVBs when the end of the AVC bootscript is detected

Reset-system is switched HIGH by the AVC at the end of the bootscript

This cannot be done through the bootscript, the I/O is on the standby P

AVC releases Reset-Ethernet, Reset-USB and Reset-DVBs when the end of the AVC bootscript is detected

Timing need to be updated if more mature info is available.

Reset-Audio and Audio-Mute-Up are switched by MIPS code later on in the startup process

Reset-Audio and Audio-Mute-Up are switched by MIPS code later on in the startup process

No

Bootscript ready in 1250 ms?

Yes Set IC slave address of Standby P to (60h)

RPC start (comm. protocol) Timing needs to be updated if more mature info is available.

No Code = Layer1: 2 Layer2: 15

Flash to Ram image transfer succeeded within 30s? Yes

Switch AVC PNX85500 in reset (active low)

Code = Layer1: 2 Layer2: 53

No

SW initialization succeeded within 20s?

Timing needs to be updated if more mature info is available.

Wait 10ms

Yes

Enable Alive check mechanism Disable all supply related protections and switch off the +3V3 +5V DC/DC converter. MIPS reads the wake up reason from standby P. Wait 5ms Startup screen shall only be visible when there is a coldboot to an active state end situation. The startup screen shall not be visible when waking up for reboot reasons or waking up to semistandby conditions or waking up to enter Hibernate mode.. Wait until AVC starts to communicate

switch off the remaining DC/DC converters

Wake up reason coldboot & not semistandby? yes

3-th try?

Switch Standby I/O line high and wait 4 seconds

Yes Blink Code as error code

Startup screen cfg file present? yes

The first time after the option turn on of the startup screen or when the set is virgin, the cfg file is not present and hence the startup screen will not be shown.

200Hz set?

yes

Enter protection
No

No

85500 sends out startup screen

85500 sends out startup screen

85500 starts up the display. No To keep this flowchart readable, the exact display turn on description is not copied here. Please see the Semi-standby to On description for the detailed display startup During the complete display time of the Startup screen, the preheat condition of sequence. 100% PWM is valid. Startup screen visible

200Hz Tcon has started up the display.

85500 requests Lamp on

Startup screen visible

Initialize audio initialize tuner and channel decoders Initialize source selection Initialize video processing ICs

initialize AutoTV by triggering CHS AutoTV Init interface Initialize Ambilight with Lights off.

Semi-Standby
18770_252_100216.eps 100216

Figure 5-5 Off to Semi Stand-by flowchart (part 2)

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Service Modes, Error Codes, and Fault Finding

Constraints taken into account:


- Display may only be started when valid LVDS output clock can be delivered by the AVC. - To have a reliable operation of the EEFL backlight, the backlight should be driven with a maximum PWM duty cycle during the first seconds. Only after this first one or two seconds, the PWM may be set to the required output level (Note that the PWM output should be present before the backlight is switched on). To minimize the artefacts, the picture should only be unblanked after these first seconds.

The assumption here is that a fast toggle (<2s) can only happen during ON->SEMI ->ON. In these states, the AVC is still active and can provide the 2s delay. A transition ON->SEMI->STBY->SEMI->ON cannot be made in less than 2s, because the standby state will be maintained for at least 4s.

Semi Standby
Wait until previous on-state is left more than 2 seconds ago. (to prevent LCD display problems)

CPipe already generates a valid output clock in the semi-standby state: display startup can start immediately when leaving the semi-standby state.

Assert RGB video blanking and audio mute

Display already on? (splash screen) No

The exact timings to switch on the display (LVDS delay, lamp delay) are defined in the display file.

Switch on the display power by switching LCD-PWR-ON low Yes Wait x ms Switch on LVDS output in the 85500 Delay Lamp-on with the sum of the LVDS delay and the Lamp delay indicated in the display file Initialize audio and video processing IC's and functions according needed use case.

Switch off the dimming backlight feature, set the BOOST control to nominal and make sure PWM output is set to maximum allowed PWM

Switch on LCD backlight (Lamp-ON)

Start POK line detection algorithm

return

Wait until valid and stable audio and video, corresponding to the requested output is delivered by the AVC AND the backlight has been switched on for at least the time which is indicated in the display file as preheat time.

Switch Audio-Reset low and wait 5ms A LED set does not normally need a preheat time. The preheat remains present but is set to zero in the display file.

Release audio mute and wait 100ms before any other audio handling is done (e.g. volume change)

The higher level requirement is that audio and video should be demuted without transient effects and that the audio should be demuted maximum 1s before or at the same time as the unblanking of the video.

Restore dimming backlight feature, PWM and BOOST output and unblank the video.

Switch on the Ambilight functionality according the last status settings.

Startup screen Option and Installation setting Photoscreen ON? Yes Display cfg file present and up to date, according correct display option? No No Yes Prepare Start screen Display config file and copy to Flash

Active
18770_253_100216.eps 100216

Figure 5-6 Semi Stand-by to Active flowchart (EEFL or LED backlight 50/100 Hz only)

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Service Modes, Error Codes, and Fault Finding

Q552.2L LA

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EN 29

The assumption here is that a fast toggle (<2s) can only happen during ON->SEMI ->ON. In these states, the AVC is still active and can provide the 2s delay. If the transition ON->SEMI>STBY->SEMI->ON can be made in less than 2s, we have to delay the semi -> stby transition until the requirement is met.

Semi Standby
Wait until previous on-state is left more than 2 seconds ago. (to prevent LCD display problems)

Assert RGB video blanking and audio mute

There is no need to define the display timings since the timing implementation is part of the Tcon.

Backlight already on? (splash screen) Yes No Request Tcon to Switch on the backlight in a direct LED or set Lamp-on I/O line in case of a side LED Initialize audio and video processing IC's and functions according needed use case.

Start POK line detection algorithm Wait until valid and stable audio and video, corresponding to the requested output is delivered by the AVC. return Switch Audio-Reset low and wait 5ms

The higher level requirement is that audio and video should be demuted without transient effects and that the audio should be demuted maximum 1s before or at the same time as the unblanking of the video.

Release audio mute and wait 100ms before any other audio handling is done (e.g. volume change)

unblank the video.

Switch on the Ambilight functionality according the last status settings.

Startup screen Option and Installation setting Photoscreen ON? Yes Display cfg file present and up to date, according correct display option? No No Yes Prepare Start screen Display config file and copy to Flash

Active
18770_254_100216.eps 100216

Figure 5-7 Semi Stand-by to Active flowchart (LED backlight 200 Hz)

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Service Modes, Error Codes, and Fault Finding

Active
Mute all sound outputs via softmute

Wait 100ms

Set main amplifier mute (I/O: audio-mute)

Force ext audio outputs to ground (I/O: audio reset) And wait 5ms

switch off Ambilight

Wait until Ambilight has faded out: Output power Observer should be zero

Switch off POK line detection algorithm

switch off LCD backlight (I/O or IC)

Mute all video outputs

Yes

200Hz set?

No

Wait x ms (display file) Instruct 200Hz Tcon to turn off the display

Switch off LVDS output in 85500

Wait x ms

The exact timings to switch off the display (LVDS delay, lamp delay) are defined in the display file.

Switch off the display power by switching LCD-PWR-ON high

Semi Standby
18770_255_100216.eps 100216

Figure 5-8 Active to Semi Stand-by flowchart

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Service Modes, Error Codes, and Fault Finding

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EN 31

Semi Stand by

If ambientlight functionality was used in semi-standby (lampadaire mode), switch off ambient light (see CHS ambilight)

Delay transition until ramping down of ambient light is finished. *)

*) If this is not performed and the set is switched to standby when the switch off of the ambilights is still ongoing, the lights will switch off abruptly when the supply is cut.

transfer Wake up reasons to the Stand by P.

Switch Memories to self-refresh (this creates a more stable condition when switching off the power).

Switch AVC system in reset state (reset-system and reset-AVC lines) Switch reset-USB, Reset-Ethernet and Reset-DVBs LOW

Wait 10ms

Disable all supply related protections and switch off the DC/DC converters (ENABLE-3V3n)

Wait 5ms

Switch OFF all supplies by switching HIGH the Standby I/O line

Important remarks: release reset audio 10 sec after entering standby to save power Also here, the standby state has to be maintained for at least 4s before starting another state transition.

Stand by
18770_256_100216.eps 100216

Figure 5-9 Semi Stand-by to Stand-by flowchart

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EN 32 5.4
5.4.1

5.

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Service Modes, Error Codes, and Fault Finding 5.5


5.5.1

Service Tools
ComPair Introduction ComPair (Computer Aided Repair) is a Service tool for Philips Consumer Electronics products. and offers the following: 1. ComPair helps to quickly get an understanding on how to repair the chassis in a short and effective way. 2. ComPair allows very detailed diagnostics and is therefore capable of accurately indicating problem areas. No knowledge on I2C or UART commands is necessary, because ComPair takes care of this. 3. ComPair speeds up the repair time since it can automatically communicate with the chassis (when the P is working) and all repair information is directly available. 4. ComPair features TV software up possibilities. Specifications ComPair consists of a Windows based fault finding program and an interface box between PC and the (defective) product. The ComPair II interface box is connected to the PC via an USB cable. For the TV chassis, the ComPair interface box and the TV communicate via a bi-directional cable via the service connector(s). The ComPair fault finding program is able to determine the problem of the defective television, by a combination of automatic diagnostics and an interactive question/answer procedure. How to Connect This is described in the chassis fault finding database in ComPair.
TO TV
TO UART SERVICE CONNECTOR TO I2C SERVICE CONNECTOR TO UART SERVICE CONNECTOR

Error Codes
Introduction The error code buffer contains all detected errors since the last time the buffer was erased. The buffer is written from left to right, new errors are logged at the left side, and all other errors shift one position to the right. When an error occurs, it is added to the list of errors, provided the list is not full. When an error occurs and the error buffer is full, then the new error is not added, and the error buffer stays intact (history is maintained). To prevent that an occasional error stays in the list forever, the error is removed from the list after more than 50 hrs. of operation. When multiple errors occur (errors occurred within a short time span), there is a high probability that there is some relation between them. New in this chassis is the way errors can be displayed: If no errors are there, the LED should not blink at all in CSM or SDM. No spacer must be displayed as well. There is a simple blinking LED procedure for board level repair (home repair) so called LAYER 1 errors next to the existing errors which are LAYER 2 errors (see Table 5-2). LAYER 1 errors are one digit errors. LAYER 2 errors are 2 digit errors. In protection mode. From consumer mode: LAYER 1. From SDM mode: LAYER 2. Fatal errors, if I2C bus is blocked and the set reboots, CSM and SAM are not selectable. From consumer mode: LAYER 1. From SDM mode: LAYER 2. In CSM mode. When entering CSM: error LAYER 1 will be displayed by blinking LED. Only the latest error is shown. In SDM mode. When SDM is entered via Remote Control code or the hardware pins, LAYER 2 is displayed via blinking LED. Error display on screen. In CSM no error codes are displayed on screen. In SAM the complete error list is shown.

ComPair II RC in RC out

Multi function

Optional Power Link/ Mode Switch Activity

I2C

RS232 /UART

PC

ComPair II Developed by Philips Brugge Optional power 5V DC

HDMI I2C only

10000_036_090121.eps 091118

Figure 5-10 ComPair II interface connection Caution: It is compulsory to connect the TV to the PC as shown in the picture above (with the ComPair interface in between), as the ComPair interface acts as a level shifter. If one connects the TV directly to the PC (via UART), ICs can be blown! How to Order ComPair II order codes: ComPair II interface: 3122 785 91020. Software is available via the Philips Service web portal. ComPair UART interface cable for Q55x.x. (using 3.5 mm Mini Jack connector): 3138 188 75051. Note: When you encounter problems, contact your local support desk.
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Basically there are three kinds of errors: Errors detected by the Stand-by software which lead to protection. These errors will always lead to protection and an automatic start of the blinking LED LAYER 1 error. (see section 5.6 The Blinking LED Procedure). Errors detected by the Stand-by software which not lead to protection. In this case the front LED should blink the involved error. See also section 5.5 Error Codes, 5.5.4 Error Buffer. Note that it can take up several minutes before the TV starts blinking the error (e.g. LAYER 1 error = 2, LAYER 2 error = 15 or 53). Errors detected by main software (MIPS). In this case the error will be logged into the error buffer and can be read out via ComPair, via blinking LED method LAYER 1-2 error, or in case picture is visible, via SAM. 5.5.2 How to Read the Error Buffer Use one of the following methods: On screen via the SAM (only when a picture is visible). E.g.: 00 00 00 00 00: No errors detected 23 00 00 00 00: Error code 23 is the last and only detected error. 37 23 00 00 00: Error code 23 was first detected and error code 37 is the last detected error. Note that no protection errors can be logged in the error buffer.

Service Modes, Error Codes, and Fault Finding


5.5.3 Via the blinking LED procedure. See section 5.5.3 How to Clear the Error Buffer. Via ComPair.

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How to Clear the Error Buffer Use one of the following methods: By activation of the RESET ERROR BUFFER command in the SAM menu. If the content of the error buffer has not changed for 50+ hours, it resets automatically.

content, as this history can give significant information). This to ensure that old error codes are no longer present. If possible, check the entire contents of the error buffer. In some situations, an error code is only the result of another error code and not the actual cause (e.g. a fault in the protection detection circuitry can also lead to a protection). There are several mechanisms of error detection: Via error bits in the status registers of ICs. Via polling on I/O pins going to the stand-by processor. Via sensing of analog values on the stand-by processor or the PNX8550. Via a not acknowledge of an I2C communication. Take notice that some errors need several minutes before they start blinking or before they will be logged. So in case of problems wait 2 minutes from start-up onwards, and then check if the front LED is blinking or if an error is logged.

5.5.4

Error Buffer In case of non-intermittent faults, clear the error buffer before starting to repair (before clearing the buffer, write down the Table 5-2 Error code overview

Description I2C3 I2C2 I2C4 12V Inverter or display supply PNX51X0 HDMI mux I2C switch Channel dec DVB-S Lnb controller Tuner Main nvm Tuner DVB-S T sensor SSB/set T sensor LED driver/Tcon Display

Monitored Error/ Error Buffer/ Layer 1 Layer 2 by Prot Blinking LED Device 2 2 2 3 3 2/9 2 2 2 2 2 2 2 2 7 5 13 14 18 15 16 17 21 23 24 28 31 34 35 36 42 42 53 64 MIPS MIPS MIPS Stby P Stby P MIPS MIPS MIPS MIPS MIPS MIPS MIPS MIPS MIPS MIPS MIPS Stby P MIPS E E E P P E E E E E E E E E E E P E BL / EB BL / EB BL / EB BL BL EB EB EB EB EB EB EB EB EB EB EB BL BL / EB SSB SSB SSB PNX8550 / / PNX51X0 Sil9x87A PCA9540 STV0903 LNBH23 DTT 71300 STM24C64 STV6110 LM 75 LM 75 PNX8550 Altera

Defective Board SSB SSB SSB SSB Supply Supply 200 Hz board SSB SSB SSB SSB SSB SSB SSB T sensor T sensor SSB Display

PNX doesnt boot (HW cause) 2

PNX doesnt boot (SW cause) 2

Extra Info Rebooting. When a TV is constantly rebooting due to internal problems, most of the time no errors will be logged or blinked. This rebooting can be recognized via a ComPair interface and Hyperterminal (for Hyperterminal settings, see section 5.8 Fault Finding and Repair Tips, 5.8.7 Logging). Its shown that the loggings which are generated by the main software keep continuing. In this case diagnose has to be done via ComPair. Error 13 (I2C bus 3, SSB bus blocked). Current situation: when this error occurs, the TV will constantly reboot due to the blocked bus. The best way for further diagnosis here, is to use ComPair. Error 14 (I2C bus 2, TV set bus blocked). Current situation: when this error occurs, the TV will constantly reboot due to the blocked bus. The best way for further diagnosis here, is to use ComPair. Error 18 (I2C bus 4, Tuner bus blocked). In case this bus is blocked, short the SDM solder paths on the SSB during startup, LAYER error 2 = 18 will be blinked. Error 15 (PNX8550 doesnt boot). Indicates that the main processor was not able to read his bootscript. This error will point to a hardware problem around the PNX8550 (supplies not OK, PNX 8550 completely dead, I2C link between PNX and Stand-by Processor broken, etc...). When error 15 occurs it is also possible that I2C1 bus is blocked (NVM). I2C1 can be indicated in the schematics as follows: SCL-UP-MIPS, SDA-UP-MIPS.

Other root causes for this error can be due to hardware problems regarding the DDRs and the bootscript reading from the PNX8550. Error 16 (12V). This voltage is made in the power supply and results in protection (LAYER 1 error = 3) in case of absence. When SDM is activated we see blinking LED LAYER 2 error = 16. Error 17 (Invertor or Display Supply). Here the status of the Power OK is checked by software, no protection will occur during failure of the invertor or display supply (no picture), only error logging. LED blinking of LAYER 1 error = 3 in CSM, in SDM this gives LAYER 2 error = 17. Error 21 (PNX51X0). When there is no I2C communication towards the PNX51X0 after start-up, LAYER 2 error = 21 will be logged and displayed via the blinking LED procedure if SDM is switched on. This device is located on the 200 Hz panel from the display. Error 23 (HDMI). When there is no I2C communication towards the HDMI mux after start-up, LAYER 2 error = 23 will be logged and displayed via the blinking LED procedure if SDM is switched on. Error 24 (I2C switch). When there is no I2C communication towards the I2C switch, LAYER 2 error = 24 will be logged and displayed via the blinking LED procedure when SDM is switched on. Remark: this only works for TV sets with an I2C controlled screen included. Error 28 (Channel dec DVB-S). When there is no I2C communication towards the DVB-S channel decoder,

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Service Modes, Error Codes, and Fault Finding


2. 3. 4. 5. 6. 5.6.2 Two short blinks of 250 ms followed by a pause of 3 s Eight short blinks followed by a pause of 3 s Six short blinks followed by a pause of 3 s One long blink of 3 s to finish the sequence (spacer). The sequence starts again.

LAYER 2 error = 28 will be logged and displayed via the blinking LED procedure if SDM is switched on. Error 31 (Lnb controller). When there is no I2C communication towards this device, LAYER 2 error = 31 will be logged and displayed via the blinking LED procedure if SDM is activated. Error 34 (Tuner). When there is no I2C communication towards the tuner during start-up, LAYER 2 error = 34 will be logged and displayed via the blinking LED procedure when SDM is switched on. Error 35 (main NVM). When there is no I2C communication towards the main NVM during start-up, LAYER 2 error = 35 will be displayed via the blinking LED procedure when SDM is switched on. All service modes (CSM, SAM and SDM) are accessible during this failure, observed in the Uart logging as follows: "<< ERRO >>> PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)". Error 36 (Tuner DVB-S). When there is no I2C communication towards the DVB-S tuner during start-up, LAYER 2 error = 36 will be logged and displayed via the blinking LED procedure when SDM is switched on. Error 42 (Temp sensor). Only applicable for TV sets equipped with temperature devices. Error 53. This error will indicate that the PNX8550 has read his bootscript (when this would have failed, error 15 would blink) but initialization was never completed because of hardware problems (NAND flash, ...) or software initialization problems. Possible cause could be that there is no valid software loaded (try to upgrade to the latest main software version). Note that it can take a few minutes before the TV starts blinking LAYER 1 error = 2 or in SDM, LAYER 2 error = 53. Error 64. Only applicable for TV sets with an I2C controlled screen.

How to Activate Use one of the following methods: Activate the CSM. The blinking front LED will show only the latest layer 1 error, this works in normal operation mode or automatically when the error/protection is monitored by the Stand-by processor. In case no picture is shown and there is no LED blinking, read the logging to detect whether error devices are mentioned. (see section 5.8 Fault Finding and Repair Tips, 5.8.7 Logging). Activate the SDM. The blinking front LED will show the entire content of the LAYER 2 error buffer, this works in normal operation mode or when SDM (via hardware pins) is activated when the tv set is in protection.

5.7
5.7.1

Protections
Software Protections Most of the protections and errors use either the stand-by microprocessor or the MIPS controller as detection device. Since in these cases, checking of observers, polling of ADCs, and filtering of input values are all heavily software based, these protections are referred to as software protections. There are several types of software related protections, solving a variety of fault conditions: Related to supplies: presence of the +5V, +3V3 and 1V2 needs to be measured, no protection triggered here. Protections related to breakdown of the safety check mechanism. E.g. since the protection detections are done by means of software, failing of the software will have to initiate a protection mode since safety cannot be guaranteed any more. Remark on the Supply Errors The detection of a supply dip or supply loss during the normal playing of the set does not lead to a protection, but to a cold reboot of the set. If the supply is still missing after the reboot, the TV will go to protection. Protections during Start-up During TV start-up, some voltages and IC observers are actively monitored to be able to optimise the start-up speed, and to assure good operation of all components. If these monitors do not respond in a defined way, this indicates a malfunction of the system and leads to a protection. As the observers are only used during start-up, they are described in the start-up flow in detail (see section 5.3 Stepwise Start-up).

5.6
5.6.1

The Blinking LED Procedure


Introduction The blinking LED procedure can be split up into two situations: Blinking LED procedure LAYER 1 error. In this case the error is automatically blinked when the TV is put in CSM. This will be only one digit error, namely the one that is referring to the defective board (see table 5-2 Error code overview) which causes the failure of the TV. This approach will especially be used for home repair and call centres. The aim here is to have service diagnosis from a distance. Blinking LED procedure LAYER 2 error. Via this procedure, the contents of the error buffer can be made visible via the front LED. In this case the error contains 2 digits (see table 5-2 Error code overview) and will be displayed when SDM (hardware pins) is activated. This is especially useful for fault finding and gives more details regarding the failure of the defective board. Important remark: For an empty error buffer, the LED should not blink at all in CSM or SDM. No spacer will be displayed. When one of the blinking LED procedures is activated, the front LED will show (blink) the contents of the error buffer. Error codes greater then 10 are shown as follows: 1. n long blinks (where n = 1 to 9) indicating decimal digit 2. A pause of 1.5 s 3. n short blinks (where n= 1 to 9) 4. A pause of approximately 3 s, 5. When all the error codes are displayed, the sequence finishes with a LED blink of 3 s (spacer). 6. The sequence starts again. Example: Error 12 8 6 0 0. After activation of the SDM, the front LED will show: 1. One long blink of 750 ms (which is an indication of the decimal digit) followed by a pause of 1.5 s

5.7.2

Hardware Protections The only real hardware protection in this chassis appears in case of an audio problem e.g. DC voltage on the speakers. This protection will only affect the Class D audio amplifier (item 7D10; see diagram B03A) and puts the amplifier in a continuous burst mode (cyclus approximately 2 seconds). Repair Tip There still will be a picture available but no sound. While the Class D amplifier tries to start-up again, the cone of the loudspeakers will move slowly in one or the other direction until the initial failure shuts the amplifier down, this cyclus starts over and over again. The headphone amplifier will also behaves similar.

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Service Modes, Error Codes, and Fault Finding 5.8 Fault Finding and Repair Tips
Read also section 5.5 Error Codes, 5.5.4 Error Buffer, Extra Info. 5.8.1 Ambilight Due to degeneration process of the LEDs fitted on the ambi module, there can be a difference in the color and/or light output of the spare ambilight modules in comparison with the originals ones contained in the TV set. Via SAM => alignments => ambilight, the spare module can be adjusted. 5.8.2 Audio Amplifier The Class D-IC 7D10 has a powerpad for cooling. When the IC is replaced it must be ensured that the powerpad is very well pushed to the PWB while the solder is still liquid. This is needed to insure that the cooling is guaranteed, otherwise the Class DIC could break down in short time. 5.8.3 AV PIP To check the AV PIP board (if present) functionality, a dedicated testpattern can be invoked as follows: select the multiview icon in the User Interface and press the OK button. Apply for the main picture an extended source, e.g. HDMI input. Proceed by entering CSM (push 123654 on the remote control) and press the yellow button. A colored testpattern should appear now, generated by the AV PIP board (this can take a few seconds). 5.8.4 CSM When CSM is activated and there is a USB stick connected to the TV, the software will dump the complete CSM content to the USB stick. The file (Csm.txt) will be saved in the root of the USB stick. If this mechanism works it can be concluded that a large part of the operating system is already working (MIPS, USB...) 5.8.5 DC/DC Converter Description basic board The basic board power supply consists of 4 DC/DC converters and 5 linear stabilizers. All DC/DC converters have +12V input voltage and deliver: +1V1 supply voltage (1.15V nominal), for the core voltage of PNX855xx, stabilized close to the point of load; SENSE+1V1 signal provides the DC-DC converter the needed feedback to achieve this. +1V8 supply voltage, for the DDR2 memories and DDR2 interface of PNX855xx. +3V3 supply voltage (3.30V nominal), overall 3.3 V for onboard ICs, for non-5000 series SSB diversities only. +5V (5.15V nominal) for USB, WIFI and Conditional Access Module and +5V5-TUN for +5V-TUN tuner stabilizer. The linear stabilizers are providing: +1V2 supply voltage (1.2V nominal), stabilized close to PNX855xx device, for various other internal blocks of PNX855xx; SENSE+1V2 signal provides the needed feedback to achieve this. +2V5 supply voltage (2.5V nominal) for LVDS interface and various other internal blocks of PNX855xx; for 5000 series SSB diversities the stabilizer is 7UD2 while for the other diversities 7UC0 is used. +3V3 supply voltage (3V3 nominal) for 5000 series SSB diversities, provided by 7UD3; in this case the 12V to 3V3 DC-DC converter is not present.

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EN 35

+5V-TUN supply voltage (5V nominal) for tuner and IF amplifier.

+3V3-STANDY (3V3 nominal) is the permanent voltage, supplying the Stand-by microprocessor inside PNX855xx. Supply voltage +1V1 is started immediately when +12V voltage becomes available (+12V is enabled by STANDBY signal when "low"). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN are switched "on" by signal ENABLE-3V3 when "low", provided that +12V (detected via 7U40 and 7U41) is present. +12V is considered OK (=> DETECT2 signal becomes "high", +12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter can be started up) if it rises above 10V and doesnt drop below 9V5. A small delay of a few milliseconds is introduced between the start-up of 12V to +1V8 DC-DC converter and the two other DC-DC converters via 7U48 and associated components. Description DVB-S2: LNB-RF1 (0V = disabled, 14V or 18V in normal operation) LNB supply generated via the second conversion channel of 7T03 followed by 7T50 LNB supply control IC. It provides supply voltage that feeds the outdoor satellite reception equipment. +3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal) and +1V-DVBS (1.03V nominal) power supply for the silicon tuner and channel decoder. +1V-DVBS is generated via a 5V to 1V DC-DC converter and is stabilized at the point of load (channel decoder) by means of feedback signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS are generated via linear stabilizers from +5V-DVBS that by itself is generated via the first conversion channel of 7T03. At start-up, +24V becomes available when STANDBY signal is "low" (together with +12V for the basic board), when +3V3 from the basic board is present the two DC-DC converters channels inside 7T03 are activated. Initially only the 24V to 5V converter (channel 1 of 7T03 generating +5V-DVBS) will effectively work, while +V-LNB is held at a level around 11V7 via diode 6T55. After 7T05 is initialized, the second channel of 7T03 will start and generates a voltage higher then LNB-RF1 with 0V8. +5VDVBS start-up will imply +3V3-DVBS start-up, with a small delay of a few milliseconds => +2V5-DVBS and +1V-DVBS will be enabled. If +24V drops below +15V level then the DVB-S2 supply will stop, even if +3V3 is still present. Debugging The best way to find a failure in the DC/DC converters is to check their start-up sequence at power on via the mains cord, presuming that the stand-by microprocessor and the external supply are operational. Take STANDBY signal "high"-to-"low" transition as time reference. When +12V becomes available (maximum 1 second after STANDBY signal goes "low") then +1V1 is started immediately. After ENABLE-3V3 goes "low", all the other supply voltages should rise within a few milliseconds. Tips Behavior comparison with a reference TV550 platform can be a fast way to locate failures. If +12V stays "low", check the integrity of fuse 1U40. Check the integrity (at least no short circuit between drain and source) of the power MOS-FETs before starting up the platform in SDM, otherwise many components might be damaged. Using a ohmmeter can detect short circuits between any power rail and ground or between +12V and any other power rail. Short circuit at the output of an integrated linear stabilizer (7UC0, 7UD2 or 7UD3) will heat up this device strongly. Switching frequencies should be 500 kHz ...600 kHz for 12 V to 1.1 V and 12 V to 1.8 V DC-DC converters,
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5.

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Service Modes, Error Codes, and Fault Finding


Uart loggings reporting fault conditions, error messages, error codes, fatal errors: Failure messages should be checked and investigated.For instance fatal error on the PNX51x0: check startup of the back-end processor, supplies..reset, I2C bus. => error mentioned in the logging as: *51x0 failed to start by itself*. Some failures are indicated by error codes in the logging, check with error codes table (see Table 5-2 Error code overview).e.g. => <<<ERROR>>>PLFPOW_MERR.C : First Error (id=10,Layer_1=2,Layer_2=23). I2C bus error mentioned as e.g.: I2C bus 4 blocked. Not all failures or error messages should be interpreted as fault.For instance root cause can be due to wrong option codes settings => e.g. DVBS2Suppoprted : False/True. In the Uart log startup script we can observe and check the enabled loaded option codes. Defective sectors (bad blocks) in the Nand Flash can also be reported in the logging. Startup in the SW upgrade application and observe the Uart logging: Starting up the TV set in the Manual Software Upgrade mode will show access to USB, meant to copy software content from USB to the DRAM.Progress is shown in the logging as follows: cosupgstdcmds_mcmdwritepart: Programming 102400 bytes, 40505344 of 40607744 bytes programmed. Startup in Jett Mode: Check Uart logging in Jet mode mentioned as : JETT UART READY. Uart logging changing preset: => COMMAND: calling DFB source = RC6, system=0, key = 4.

900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V LNB DC-DC converters operates at 300 kHz while for 5 V to 1.1 V DC-DC converter 900 kHz is used. 5.8.6 Exit Factory Mode When an F is displayed in the screens right corner, this means the set is in Factory mode, and it normally happens after a new SSB is mounted. To exit this mode, push the VOLUME minus button on the TVs local keyboard for 10 seconds (this disables the continuous mode). Then push the SOURCE button for 10 seconds until the F disappears from the screen. 5.8.7 Logging When something is wrong with the TV set (f.i. the set is rebooting) you can check for more information via the logging in Hyperterminal. The Hyperterminal is available in every Windows application via Programs, Accessories, Communications, Hyperterminal. Connect a ComPair UARTcable (3138 188 75051) from the service connector in the TV to the multi function jack at the front of ComPair II box. Required settings in ComPair before starting to log: - Start up the ComPair application. - Select the correct database (open file Q55X.X, this will set the ComPair interface in the appropriate mode). - Close ComPair After start-up of the Hyperterminal, fill in a name (f.i. logging) in the Connection Description box, then apply the following settings: 1. COMx 2. Bits per second = 115200 3. Data bits = 8 4. Parity = none 5. Stop bits = 1 6. Flow control = none During the start-up of the TV set, the logging will be displayed. This is also the case during rebooting of the TV set (the same logging appears time after time). Also available in the logging is the Display Option Code (useful when there is no picture), look for item DisplayRawNumber in the beginning of the logging. Tip: when there is no picture available during rebooting you are able to check for error devices in the logging (LAYER 2 error) which can be very helpful to determine the failure cause of the reboot. For protection state, there is no logging. 5.8.8 Guidelines Uart logging Description possible cases: Uart loggings are displayed: When Uart loggings are coming out, the first conclusion we can make is that the TV set is starting up and communication with the flash RAM seems to be supported. The PNX855xx is able to read and write in the DRAMs. We can not yet conclude : Flash RAM and DRAMs are fully operational/reliable.There still can be errors in the data transfers, DRAM errors, read/write speed and timing control. No Uart logging at all: In case there is no Uart logging coming out, check if the startup script can be send over the I2C bus (3 trials to startup) + power supplies are switched on and stable. No startup will end up in a blinking LED status : error LAYER 1 = 2, error LAYER 2 = 53 (startup with SDM solder paths short). Error LAYER 2 = 15 (hardware cause) is more related to a supply issue while error LAYER 2 = 53 (software cause) refers more to boot issues.

5.8.9

Loudspeakers Make sure that the volume is set to minimum during disconnecting the speakers in the ON-state of the TV. The audio amplifier can be damaged by disconnecting the speakers during ON-state of the set!

5.8.10 PSL In case of no picture when CSM (test pattern) is activated and backlight doesnt light up, its recommended first to check the inverter on the PSL + wiring (LAYER 2 error = 17 is displayed in SDM). 5.8.11 Tuner Attention: In case the tuner is replaced, always check the tuner options! 5.8.12 Display option code Attention: In case the SSB is replaced, always check the display option code in SAM, even when picture is available. Performance with the incorrect display option code can lead to unwanted side-effects for certain conditions. New in this chassis: While in the download application (start up in TV mode + OK button pressed), the display option code can be changed via 062598 HOME XXX special SAM command (XXX=display option in 3 digits).

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Service Modes, Error Codes, and Fault Finding


5.8.13 SSB Replacement Follow the instructions in the flowchart in case a SSB has to be exchanged. See figure SSB replacement flowchart.

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In s t ru ct io n n o t e SS B rep lacem en t Q543.x, Q548.x, Q549.x, and Q55x.x

Before starting: - prepare a USB memory stick with the latest software - download the latest Main Software (Fus) from www.p4c.philips.com - unzip this file - create a folder upgrades in the root of a USB stick (size > 50 MB) and save the autorun.upg file in this "upgrades" folder. Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in case there are more than one "autorun.upg" files on the USB stick.

S T AR T

S et i s s till oper a ting? No Ye s

C onnect the U S B s tick to the set, go to SAM and save the current TV settings via Upload to USB 1. D i s connect the WiF i mod u le fr om the PC I connector (only for Q549.x SSB) 2. Replace the SSB by a Service SSB. 3. Place the WiFi module in the PCI connector. 4. Mount the Service SSB in the set.

Start-up the set Due to a possible wrong display option code in the received Service SSB (NVM), its possible that no picture is displayed. Due to this the download application will not be shown either. This tree enables you to load the main software step-by-step via the UART logging on the PC (this for visual feedback). No pictu r e displayed

S et b eh a vio u r?

Pictu r e displayed Set is starting up without software upgrade menu appearing on screen

1) Start up the TV set, equiped with the Service SSB, and enable the UART logging on the PC. 2) The TV set will start-up automatically in the download application if main TV software is not loaded.

Pictu r e displayed Set is starting up with software upgrade menu appearing on screen

3) Plug the prepared USB stick into the TV set. Follow the instructions in the UART log file, press Right cursor key to enter the list. Navigate to the autorun.upg file in the UART logging printout via the cursor keys on the remote control. When the correct file is selected, press Ok.

1) Plug the USB stick into the TV set and select the autorun .upg file in the displayed browser.

2) Now the main software will be loaded automatically, supported by a progress bar. 4) Press "Down" cursor and Ok to start flashing the main TV software. Printouts like: L: 1-100%, V: 1-100% and P: 1-100% should be visible now in the UART logging. 3) Wait until the message Operation successful ! is displayed and remove all inserted media. Restart the TV set.

5) Wait until the message Operation successful ! is logged in the UART log and remove all inserted media. Restart the TV set.

Set the correct Display code via 062598 -HOME- xxx where xxx is the 3 digit display panel code (see sticker on the side or bottom of the cabinet)

After entering the Display Option code, the set is going to Standby (= validation of code) Restart the set

No

Connect PC via the ComPair interface to Service connector.

Saved settings on USB stick?

Start TV in Jett mode (DVD I + (OSD)) Open ComPair browser Q54x

Ye s
In case of settings reloaded from USB, the set type, serial number, display 12 NC, are automatically stored when entering display options.

Go to SAM and reload settings via Download from USB function. Program set type number, serial number, and display 12 NC Program E - DFU if needed. If not already done: Check latest software on Service website. Update main and Stand-by software via USB.

- Check if correct display option code is programmed. - Verify option codes according to sticker inside the set. - Default settings for white drive > see Service Manual.

Attention point for Net TV: If the set type and serial number are not filled in, the Net TV functionality will not work. It will not be possible to connect to the internet.

Check and perform alignments in SAM according to the Service Manual. Option codes, colour temperature, etc.

Final check of all menus in CSM. Special attention for HDMI Keys and Mac address. Check if E - D F U is present.

End

Q54x.E SSB Board swap VDS Updated 22-03-2010

H_16771_007a.eps 100402

Figure 5-11 SSB replacement flowchart

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S et is s t art in g u p in F act o ry m o d e

S et is s t a rting u p in F a ctory m ode?

Noisy picture with bands/lines is visible and the RED LED is continuous on.

An F is displayed (and the HDMI 1 input is displayed).

- Press the volume minus button on the TVs local keyboard for 5 ~10 seconds - Press the SOURCE button for 10 seconds until the F disappears from the screen or the noise on the screen is replaced by blue mute

The noise on the screen is replaced with the blue mute or the F is disappeared!

Unplug the mains cord to verify the correct disabling of the Factory mode.

Program display option code via 062598 MENU, followed by the 3 digits code of the display (this code can be found on a sticker on - or inside - the set).

After entering display option code, the set is going in stand-by mode (= validation of code)

R e s t a rt the s et

H_16771_007b.eps 100322

Figure 5-12 SSB replacement flowchart - Factory mode

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Service Modes, Error Codes, and Fault Finding

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5.

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18753_211_100811.eps 100811

Figure 5-13 SSB start-up

5.9

Software Upgrading
Attention! Software version numbers for 2011 sets are all defined below number 0.40.x.x. This might confuse servicers who store software versions for more than one set and/or platform on the same storage device (USB stick). Always check the latest software version on the servicer website in relation to the correct CTN!!! 5.9.2

For the correct order number of a new SSB, always refer to the Spare Parts list! Main Software Upgrade The UpgradeAll.upg file is only used in the factory.

5.9.1

Introduction The set software and security keys are stored in a NANDFlash, which is connected to the PNX855xx. It is possible for the user to upgrade the main software via the USB port. This allows replacement of a software image in a stand alone set, without the need of an E-JTAG debugger. A description on how to upgrade the main software can be found in the electronic User Manual. Important: When the NAND-Flash must be replaced, a new SSB must be ordered, due to the presence of the security keys! (CI +, MAC address, ...). Perform the following actions after SSB replacement: 1. Set the correct option codes (see sticker inside the TV). 2. Update the TV software => see the eUM (electronic User Manual) for instructions. 3. Perform the alignments as described in chapter 6 (section 6.5 Reset of Repaired SSB). 4. Check in CSM if the CI + key, MAC address.. are valid.
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Automatic Software Upgrade In normal conditions, so when there is no major problem with the TV, the main software and the default software upgrade application can be upgraded with the AUTORUN.UPG (FUS part of the one-zip file: e.g. 3104 337 05661 _FUS _Q555X_ x.x.x.x_prod.zip). This can also be done by the consumers themselves, but they will have to get their software from the commercial Philips website or via the Software Update Assistant in the user menu (see eUM). The autorun.upg file must be placed in the root of the USB stick. How to upgrade: 1. Copy AUTORUN.UPG to the root of the USB stick. 2. Insert USB stick in the set while the set is operational. The set will restart and the upgrading will start automatically. As soon as the programming is finished, a message is shown to remove the USB stick and restart the set. Manual Software Upgrade In case that the software upgrade application does not start automatically, it can also be started manually. How to start the software upgrade application manually: 1. Disconnect the TV from the Mains/AC Power. 2. Press the OK button on a Philips TV remote control or a Philips DVD RC-6 remote control (it is also possible to use

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a TV remote in DVD mode). Keep the OK button pressed while reconnecting the TV to the Mains/AC Power. 3. The software upgrade application will start. Attention! In case the download application has been started manually, the autorun.upg will maybe not be recognized. What to do in this case: 1. Create a directory UPGRADES on the USB stick. 2. Rename the autorun.upg to something else, e.g. to software.upg. Do not use long or complicated names, keep it simple. Make sure that AUTORUN.UPG is no longer present in the root of the USB stick. 3. Copy the renamed upg file into this directory. 4. Insert USB stick into the TV. 5. The renamed upg file will be visible and selectable in the upgrade application. Back-up Software Upgrade Application If the default software upgrade application does not start (could be due to a corrupted boot sector) via the above described method, try activating the back-up software upgrade application. How to start the back-up software upgrade application manually: 1. Disconnect the TV from the Mains/AC Power. 2. Press the CURSOR DOWN-button on a Philips TV remote control while reconnecting the TV to the Mains/AC Power. 3. The back-up software upgrade application will start. 5.9.3 Stand-by Software Upgrade via USB In this chassis it is possible to upgrade the Stand-by software via a USB stick. The method is similar to upgrading the main software via USB. Use the following steps: 1. Create a directory UPGRADES on the USB stick. 2. Copy the Stand-by software (part of the one-zip file, e.g. StandbyFactory_88.0.0.0.upg) into this directory. 3. Insert the USB stick into the TV. 4. Start the download application manually (see section Manual Software Upgrade. 5. Select the appropriate file and press the OK button to upgrade. 5.9.4 Content and Usage of the One-Zip Software File Below the content of the One-Zip file is explained, and instructions on how and when to use it. AmbiCpld_Q55XX_x.x.x.x_prod.zip. Contains the program instruction and software content, needed to upgrade the ambilight CPLD on the TV550 platform. BalanceFPGA_Q555X_x.x.x.x_prod.zip. Contains the BalanceFPGA software in upg format. FUS_Q555X_x.x.x.x_prod.zip. Contains the autorun.upg which is needed to upgrade the TV main software and the software download application. PNX5130UPG_Q555X_x.x.x.x_prod.zip. Contains the PNX5130 software in upg format. StandbySW_Q555X_x.x.x.x_prod.zip. Contains the StandbyFactory software in upg format. ProcessNVM_Q55XX_x.x.x.x_prod.zip. Default NVM content. Must be programmed via ComPair or can be loaded via USB, be aware that all alignments stored in NVM are overwritten here. 5.9.5 UART logging 2K10 (see section 5.8 Fault Finding and Repair Tips, 5.8.7 Logging)

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Alignments

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EN 41

6. Alignments
Index of this chapter: 6.1 General Alignment Conditions 6.2 Hardware Alignments 6.3 Software Alignments 6.4 Option Settings 6.5 Reset of Repaired SSB 6.6 Total Overview SAM modes EU/AP-PAL models: a PAL B/G TV-signal with a signal strength of at least 1 mV and a frequency of 475.25 MHz US/AP-NTSC models: an NTSC M/N TV-signal with a signal strength of at least 1 mV and a frequency of 61.25 MHz (channel 3). LATAM models: an NTSC M TV-signal with a signal strength of at least 1 mV and a frequency of 61.25 MHz (channel 3).

6.1

General Alignment Conditions


Perform all electrical adjustments under the following conditions: Power supply voltage (depends on region): AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%). AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%). EU: 230 VAC / 50 Hz ( 10%). LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%). US: 120 VAC / 60 Hz ( 10%). Connect the set to the mains via an isolation transformer with low internal resistance. Allow the set to warm up for approximately 15 minutes. Measure voltages and waveforms in relation to correct ground (e.g. measure audio signals in relation to AUDIO_GND). Caution: It is not allowed to use heat sinks as ground. Test probe: Ri > 10 M, Ci < 20 pF. Use an isolated trimmer/screwdriver to perform alignments.

6.3.1

White Point Choose TV menu, Setup, More TV Settings and then Picture and set picture settings as follows:
100 50 0 Off Unscaled

Picture Setting Contrast Brightness Colour Light Sensor Picture format

In menu Picture, choose Pixel Plus HD and set picture settings as follows:
Off Off Off 0

Picture Setting Dynamic Contrast Dynamic Backlight Colour Enhancement Gamma

6.1.1 Alignment Sequence First, set the correct options: In SAM, select Option numbers. Fill in the option settings for Group 1 and Group 2 according to the set sticker (see also paragraph 6.4 Option Settings). Press OK on the remote control before the cursor is moved to the left. In submenu Option numbers select Store and press OK on the RC. OR: In main menu, select Store again and press OK on the RC. Switch the set to Stand-by. Warming up (>15 minutes).

Go to the SAM and select Alignments-> White point.

White point alignment LCD screens: Use a 100% white screen (format: 720p50) to the HDMI input and set the following values: Color temperature: Cool. All White point values to: 127. In case you have a color analyzer: Measure, in a dark environment, with a calibrated contactless color analyzer (Minolta CA-210 or Minolta CS200) in the centre of the screen and note the x, y value. Change the pattern to 90% white screen. If a Quantum Data generator is used, select the GreyAll test pattern at level = 230. Adjust the correct x, y coordinates (while holding one of the White point registers R, G or B on 127) by means of decreasing the value of one or two other white points to the correct x, y coordinates (see Table 6-1 White D alignment values - LED - Minolta CA-210, or 6-2 White D alignment values - LED - Minolta CS-200). Tolerance: dx: 0.002, dy: 0.002. Repeat this step for the other color temperatures that need to be aligned. When finished press OK on the RC and then press STORE (in the SAM root menu) to store the aligned values to the NVM. Restore the initial picture settings after the alignments. Table 6-1 White D alignment values - LED - Minolta CA-210
Value x y Cool (9420K) 0.282 0.298 Normal (8120K) 0.292 0.311 Warm (6080K) 0.320 0.345

6.2

Hardware Alignments
Not applicable.

6.3

Software Alignments
Put the set in SAM mode (see Chapter 5. Service Modes, Error Codes, and Fault Finding). The SAM menu will now appear on the screen. Select ALIGNMENTS and go to one of the sub menus. The alignments are explained below. The following items can be aligned: White point Ambilight. To store the data: Press OK on the RC before the cursor is moved to the left In main menu select Store and press OK on the RC Switch the set to stand-by mode. For the next alignments, supply the following test signals via a video generator to the RF input:
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Table 6-2 White D alignment values - LED - Minolta CS-200


Value x y Cool (11000K) 0.276 0.282 Normal (9000K) 0.287 0.296 Warm (6500K) 0.313 0.329

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Alignments 6.4
6.4.1

If you do not have a color analyzer, you can use the default values. This is the next best solution. The default values are average values coming from production. Select a COLOUR TEMPERATURE (e.g. COOL, NORMAL, or WARM). Set the RED, GREEN and BLUE default values according to the values in Table 6-3. When finished press OK on the RC, then press STORE (in the SAM root menu) to store the aligned values to the NVM. Restore the initial picture settings after the alignments. Table 6-3 White tone default setting 32" sets (Blockbuster)
White Tone Colour Temp Normal Cool Warm e.g. 32PFL6606/xx R t.b.d. t.b.d. t.b.d. G t.b.d. t.b.d. t.b.d. B t.b.d. t.b.d. t.b.d.

Option Settings
Introduction The microprocessor communicates with a large number of I2C ICs in the set. To ensure good communication and to make digital diagnosis possible, the microprocessor has to know which ICs to address. The presence / absence of these PNX51XX ICs (back-end advanced video picture improvement IC which offers motion estimation and compensation features (commercially called HDNM) plus integrated Ambilight control) is made known by the option codes. Notes: After changing the option(s), save them by pressing the OK button on the RC before the cursor is moved to the left, select STORE in the SAM root menu and press OK on the RC. The new option setting is only active after the TV is switched off / stand-by and on again with the mains switch (the NVM is then read again).

Table 6-4 White tone default setting 40" sets (Blockbuster)


White Tone Colour Temp Normal Cool Warm e.g. 40PFL6606/xx R 117 113 126 G 127 127 125 B 95 111 60

6.4.2

Dealer Options For dealer options, in SAM select Dealer options. See Table 6-11 SAM mode overview.

Table 6-5 White tone default setting 32" sets (Emmy)


White Tone Colour Temp Normal Cool Warm e.g. 32PFL7606/xx R 112 106 125 G 127 127 126 B 85 100 53

6.4.3

(Service) Options From 2011 onwards, it is not longer possible to change individual option settings in SAM. Options can only be changed all at once by using the option codes as described in section 6.4.4.

6.4.4 Table 6-6 White tone default setting 40" sets (Emmy)
White Tone Colour Temp Normal Cool Warm e.g. 40PFL7606/xx R 115 111 125 G 127 127 127 B 84 99 49

Opt. No. (Option numbers) Select this sub menu to set all options at once (expressed in two long strings of numbers). An option number (or option byte) represents a number of different options. When you change these numbers directly, you can set all options very quickly. All options are controlled via eight option numbers. When the NVM is replaced, all options will require resetting. To be certain that the factory settings are reproduced exactly, you must set both option number lines. You can find the correct option numbers on a sticker inside the TV set. Example: The options sticker gives the following option numbers: 08192 00133 01387 45160 12232 04256 00164 00000 The first line (group 1) indicates hardware options 1 to 4, the second line (group 2) indicate software options 5 to 8. Every 5-digit number represents 16 bits (so the maximum value will be 65536 if all options are set). When all the correct options are set, the sum of the decimal values of each Option Byte (OB) will give the option number. Diversity Not all sets with the same Commercial Type Number (CTN) necessarily have the same option code! Use of Alternative BOM => an alternative BOM number usually indicates the use of an alternative display or power supply. This results in another display code thus in another Option code. Refer to Chapter 2. Technical Specifications, Diversity, and Connections.

Table 6-7 White tone default setting 46" sets (Emmy)


White Tone Colour Temp Normal Cool Warm e.g. 46PFL7606/xx R 124 120 127 G 127 127 121 B 98 121 58

Table 6-8 White tone default setting 42" sets (Sundance)


White Tone Colour Temp Normal Cool Warm e.g. 42PFL8606/xx R 125 106 127 G 125 108 110 B 127 127 79

Table 6-9 White tone default setting 47" sets (Sundance)


White Tone Colour Temp Normal Cool Warm e.g. 47PFL8606/xx R t.b.d. t.b.d. t.b.d. G t.b.d. t.b.d. t.b.d. B t.b.d. t.b.d. t.b.d.

6.4.5

Option Code Overview Refer to the sticker in the set for the correct option codes. Important: after having edited the option numbers as described above, you must press OK on the remote control before the cursor is moved to the left!

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Alignments
6.4.6 Option Bit Overview For test purposes, please find below an overview of the Option Codes on bit level. With a bin/dec converter, you can calculate the Option Code.

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Caution When manipulating option codes, know what youre doing. Wrong option codes could damage the set. Prescribed option codes below are an example, not valid for all sets and are subject to modification. The correct option codes are always present on a sticker inside the set!

Table 6-10 Option codes at bit level (Option 1 - Option 8)


Option & Bit Dec. Value Option Name Video Store Streaming Multi App Prescribed Value1) 11) 001) Description 0 = OFF 1 = ON 00 = none 01 = multi app (Multiview BASIC) 10 = AVPIP + multi app (Multiview ENHANCED) 11 = future use 00 = Pixel Plus HD 01 = Pixel Precise HD 10 = Perfect Pixel HD 11 = future use 000 = TH2603 (Europe/AP) 001 = FA2307 (Brazil) 010 = VA1E1ED2411 011 = future use 100 = future use 101 = future use 110 = future use 111 = future use 000 = profile 0 001 = profile 1 010 = profile 2 011 = profile 3 100 = profile 4 101 = profile 5 110 = profile 6 111 = profile 7 00 = Perfect Natural Motion 01 = HD Natural Motion 10 = future use 11 = future use CPLD, not used in 2011 00 = 140 nit 01 = 200 nit 10 = future use 11 = future use 0 = boost mode in shop is OFF 1 = boost mode in shop is ON 0 = stored in AL modules 1 = stored in SSB 0 = OFF 1 = ON 0 = OFF 1 = ON 0000 = none 0001 = 2-sided (3/3) 0010 = 2-sided (4/4) 0011 = 2-sided (5/5) 0100 = 2-sided (6/6) 0101 = 2-sided (7/7) 0110 = 3-sided (5/5/5) 0111 = 3-sided (6/6/6) 1000 = 3-sided (3/6/3) 1001 = 3-sided (6/9/6) 1010 = 2-sided (8/8) 1011 = 3-sided (4/4/4) 1100 = 2-sided (1/1) 1101 = 2-sided (2/2) 1110 = future use 1111 = future use 0 = OFF 1 = ON 0 = AL2k10 1 = AL2k11 0 = 2D 1 = 3D passive 0 = off 1 = on (200 Hz board present) 0 = Super Resolution SD 1 = Super Resolution HD 00 = Lut 0 01 = Lut 1 10 = Lut 2 11 = Lut 3 0 = OFF 1 = ON 0 = not present 1 = present

Option 1 (prescribed value 327761)) Bit 15 (MSB) 32768 Bit 14 Bit 13 16384 8192

Bit 12 Bit 11

4096 2048

Perfect Pixel

001)

Bit 10 Bit 9 Bit 8

1024 512 256

Tuner Type

0001)

Bit 7 Bit 6 Bit 5

128 64 32

PQ Profiles

0001)

Bit 4 Bit 3

16 8

DNM

011)

Bit 2 Bit 1 Bit 0 (LSB)

4 2 1

MOP AL AL Optical Syst

01) 001)

Option 2 (prescribed value 000011)) Bit 15 (MSB) 32768 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 16384 8192 4096 2048 1024 512 256

AL Shop Mode AL settings storage location Wall Adaptive AL Sunset Ambient Light

01) 01) 01) 01) 00001)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

128 64 32 16 8 4 2

FPGA3Dact/1Ddimm AL Select 3D Passive Smart Bit Enhancement (SBE) Super Resolution Light Sensor LUT

01) 01) 01) 01) 01) 001)

Bit 0 (LSB)

Light Sensor

11)

Option 3 (prescribed value 154211)) Bit 15 (MSB) 32768

Side IO

01)

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EN 44

6.

Q552.2L LA
Dec. Value 16384 8192 4096

Alignments
Prescribed Value1) 0111) Description 000 = none 001 = CVBS 010 = YPbPr 011 = YPbPr/LR 100 = YPbPr/HV/LR 101 = CVBS/LR 110 = CVBS/Yc/LR 111 = future use 00 = Scart/CVBS/RGB/LR 01 = CVBS/LR 10 = YPbPr/LR 11 = none 00 = Scart/CVBS/RGB/LR 01 = CVBS/YC/YPbPr/HV/LR 10 = CVBS/YC/YPbPr/LR 11 = YPbPr/LR 0 = not prepared 1 = prepared 0 = Sound in Cabinet 1 = Sound in Stand 0 = OFF 1 = ON 0 = OFF 1 = ON 0 = OFF 1 = ON 0 = OFF 1 = ON 0 = OFF 1 = ON 0 = OFF 1 = ON Cabinet type (no detailed info available)

Option & Bit Bit 14 Bit 13 Bit 12

Option Name AV3

Bit 11 Bit 10

2048 1024

AV2

111)

Bit 9 Bit 8

512 256

AV1

001)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

128 64 32 16 8 4 2 1

3D Prepared Sound in Stand Headphone Seamless System ViewPort 21_9/PQL HDMI Side HDMI 3 HDMI 2

01) 01) 11) 11) 11) 11) 01) 11)

Option 4 (prescribed value 022351)) Bit 15 (MSB) 32768 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 16384 8192 4096 2048 1024 512 256

Cabinet

000011)

Region

0001)

000 = Europe (/02, /05 & /12) 001 = AP PAL multi 010 = AP NTSC 011 = Russian (/60) 100 = Latam (/78 & /77) 101 = Australia 110 = China (/93) 111 = future use 0 = display option =< 255 1 = display option > 255 0 = OFF 1 = ON 0 = OFF 1 = ON 0 = OFF 1 = ON (automatic software upgradable via internet) 0 = OFF 1 = ON (connection to internet provider Philips) 0 = OFF 1 = ON (wireless connection to ethernet; no link with Ethernet option bit 0) 0 = OFF 1 = PC link 0 = OFF 1 = Ethernet vonnector and HW present 0 = OFF 1 = ON (country dependent) 00 = OFF 01 = Country dependent 10 = ON 11 = future use 00 = OFF 01 = Country dependent 10 = ON 11 = future use 0 = OFF 1 = ON (ATSC/DVB should be ON) 0 = OFF 1 = ON (ATSC/DVB should be ON) 0 = analogue only 1 = DVBT (and C/S depending DVBC/S option) Display Type (ex.: 327)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

128 64 32 16 8 4

Display MSB S Video Video Store SD Card Internet SW Upgrade Online Service WiFi

11) 01) 11) 11) 11) 01)

Bit 1 Bit 0 (LSB)

2 1

DLNA Ethernet

11) 11)

Option 5 (prescribed value 438471)) Bit 15 (MSB) 32768 Bit 14 Bit 13 16384 8192

8 Days EPG DVBC Installation

11) 011)

Bit 12 Bit 11

4096 2048

DVBT Installation

011)

Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

1024 512 256 128 64 32 16 8 4 2 1

DVB-S DVB-C DVB Display Type

01) 11) 11) 010001111)

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Alignments
Option & Bit Dec. Value Option Name E-sticker Hotel Mode Prescribed Value1) 11) 001)

Q552.2L LA
Description 0 = OFF 1 = ON 00 = OFF 01 = 1V1 10 = 1V2 11 = future use 0 = ON 1 = OFF 0 = OFF 1 = ON 00 = none 01 = PDC_VPS 10 = TXT page 11 = PDC_VPS_TXT 0 = OFF 1 = ON 00 = OFF 01 = Country dependent 10 = ON 11 = future use 00 = OFF 01 = Country dependent 10 = ON 11 = future use 00 = OFF 01 = Country dependent 10 = ON 11 = future use

6.

EN 45

Option 6 (prescribed value 366151)) Bit 15 (MSB) 32768 Bit 14 Bit 13 16384 8192

Bit 12 Bit 11 Bit 10 Bit 9

4096 2048 1024 512

Virgin USB Time Shift Auto Store Mode

01) 11) 111)

Bit 8 Bit 7 Bit 6

256 128 64

PVR Ginga

11) 001)

Bit 5 Bit 4

32 16

MHP

001)

Bit 3 Bit 2

8 4

Over the Air Download

011)

Bit 1

DVBC light

11)

0 = OFF 1 = ON (when DVBC Installation is OFF or when ON but selected country is OFF, this option is used) 0 = OFF 1 = ON (when DVBT Installation is OFF or Country depend to a country is OFF, this option is used) 0 = User Interface 2k10 1 = User Interface 2k11 000 = LED config LUT 0 001 = LED config LUT 1 010 = LED config LUT 2 011 = LED config LUT 3 100 = LED config LUT 4 101 = LED config LUT 5 110 = LED config LUT 6 111 = LED config LUT 7 not used, should always be 00 0 = all sets except Manet 1= Manet 0 = OFF 1 = ON 0 = OFF 1 = ON 0 = integrated set 1 = e-box/monitor 000 = temp lut 0 001 = temp lut 1 010 = temp lut 2 011 = temp lut 3 100 = future use 101 = future use 110 = future use 111 = future use 00 = no temp sensor 01 = temp sensor in display 10 = temp sensor on additional board 11 = temp sensor in AL module 0 = no fan 1 = fan(s) present) 0 = OFF 1 = ON 0 = OFF 1 = ON 0 = OFF 1 = ON 0 = OFF 1 = ON -

Bit 0 (LSB)

DVBT light

11)

Option 7 (prescribed value 330241)) Bit 15 (MSB) Bit 14 Bit 13 Bit 12 32768 16384 8192 4096 Visual Identity Red LED Config LUT 11) 0001)

Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

2048 1024 512 256 128 64 32 16 8

Board Identifier Manet Auto Power Down Light Guide E-box Temp LUT

001) 01) 11) 01) 01) 0001)

Bit 2 Bit 1

4 2

Temp Sensor

001)

Bit 0 (LSB)

FAN

01)

Option 8 (prescribed value 000121)) Bit 15 (MSB) 32768 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 16384 8192 4096 2048 1024 512 256 128 64 32 16 8

Test 8 Test 7 Test 6 Test 5 Test 4 (Trick Mode) Test 3 (XRay) Test 2 (DBV-T light) Test 1 (Monitor out) not used

01) 01) 01) 01) 01) 01) 01) 01) 00001)

WM DRM10

11)

0 = OFF 1 = ON

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EN 46

6.

Q552.2L LA
Dec. Value 4 2 1

Alignments
Prescribed Value1) 11) 01) 01) Description 0 = OFF 1 = ON 0 = OFF 1 = ON 0 = OFF 1 = ON

Option & Bit Bit 2 Bit 1 Bit 0 (LSB)

Option Name HBBTV DVB-T2 Installation DVB-T2

Note 1). Example

In case of a display replacement, reset the Operation hours display to 0, or to the operation hours of the replacement display. 6.5.1 SSB identification Whenever ordering a new SSB, it should be noted that the correct ordering number (12nc) of a SSB is located on a sticker on the SSB. The format is <12nc SSB><serial number>. The ordering number of a Service SSB is the same as the ordering number of an initial factory SSB.

6.5

Reset of Repaired SSB


A very important issue towards a repaired SSB from a Service repair shop (SSB repair on component level) implies the reset of the NVM on the SSB. A repaired SSB in Service should get the service Set type 00PF0000000000 and Production code 00000000000000. Also the virgin bit is to be set. To set all this, you can use the ComPair tool or use the NVM editor and Dealer options items in SAM (do not forget to store). After a repaired SSB has been mounted in the set (set repair on board level), the type number (CTN) and production code of the TV has to be set according to the type plate of the set. For this, you can use the NVM editor in SAM. This action also ensures the correct functioning of the Net TV feature and access to the Net TV portals. The loading of the CTN and production code can also be done via ComPair (Model number programming). After a SSB repair, the original channel map can be restored, provided that the original channel map was stored on a USB stick before repair was commenced and that basic functionality of the TV, needed for this procedure, was not hampered as a result of the defect. The procedure of channel map cloning is clearly described in the (electronic) user manual.

18310_221_090318.eps 090319

6.6

Total Overview SAM modes


Table 6-11 SAM mode overview
Main Menu Hardware Info Sub-menu 1 A. SW version C. Production code Operation hours Errors Reset error buffer Alignment White point Colour temperature Normal Warn Cool White point red White point green White point blue Ambilight Select module Brightness Select matrix Dealer options Virgin mode Off/On Select Virgin mode On/Off. TV starts up / does not start up (once) with a language selection menu after the mains switch is turned on for the first time (virgin mode) Select E-sticker On/Off (USPs on-screen) LCD White Point Alignment. For values, see Table 6-3 White tone default setting 32" sets (Blockbuster) Sub-menu 2 e.g. Q5551_0.9.1.0 e.g. see type plate Displays the accumulated total of operation hours.TV switched on/off & every 0.5 hours is increase one Displayed the most recent errors Clears all content in the error buffer 3 different modes of colour temperature can be selected Sub-menu 3 Description Display TV & Stand-by SW version and CTN serial number

B. Stand-by processor version e.g. STDBY_83.84.0.0

E-sticker Auto store mode

Off/On None PDC/VPS TXT page PDC/VPS/TXT

Option numbers

Group 1 Group 2 Store

e.g. 00008.00001.15421.02239 e.g. 44816.34311.33024.00000

The first line (group 1) indicates hardware options 1 to 4 The second line (group 2) indicates software options 5 to 8 Store after changing N.A.

Initialise NVM

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Alignments
Main Menu Store Operation hours display 0003 Sub-menu 1 Sub-menu 2 Sub-menu 3

Q552.2L LA
Description

6.

EN 47

Select Store in the SAM root menu after making any changes In case the display must be swapped for repair, you can reset the Display operation hours to 0. So, this one does keeps up the lifetime of the display itself (mainly to compensate the degeneration behaviour) Display information is for development purposes

Software maintenance

Software events

Display Clear Test reboot Test cold reboot Test application crash

Hardware events Test setting Digital info

Display Clear Current frequency: 538 QAM modulation: 64-qam Symbol rate: Original network ID: 12871 Network ID: 12871 Transport stream ID: 2 Service ID: 3 Hierarchical modulation: 0 Selected video PID: 35 Selected main audio PID: 99 Selected 2nd audio PID: 8191

Display information is for development purposes

Display information is for development purposes

Install start frequency Install end frequency Default install frequency Installation Development file versions Development 1 file version

000 999 Digital only Digital + Analogue Display parameters DISPT5.0.9.29 Acoustics parameters ACSTS 5.0.6.20 PQ - TV550 1.0.27.22 PQS- Profile set PQF - Fixed settings PQU - User styles Ambilight parameters PRFAM 5.0.5.2

Install start frequency from 0 MHz Install end frequency as 999 MHz Select Digital only or Digital + Analogue before installation Display information is for development purposes

Development 2 file version

12NC one zip software Initial main software NVM version Q55x1_0.4.5.0 Flash units software Temp com file version none

Display information is for development purposes

Upload to USB

Channel list Personal settings Option codes Alignments Identification data History list All (options included)

To upload several settings from the TV to an USB stick

Download from USB

Channel list Personal settings Option codes Alignments Identification data All (options included)

To download several settings from the USB stick to the TV

NVM editor

Type number AG code

see type plate see type plate

NVM editor; re key-in type number and production code after SSB replacement

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EN 48

7.

Q552.2L LA

Circuit Descriptions

7. Circuit Descriptions
Index of this chapter: 7.1 Introduction 7.2 Power Supply 7.3 DC/DC Converters 7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception 7.5 Front-End DVB-S(2) reception 7.6 HDMI 7.7 Video and Audio Processing - PNX855xx Notes: Only new circuits (circuits that are not published recently) are described. Figures can deviate slightly from the actual situation, due to different set executions. For a good understanding of the following circuit descriptions, please use the wiring-, block- (see chapter 9. Block Diagrams) and circuit diagrams (see chapter 10. Circuit Diagrams and PWB Layouts).Where necessary, you will find a separate drawing for clarification. removal of TCON from the SSB (comes with the display) changed power architecture new USB hub (where applicable).

The Q552.2L LA chassis comes with the following stylings: Berlinale (series xxPFL58xx), Blockbuster (series xxPFL66xx), Emmy (series xxPFL76xx), Sundance (series xxPFL86xx). 7.1.1 Implementation Key components of this chassis are: PNX855xx System-On-Chip (SOC) TV Processor TX26xx Hybrid Tuner (DVB-T/C, analogue) STV6110AT DVB-S Satellite Tuner SII9x87 HDMI Switch TPA312xD2PWP Class D Power Amplifier LAN8710 Dual Port Gigabit Ethernet media access controller. 7.1.2 TV550 Architecture Overview For details about the chassis block diagrams refer to chapter 9. Block Diagrams. An overview of the TV550 2011 architecture can be found in Figure 7-1.

7.1

Introduction
The Q552.2L LA is part of the TV550 platform and uses the (same) PNX855xx chipset. The major deltas versus its predecessor Q551 are: support of DVB-T2 (second generation DVBT) implementation of passive 3D

19110_053_110421.eps 110421

Figure 7-1 Architecture of TV550 platform 2011

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Circuit Descriptions
7.1.3 SSB Cell Layout

Q552.2L LA

7.

EN 49

19110_052_110421.eps 110421

Figure 7-2 SSB layout cells (top view)

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EN 50 7.2
7.2.1

7.

Q552.2L LA

Circuit Descriptions
Stand-by microcontroller and ENABLE-3V3n is the signal coming from the Stand-by microcontroller. Diagram B03D contains the following linear stabilizers: +2V5 stabilizer, built around item no. 7UCO +5V-TUN stabilizer, built around items no. 7UA6 and 7UA7 +1V2 stabilizer, built around items no. 7UA3 and 7UA4. Diagram B08A contains the DVB-S2-related DC/DC converters and -stabilizers: a +24V under-voltage detection circuitry is built around item no. 7T04 the switching frequency of the 24 to 14...20V switched mode converter is 350 kHz (item no. 7T03 and +V-LNB lines) the output signal on the +V-LNB line goes to the LNBH23Q (item no. 7T50) the LNBH23Q (item no. 7T50) sends a feedback signal via the V0-CNTRL line the switching frequency of the +5V-DVBS to +1-DVBS switched mode converter is 900 kHz (item no. 7T00) a delay line for the +2V5-DVBS and +1V-DVBS lines is created with item no. 3T03 (R=10k) and 2T06 (C=100n) a 3.3V to 2.5V linear stabilizer is built around item no. 7T01 a 5V to 3.3V linear stabilizer is built around item no. 7T02. Diagram B08B contains the DVB-S2 LNB supply: the +V-LNB signal comes from item no. 7T03 the V0-CTRL signal goes to item no. 7T03 the LNB-RF1 goes to the LNB. Figures gives a graphical representation of the DC/DC converters with its current consumptions:
+ 5V 5-TUN 196 m A + 5V dc -dc + 5V 2179 m A + 5V 5-TUN + 5V -TUN s t ab iliz er + 5V -TUN 196 m A

Power Supply
Power Supply Unit All power supplies are a black box for Service. When defective, a new board must be ordered and the defective one must be returned, unless the main fuse of the board is broken. Always replace a defective fuse with one with the correct specifications! This part is available in the regular market. Consult the Philips Service web portal for the order codes of the boards. In this manual, no detailed information is available because of design protection issues.

7.2.2

Connector overview Table 7-1 Connector overview


Connector no. Descr. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1308 Mains CN1 N L 1316 to display CN2 Anode 1 n.c. Cathode 1 n.c. Anode 2 n.c. Cathode 2 n.c. Anode 3 n.c. Cathode 3 n.c. Anode 4 n.c. Cathode 4 1M95 to SSB CN4 +3V3stdby Standby GND1 GND1 +12V +12V +Vsnd GND_SND BL-ON-OFF BL-DIM1 (Vsync) BL-I-CTRL POK +24V (AL2_DVBS) GND1 -

+ 12V 2919 m A

7.3

DC/DC Converters
The on-board DC/DC converters deliver the following voltages (depending on set execution): +3V3-STANDBY, permanent voltage for the Stand-by controller, LED/IR receiver and controls; connector 1M95 pin 1 +12V, input from the power supply for TV550 common (active mode); connector 1M95 pins 6, 7 and 8 +24V, input from the power supply for DVB-S2 (in active mode); connector 1M09 pins 1 and 2 +1V1, core voltage supply for PNX855xx; has to be started up first and switched "off" last (diagram B03B) +1V2, supply voltage for analogue blocks inside PNX855xx +1V8, supply voltage for DDR2 (diagram B03B) +2V5, supply voltage for analogue blocks inside PNX855xx (see diagram B03E) +3V3, general supply voltage (diagram B03E) +5V, supply voltage for USB and CAM (diagram B03E) +5V-TUN, supply voltage for tuner (diagram B03E) +V-LNB, input voltage for LNB supply IC (item no. 7T50) +5V-DVBS, input intermediate supply voltage for DVB-S2 (diagram B08A) +3V3-DVBS, clean voltage for silicon tuner and DVB-S2 channel decoder +2V5-DVBS, clean voltage for DVB-S2 channel decoder +1V-DVBS, core voltage for DVB-S2 channel decoder. A +12 V under-voltage detector (see diagram B03C) enables the 12V to 3.3V and 12V to 5V DC/DC converters via the ENABLE-3V3-5V line, and the 12V to 1.8V DC/DC converter via the ENABLE-1V8 line. DETECT2 is the signal going to the

+ 3V 3 dc -dc

+ 3V 3 2 3 71 m A

+ 3V 3

+ 2V 5 s t ab iliz er

+ 2V 5 450 m A

+ 1V 8 dc -dc

+ 1V 8 2450 m A

+ 1V 8

+ 1V 2 s t ab iliz er

+ 1V 2 550 m A

+ 1V 1 dc -dc

+ 1V 1 5100 m A

18770_226_100127.eps 100426

Figure 7-3 DC/DC converters

7.4

Front-End Analogue and DVB-T, DVB-C; ISDB-T reception


Brazil region The Front-End for the Brazil region consist of the following key components: Hybrid Tuner with integrated SAW filter and amplifier External ISDB-T channel decoder covering the Brazilian digital terrestrial TV standard Bandpass filter Amplifier PNX85500 SoC TV with integrated analogue demodulator.

7.4.1

Below find a block diagram of the front-end application for this region.

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Circuit Descriptions

Q552.2L LA

7.

EN 51

18770_236_100127.eps 100219

Figure 7-4 Front-End block diagram Brazil region

7.5

Front-End DVB-S(2) reception


The Front-End for the DVB-S(2) application consist of the following key components: Satellite Tuner; I2C address 0xC6 (bridged via channel decoder) Channel decoder; I2C address 0xD0 LNB switching regulator; I2C address 0x14 Amplifier PNX855xx SoC TV processor with integrated DVB-T and DVB-C channel decoder and analogue demodulator.

18770_243_100203.eps 100203

Figure 7-6 HDMI input configuration The following multiplexers can be used: Sil9187A (does not support Instaport technology for fast switching between input signals) Sil9287B (supports Instaport technology for fast switching between input signals). The hardware default I2C addresses are: Sil9187A: 0xB0/0xB2 (random: software workaround) Sil9287B: 0xB2 (fixed). The Sil9x87 has the following specifications: +5V detection mechanism Stable clock detection mechanism Integrated EDID RT control HPD control Sync detection TMDS output control CEC control EDID stored in Sil9x87, therefore there are no EDID pins on the SSB.

Below find a block diagram of the front-end application for DVB-S(2) reception.

18770_237_100127.eps 100219

Figure 7-5 Front-End block diagram DVB-S(2) reception This application supports the following protocols: Polarization selection via supply voltage (18V = horizontal, 13V = vertical) Band selection via toneburst (22 kHz): tone on = high band, tone off = low band Satellite (LNB) selection via DiSEqC 1.0 protocol Reception of DVB-S (supporting QPSK encoded signals) and DVB-S2 (supporting QPSK, 8PSK, 16APSK and 32APSK encoded signals), introducing LDPC low-density parity check techniques.

7.7

Video and Audio Processing - PNX855xx


The PNX855xx is the main audio and video processor (or System-on-Chip) for this platform. It has the following features: Multi-standard digital video decoder (MPEG-2, H.264, MPEG-4) Integrated DVB-T/DVB-C channel decoder Integrated CI+ Integrated motion accurate picture processing (MAPP2) High definition ME/MC 2D LED backlight dimming option Embedded HDMI HDCP keys Extended colour gamut and colour booster Integrated USB2.0 host controller Improved MPEG artefact reduction compared with PNX8543 Security for customers own code/settings (secure flash).

7.6

HDMI
In this platform, the Silicon Image Sil9x87 HDMI multiplexer is implemented. Refer to figure 7-6 HDMI input configuration for the application.

The TV550 combines front-end video processing functions, such as DVB-T channel decoding, MPEG-2/H.264 decode, analog video decode and HDMI reception, with advanced back-end video picture improvements. It also includes next generation Motion Accurate Picture Processing (MAPP2). The MAPP2 technology provides state-of-the-art motion artifact reduction with movie judder cancellation, motion sharpness
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EN 52

7.

Q552.2L LA

Circuit Descriptions
combination with LED backlights for optimum contrast and power savings up to 50%. For a functional diagram of the PNX855xx, refer to Figure 7-7.

and vivid colour management. High flat panel screen resolutions and refresh rates are supported with formats including 1366 768 @ 100Hz/120Hz and 1920 1080 @ 100Hz/120Hz. The combination of Ethernet, CI+ and H.264 supports new TV experiences with IPTV and VOD. On top of that, optional support is available for 2D dimming in

PNX85500x

MEMORY CONTROLLER

TS input TS out/in for PCMCIA CI/CA

MPEG SYSTEM PROCESSOR

PRIMARY VIDEO OUTPUT

LVDS

LVDS for flat panel display (single, dual or quad channel)

DVB

DVB-T/C channel decoder AV-PIP SUB-PICTURE

CVBS, Y/C, RGB

VIDEO DECODER

3D COMB SECONDARY VIDEO OUTPUT VIDEO ENCODER analog CVBS

Low-IF

DIGITAL IF

MPEG/H.264 VIDEO DECODER

Motion-accurate pixel processing SCALER, DE-INTERLACE AND NOISE REDUCTION AUDIO DACS analog audio

SSIF, LR

AUDIO DEMOD AND DECODE

SPDIF

AUDIO IN AUDIO DSP AUDIO OUT I 2S SPDIF

HDMI

HDMI RECEIVER

450 MHz AV-DSP 560 MHz MIPS32 24KEf CPU DRAWING ENGINE

SYSTEM CONTROLLER (8051)

DMA BLOCK

I2C

PWM GPIO

IR

ADC

SPI

UART

I2C

GPIO Flash USB 2.0 SD Ethernet Memory MAC x8 Card

18770_241_100201.eps 100219

Figure 7-7 PNX855xx functional diagram

7.8

Ambilight
Sets in the xxPFL7606D/xx range are equipped with Ambilight. For the implementation of Ambilight, refer to Figure 7-8.

with the CPLD located on the SSB whereas the Slave Ambilight module communicates via the PWM communication protocol with the Master Ambilight module. The supply voltage of the modules is +24 V. Refer to Figure 7-9 and Figure 7-10 for the Ambilight board implementation.

PNX85500

CPLD

SPI

1 M 9 5

SPI

1 M 8 3

AmbiLight

1 M 8 5

PWM

1 M 8 6

AmbiLight

SSB

19111_009_110519.eps 110519

Figure 7-8 Ambilight configuration The Ambilight implementation consists of 2 separate units in the set, where the Ambilight module located on the right (seen from the back of the set) acts as a Master and the module on the left acts as a Slave. The NVM is located on the Master Ambilight module. This module communicates via the SPI communication protocol
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Circuit Descriptions

Q552.2L LA

7.

EN 53

AMBI-SPI-SDI AMBI-SPI-SDO

EEPROM 1M83
AMBI-SPI-CLK

+24 V

AMBI-SPI-CLK

OR

CS-Local

AMBI-PWM-CLK AMBI-BLANK AMBI-PROG AMBI-LATCH

19111_010_110519.eps 110519

Figure 7-9 Master Ambilight module

PWM-R3 PWM-G3

+24 V +24 V +24 V +24 V +24 V +24 V

1M86

PWM-B3 PWM-R4 PWM-G4 PWM-B4

19111_011_110519.eps 110519

Figure 7-10 Slave Ambilight module

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1M85

LED Driver

PWM-R3 PWM-G3 PWM-B3 PWM-R4 PWM-G4 PWM-B4

EN 54

8.

Q552.2L LA

IC Data Sheets

8. IC Data Sheets
This chapter shows the internal block diagrams and pin configurations of ICs that are drawn as black boxes in the electrical diagrams (with the exception of memory and logic ICs).

8.1

Diagram USB Hub B01C, USB2513B (IC 7F25)

Block diagram
To Upstream VBUS Upstream USB Data 3.3 V 24 MHz Crystal To EEPROM or SMBus Master SDA SCL

BusPower Detect/ Vbus Pulse

Upstream PHY

Regulator

PLL

Serial Interface

Repeater

Serial Interface Engine

Controller

3.3 V Regulator
CRFILT

TT #1

...

TT #x

Port Controller

Routing & Port Re-Ordering Logic

Port #1 PHY#1
OC Sense Switch Driver/ LED Drivers

...

Port #x PHY#x
OC Sense Switch Driver/ LED Drivers

OC USB Data Port Downstream Sense Power Switch/ LED Drivers

USB Data OC Port Downstream Sense Power Switch/ LED Drivers

The x indicates the number of available downstream ports: 2, 3, 4, or 7.


Note : The LED port indicators only apply to USB2513i.
SDA / SMBDATA / NON_REM[1]

SCL / SMBCLK / CFG_SEL[0]

Pinning information
HS_IND / CFG_SEL[1] VBUS_DET RESET_N

VDD33

NC

NC

23

22

27

26

25

24

21

SUSP_IND / LOCAL_PWR / NON_REM[0] VDD33 USBDM_UP USBDP_UP XTALOUT XTALIN / CLKIN PLLFILT RBIAS VDD33

28 29 30 31 32 33 34 35 36

20

19
18 17

NC

NC OCS_N[2] PRTPWR[2] / BC_EN[2]* VDD33 CRFILT OCS_N[1] PRTPWR[1] / BC_EN[1]* TEST VDD33

SMSC USB2512/12A/12B USB2512i/12Ai/12Bi (Top View QFN-36)


Ground Pad (must be connected to VSS)

16 15 14 13 12 11 10

8
NC

USBDM_DN[1]

USBDM_DN[2]

USBDP_DN[1]

USBDP_DN[2]

VDD33

NC

Indicates pins on the bottom of the device.

NC

NC

18770_301_100217.eps 100217

Figure 8-1 Internal block diagram and pin configuration


2011-Jul-15
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IC Data Sheets 8.2 Diagram Temp sensor & headphone B01J, LM75BDP (IC 7FD1)

Q552.2L LA

8.

EN 55

Block diagram
VCC

LM75B
BIAS REFERENCE POINTER REGISTER COUNTER 11-BIT SIGMA-DELTA A-to-D CONVERTER CONFIGURATION REGISTER TEMPERATURE REGISTER TOS REGISTER THYST REGISTER OS

BAND GAP TEMP SENSOR

TIMER COMPARATOR/ INTERRUPT

OSCILLATOR

POWER-ON RESET

LOGIC CONTROL AND INTERFACE

A2

A1

A0

SCL SDA

GND

Pinning information

SDA SCL OS GND

1 2 3 4

8 7

VCC A0 A1 A2
18770_300_100217.eps 100217

LM75BDP

6 5

Figure 8-2 Pin configuration

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2011-Jul-15

EN 56 8.3

8.

Q552.2L LA

IC Data Sheets

Diagram NANDflash - conditional access B02A, PNX855xx (IC7S00)

Block diagram
PNX8550x
MEMORY CONTROLLER

TS input TS out/in for PCMCIA CI/CA

MPEG SYSTEM PROCESSOR

PRIMARY VIDEO OUTPUT

LVDS

LVDS for flat panel display (single, dual or quad channel)

DVB

DVB-T/C channel decoder AV-PIP SUB-PICTURE

CVBS, Y/C, RGB

VIDEO DECODER

3D COMB SECONDARY VIDEO OUTPUT VIDEO ENCODER analog CVBS analog Y/C

Low-IF Direct-IF

DIGITAL IF

MULTISTANDARD VIDEO DECODER

Motion-accurate pixel processing SCALER, DE-INTERLACE AND NOISE REDUCTION AUDIO DACS analog audio

SSIF, LR

AUDIO DEMOD AND DECODE

SPDIF

AUDIO IN AUDIO DSP AUDIO OUT I2S SPDIF

HDMI

HDMI RECEIVER

450 MHz AV-DSP 500 MHz MIPS32 24KEf CPU DRAWING ENGINE Scatter/Gather TS Demux

SYSTEM CONTROLLER (8051)

I2C

PWM Px_x

IR

ADC

SPI

UART

I2C

GPIO Flash USB 2.0 SD Ethernet Memory MAC x 10 Card

Pinning information
ball A1 index area A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Transparent top view
18770_308_100217.eps 100217

PNX8550xE
2 4 6 8 10 12 14 16 18 20 22 24 26 1 3 5 7 9 11 13 15 17 19 21 23 25

Figure 8-3 Internal block diagram and pin configuration

2011-Jul-15

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IC Data Sheets 8.4 Diagram Audio B03A, TPA312xD2PWP (IC7D10)

Q552.2L LA

8.

EN 57

Block diagram
TPA3120D2
1 F LIN RIN 1 F BSR ROUT PGNDR 1 F BYPASS AGND PGNDL LOUT BSL 0.22 F 22 H 470 F 0.68 F 0.68 F 0.22 F 22 H 470 F

PVCCL AVCC PVCCR

VCLAMP Shutdown Control SD 1 F

MUTE GAIN0 GAIN1

}
PGNDL PGNDL LOUT BSL AVCC AVCC GAIN0 GAIN1 BSR ROUT PGNDR PGNDR

Control

Pinning information

PWP (TSSOP) PACKAGE (TOP VIEW)


1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13

PVCCL SD PVCCL MUTE LIN RIN BYPASS AGND AGND PVCCR VCLAMP PVCCR

I_18020_142.eps 100402

Figure 8-4 Internal block diagram and pin configuration

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2011-Jul-15

EN 58 8.5

8.

Q552.2L LA

IC Data Sheets

Diagram DC/DC B03B, TPS53126PW (IC7U03)

Block diagram

Pinning information
VBST1 NC EN1 VO1 VFB1 NC GND TEST1 NC VFB2 VO2 EN2 NC VBST2 1 2 3 4 5 TPS53124 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DRVH1 LL1 DRVL1 PGND1 TRIP1 VIN VREG5 V5FILT TEST2 TRIP2 PGND2 DRVL2 LL2 DRVH2

18310_300_090319.eps 100416

Figure 8-5 Internal block diagram and pin configuration

2011-Jul-15

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IC Data Sheets 8.6 Diagram DC/DC B03E, ST1S10PH (IC 7UD0)

Q552.2L LA

8.

EN 59

Block diagram

ST1S10PH

Pinning information

DFN8 (4 4)

PowerSO-8
I_18010_083.eps 110601

Figure 8-6 Internal block diagram and pin configuration

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2011-Jul-15

EN 60 8.7

8.

Q552.2L LA

IC Data Sheets

Diagram DC/DC B03E, LD1117DT25 (IC 7UD2)

Block diagram

LD1117DT

Pinning information

DPAK

F_15710_166.eps 100402

Figure 8-7 Internal block diagram and pin configuration

2011-Jul-15

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IC Data Sheets 8.8 Diagram Ethernet & Service B04C, LAN8710A-EZKH (IC 7E10)

Q552.2L LA

8.

EN 61

Block diagram
MODE0 MODE1 MODE2 nRST RMIISEL MODE Control Reset Control

AutoNegotiation

10M Tx Logic

10M Transmitter

HP Auto-MDIX
TXP / TXN RXP / RXN

Transmit Section Management Control 100M Tx Logic 100M Transmitter MDIX Control

SMI

TXD[0:3] TXEN TXER TXCLK RMII / MII Logic RXD[0:3] RXDV RXER RXCLK CRS COL/CRS_DV MDC MDIO

100M Rx Logic

DSP System: Clock Data Recovery Equalizer

Analog-toDigital

PLL Interrupt Generator

XTAL1/CLKIN XTAL2 nINT

Receive Section 10M Rx Logic 10M PLL

100M PLL LED Circuitry Squelch & Filters Central Bias PHY Address Latches
LED1 LED2

RBIAS

PHYAD[0:2]

Pinning information
RBIAS VDD1A RXDV 26 RXN RXP TXN TXP TXD3 25 24 23

32

30

29

31

VDD2A LED2/nINTSEL LED1/REGOFF XTAL2 XTAL1/CLKIN VDDCR RXCLK/PHYAD1 RXD3/PHYAD2

1 2 3 4 5 6 7 8 13 10 12 11 9 14 15 16

28

27

TXD2 TXD1 TXD0 TXEN TXCLK nRST nINT/TXER/TXD4 MDC

SMSC LAN8710/LAN8710i 32 PIN QFN (Top View)


VSS

22 21 20 19 18 17

RXD1/MODE1

RXD0/MDE0

RXD2/RMIISEL

CRS

COL/CRS_DV/MODE2

VDDIO

RXER/RXD4/PHYAD0

MDIO

18770_302_100217.eps 100217

Figure 8-8 Internal block diagram and pin configuration

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2011-Jul-15

EN 62 8.9

8.

Q552.2L LA

IC Data Sheets

Diagram HDMI B04D, SII9x87B (IC 7EC1)

Block diagram

Pinning information

18770_303_100217.eps 100217

Figure 8-9 Internal block diagram and pin configuration

2011-Jul-15

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IC Data Sheets 8.10 Diagram Headphone B04E, TPA6111A2DGN (IC 7EE1)

Q552.2L LA

8.

EN 63

Block diagram
VDD 8

VDD/2 2 IN 1 + VO1 1

BYPASS TPA6111A2

IN 2 + SHUTDOWN

VO2 7

Bias Control

Pinning information
D OR DGN PACKAGE (TOP VIEW)

VO1 IN1 BYPASS GND

1 2 3 4

8 7 6 5

VDD VO2 IN2 SHUTDOWN


18770_309_100217.eps 110602

Figure 8-10 Internal block diagram and pin configuration

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2011-Jul-15

EN 64

8.

Q552.2L LA

IC Data Sheets

Personal Notes:

10000_012_090121.eps 090121

2011-Jul-15

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Block Diagrams

Q552.2L LA

9.

EN 65

9. Block Diagrams
9-1 Wiring diagram Blockbuster/Emmy 32"
WIRING DIAGRAM 32" BLOCKBUSTER / EMMY

8M85 8M95

TO DISPLAY SUPPLY

8M59

1316 10P

1M95 14P

18P 1M86

1M95 14P

1M59 26P

LOUDSPEAKER
1G50 41P

(5213)

SSB
3139 123 6521.x (1150)

MAIN POWER SUPPLY 32" PLDC-P005A


(1005)
*AMBILIGHT MODULE *AMBILIGHT MODULE

1D38

USB

(1162)

1G51

AL

8G51

TUNER

PHONE HDMI

2P 130 8

51P

41P

SPDIF

SPDIF

TO DISPLAY

TO DISPLAY

ETHER NET

LCD DISPLAY (1004)

1M19

HDMI

HDMI

HDMI

VGA

LOUDSPEAKER

LOUDSPEAKER

(5216)

8308

INLET

MAINS SWITCH (8308)

C2

C1

*AMBILIGHT ONLY APLICABLE FOR EMMY STYLING

IR/LED/CONTROL BOARD

J1 8P

(1108)
1308 (PSU)
1. N 2. L

1316 (PSU) 1. ANODE 1 2. NC 3. CATHODE 1 4. GND 5. ANODE 2 6. NC 7. CATHODE 2 8. NC 9. ANODE 3 10. NC 11. CATHODE 3 12. NC 13. ANODE 4 14. NC 15. CATHODE 4

1M95 (PSU)
1. +3V3STDBY 2. STANDBY 3. GND 4. GND 5. +12V 6. +12V 7. +VSND 8. GND_SND 9. BL-ON-OFF 10. BL-DIM1 11. BL-I-CTRL 12. POK 13. +24V 14. GND1

LEADING EDGE

1M95 (B03C) 1. +3V3-STANDBY 2. STANDBY 3. GND 4. GND 5. +12VIN 6. +12VIN 7. +24V-AUDIO-POWER 8. GND 9. LAMP-ON 10. BACKLIGHT-PWM_BL-VS 11. BACKLIGHT-BOOST 12. POWER-OK 13. +24V 14. GND

173 1D 38 5 (B0 (B0 3 3 A) A)


1. 2. 3. 4. LEFT-SPEAKER GND-AUDIO RIGHTGND-AUDIO SPEAKER RIGHT-SPEAKER

1M19 (B09A)
1. 2. 3. 4. 5. 6. 7. 8. LIGHT-SENSOR GND RC LED-2 +3V3-STANDBY LED-1 KEYBOARD +5V

1M59 (B09A)
1. AMBI-SPI-CLK-OUT 2. GND 3. AMBI-SPI-SDO-OUT 4. AMBI-SPI-SDI-OUT-GI 5. V-AMBI 6. AMBI-PWM-CLK_B2 7. GND 8. AMBI-SPI-CS-OUTn_R2 9. AMBI-LATCH1_G2 10. V-AMBI 11. AMBI-BLANK_R1 12. AMBI-PROG_B1 13. AMBI-LATCH2_DIS 14. AMBI-TEMP 15. GND_AL 16. GND_AL 17. GND_AL 18. GND_AL 19. GND_AL 20. N.C. 21. +24V 22. +24V 23. +24V 24. +24V 25. +24V 26. +24V

1G51 (B06B) 1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51. CTRL-DISP

19110_008_110323.eps 110711

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(5216)

1M83 26P

8P

AL

51P

(1161)

8G50

SD-CARD READER

3P

1M85 18P

Block Diagrams

Q552.2L LA

9.

EN 66

9-2 Wiring diagram Blockbuster/Emmy 40" - 46"


WIRING DIAGRAM 40"- 46" BLOCKBUSTER / EMMY

TO DISPLY SUPPLT

1316 10P

1M99

14P

1M86

8M95
1M85

18P

1G50

MAIN POWER SUPPLY 40" PLDE-P008A 46" PLDG-P010A


(1005)

1M95 14P

1M59 26P

41P

*AMBILIGHT MODULE 24 LED

3139 123 6521.x (1150)

*AMBILIGHT MODULE 24 LED


1M83

SSB

8M59

1308

2P

1G51

USB

SD-CARD READER

1D38

3P

(1162)

PHONE

AL

8G50
1M19 8P
ETHER NET SPDIF SPDIF

HDMI

HDMI

HDMI

VGA

TO DISPLAY 51P

LCD DISPLAY (1004)

TO DISPLAY 41P

8308

INLET LOUDSPEAKER
(5216)
MAINS SWITCH (8308)

LOUDSPEAKER
(5216)
C2 C1

*AMBILIGHT ONLY APLICABLE FOR EMMY STYLING

IR/LED/CONTROL BOARD

J1 8P

1316 (PSU)
1. ANODE 1 2. NC 3. CATHODE 1 4. GND 5. ANODE 2 6. NC 7. CATHODE 2 8. NC 9. ANODE 3 10. NC 11. CATHODE 3 12. NC 13. ANODE 4 14. NC 15. CATHODE 4

1M95 (PSU)
1. +3V3STDBY 2. STANDBY 3. GND 4. GND 5. +12V 6. +12V 7. +VSND 8. GND_SND 9. BL-ON-OFF 10. BL-DIM1 11. BL-I-CTRL 12. POK 13. +24V 14. GND1

1308 (PSU)
1. N 2. L

(1108)
LEADING EDGE

1M95 (B03C)
1. +3V3-STANDBY 2. STANDBY 3. GND 4. GND 5. +12VIN 6. +12VIN 7. +24V-AUDIO-POWER 8. GND 9. LAMP-ON 10. BACKLIGHT-PWM_BL-VS 11. BACKLIGHT-BOOST 12. POWER-OK 13. +24V 14. GND

1D38 (B03A)
1. LEFT-SPEAKER 2. GND-AUDIO 3. RIGHT-SPEAKER

1G51 (B06B)
1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51. CTRL-DISP

1M59 (B09A)
1. AMBI-SPI-CLK-OUT 2. GND 3. AMBI-SPI-SDO-OUT 4. AMBI-SPI-SDI-OUT-GI 5. V-AMBI 6. AMBI-PWM-CLK_B2 7. GND 8. AMBI-SPI-CS-OUTn_R2 9. AMBI-LATCH1_G2 10. V-AMBI 11. AMBI-BLANK_R1 12. AMBI-PROG_B1 13. AMBI-LATCH2_DIS 14. AMBI-TEMP 15. GND_AL 16. GND_AL 17. GND_AL 18. GND_AL 19. GND_AL 20. N.C. 21. +24V 22. +24V 23. +24V 24. +24V 25. +24V 26. +24V

1M19 (B09A)
1. 2. 3. 4. 5. 6. 7. 8. LIGHT-SENSOR GND RC LED-2 +3V3-STANDBY LED-1 KEYBOARD +5V

19110_009_110323.eps 110711

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26P

AL

(5213)

HDMI

LOUDSPEAKER

8G51

TUNER

(1161)

51P

18P

Block Diagrams

Q552.2L LA

9.

EN 67

9-3 Wiring diagram Sundance 42" - 47"


WIRING DIAGRAM 42"- 47" SUNDANCE
LED POWER

8M84

TS
1T02
1M09 4P

TEMP. SENSOR
(1027)

1316 10P

1319 10P

8M71

1M83

8M99 8M95
1M95 1M99 4P

26P

4P

1M71 4P

1M59 26P

MAIN POWER SUPPLY 42" - 47" PLDHP018A


(1005)
1G50

1M99

14P

14P

B
41P

SSB
3139 123 6521.x (1150)

AMBILIGHT MODULE

(5213)

AMBILIGHT MODULE
1M83

LOUDSPEAKER

1D38

1308

2P

3P

(1163)

1G51

51P

TUNER

AL

1M20

11P

ETHER NET

8G51

8308

8M21
TO DISPLAY 41P

INLET

LCD DISPLAY (1004)

TO DISPLAY 51P

LOUDSPEAKER
(5216)
MAINS SWITCH (8308)

LOUDSPEAKER
CN1 CN2

(5217)

IR/LED/CONTROL BOARD

J1 11P

WIFI MODULE

(1108)

(1115)

1D38 (B03A)
1. LEFT-SPEAKER 2. GND-AUDIO 3. RIGHT-SPEAKER

1735 (B03A)
1. 2. 3. 4. LEFT-SPEAKER GND-AUDIO GND-AUDIO RIGHT-SPEAKER

1G51 (B06B)
1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51. N.C.

1M71 (B09A)
1. 2. 3. 4. SCL-BL GND SDA-BL +3V3

1M99 (B03C) 1. GND_AL 2. +12V_AL 3. GND_AL 4. +12V_AL

1M20 (B09A) 1. LIGHT-SENSOR 2. LED-1 3. LED-2 4. GND 5. KEYBOARD 6. +3V3-STANDBY 7. RC 8. +5V 9. SCL-SET 10. GND 11. SDA-SET

1M95 (B03C) 1. +3V3-STANDBY 2. STANDBY 3. GND 4. GND 5. +12VIN 6. +12VIN 7. +24V-AUDIO-POWER 8. GND 9. LAMP-ON 10. BACKLIGHT-PWM_BL-VS 11. BACKLIGHT-BOOST 12. POWER-OK 13. +24V 14. GND

1M59 (B09A)
1. AMBI-SPI-CLK-OUT 2. GND 3. AMBI-SPI-SDO-OUT 4. AMBI-SPI-SDI-OUT-GI 5. V-AMBI 6. AMBI-PWM-CLK_B2 7. GND 8. AMBI-SPI-CS-OUTn_R2 9. AMBI-LATCH1_G2 10. V-AMBI 11. AMBI-BLANK_R1 12. AMBI-PROG_B1 13. AMBI-LATCH2_DIS 14. AMBI-TEMP 15. GND_AL 16. GND_AL 17. GND_AL 18. GND_AL 19. GND_AL 20. N.C. 21. +12V_AL 22. +12V_AL 23. +12V_AL 24. +12V_AL 25. +12V_AL 26. +12V_AL 19110_063_110711.eps 110711

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26P

8G50

HDMI

HDMI HDMI

VGA

HDMI

AL

USB

(1163)

USB

26P

8M59

1M84

Block Diagrams

Q552.2L LA

9.

EN 68

Block Diagram Video


VIDEO
B01F TUNER B01K TUNER BRASIL
7FE0 TC90517FG 58 59 61 60 18 25M4 1FE0 TS-FE-VALID TS-FE-SOP TS-FE-CLOCK TS-FE-DATA

B02 PNX85500
7S00 PNX85537EB B02A VIDEO STREAM R23 TNR_SER1_MIVAL R22 TNR_SER1_SOP T22 TNR_SER1_MICLK T21 TNR_SER1_DATA B02F LVDS

B06B VIDEO OUT - LVDS


1G50 1 2 3 LOUT1 PX1

1T01 FA2327

4MHZ_REF

IF AGC 3F80 3F81 IFIF+

DEMODULATOR (ISDB-T)

MAIN HYBRID TUNER

9 29 30

TO DISPLAY
LOUT2 PX2

3 41

19

RF IN B02I ANALOG VIDEO 42 2F75 2F79 RESET-SYSTEMn B02E AE12 AF12 N.C.

IF-OUT1 IF-OUT2

10 11

TUN-IF-P TUN-IF-N

PNX-IF-P

BANDPASS FILTER

TUNER_P N.C. TUNER_N

1G51 51 50 49 40

PNX-IF-N

I2C

PNX-IF-AGC

AD12

IF_AGC LOUT3 PX3

B01H HDMI

B04D HDMI
*7EC1 SII9187BC SII9287BC 1P05 1 3 DRX2+ DRX2DRX1+ DRX1DRX0+ DRX0DRXC+ DRXC26 25 24 23 RXD 22 21 20 19

B04A ANALOGUE EXTERNALS A


TO DISPLAY

PNX85537

1E01 YPBPR1-PR YPBPR1-SYNCIN1 YPBPR1-PB 3E90 3E87 3E89 AV3-PR AV3-Y AV3-PB AC15 AE15 AD15 PR_R_C1 Y_G1 PB_B1

LOUT4

PX4

40 4 3 2 +VDISP 1

YPBPR

1 2

4 6 7 9 10 12

19 18

B01C USB HUB


B02E CONROL 9F26 9F25 USB1-DM USB1-DP
+5V-USB1 1P08 1

HDMI SIDE CONNECTOR

B04B ANALOGUE EXTERNALS B

1P04 1
1 2

ARX2+ ARX2ARX1+ ARX1ARX0+ ARX0ARXC+ ARXCOPTIONAL

72 71 70

3 4 6 7 9 10 12

VIDEO

AV2-CVBS

AB14

CVBS-_Y2

R25

69 RXA 68 67 66 65

SIDE USB CONNECTOR

B02A FLASH

B01B FLASH
7F20 H27U4G8F2DTR-BC 17 18 XIO_D XIO-D(00-07) E21 NAND-CE1n F21 NAND-RDY1n NAND-WPn A21 9 7 19 1FL5 21 24M

19 18

7FL5 CY7C65631

B01I VGA
8 7 6 5 RXB 4 3 2 1
10 15 5

13 14

1P03 1 3
1 2

BRX2+ BRX2BRX1+ BRX1BRX0+ BRX0BRXC+ BRXC-

NAND FLASH

USB2-DM USB2-DP

2 3 4

1E05 1 2 3 13 14 R-VGA G-VGA B-VGA H-SYNC-VGA V-SYNC-VGA AF16 VGA_R AD16 VGA_G AE16 VGA_B AB18 HSYNC_IN AC18 VSYNC_IN

4 6 7 9 10 12

NAND_CE1 NAND_RDY1 NAND_WP_

22 42 VCC 21,37 +3V3 RESET-USBn

SIDE USB CONNECTOR

B02G

19 18

11

HDMI 2 CONNECTOR

B02B MEMORY VREF_1 VREF_2

VGA CONNECTOR

A2 V1

DDR2-VREF-CTRL2 DDR2-VREF-CTRL3

ONLY FOR 8000 SERIE

1P02 1 3
1 2

B05A DDR
CRX2+ CRX2CRX1+ CRX1CRX0+ CRX0CRXC+ CRXC18 17 16 15 14 13 12 11 9,27,64 RXC 62 TXC_P 63 TXC_N 60 TX0_P 61 TX0_N 58 TX1_P TX1_N TX2_P TX2_N 59 56 57 HDMIA-RXC+ HDMIA-RXCHDMIA-RX0+ HDMIA-RX0HDMIA-RX1+ HDMIA-RX1HDMIA-RX2+ HDMIA-RX23S0W +3V3 B02C HDMI_DV W25 RXC_A_P W26 RXC_A_N V25 RX2_A_P V26 RX2_A_N U25 RX1_A_P U26 RX1_A_N T25 RX0_A_P T26 RX0_A_N W24 RREF A DQ D(16-23) D(24-31) D(8-15) D(0-7)
7B00 H5PS1G83E 7B02 H5PS1G83E 7B03 H5PS1G83E

4 6 7 9 10 12

DDR2-D(0-31)
7B01 H5PS1G83E

19 18

HDMI 1 CONNECTOR

SDRAM 128Mx8
VDDL VREF

SDRAM 128Mx8
VDDL VREF

SDRAM 128Mx8
VDDL VREF

SDRAM 128Mx8
VDDL VREF

+3V3-HDMI

VCC33

A1 E2

A1 E2

A1 E2

A1 E2 DDR2-A(0-14) +1V8

*6000/7000 SERIE MUX SII9187 NON INSTAPORT 8000 SERIE MUX SII9287 INSTAPORT

DDR2-VREF-DDR

19110_005_110309.eps 110321

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3 2

HDMI 3 CONNECTOR

USB HUB

9 10

+5V-USB2 1P07 1

HDMI SWITCH

1E08

USB_DN USB_DP

R26

USB-DM USB-DP

2 3

3 2

Block Diagrams

Q552.2L LA

9.

EN 69

9-4 Block Diagram Audio


AUDIO
B01F TUNER B01K TUNER BRASIL
7FE0 TC90517FG 58 59 61 60 18 25M4 1FE0 TS-FE-VALID TS-FE-SOP TS-FE-CLOCK TS-FE-DATA

B02 PNX85500
7S00 PNX85537EB

B02D PNX85500: AUDIO B03A AUDIO


7D10 TPA3123D2PWP

1T01 FA2327

B02A VIDEO STREAM R23 TNR_SER1_MIVAL R22 TNR_SER1_SOP T22 TNR_SER1_MICLK T21 TNR_SER1_DATA 7S05 LM324P B02D AUDIO ADAC_1 AD7 ADAC(1) 12 14 +AUDIO-L 5

CLASS D POWER AMPLIFIER


IN-L PVCC_L PVCC_R OUT-L 6 IN-R 5D07 10,12 5D08 1,3 22 +24V-AUDIO-POWER 1735 1 2 3 15 RIGHT-SPEAKER 4 RES 7D03 STANDBY & PROTECTION 1D38 1 5D03 2 3 SPEAKERS

4MHZ_REF

IF AGC 3F80 3F81 IFIF+

9 29 30

DEMODULATOR (ISDB-T)

MAIN HYBRID TUNER

LEFT-SPEAKER

ADAC_2 B02G STANDBY

AE7

ADAC(2)

10

8 7D15 A-PLOP

-AUDIO-R A-PLOP

19

RF IN 42 2F75 2F79 RESET-SYSTEMn B02I ANALOG VIDEO B02E AE12 AF12

B04E 4 MUTE OUT-R

PO_7 TUNER_P TUNER_N

AC19

AUDIO-MUTE-UP A-STBY 7D11 MAINS SWITCH DETECT

IF-OUT1 IF-OUT2

10 11

TUN-IF-P TUN-IF-N

PNX-IF-P

BANDPASS FILTER

SD

PNX-IF-N

B03C PNX-IF-AGC AD12 IF_AGC

DETECT2

A-STBY

B01H HDMI

B04D HDMI
*7EC1 SII9187BCNU SII9287BCNU

B04A ANALOGUE EXTERNALS A


1E02 4 AUDIO-IN1-L AUDIO-IN1-R

B02D AUDIO

B04E HEADPHONE
7EE0-1 PO_6 AB19 RESET-AUDIO 7EE0-2 A-PLOP B03A B04A 7EE1 TPA6111A2DGN HEADPHONE AMPLIFIER 5 SHUTDOWN VO_1 2 IN-1 VO_2 VDD 1 7 8

B01J TEMP SENSOR + HEADPHONE

1P05 1 3
1 2

AE10 AIN1_L AF10 AIN1_R

DRX2+ DRX2DRX1+ DRX1DRX0+ DRX0DRXC+ DRXC-

26 25 24 23 RXD 22 21 20 19

AUDIO IN L+R

4 6 7 9 10 12

PNX85537

19 18

1328

B04B ANALOGUE EXTERNALS B

B02D PNX85500: AUDIO

AMP1 AMP2

2 3 1 HEADPHONE OUT 3.5mm

HDMI SIDE CONNECTOR

ADAC3

AF7

ADAC(3)

1P04 1
1 2

HDMI SWITCH
ARX2+ ARX2ARX1+ ARX1ARX0+ ARX0ARXC+ ARXCOPTIONAL 72 71 69 68 RXA 67 66 65 70 VGA AUDIO AUDIO IN L+R

1E08 6 4 AUDIO-IN3-L AUDIO-IN3-R AE9 AF9 AIN3_L AIN3_R

AD6 ADAC4

ADAC(4)

IN-2

+3V3

3 4 6 7 9 10 12

B01C USB HUB


B02E CONROL R26 R25 USB-DM USB-DP 9F26 9F25 USB1-DM USB1-DP
+5V-USB1 1P08 1
1

1E09

19 18

AIN4_L AIN4_R

HDMI 3 CONNECTOR

3 1

B01B FLASH
7F20 H27U4G8F2DTR-BC B02A FLASH XIO_D XIO-D(00-07) E21 NAND-CE1n F21 NAND-RDY1n NAND-WPn A21 9 7 19 17 18

7FL5 CY7C65631 9

1P03 1 3
1 2

BRX2+ BRX2BRX1+ BRX1BRX0+ BRX0BRXC+ BRXC-

8 7 6 5 RXB 4 3 2 1 DIGITAL AUDIO OUT

1E10

4 6 7 9 10 12

8000 SERIES 1E07 1 SPDIF-OUT

1FL5

4 B02G STANDBY 8 5 SEL-HDMI-ARC AF18 P0_4

HDMI 2 CONNECTOR

NAND_CE1 NAND_RDY1 NAND_WP_

6000/7000 SERIES +3V3-HDMI 1P02 1 3 CRX2+ CRX2CRX1+ CRX1CRX0+ CRX0CRXC+ CRXC9,27,64 VCC33

VCC

21,37

+3V3 42 RESET-USBn B02G ONLY FOR 8000 SERIE

B02C HDMI_DV 18 17 16 15 RXC 14 13 12 11 62 TXC_P 63 TXC_N 60 TX0_P 61 TX0_N 58 TX1_P 59 TX1_N 56 TX2_P 57 TX2_N 5EC2 eHDMI+ HDMIA-RXC+ HDMIA-RXCHDMIA-RX0+ HDMIA-RX0HDMIA-RX1+ HDMIA-RX1HDMIA-RX2+ HDMIA-RX23S0W +3V3 W25 RXC_A_P W26 RXC_A_N V25 RX2_A_P V26 RX2_A_N U25 RX1_A_P U26 RX1_A_N T25 RX0_A_P T26 RX0_A_N W24 RREF B02B MEMORY DQ D(16-23) D(24-31) D(8-15) D(0-7)
7B00 H5PS1G83EFR 7B02 H5PS1G83EFR 7B03 H5PS1G83EFR

B05A DDR
DDR2-D(0-31)
7B01 H5PS1G83EFR

1 2

4 6 7 9 10 12 14

19 18

HDMI 1 CONNECTOR

SDRAM 128Mx8
VDDL VREF

SDRAM 128Mx8
VDDL VREF

SDRAM 128Mx8
VDDL VREF

24M

SPDIF-OUT-PNX

AF5

NAND FLASH

14 21

19 18

SPDIF_OUT

22

SDRAM 128Mx8
VDDL VREF

ARC-eHDMI+

A1 E2 A

A1 E2

A1 E2

A1 E2 DDR2-A(0-14) +1V8

VREF_1 VREF_2 *6000/7000 SERIE MUX SII9187 NON INSTAPORT 8000 SERIE MUX SII9287 INSTAPORT

A2 V1

DDR2-VREF-DDR DDR2-VREF-CTRL2 DDR2-VREF-CTRL3

3 2

2 1 3

+3V3

SPDIF-OPT 7S09 74LVC00 2 3 & 1

+3V3

13

USB2-DM USB2-DP

2 3

USB HUB

10

+5V-USB2 1P07 1

AUDIO-IN4-R

AC9

3 2

AUDIO-IN4-L

AD9

USB_DN USB_DP

2 3

USB 1 SIDE CONNECTOR

USB 2 SIDE CONNECTOR

19110_006_110309.eps 110321

2011-Jul-15 back to

div. table

Block Diagrams

Q552.2L LA

9.

EN 70

9-5 Block Diagram Control & Clock Signals


CONTROL + CLOCK SIGNALS
B01D
SD-CARD

B02A
1P09 1 2
Pin1

PNX85500
B02B MEMORY

B05A
DQ

DDR

7S00 PNX85537EB B02E ETHERNET


SDIO-DAT3 SDIO-CMD SDIO-CLK SDIO-DAT0 SDIO-DAT1 SDIO-DAT2 SDIO-CDn SDIO-WP W2 CC_DAT3 W6 CMD W1 CLK W5 DAT_0 W4 DAT_1 W3 DAT_2 U6 SDCD V6 SDWP

DDR2-D(0-31) D(16-23) D(24-31) D(8-15) D(0-7)


7B00 H5PS1G83EFR 7B02 H5PS1G83EFR 7B03 H5PS1G83EFR 7B01 H5PS1G83EFR

Pin9

5 7 8 9 10 12

Pin4

Pin3

Pin2

SDRAM 128Mx8

SDRAM 128Mx8

SDRAM 128Mx8

SDRAM 128Mx8

SD-CARD CONNECTOR

Pin 8 Pin7

Pin6 Pin5

F8 E8

F8 E8 DDR-CLK_N DDR-CLK_P

F8 E8 DDR2-A(0-13)

F8 E8

B04C

ETHERNET + SERVICE
7E10 LAN8710A-EZK 1N00 1 2 3 6 ETHERNET CONNECTOR RJ45 19

A CLK_N CLK_P ETH-RXD ETH-TXD 7 20 5 1E70 25M ETH-RXCLK ETH-TXCLK AA3 AA2 RXD TXD RXCLK TXCLK B02H POWER AF1 VDD_1V1 AA15 VDDA_1V2 N5 N4

ETH-TXP ETH-TXN ETH-RXP ETH-RXN

29 28 31 30

ETHERNET

B06C

AMBILIGHT CPLD
B03B B03D 5 41 40 39

7GA0 XC9572XL

B09A

NON DVBS CONNECTOR BOARD

SENSE+1V1 SENSE+1V2

22

AMBI-SPI-CLK-OUT AMBI-SPI-SDO-OUT AMBI-SPI-SDI-OUT_G1 AMBI-PWM-CLK_B2 AMBI-SPI-CS-OUTn_R2 AMBI-LATCH1_G2 AMBI-BLANK_R1 AMBI-PROG_B1 AMBI-LATCH2_DIS AMBI-TEMP

1M59 1

PNX-SPI-CSBn B02E CONTROL PNX-SPI-CLK PNX-SPI-SDI PNX-SPI-SDO B02G

CPLD

27 23 29 30 31 20 19 28 32

3 4 6 8 9 11 12 13 14

4 RESET-ETHERNETn

TO AMBILIGHT MODULE

B1K

TUNER BRASIL
7FJ0 CXD2820R 4 3 5 7 19 25M4 1FE0 TS-FE-VALID TS-FE-SOP TS-FE-CLOCK TS-FE-DATA

B02A VIDEO STREAM


GPIO_1

Y22 AC5 V22

B02G

3D-LR

7 43 3 VCCIO 26

PNX85537

CLK_54_OUT GPI0_7

PXCLK54 PNX-SPI-CS-BLn

B01F B01F

DEMODULATOR (ISDB-T)

IF+ IF-

30 29

R23 TNR_SER1_MIVAL R22 TNR_SER1_SOP T22 TNR_SER1_MICLK T21 TNR_SER1_DATA

VIO BACKLIGHT-PWM_BL-VS B03C

BL_PWM

AD5

BACKLIGHT-PWM

9GA0

OPTIONAL

B02E

PNX85500: MIPS

B01C

USB HUB
3 2

18

+5V-USB1 1P08 1

B02E

RESET-SYSTEMn

USB_DN USB_DP

R26 R25

USB-DM USB-DP RESET-SYSTEMn SELECT-SAW

9F25 ONLY FOR 6000/7000 SERIE 7FL5 CY7C65631

4 B01K B02G B01F

B01B

FLASH
7F20 H27U4G8F2DTR B02A FLASH

AE4 RESET_SYS U23 GPI0_11

SIDE USB CONNECTOR

B04C

ETHERNET + SERVICE
17 18
1E06

NAND FLASH

9 7 19

NAND-CE1n NAND-RDY1n NAND-WPn

E21 NAND_CE1 F21 NAND_RDY1 A21 NAND_WP_

USB HUB

9
1

10

GPI0_2 GPI0_3

Y23 Y24

RXD1-MIPS TXD1-MIPS

2 3 1 UART SERVICE CONNECTOR 1FL5

21 24M

13 14

USB-DM2 USB-DP2

2 3 4

XIO-D(00-07) VCC 12,37

XIO_D

SIDE USB CONNECTOR

22 ONLY FOR 8000 SERIE

+3V3

B09A

CONNECTORS COMP
*1M20 1 4 7 3 1M19 1 2 3 4 5 6 7 8 +5V SUNDANCE / INFINITY +3V3-STANDBY LED-1

B03C

DC / DC
LIGHT-SENSOR RC AE26 AD19 AC25 AD26 AD23

B02G STANDBY V23

B02G
GPIO_10

PNX85500: STANDBY CONTROLLER


BOOST-PWM

B01E

PNX85500-CONTROL
BACKLIGHT-BOOST

9CH0

P5_1 P1_0 PWM_1 PWM_0 P5_0

B03C

B06C 7F52 M25P05-AVMN6P SPI_CLK P6_5 SPI_CSB SPI_SDO SPI_SDI P3_0 P3_1 AF24 AE22 AF23 AE23 AF25 PNX-SPI-CLK PNX-SPI-WPn PNX-SPI-CSBn PNX-SPI-SDO PNX-SPI-SDI 6 3 1 5 2

LED-2

9U41 7U43

LED2 LED1 KEYBOARD

TO IR / LED BOARD AND KEYBOARD CONTROL

6 2 5 8

FLASH
VCC 8 +3V3-STANDBY

512K
1F51 3 FF04 SDM FF29 SPI-PROG 1 LEVEL SHIFTED 2 FOR DEBUG USE 4 ONLY 5

B02G

PNX85500: STANDBY CONTROLLER


B03C B02E B03H DETECT2 RESET-SYSTEMn LCD-PWR-ONn AA22 AB22 AC20 P3_2 P3_3 P2_0

P1_7 RESET_IN P6_4 XTAL_IN

AE21 AF21 AB20 AA26


AF22 AE17 1S02

RXD-UP TXD-UP
SDM RESET-STBYn SPI-PROG +3V3-STANDBY 7S20 NCP303LSN28G 2 3 INP OUTP GND 1 RESET-STBYn

3 2

+5V-USB2 1P07 1

9F26

USB-DM1 USB-DP1

2 3

RES
ENABLE-3V3-5V ENABLE-1V8 DETECT2

54M

B03C

DC / DC

CONTROL

XTAL_OUT

AF17 AD18 AD21 AF18 AE20 AE18 AC21 AF20 AB19 AC19

B03E B03B B03D B02G B03A

B04D

HDMI
TO PIN: 1P02-13 1P03-13 PCEC-HDMI 1P04-13 1P05-13 ARX-HOTPLUG 1P02-19 BRX-HOTPLUG 1P03-19 CRX-HOTPLUG 1P04-19 DRX-HOTPLUG 1P05-19 31 35 41 45 7EC0 EF 7EC1 SII9187BCNU SII9287BCNU P1_1 CEC-HDMI AF19 P1_2 P2_7 P0_4 P2_2 P0_3 P2_6 P2_3 RREF P0_6 P0_7

RESET-USBn ENABLE-3V3n SEL-HDMI-ARC LAMP-ON RESET-ETHERNETn POWER-OK STANDBY RESET-AUDIO AUDIO-MUTE-UP

B01C

+12V +3V3-STANDBY

B02D B06C B04C B01E BACKLIGHT-PWM_BL-VS BACKLIGHT-BOOST

B02C HDMI_DV HDMIA-RX 3S0W +3V3 RX

4x HDMI CONNECTOR

HDMI SWITCH

1M95 9 10 TO 11 POWER SUPPLY 12 2

19 18

1 2

W24

B04E B03A 19110_007_110318.eps 110321

2011-Jul-15 back to

div. table

Block Diagrams

Q552.2L LA

9.

EN 71

9-6 Block Diagram I2C


IC
B01E
PNX85500: CONTROL

B02E

PNX85500: MIPS 7S00 PNX85537EB 3S6D B02E B25 3_SDA 3_SCL A24 3S5Z +3V3 3S6A 3S5Y +3V3 3S6E

B01E

PNX85500-CONTROL

B01J

TEMP SENSOR + HEADPHONE

B04D

HDMI

B01K

TUNER BRAZIL

SDA-SSB SCL-SSB 3EC5 3FD3 3FD4 3EC3 AIN-5V 3EC1-3 3EC1-1 54 29 30 BIN-5V 3ECA-1 3ECA-2 3FE8 16 15
19 18

PNX85537
CONTROL C25 1_SDA 7F52 M25P05-AVMN6P 1_SCL B02G PNX-SPI-CLK PNX-SPI-WPn PNX-SPI-CSBn PNX-SPI-SDO PNX-SPI-SDI AF24 SPI_CLK AE22 P6_5 AF23 SPI_CSB AE23 SPI_SDO AF25 SPI_SDI C26

ERR 13

53 7EC1 SII9287B SII9187A HDMI MUX


ERR 23

3FE9

46

45

3S69

1P04 ARX-DDC-SDA ARX-DDC-SCL 16 15 7FE0 TC90517FG DEMODULATOR


1 2

3S56 3S57

SDA-UP-MIPS SCL-UP-MIPS 3F60

7FD1 LM75BDP TEMP SENSOR 6


ERR 42

B02G

PNX85500: STANDBY CONTROLER +3V3-STANDBY

3F59

HDMI CONNECTOR 3
1P03 BRX-DDC-SDA BRX-DDC-SCL 16 15
1 2

+3V3-STANDBY

FLASH
VCC

6 3 1 5 2

STANDBY 3S6W 3S6V


ERR 15 ERR 53

512K
STANDBY SW

7F58 M24C64 EEPROM (NVM) RES


ERR 35

33 34

AC23 MC_SDA MC_SCL AC24

3S2F 3S2G

RES
3ECA-3 3F63 3F62 1F52 3 1 DEBUG ONLY 39 40

CIN-5V 3ECA-4

HDMI CONNECTOR 2
1P02 CRX-DDC-SDA CRX-DDC-SCL 16 15
19 18 1 2

19 18

19 18

B01H

HDMI

+3V3-STANDBY 3S1G 3S1H

B01B

FLASH AE21 7F20 H27U4G8F2DTR P3_0 P3_1 B02A FLASH XIO-D(00-07) MAIN SW Y23 GPIO_2 GPIO_3 B02I Y24 XIO_D DDC_A_SCL HDMI_DV B02C DDC_A_SDA Y26 AF21

MAIN NVM SW RXD-UP TXD-UP 3F65 3F64

DIN-5V 3FBF-2 3FBF-1

1F51 3

3ECU-2

FLASH (4Gx16)

RES
Y25 DDCA-SDA DDCA-SCL +3V3

3ECU-4

uP LEVEL SHIFTED FOR DEBUG 1 USE ONLY

+3V3 43 44 DRX-DDC-SDA DRX-DDC-SCL

HDMI CONNECTOR 1

1P05
1 2

HDMI CONNECTOR SIDE

B01I B04C
ETHERNET + SERVICE 3E53-4 3E53-2 3E53-3 3E53-1
1E06

VGA +5V-VGA

+5V-EDID 3ECP-3 3ECP-1

3S84

3S83

3FC1

3FC2

RXD1-MIPS TXD1-MIPS

3 2 1 UART SERVICE CONNECTOR 47 EDID SW 48

1E05
5

VGA-SDA-EDID-HDMI VGA-SCL-EDID-HDMI

9FC1 9FC3

12 15

10 1 6

B02I
AD25

PNX85500: ANALOG VIDEO 3S5V-1 3S5V-3 RES

B05A

DDR

VGA_EDID_SDA VGA_EDID_SCL AD24

VGA-SDA-EDID VGA-SCL-EDID

9FC2 9FC4

VGA CONNECTOR

7B00 H5PS1G83EFR

7B01 H5PS1G83EFR

RES

ANALOGUE VIDEO +3V3 3S6G 3S6F

SDRAM 128Mx8
D(0-7)

SDRAM 128Mx8
D(8-15) B02B B24 MEMORY A DQ 4_SDA 4_SCL A23 3S61 3S60

B01F

TUNER

SDA-TUNER SCL-TUNER

3F75 3F76

TUN-P7 TUN-P6

DDR2-A(0-13) DDR2-D(0-31)
7B02 H5PS1G83EFR 7B03 H5PS1G83EFR

ERR 18

7 1T01 TH2627 MAIN TUNER


ERR 34

D(16-23)

SDRAM 128Mx8

SDRAM 128Mx8

D(24-31)

B04C

ETHERNET + SERVICE

+3V3 3S6C 3S6B

B06B

VIDEO OUT - LVDS

7E10 LAN8710A-EZK 11 10 9 ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3) ETH-RXCLK ETH-TXD(0) ETH-TXD(1) ETH-TXD(2) ETH-TXD(3) ETH-TXCLK Y5 Y6 AB4 AC1 AA3 AA1 AA4 AB1 AB2 AA2

1G51 SDA-SET SCL-SET +3V3 3S67 3S65 3S68 3S66 9S12 9S11 SDA-DISP SCL-DISP 3G2W 3G2Y 50 49

B26 2_SDA 2_SCL RXD_0 RXD_1 RXD_2 RXD_3 RXCLK GPIO_2 TXD_0 TXD_1 TXD_2 TXD_3 TXCLK GPIO_3 W22 A25

3S58 3S5W

LVDS CONNECTOR

ERR 14

+3V3 2 3S81 3S80 7S01 PCA9540B 2 CHAN. MULTIPLEX.


ERR 24

ETHERNET

8 7 22 23 24 25 20

1 4 5

ERR 64

B09A

DVBS CONNECTOR BOARD 3C83 3C81 1M71 3 1

TS1
1T02 3 1

TEMP SENSOR 3124 3123

W21

RXD2-MIPS TXD2-MIPS

SDA-TEMP1 SCL-TEMP1

ETHERNET CONNECTOR RJ45

7 8

1 RES 9S13 9S10 SDA-BL SCL-BL

7104 LM75ADP TEMP SENSOR

11

15

SW

Programmable via USB


19110_004_110309.eps 110321

OPTIONAL

2011-Jul-15 back to

div. table

Block Diagrams

Q552.2L LA

9.

EN 72

9-7 Supply Lines Overview


SUPPLY LINES OVERVIEW
B03C
1M99 1 GND1 2 +12V3 3 GND1 4 +12V3 5 GND1 6 +12V3 1M99 1
2 3 4 5 6 7 8 9 +12V_AL B09a

DC / DC

B01H

HDMI
1P05 18 DIN-5V B03c B03c B04d

B03A

AUDIO
+3V3-STANDBY +24V-AUDIO-POWER +AVCC B03e

B04A

ANALOGUE EXTERNALS A
B03e

B09A
+3V3

CONNECTORS COMP
+3V3 1M71 4 TEMP SENSOR (OPTIONAL)

+3V3-STANDBY +24V-AUDIO-POWER 3D09

HDMI SIDE CONNECTOR

+3V3

+3V3

B01I
GND_AL

VGA
1E05 9 +5V-VGA B04d B03c

+3V3-STANDBY

+3V3-STANDBY +5V 1M19 1M20 5 6 8 8

B04B B03B
DC / DC
+3V3-STANDBY +12V 5U02 +3V3 B03e +3V3-STANDBY +12V

ANALOGUE EXTERNALS B

B03c B03e +3V3 +5V

N.C. GND1 +12V3

7 8 9

3D-LR

B02E +12VIN ONLY 8000 SERIES B03e

VGA CONNECTOR

TO IR/LED BOARD

PSU
3V3SB
1M95 1
2 3 4 5 6

B01J
+3V3

TEMP SENSOR + HEADPHONE


+3V3

B03c

1M95 1
2 3 4 5 6 1U40

+3V3-STANDBY

STANDBY GND1 GND1 +12V3 +12V3

STANDBY

B02G

B01e,B02e, g,h,B03a,b,h, B04d,e,B09a

7U03 TPS53126PW

7U02-1

12V/1V8 COVERSION B03e 5U00 +1V8 B02b,h,B03d, B05a

B04C
+3V3

ETHERNET + SERVICE
+3V3 5E08 +3V3-ET-ANA

B03c

+12V_AL 1C87 T 2.0A

+12V_AL

B01K
+12VIN B03h +12VD +12V +24V-AUDIO-POWER B01g

TUNER BRAZIL
+1V2-BRA-VDDC +1V2-BRA-DR1 +3V3 5FE7 5FE4 +3V3-BRA +3V3-BRA-FLT +5V 5FE9 +2V5-BRA

+1V2-BRA-VDDC +1V2-BRA-DR1 B01g

12 Dual Synchronous 7U02-2 Step-Down Controller 14

ONLY 8000 SERIES +24V

B03c

+24V 1C86

B04D
12V/1V1 COVERSION 5U01 +1V1 +3V3 B03e

HDMI
+3V3 5EC0 +3V3-HDMI B03f +3V3-STANDBY +5V-VGA +5V-EDID V-AMBI

1M59 21 10 5 TO AMBILIGHT MODULE

7U01

T 2.0A

+24V

13 14

13 14

+24V B09a

IN OUT COM

+5V B03e

6EC1

9 BL-ON-OFF 10 BL-DIM1 11 BL-I-CTRL 12 POK

+VSND GND1

7 8

7 8 9 10 11 12

T 3.0A

B03b,d,e,g, B09a B02d,B03a

B03e

+3V3

1
7U04

B02h,g,B03e +3V3-STANDBY B03c +5V-VGA B01I

LAMP-ON B02G BACKLIGHT-PWM_BL-VS B06C BACKLIGHT-BOOST B01E POWER-OK B02G

23

B03e

+5V

7FE3

+5V 1P04 18 1P03 18 1P02 18

GND1

B03D
+1V8

DC / DC
+1V8 7UA3 +1V2 B02g,h, B03e

HDMI 3 CONNECTOR HDMI 2 CONNECTOR HDMI 1 CONNECTOR

AIN-5V

B02A
+3V3 B03e +5V B03e +5V +3V3 B03e +3V3

PNX85500: NANDFLASH CONDITIONAL ACCESS


+3V3

B03b

BIN-5V

CIN-5V DIN-5V

+12V
+5V +5V 3U16 +3V3 B01h

B01A
+3V3 B03e

COMMON INTERFACE
B03b +3V3

B02B
+1V8

PNX85500: SDRAM
+1V8

B03e

DIN-5V

7UC0
3U15
IN OUT COM

3S20 3S06

+2V5 B02d,h CUA0 +2V5-LVDS B03e B02h

DDR2-VREF-CTRL3 DDR2-VREF-CTRL2 +5V5-TUN B03e

B04E
+3V3

HEADPHONE
+3V3 +3V3-STANDBY

+5V5-TUN B03c 7UA6 +5V-TUN B01f

+3V3-STANDBY

B01B
+3V3 B03e

FLASH
+3V3 B03e

B02C
+3V3

PNX85500: DIGITAL VIDEO IN


+3V3 B03c +12V 3UA0

ENABLE-1V8 7UA0 VOLT. REG.

B05A
+12V B03b +2V5-REF +1V8

DDR
+1V8 3B20 DDR2-VREF-DDR

B01C
+3V3 B03e +5V B03e

USB HUB

B02D
+3V3 B03d +5V 3F32 +T 3FL2 +T B03c +5V-USB1 +5V-USB2 B03e +2V5 +3V3

PNX85500: AUDIO
+2V5 +3V3 3S11 +3V3-ARC

B06A B03E
+1V1 B03b B03c B02h +12V

DISPLAY INTERFACING-VDISP
+VDISP-INT

DC / DC
+VDISP-INT +1V1 +12V B03h B01,a,b,c,d,e, g,j,k, B02a,c,d,e,h, B03c,f,g,h, B04a,c,d,e, B06b,c,d, B09a B03d 6UD0 +5V B01,c,e,k, B03c,d,e, B04d,B09a B03e 1G03 T 3.0A +VDISP

7S08
IN OUT COM

+2V5-AUDIO +24V-AUDIO-POWER

B06b

+24V-AUDIO-POWER 3S0Z

7UD1
5UD3
IN OUT COM

5UD2

+3V3

B01D
+3V3 B03e

SD-CARD
+3V3 3F40 +T +3V3-SD B03e B03c

+24V-AUDIO-VDD

7UD0
5UD0 5UD1
IN OUT COM

+5V5-TUN

B02E
+3V3

PNX85500: MIPS
+3V3 +3V3-STANDBY

B06B
+3V3 +VDISP

VIDEO OUT - LVDS


+3V3 +VDISP

+3V3-STANDBY

B03F
+3V3

TEMPSENSOR + AMBILIGHT
B06a +3V3 5UM1 1UM0 T 1.0A B03e V-AMBI

B01E
+3V3 B03e B03c B03e

PNX85500: CONTROL
+3V3 +3V3-STANDBY B03b +5V +3V3-STANDBY B03c +3V3-STANDBY

B02G
+1V1

PNX85500: STANDBY CONTROLLER


+1V1

B03b B09a

+3V3-STANDBY +5V

B06C
+3V3

AMBILIGHT CPLD
+3V3 5GA0 VINT VIO

B03G
+3V3 B03e B03c +12V

FAN - CONTROL
+3V3 +12V

5GA1

B01F
+5V-TUN B03d

TUNER
+5V-TUN 9F71 +5V-TUN-PIN B03b B03d B03b

B02H
+1V1 +1V2 +1V8 +2V5

PNX85500: POWER
+1V1 +1V2 +1V8 +2V5 +2V5-AUDIO +2V5-LVDS +3V3 +3V3-STANDBY B03e B03c B03c

B06D
+3V3 B03e

SPI-BUFFER
+3V3

B03H
+3V3

VDISP - SWITCH
+3V3 +3V3-STANDBY +12VD 7UU0 +VDISP-INT

+3V3-STANDBY +12VD

B01G
+3V3 B03e

TOSHIBA SUPPLY
+3V3

B03d B02d B03d B01k B03e B01k B03c

+2V5-AUDIO +2V5-LVDS +3V3 +3V3-STANDBY

B06a

7FA3
IN OUT COM

5FA3 5FA4

+1V2-BRA-VDDC +1V2-BRA-DR1

7UU2 LCD-PWR-ONn

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Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 73

10. Circuit Diagrams and PWB Layouts


10-1 B01 313912365213
Common Interface

B01A

Common Interface

B01A

CA-CD1n CA-CD2n

FF05 FF06

3 4

6 10K 5 10K 3F07-1 1 8 10K 3F07-2 2 7 10K 3F07-4 1 3F08-1

3F07-3

+3V3

CA-MOCLK CA-MOVAL CA-MOSTRT

8 10K 5 10K FF07 3F08-3 3 6 10K 3F08-2 2 7 10K 4 3F08-4 RES 1 3F09-1 8 10K RES 2 3F09-2 7 10K RES 3 3F09-3 6 10K RES 4 3F09-4 5 10K RES 4 3F10-4 5 10K RES 3 3F10-3 6 10K RES 2 3F10-2 7 10K RES 1 3F10-1 8 10K 3F12 10K 2 3F11-2 7 10K 3 3F11-3 6 10K 4 3F11-4 5 10K 8 3F11-1 1 10K

+3V3

CA-MDO0 CA-MDO1 CA-MDO2 CA-MDO3

IF04

CA-MDO4 CA-MDO5 CA-MDO6 CA-MDO7

CA-RDY

FF08

+3V3

IF08

FF09 CA-VS1n

+3V3

1X07 REF EMC HOLE

1X04 EMC HOLE

1X08 REF EMC HOLE

1X01 REF EMC HOLE

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


Flash

Q552.2L LA

10.

EN 74

B01B

Flash

B01B

+3V3

2F20

100n 2F21

7F20 NAND04GW3B2DN6F

100n 12

[FLASH] 4G 16
XIO-D00 XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07 3F20-1 1 3F20-3 3 3F21-1 1 3F21-3 3 8 6 8 6 100R 3F20-2 100R 3F20-4 100R 3F21-2 100R 3F21-4 2 4 2 4 7 5 7 5 100R 100R 100R 100R IF21 3F22-2 +3V3 XIO-OEn XIO-WEn NAND-WPn +3V3 NAND-RDY1n 2K2 IF23 10K 3F19 VSS 13 36 2 100R 3F22-3 3 10K 3F22-1 1 5 100R 3F24 7 16 17 9 8 18 19 7 29 30 31 32 41 42 43 44 0 1 2 3 IO 4 5 6 7

37

VCC

NC

NAND-CE1n NAND-CLE NAND-ALE

6 8

100R 100R IF22

3F23 3F22-4 4

CLE ALE CE RE WE WP R B

1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 27 28 33 34 35 38 39 40 45 46 47 48

+3V3

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


USB Hub

Q552.2L LA

10.

EN 75

B01C

USB Hub

B01C
+3V3

USB-OVR1 3FL2 +5V 100n 100n 100n 100n 1u0 10n 10n 10n 2FLB 1n0 2FLC 1n0 2FLA 1n0 +T 0R3 4 3FL4-4 5 100K 3 3FL4-3 100K +3V3 3 7 11 15 19 23 27 33 39 55 7FL5 CY7C65621-56LTXCT IFL4 IFLG +3V3 +5V 3FLD 1 3FLE-1 100K 2 3FLE-2 100K 4 3FLE-4 5 100K 3 3FLE-3 100K +3V3 RESET-USBn USB1-DM USB1-DP USB-DM USB-DP USB2-DM USB2-DP USB-WIFI-DDn USB-WIFI-DDp 3FLF 9FLF 9FLG 9FLH 9FLJ 10K 6 9 10 7 9F26 9F25 9FLC 9FLD IFL1 IFL2 17 18 13 14 10K 8 IFLA 21 22 45 26 46 XIN XOUT SELFPWR VBUSPOWER RESET DD+ DD1DD1+ DD2DD2+ PWR2 OVR2 SPI_CS SPI_SCK SPI_SD GREEN2 AMBER2 PWR1 OVR1 12p 1 3FL4-1 8 100K 2 3FL4-2 100K USB-16-PBT-B-30-CU1-BRF 9FL3 3FL7 10K 3F32 +5V 4 3F34-4 100K 3F34-3 100K +3V3 +3V3 2 3F34-2 100K 1 3F34-1 8 100K +3V3 RES RES RES RES 1 2 3 4 1 2 3 4 9FL1-1 9FL1-2 9FL1-3 9FL1-4 9FL2-1 9FL2-2 9FL2-3 9FL2-4 8 7 6 5 8 7 6 5 USB-16-PBT-B-30-CU1-BRF 7 +T 0R3 +5V-USB1 +5V-USB2 6 USB2-DM USB2-DP FL42 FL40 FL41 FL32 7 6 +5V-USB1 USB1-DM USB1-DP FL43 FL36 FL37 1 2 3 4 5 FL33 +5V-USB2

2FL2

2FLD

2FL5

2FL3

1FL5

2FL8

2FL9

2FL4

2FL1

USB1
1P08

2FL6

4 2 12p

24M 2FL7

VCC GREEN1 AMBER1

6 IFLF

35 36 37 38 29 30 31 32 25 48 49 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 IFLC IFLD IFLE 3FLA 3FLB 3FLC 10K 15K 10K IFLB

USB2
1P07 1 2 3 4 5

9FLE

+5V

IFL3

53 51 5 6 42 41 54 1 2 44 43 52

RES

VIA

RES 3FLJ +T 0R3 USB-WIFI-DDn USB-WIFI-DDp FL31 FL38 FL39 FL30

(WIFI)
RES 1F24 1 2 3 4 5 6

USB2-DM USB2-DP +3V3 USB-OVR1 +3V3

9FLK 9FLL 3FLG 10K 3FLH 10K

NC

502386-0570

GND 4 8 12 16 20 24 28 34 40 47 50 56 SCENARIO 1x USB 1x USB + WIFI 2x USB 2x USB + WIFI 1P07 N N Y Y 1P08 Y Y Y Y 1F24 N Y N Y 3FLG N Y Y N 3FL2 N N Y Y 3FL4 N N Y Y 3FL7 N Y N Y 3F32 Y Y Y Y 3F34 N Y Y Y 7FL5 CY7C65621 CY7C65621 CY7C65631 9FLE 9FLC/D 9F25/6 9FL2 N N N Y Y N N N Y N Y N N N N Y 9FL3 N N N Y

GND HS 57

9FLF/G 9FLH/J 9FLK/L N N N N Y N Y N N N Y Y

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


SD Card

Q552.2L LA

10.

EN 76

B01D

SD-Card

B01D

3F40 +3V3 +T 22u 16V 2F40 0R3

FF45

+3V3-SD

+3V3

3F41-4 47K

5 3 3F41-3 47K

IF47 SDIO-DAT3 6 SDIO-CMD SDIO-DAT3 SDIO-CMD

3F44-2 100R

7 3 3F43-3 100R 6

FF47 1P09-1 FF48 1 2 3 4 5 6 7 8 9

3F45 RES 10K 2 3F41-2 7 47K 1 3F42-1 8 47K 1 3F41-1 8 47K

SDIO-CLK

SDIO-CLK

3F44-1 100R

+3V3-SD 8 FF49 FF41 1 3F43-1 8 100R FF42 FF43 13 15

SDIO-DAT0 SDIO-DAT1 SDIO-DAT2

SDIO-DAT0 SDIO-DAT1 SDIO-DAT2

2 3F43-2 7 100R 3 3F44-3 6 100R

14 16

FF46

SCDA7A0200

2 3 3F42-3 6 47K

3F42-2 47K

1P09-2 7 SDIO-CDn SDIO-CDn FF44 10 11 12 SCDA7A0200

SDIO-WP

SDIO-WP

FF50

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


PNX85500 Control

Q552.2L LA

10.

EN 77

B01E

PNX85500 Control

B01E

+3V3-STANDBY

+3V3-STANDBY

+3V3-STANDBY 2F49 100p 2F52 100n RES

+3V3

+3V3

+3V3

3F52

3F67

10K

7F52 M25P05-AVMN6 IF50 D C S W 5 IF52 6 IF53 1 IF54 3 7 +3V3-STANDBY

10K

3F66

10K RES

BACKLIGHT-BOOST 7F53 RES PDTA114EU +5V

VCC PNX-SPI-SDI IF51 2 Q

512K FLASH

PNX-SPI-SDO PNX-SPI-CLK PNX-SPI-CSBn PNX-SPI-WPn BOOST-PWM IF55

3F68 RES 7F54-2 RES BC847BPN(COL) IF57

HOLD VSS 4

7F54-1 RES BC847BPN(COL) 6 IF56 4 2 1

FF29

IF61 SPI-PROG

FF04

IF62 SDM

5 3 3F53 RES RES 10K 2F53

47K

9CH0

FF58

3F69

3F54

1u0

+3V3

MAIN NVM DEBUG ONLY


IF58 2F58 RES 100n 8 7F58 SCL-SSB SDA-SSB FF63 7 6 5 3F59 100R 3F60 100R FF55 FF56 SCL-UP-MIPS SDA-UP-MIPS 3F63 100R FF61 3F62

10K

1K0 RES

RES 1F52 100R FF62 4 1 2 3 5

SCL SDA

3F58 IF59

1 2 3

(8K 8) EEPROM
0 1 2 ADR

10K

WC SCL

SDA 4 FF57

DEBUG / RS232 INTERFACE


FF65 FF66 3F64 100R 3F65 100R 7 6 FF64 RES 1F51 1 2 3 4 5

LEVEL SHIFTED UP FOR DEBUG USE ONLY

TXD-UP RXD-UP RESET-STBYn SPI-PROG

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


Tuner

Q552.2L LA

10.

EN 78

B01F
FF71

Tuner
IF10

B01F
IF11 4MHZ_REF

1T01 15 RF_AGC B+_LNA RF_IO TUN 16

TUNER
I2C_ADR I2C_SDA I2C_SCL B+_TUN

14 IF_OUT1 IF_OUT2 9F00 9F01 9F02 13 NC +5V-TUN-PIN 10n 7F75 UPC3221GV-E1 1F75 IF75 O1 O2 5 4 IF81 2F74 10n 2F78 10n GND1 GND2 4 VAGC 10n
AGC CONTROL

9F03

2F71

PNX-IF-P

2F72

*
VCC OUTPUT1 7 IF78 2F79 IF74 2F75 10n IF76 1 3F79-1 RES 2F76 5F71 220R IF80 4 3F79-4 220R AF72 2p2 2F77

*
2F70 RES

2F65 RES 1p0

10

11

12

2F73

IF73 2 IF77 3 INPUT2 INPUT1

5F74

2F62

6p8

6p8

6p8

6p8

6p8

6p8

6p8

1 2 3

OUTPUT2

RES 2F9C

RES 2F9D

RES 2F9A

RES 2F9B

RES 2F98

RES 2F97

RES 2F99

X7251M 36M17

AF73 2F80 2F82

*
FF74 TUN-P1 100n 4n7 4n7 FF00 FF75 RES 2F81 2F59 2F60 2F61 FF76 AF71 AF70 TUN-IF-N TUN-IF-P IF-AGC PNX-IF-AGC IF82 3F77 4K7 IF-AGC 100p 100p FF01 IF72 9F05 9F06 BA591 2F85 3F71 6F72 3F72 1K0 2F92 +5V-TUN-PIN 4K7 10n IF79 3F80 220R 3F81 220R IF86 2F90 3F78 3K3 10n 5F70 +5V-TUN-PIN TUN-IF-N TUN-IF-P 470n 3 4 ATB2012 10n IF89 2F84 15p 2F86 15p 3F76 47R TUN-P6 3F75 47R TUN-P7 IF88 SDA-TUNER IF87 SCL-TUNER SELECT-SAW RES IF90 7F70 PDTC114EU 5F73 2 1 IF14 IF12 2F63 10n 2F64 10n

*
PNX-IF-N

IF13 IF5F66 680n 2F66 15p

9F04

47n

*
FF81 FF82

RES 2F95

RES 2F96

2F93

100n

IF15

RES 5F76

820R IF+
3

GND

TUN-P6 TUN-P7

* For BR NIM Tuner only

2F91 RES

* For EU Hybrid Tuner Only


9F71 5F72 RES +5V-TUN 30R +5V-TUN-PIN 2F88

* Remarks
Item No. 1T01 2F61 2F62 9F02 9F03 9F04 9F05 9F06 2F73 2F82 2F72 2F80 2F77 5F71 5F74

Component Europe Brazil FA23X7 TH26X3 RES 4u7 5p6 10p Used RES Used RES Used RES Used RES Used RES RES 1p0 RES 1p0 12p 15p 12p 15p 18p 22p 560n 680n 680n 820n

22u

2F94

10n

330n 3F82 RES

I ISWI

IF16

15p

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


Toshiba Supply

Q552.2L LA

10.

EN 79

B01G

Toshiba supply

B01G

+3V3

+1V2-BRA-DR1 +1V2-BRA-VDDC

5FA3

5FA4 2FA4

30R

7FA3 LD1117DT12 3 IN OUT COM 2FA2 2 FFAF

2FA3

100n

100n

FFA2

10u

30R

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


HDMI

Q552.2L LA

10.

EN 80

B01H

HDMI

B01H

HDMI CONNECTOR SIDE


1P05 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FFB5 21 23 DRX2+ DRX2DRX1+ DRX1DRX0+ 1 3FBF-1 8 DRX-DDC-SCL DRX-DDC-SDA DRX0DRXC+ DRXCPCEC-HDMI FFB1 FFB2 FFB3 FFB4 20 22 FFB6 DIN-5V DRX-HOTPLUG DRX-DDC-SCL DRX-DDC-SDA DIN-5V

47K 2 3FBF-2 7 47K

DIN-5V

2011-03-09 2010-12-23

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VGA

Q552.2L LA

10.

EN 81

B01I

VGA

B01I
FFC1 CDS4C12GTA 12V 3FC5 18R R-VGA RES 2FC1 1FC1 RES 6FC1 100p

FFC2 CDS4C12GTA 12V

3FC6 18R

G-VGA

RES 2FC2

1E05 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FFC6 1216-02D-15L-2EC FFC7

RES 6FC2

1FC2

100p

3FC7 CDS4C12GTA 12V FFC3 RES 2FC3 RES 6FC3 1FC3 100p 18R

B-VGA

VGA CONNECTOR

FFC4 FFC5

9FC5 RES 6FC4 CDS4C12GTA 12V 2FC4 1FC4

H-SYNC-VGA

3FC3

17

4K7

47p

9FC6 CDS4C12GTA 12V RES 6FC5 2FC5 1FC5 3FC4

V-SYNC-VGA

47p

4K7

RES 3FC1 10K

9FC1 FFC8 CDS4C12GTA 12V 9FC2 RES RES 6FC6

VGA-SDA-EDID-HDMI VGA-SDA-EDID

2FC6

47p

RES 3FC2 10K

9FC3 FFC9 CDS4C12GTA 12V 9FC4 RES

VGA-SCL-EDID-HDMI VGA-SCL-EDID

2FC7

RES 6FC7

47p

+5V-VGA RES 6FC8 CDS4C12GTA 12V 2FC8 1FC6

47p

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


Temp sensor & headphone

Q552.2L LA

10.

EN 82

B01J

Temp sensor & headphone

B01J

+3V3 9FD1 RES 9FD2 RES RES 3FD1

1K0

2FD1

3FD2 IFD5 9FD5 1K0

100n

LTST-C190KGKT

RES

6FD1

7FD1 LM75BDP 3 1 2 OS SDA

+VS

A0 A1

7 6 5

IFD1 IFD3

SDA-SSB SCL-SSB 3FD4 100R

3FD3 100R

IFD2 IFD4

GND

SCL

A2

3FD6

1K0 3FD7

RES

1K0

RES 1329 1 2 3

502382-0370 1328 2MSJ-035-69A-B-RF-PBT-BRF AMP1 AMP2 CDS4C12GTA 12V 1FD3 CDS4C12GTA 12V 2FDC FFDB 22n 2FDD 22n FFDC 7 8 3FDG-2 1K0 3FDG-1 1 FFDA 3

1FD2

RES

6FD2

RES

6FD3

1K0

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Tuner Brazil

Q552.2L LA

10.

EN 83

B01K

Tuner Brazil

B01K

5FE0 +2V5-BRA 30R

IF63

IF64 +1V2-BRA-VDDC 2FE3 100n 2FE4

2FE0

100n 2FE5

100n 2FF0

100n 2FF1

1u0

1u0

AGND 5FE3 30R 2FE6 2FF2 100n 2FF5 100n 2FF4 100n 2FF6 100n 2FF3 1u0 1u0 IF65 IF66 +3V3-BRA-FLT

+3V3-BRA-FLT

5FE4 +3V3-BRA 30R

AGND 5FE5 30R 2FE8 2FF7 100n 2FF8 100n 2FF9 1u0 1u0 +3V3 30R IF67 IF68 +1V2-BRA-DR1 5FE7 IF48 +3V3-BRA

IF69

5FE8 +2V5-BRA 30R 2FG0 1u0 7FE3 LD3985M25 5FE9 +5V 30R 1 3 IN INH OUT BP 5 4 FF03 +2V5-BRA

25M4 2FG2 2FG3 18p 18p 4 2

100n 2FG1

1FE0

COM 2FH2 2FH3 2FH4 1u0 10n AGND AGND AGND 1u0 2 7FE0 TC90517FG 19 18 3 2 IF+ IF2FG4 10n 2FG6 2FG7 AGND 100n 2FG8 100n 2FH6 2FH7 10n IF17 IF18 BFE2 BFE3 100n 100n 30 29 28 27 24 25 26 39 +3V3-BRA-FLT 40 8 3FE6 10K 1 41 10K IF29 7 11 SCL-SSB SDA-SSB 3FE8 100R 3FE9 IF49 100R 45 46 I X O 16 36 56 63 32 13 35 49 64 34 48 DR1VDD 22 20 43 DR2VDD

AD_DVDD

AD_AVDD

PLLVDD

VDDC

VDDS

FIL

21 58 53 54 55 59 52 61 60 38 9 10 51 42 6 5 12 14

2FH5 1n5 DFE6 DFE7 DFE8 3FG6-3 DFE9 3 6 33R TS-BR-SOP 2 AGND 3FG6-4 4 5 33R TS-BR-VALID 1

* To be drawn near PNX85500

PBVAL RERR RLOCK

9F27-1

TS-FE-VALID

0 XSEL 1 P ADI_AI N P ADQ_AI N P AD_VREF N AD_VREF DTCLK DTMB S_INFO 0 TSMD 1 AGCI CKI AD_DVSS AD_AVSS PLLVSS SCL SDA

RSEORF SBYTE SLOCK SRCK SRDT STSFLG1 AGCCNTI AGCCNTR STSFLG0 SYRSTN SLADRS 0 1

9F27-2

TS-FE-SOP 5FG0

100n

2FG9

3FG7 3FG6-2 DFF1 2

33R 7

TS-BR-CLOCK 4

9F28 9F27-4 5

* *

TS-FE-CLOCK TS-FE-DATA

30R 5FG2 30R

AGND

33R TS-BR-DATA

AGND

IF27

3FE5 18K

IF28 IF-AGC 2FH8 10n

AGND

DFF2

3FE7

3FG2-1 10K 3FG4-2 4K7 3FG4-1 4K7 3FG2-2 10K +3V3-BRA-FLT

RESET-SYSTEMn

TN VSS 4 15 33 37 44 47 50 57 62

SCL SDA

23

31

AGND

AGND

17

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Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 84

10-2 B02 313912365213


NANDflash - conditional access

B02A

PNX85500: NANDflash - conditional access

+3V3

B02A
XIO-D00 XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07

3S1W

7S00-5 PNX85500

FLASH

NAND-ALE NAND-CLE

D22 ALE NAND C21 CLE J25 J26 H21 H22 H23 H24 H25 H26 G21 G22 G23 G24 G25 G26 F22 F23 00 01 02 03 04 05 06 07 XIO_A 08 09 10 11 12 13 14 15

00 01 02 03 04 05 06 07 XIO_D 08 09 10 11 12 13 14 15 XIO

D25 D26 C24 D23 C23 B23 A22 E22 F24 F25 F26 E23 E24 E25 E26 D24

10K XIO-D10 3S15 10K

INPACK

INPACK

IS26

B22 OE_ C22 WE_ B21

XIO-OEn XIO-WEn +3V3


NAND-CE1n

CLK_BURST

IS25

E21 CE1_ D21 CE2_ A20 NAND RDY2 F21 RDY1 A21 WP_

3S1V

9S08 IS00

NAND-RDY1n NAND-WPn

+3V3

3S1X

7S00-11 PNX85500 P21 P22 P23 P24 P25 P26 N21 N22 J22 K25 K26 N23 CA-MOCLK L25 N24 N25 CA-MOSTRT CA-MOVAL L22 L23 J21
CA-RDY

0 1 2 3 MDI 4 5 6 7

VIDEO_STREAM

0 1 2 3 MDO 4 5 6 7

N26 M21 M22 M23 M24 M25 M26 L21

10K

10K RES

CA-MDO0 CA-MDO1 CA-MDO2 CA-MDO3 CA-MDO4 CA-MDO5 CA-MDO6 CA-MDO7

ADD_EN DATA_DIR DATA_EN I MCLK O MISTRT MIVAL MOSTRT MOVAL OOB_EN RDY RST VCCEN VPPEN T21 DATA T23 ERR T22 TNR_SER1 MICLK R23 MIVAL R22 SOP
TS-FE-DATA TS-FE-ERR TS-FE-CLOCK TS-FE-VALID TS-FE-SOP

VS

K23 1 K24 2 K21 1 K22 2

9S00

CA-VS1n CA-MOCLK CA-CD1n CA-CD2n

CD

CA
3S1R 3S1S 3S1T 3S1U RES RES TS-FE-DATA TS-FE-CLOCK TS-FE-VALID TS-FE-SOP 3S23 470R 3S24 470R 3S28 470R 3S29 RES RES 470R 560R 560R 560R 560R

+3V3

TS-FE-DATA TS-FE-CLOCK TS-FE-VALID TS-FE-SOP

L24 L26 J23 J24

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Circuit Diagrams and PWB Layouts


SDRAM

Q552.2L LA

10.

EN 85

B02B

PNX85500: SDRAM

B02B

7S00-8 PNX85500 DDR2-BA0 DDR2-BA1


DDR2-BA2

H1 H2 G1 D1 D5 R3 T5 F3 C2 F2 C3 B4 F1 C1 E1 F4 B2 E5 C5 A4 G5 B3 F5 U3 P2 U2 P3 N1 U1 P1 T1 V4 R5 U5 P5 N3 V3 R4 V5

0 1 BA 2

MEMORY

DDR2-DQM0 DDR2-DQM1 DDR2-DQM2 DDR2-DQM3 DDR2-D0 DDR2-D1 DDR2-D3 DDR2-D2 DDR2-D6 DDR2-D5 DDR2-D4 DDR2-D7 DDR2-D8 DDR2-D9 DDR2-D10 DDR2-D11 DDR2-D12 DDR2-D13 DDR2-D14 DDR2-D15 DDR2-D16 DDR2-D17 DDR2-D19 DDR2-D18 DDR2-D22 DDR2-D23 DDR2-D20 DDR2-D21 DDR2-D24 DDR2-D30 DDR2-D26 DDR2-D25 DDR2-D28 DDR2-D31 DDR2-D27 DDR2-D29

0 1 DM 2 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DQ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

M0

+1V8

0 1 2 3 4 5 6 7 A 8 9 10 11 12 13 14 N P N P N P N P N P

J1 J3 K1 G4 L3 G3 L2 H5 L1 J5 J2 M3 J4 M2 K5 N5 N4 E2 E3 D3 D4 R1 R2 T3 T4 K3 K4 L5 M4 M1 M5 H3 A2 V1 100p 2S20 100n 2S17 DDR2-VREF-CTRL2 DDR2-VREF-CTRL3 2S24 100n 2S25 100p 1% IS42 261R 3S30 10R 3S33 10R

DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-A14 DDR2-CLK_N DDR2-CLK_P DDR2-DQS0_N DDR2-DQS0_P DDR2-DQS1_N DDR2-DQS1_P DDR2-DQS2_N DDR2-DQS2_P DDR2-DQS3_N DDR2-DQS3_P DDR2-CAS DDR2-CKE DDR2-CS DDR2-ODT DDR2-RAS DDR2-WE 3S6Q 10K 3S6P 10K RES

100u 2.0V

180R 1%

180R 1%

CLK

3S06

3S20

2S12

FS02 DDR2-VREF-CTRL3 180R 1% DDR2-VREF-CTRL2 180R 1% 3S22 FS01

DQS0

DQS1

3S07

DQS2

DQS3

CASB CKE CSB ODT PCAL RASB WEB 1 VREF 2

DDR2-CKE

DDR2-ODT

3S0V

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Circuit Diagrams and PWB Layouts


Digital video in

Q552.2L LA

10.

EN 86

B02C

PNX85500: Digital video in

B02C

7S00-6 PNX85500 HDMIA-RX2+ HDMIA-RX2HDMIA-RX1+ HDMIA-RX1HDMIA-RX0+ HDMIA-RX0HDMIA-RXC+ HDMIA-RXC+3V3 3S0W 12K RES 2S2E 10u IS01 W24 RREF T25 T26 P RX0_A N

HDMI_DV

U25 P U26 RX1_A N

Y26 SCL DDC_A Y25 SDA V25 P RX2_A V26 T24 N HOT_PLUG_A W25 P W26 RXC_A N

DDCA-SCL DDCA-SDA IS10

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Circuit Diagrams and PWB Layouts


Audio

Q552.2L LA

10.

EN 87

B02D

PNX85500: Audio

B02D
3S0Z 3S53-1 100R 3S53-2 7S08 LD3985M25 FS08 IS12 4 2S2R 10u 5 OUT BP IN INH 1 10u RES 3 IS13 1u0 RES 4S14 +2V5 ADAC(1) IS02 12 13 11 +2V5-AUDIO +3V3 2S3J 220n +24V-AUDIO-POWER 4R7 +24V-AUDIO-VDD

1 AUDIO-IN1-L

3S12-1 22K

IS1H 8

1 3S16-1 8 10K 2 3S16-2

2S2W 1u0

100R 3S53-3 100R 3S53-4

FS03 4 7S05-4 LM324 14

2S2T

3S16-3 3

6 10K

2S2Z IS1M 1u0 100u 4V 3S51 4R7 2S42 2S41 IS0V 1u0 2S2Y 1 u0 2S31 1u0 7S00-2 PNX85500

2S34

22K

1u0

100n

AUDIO-IN1-R

2 3S12-2

IS1J 7

7 10K

2S2S

3S38 100R

2S2V 100R

+AUDIO-L

COM

3S36-2 10K

7 8

10K 3S36-1 2S2G 47p +24V-AUDIO-VDD 1

3S16-4 5 4 10K 3S13-4 4 22K 3S13-3 6 22K 3S13-1 1 22K 3S13-2 22K 7 8 IS1Q 3S17-2 2 7 10K IS1P 1 3S17-1 8 10K 5 3 3S17-3 6 10K IS0R 4 3S17-4 5 10K

AUDIO-IN3-L

AUDIO-IN3-R

2S30 1u0 2S33 1u0 2S32 1u0 3S10 100R IS1B

AUDIO AE10 AC7 L P AIN1 ADACL AF10 AB7 R N


AD10 L AIN2 AC10 R AE9 L AIN3 AF9 R AD9 L AIN4 AC9 R AF8 L AE8 AIN5 R ADACR AC6 P AB6 N AD7 AE7 AF7 AD6 AE6 AF6

2S36 1u0 IS1N

1 3S3G-1 8 33R 3 3S3G-3 33R 6

ADAC(1) ADAC(2) ADAC(2) IS03 10 9 11 ADAC(3) ADAC(4) 4 7S05-3 LM324 8 3S39 100R

-AUDIO-R

AUDIO-IN4-L

AUDIO-IN4-R

1 2 3 ADAC 4 5 6

3S3G-2 2 7 4 IS1S 3S3G-4 33R 5 33R

2S2L IS19 1u0

I2S_OUT AB9 POS VR_AADC AB8 NEG AD8

AD4 OSCLK AD1 SCK AD2 WS

3 3S3H 33R 3S3U 33R


ADAC(6) ADAC(5)

3S36-3 10K

6 5

10K 3S36-4 2S2H 47p +24V-AUDIO-VDD 4

IS1A 3S3F 56R 10u 2S3G 100n 2S3H 10u 2S3E 2S3F 100n 9S06 RES DBS8

AE1 1 AF2 VREF_AADC 2 AE3 I2S_OUT_SD 3 AF3 AC8 VCOM_AADC 4 AF5 AE5 SPDIF_OUT SPDIF_IN1

2S3D

1n0 2S3C

1n0 2S3B

1n0 2S3A

1n0 2S39

1n0 2S38

1n0

IS07 ADAC(5) 3 2

7S05-1 LM324

AUDIO-OUT-L

11

3S37 10K

3S6L 22K 2S2K 47p +24V-AUDIO-VDD

+3V3 +3V3-ARC

3S11 1R0 2S3Q

IS1L

100n

ADAC(6) IS06

5 6

7S05-2 LM324 7

AUDIO-OUT-R

SPDIF-OUT-PNX

SPDIF-OUT-PNX

IS1D

7S09-1 74LVC00APW 1 2

3S6N 14

SPDIF-OPT

11

&
3

RES 2S3K 100n

47R IS1G 1 3S18-1 8 RES 3S18-2 RES 3S18-3 220R RES 7 6


SPDIF-OUT

3S34 220R 10K

3S32 22K 2S2J 47p

+3V3

220R

+3V3

+3V3-ARC 3S19 10K 7S09-2 74LVC00APW 4 IS1E 5 7 +3V3 10 7 +3V3-ARC 14 7S09-3 74LVC00APW 9

&
6

14

&
8

SEL-HDMI-ARC

2S3L 100n

180R 3S6M

IS1K

2S3M 100n 3S25 68R

IS44
eHDMI+

+3V3-ARC 7S09-4 74LVC00APW 12 +3V3 13 7

14

&
11

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


MIPS

Q552.2L LA

10.

EN 88

B02E
3S45 +3V3 10K +3V3 3S40 10K 3S82 +3V3 +3V3 +3V3 +3V3 10K 3S62 +3V3 10K 3S80 3S81 10K 10K 10K

PNX85500: MIPS

B02E
7S00-3 PNX85500 +3V3

CONTROL
IS05
BOOTMODE BOOTMODE 3D-LR RXD1-MIPS TXD1-MIPS RXD2-MIPS TXD2-MIPS

1 Y21 IS16 Y22 Y23 Y24 W21 W22 W23 V22 V23 U23 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_10 GPIO_11

C25 SDA C26 SCL

1 100R

3S56

2 1 100R 1 100R 1 100R 1 100R 2 3S57

SDA-UP-MIPS SCL-UP-MIPS SDA-SET SCL-SET SDA-SSB SCL-SSB SDA-TUNER SCL-TUNER EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TDI-PNX85500

SDA-UP-MIPS SCL-UP-MIPS SDA-SET SCL-SET SDA-SSB SCL-SSB SDA-TUNER SCL-TUNER EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TDI-PNX85500

3S69 3S6A 4K7 3S6B 3S6C 4K7 3S6D 3S6E 2K2 3S6F 3S6G 2K2 3S6K 1 10K 8 3S6H-1 10K 3 6 3S6H-3 10K 2 10K +3V3-STANDBY 7 3S6H-2 5 3S6H-4 4 10K FS57 +3V3 2K2 2K2 EJTAG-DETECTn FS53 4K7 4K7 EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDI-PNX85500 FS44 FS49 FS50 FS51 FS52

RES 1F10 1 2 3 4 5 6 7 8

3D-LR

IS17

9S09

B26 SDA A25 2 SCL 3 B25 SDA A24 SCL

3S58 1 2 100R 1 3S5Y 2 100R 1 100R 3S60 2

2 3S5W

DS52 BOOST-PWM FS10 TXD2-MIPS FS11 RXD2-MIPS IS04 GPIO6

FOR FACTORY USE ONLY

3S5Z

GPIO6
PNX-SPI-CS-BLn BOOST-PWM SELECT-SAW USB-DM USB-DP

B24 SDA A23 4 SCL TRSTN TMS TCK TDO TDI AA25 AA24 AA23 AB26 AB25 AE4 AD5 AC5

10 9

3S61

RES 3S21

PNX-SPI-CS-BLn

R26 DN R25 USB IS4Z R24 DP RREF 5K6 1% 3S55

BM08B-SRSS-TBT

3S00 33R

RESET_SYS BL_PWM CLK_54_OUT

RESET-SYSTEMn BACKLIGHT-PWM

3S64 +3V3 10K

FS64

SELECT-SAW

3S26

3S27

3S6J

RES 10K

3S83 +3V3 10K 3S84 +3V3 10K

RXD1-MIPS

+3V3 TXD1-MIPS 3S72 47R

10K

+3V3 IS40
PXCLK54

10K

RES

+3V3 2S89 100n 7S01 PCA9540B 3 +3V3 3S65

VDD

SC0 SC1

5 8 4 7

SCL-DISP SCL-BL SDA-DISP SDA-BL

SCL-DISP SCL-BL SDA-DISP SDA-BL

SCL-SET SDA-SET

1 2

SCL SDA
INP FIL

I2 C -BUS CTRL

SD0 SD1

1 4K7 1 4K7 3S67 2 1 4K7 3S68 2 1 4K7 2 3S66

VSS 6 FS31 9S10 IS08


SCL-SET

SCL-BL

9S11 9S12

FS2W FS2Y

SCL-DISP SDA-DISP SDA-BL

SDA-SET

IS09

9S13

7S00-4 PNX85500
ETH-RXCLK ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3) ETH-RXDV ETH-RXER SDIO-DAT3 SDIO-CLK SDIO-CMD SDIO-DAT0 SDIO-DAT1 SDIO-DAT2 SDIO-CDn SDIO-WP

AA3

RXCLK

ETHERNET
TXCLK AA2 AA1 AA4 AB1 AB2 AA5 AB3 AC3 Y2 Y3 Y1
ETH-TXCLK ETH-TXD(0) ETH-TXD(1) ETH-TXD(2) ETH-TXD(3) ETH-TXEN ETH-TXER ETH-COL ETH-CRS ETH-MDC ETH-MDIO

IS50

Y5 0 Y6 1 AB4 RXD ETH 2 AC1 3

0 1 AC2 TXD 2 RXDV Y4 RXER 3 ETH TXEN W2 CC_DAT3 TXER W1 COL CLK W6 CMD CRS W5 0 MDC W4 SDIO 1 DAT MDIO W3 2 U6 SDCD V6 SDWP

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Circuit Diagrams and PWB Layouts


Video out - LVDS

Q552.2L LA

10.

EN 89

B02F

PNX85500: Video out - LVDS

B02F

7S00-7 PNX85500 PX1APX1A+ PX1BPX1B+ PX1CLKPX1CLK+ PX1CPX1C+ PX1DPX1D+ PX1EPX1E+ PX2APX2A+ PX2BPX2B+ PX2CLKPX2CLK+ PX2CPX2C+ PX2DPX2D+ PX2EPX2E+ 9S92 9S93 9S90 9S91 A7 B7 C8 B8 N A P N B P

LVDS
A

N P N P

D7 E7 E8 D8 9S94 9S95

PX3APX3A+ PX3BPX3B+ PX3CLKPX3CLK+ PX3CPX3C+ PX3DPX3D+ PX3EPX3E+ PX4APX4A+ PX4BPX4B+ 9S96 9S97 PX4CLKPX4CLK+ PX4CPX4C+ PX4DPX4D+ PX4EPX4E+

C10 N CLK B10 P A9 B9 N C P LOUT1 LOUT3

CLK

E10 N D10 P N P D9 E9

A11 N D B11 P C12 N E B12 P A14 N A B14 P C15 N B B15 P C17 N CLK B17 P A16 B16 N C P A18 B18 N D P C19 B19 N E P LOUT2 LOUT4

D11 N E11 P E12 N D12 P D14 N E14 P E15 N D15 P E17 N D17 P D16 N E16 P D18 N E18 P E19 N D19 P

CLK

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


Standby controller

Q552.2L LA

10.

EN 90

B02G

PNX85500: Standby controller

B02G
+1V1 POL IS3B RES 5S04 30R

1u0 2S10

2S13 2S37 9S24 RES 1u0 2S11 100n

IS20

100n

DS50 AC17 1 7S00-9 PNX85500 XTAL_IN XTAL_OUT RESET_IN EA ALE PSEN MC AE17 AF17 AA26 AB24 AB23 AC26 3S2F 100R 3S2H 100R 100R

3 1S02 2 4 1 54M

2S4G 10p 2S4F 10p +3V3-STANDBY

AA17 VDDA_1V1_DCS

VDDA_ADC2V5

AF26

+3V3-STANDBY 3S1C 3S1E 10K +3V3-STANDBY 3S3M 10K 3S3P 10K RES 3S3S 10K 3S3T +3V3-STANDBY 3S1H 10K 10K RES 10K RES 3S1F 3S3L

3S1B 10K 3S1D 27K 10K

RC TACHO CEC-HDMI BACKLIGHT-PWM-ANA-DISP SDM LCD-PWR-ONn EJTAG-DETECTn LAMP-ON STANDBY FAN-CTRL1 FAN-CTRL2 POWER-OK ENABLE-3V3n RXD-UP TXD-UP DETECT2

2S4D 1n0

RC TACHO CEC-HDMI BACKLIGHT-PWM-ANA-DISP SDM LCD-PWR-ONn EJTAG-DETECTn LAMP-ON STANDBY FAN-CTRL1 FAN-CTRL2 POWER-OK ENABLE-3V3n RXD-UP TXD-UP DETECT2

AD19 0 AE19 1 AF19 2 P1 AA20 3 AB20 7 AC20 0 AD20 1 AE20 2 AF20 3 AA21 P2 4 AB21 5 AC21 6 AD21 7 AE21 0 AF21 1 AA22 2 P3 AB22 3 AC22 4 AD22 5 AD23 0 AE26 1 AE25 P5 2 AE24 3

VDD_XTAL

RESET-STBYn IS3F EA ALE PSEN SDA-UP-MIPS SCL-UP-MIPS LED1 LED2 PNX-SPI-SDO PNX-SPI-SDI PNX-SPI-CLK PNX-SPI-CSBn IS2V IS2Z CTRL-DISP RESET-DVBS RESET-USBn RESET-ETHERNETn SEL-HDMI-ARC RESET-AVPIP RESET-AUDIO AUDIO-MUTE-UP CTRL-DISP RESET-DVBS RESET-USBn RESET-ETHERNETn SEL-HDMI-ARC RESET-AVPIP RESET-AUDIO AUDIO-MUTE-UP RES 10K RES 3S3Y 10K 10K 3S2S RES 3S3W 4K7 3S2L RES 10K RES 10K 10K 4K7 3S46 3S47 3S2M RES 3S49 +3V3-STANDBY EA ALE PSEN
SDA-UP-MIPS SCL-UP-MIPS

RES 10K 3S3N RES 10K 3S3Q RES 10K 3S3R 10K RES

STANDBY

3S44 10K 10K 3S42 3S6V 4K7 RES 3S1P 10K 10K 4K7 3S43 10K

IS3E IS3D RES

AC23 SDA AC24 SCL

3S2G

3S6W RES

3S1G 10K 3S2A 10K RES

AD26 0 PWM AC25 1 AE23 SDO AF25 SDI AF24 SPI CLK AF23 CSB AB17 0 AA18 1 AD18 2 AE18 3 AF18 P0 4 AA19 5 AB19 6 AC19 7

100R

LED1 LED2

3S2K

3S41

3S1K 10K RES

RESET-SYSTEMn 3S1J 100K RES 3S1L 10K 2S4E 100n SPI-PROG KEYBOARD

VSS_XTAL

RESET-SYSTEMn AV2-BLK AV1-BLK KEYBOARD LIGHT-SENSOR AV1-STATUS AV2-STATUS SPI-PROG PNX-SPI-WPn

AF22 4 AE22 P6 5

AD17

+3V3-STANDBY

+3V3-STANDBY

1 3S2V 2

9S0E

1K0

FS45 1

7S20 NCP303LSN28 2 IS2U 5

FS0Z

RESET-STBYn

INP OUTP CD NC GND 3

9S0D

2S4K

100n

RES

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


Power

Q552.2L LA

10.

EN 91

RES 10u

B02H

PNX85500: Power

IS3Q

5S80 +1V1 30R

B02H

2S6A

2S5A

100n

5S81 +2V5

+1V8

RES 10u

30R

2S6B

2S5B

100n

2S26

100n 2S65

100n 2S67

100u 2S60

2S62

100n 2S63

100n 2S61

100n 2S64

100n 2S66

100n 2S68

100n

100n

IS3S

5S82 +3V3

SENSE+1V1

c001 7S00-10 PNX85500

L6 L7 R6 R7 U7 A5 A6 B5 B6 C6 D6 E6 F6 G6 F7 G7

RES 10u

30R

2S5C

2S5D

100n

5S93

30R

+2V5

100n 2S6E 2

+1V1

7S00-12 PNX85500 A1 A10 A12 A15 A17 A19 A26 A3 A8 B1 B20 C20 C4 D2 D20 E13 E20 E4 F10 F12 F14 F16 F18 F20 F8 G10 G12

VSSA

VSS

VSS

VSS

VSSA_1V1_LVDS_PLL

VSSA_2V5_LVDS_BG

2S46

VSSA_USB

VSS

+1V1

J7

G14 G16 G18 G2 G20 G8 H4 H6 H7 J20 K10 K12 K14 K16 K18 K2 K6 K7 L20 L4 M10 M12 M14 M16 M18 M6

30R

VDD_1V1_DDR

VDDA_2V5_VDAC VDDA_3V3_USB

Y10 R21

2S4S

2S5P

2S21

10u RES

100n

1u0

A13

C13

R20

100n

5S94

U24 V24 HDMI_AGND

M7 N2 N20 P10 P12 P14 P16 P18 P4 P6 P7 T10 T12 T14 T16 T18 T2 T6 T7 U4 V10 V12 V14 V16 V18 V2 Y20

AF1 AE2 AD3 AC4 AB5 H20 F11 G11 F13 G13 F15 G15 F17 G17 F19 G19 J9 J11 J13 J15 J17 L9 L11 L13 L15 L17 N9 N11 N13 N15 N17 R9 R11 R13 R15 R17 U9 U11 U13 U15 U17 J6 AA6 Y7 W7 F9 G9

HDMI_VDDA_1V1

V20 V21 U20 U21 U22 N6 N7 C7 C9 C11 C14 C16 C18 W20 P20 M20 K20 V7 Y8 Y19 Y18 IS3K B13

2S5G-1

100n 2S5G-2

100n 2S5G-4

100n 2S5G-3

100n 2S5H-1

100n 2S5H-2

100n 2S5H-3

100n 2S5H-4

2S4Q

22u 2S4R

2S43

2S28

2S27

2S23

100n

100n

100u

100n

100n

22u

VDD

HDMI_VDDA_2V5 HDMI_VDDA_3V3_TERM VDD_2V5

2S4M

2S6D

100n

VDD_1V8

220u 6.3V

+2V5-LVDS

2S4N

2S4P

100n

2S5K-1

100n 2S5K-3

100n 2S5K-2

100n 2S5K-4

100n 2S5J-3

100n 2S5J-1

100n 2S5J-2

100n 2S5J-4

100n

220u 2.5V

2S29

10u

VDD_2V5_LVDS

5S85

100n 1 2S6G 2

100n 2S6N

100n 2S6C

2S6P

2S6F

100n

AA16 AA8 Y11 Y14 Y16 Y9

VDD_3V3

10u

30R

+3V3

+3V3-STANDBY

10u 2S4U

2S4V

VDD_1V1 VDD_3V3_SBY VDDA_1V1_LVDS_PLL

100n
5S83 +1V1

RES 1u0 2S4W

2S4Y

AA15 Y15 VDDA_1V2 AA13 VDDA_2V5 VDDA_2V5_AADC VDDA_2V5_ADAC VDDA_2V5_DCS VDDA_2V5_LVDS_BG VDDA_2V5_USB VDDA_2V5_VADC Y12

5S95

+2V5

100n

IS3L

30R

5S84

6.3V

AA9

30R

+1V2

2S4Z

2S51

2S52

2S50

100n

100n

10u

30R c000
SENSE+1V2

Y17 D13 T20 Y13 POL +2V5-AUDIO

10u

AA7

+2V5-AUDIO

2S45

100n

5S87 +2V5 30R

2S55

2S56

100n

1u0
5S88 +2V5-LVDS

2S5M

100n 2S57

10u

30R

5S89 +2V5

2S6H

100n 2S6K

100n 2S58

10u

30R

5S90 +2V5 30R

2S4T

2S53

100n

2SHW

100n

10u

IS58

5S92 +3V3

2S6M

100n 2S6L

100n 2S59

1u0

30R
3 2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521


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2011-Jul-15 back to

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Circuit Diagrams and PWB Layouts


Analog video

Q552.2L LA

10.

EN 92

B02I
Connectivity

PNX85500: Analog video


AV1-CVBS 22n 2S87

B02I
3S59
2S8A 22n Y-SVHS

47R

AV1-R 22n

2S7J 2S22 22n C-SVHS

3S4J

56R

3S05

EU: SCART1
3S5E
22n

56R

3S5B

47R

CVBS-MON-OUT1

3S4L

56R

IS4V

2S7H AV1-G

3S4K

56R

22n IS4W

3S09
YPBPR1-SYNCIN1 2S7M 10n 2S7L AV3-Y

3S4P

56R

22n

2S7N AV3-PR

56R

EU: AP:

3S4R

YPBPR1 YPBPR1
AV3-PB

22n 7S00-1 PNX85500 2S7P

ANALOG_VIDEO
AB15 AC13 AD13 AE13 CVBS_Y1 ATV_CVBS_Y3 C3 R B AV1 CVBS_Y7 G C7 SYNCIN1 CVBS1_OUT Y_G1 CVBS2_OUT PR_R_C1 PB_B1 RESREF CURREF CVBS_Y2 SYNCIN2 1 Y_G2 2 PR_R_C2 3 PB_B2 REF 4 5 R G VGA 6 B IF_AGC HSYNC_IN RF_AGC IN VSYNC OUT P SCL VGA_EDID TUNER N SDA AGND

2S18 22n

2S16 22n

2S15 22n

3S4T

56R

22n

AD11 AC11 AF11 AE11 AB10 AA11 AC16 AB16 AB13 AB12 AA12 AA10 AD12 AB11 AE12 AF12 BS13

AV2-CVBS 22n

2S8G

9S18

AF15 AE15 AC15 AD15 AB14 AF14 AE14 AC14 AD14 AF16 AD16 AE16 AB18 AC18 AF4 AD24 AD25

IS5E IS5D IS5F IS5G IS5H IS5J

3S5S 10K

22n

IS5C

2S19

3S75

2S14

22n

AC12 AF13

8K2

560R

2S40

3S08

47p

560R

AP:

AV1-B

2S7K

PNX-IF-AGC

AV4-Y

AP:

9S19

EU:

SCART2 YPBPR2

22n

BS10

10n

2S7R

BS15

2S75

10K

3S76

IS11 PNX-RF-AGC

+CVBS
2S76
AV4-PR 22n 2S7U

9S20

AA14

10n

47K

2S77 10n

PNX-IF-P

AV4-PB

2S7E

9S21

22n

2S78 10n

PNX-IF-N

2S84 R-VGA

3S50 3S52 3S54

56R

22n

2S85 G-VGA

56R

22n

2S86 B-VGA

3S5V-4

100R

100R

H-SYNC-VGA

3S5T-1 100R

100R

V-SYNC-VGA

3 3S5T-3 6 100R RES 3 3S5V-3 100R 3S5V-1 100R


3 2011-03-09 2010-12-23

* 319803104790 - RST SM0402 47R PMS Col R at 9S18 for BRZ


6

VGA-SCL-EDID

VGA-SDA-EDID

RES

100R

AP: VGA

3S5V-2

3S5T-4

3S5T-2

EU: VGA

56R

22n

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521


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Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 93

10-3 B03 313912365213


Audio

B03A

Audio
+AVCC

B03A
6
+24V-AUDIO-POWER 4R7

3D09

7D03-1 BC847BS(COL)

+24V-AUDIO-POWER FD14

2D06

3D16 ID11 22K

ID12

220n

220R 5D08

10u 35V

220R

5D07

2D05

GND-AUDIO

-AUDIO-R

FD01

2D28 1u0

ID14

2D24

ID27

ID28

2D07

2D20

2D19

3D14-4 22K

3D02-4

3D14-3 22K

3D14-2 22K

3D14-1 220n

6 7 3D02-2 2 4K7 2 7D15-1 BC847BS(COL) 1

2D08

220n

220n

47n

220u 35V

220u 35V

A-PLOP

FD08

GND-AUDIO

GND-AUDIO 7D10-1 TPA3123D2PWP

19 20

+AUDIO-L

3 6 3D02-3 4K7 3 5 7D15-2 BC847BS(COL) 4

3D02-1 1 8

1u0

47n

AVCC ID19 ID18 6 5 18 17

1 3

10 12

FD03

2D29

ID15

2D23

R PVCC BSR R OUT L 16 15 22 21 ID31 2D09 220n ID32 2D10 ID10 220n 22u ID09 5D01 22u ID05 5D02 ID06 5D05 220R 5D04 220R ID08 ID07 2D12 35V 220u 2D11 35V 220u LEFT-SPEAKER RIGHT-SPEAKER

R IN L 0 GAIN 1 VCLAMP BYPASS MUTE SD

CLASS-D AUDIO AMP

4K7

BSL

GND-AUDIO 2D17 1u0 AUDIO-MUTE-UP A-STBY +3V3-STANDBY

2D16 1u0

ID29

ID30

11 7 4 2

ID37 FD09

PGND AGND L R GND_HS

23 24

13 14

25

8 9

3D15

4K7

3D10-2 22K

3D01-3

3D10-4 22K

3D10-3 22K

3D10-1 220n

2D21 220n 10n

2D22 220n

47K

MAINS SWITCH DETECT

CD10

FD10

7D11-1 BC847BS(COL) 1

3 7D11-2 BC847BS(COL) 4

ID34 ID35 5 4 3D01-4 47K 5 DETECT2

+3V3-STANDBY

GND-AUDIO

22K

2D03

100p

GND-AUDIO

7D10-2 TPA3123D2PWP 26 27 28 29

40 39 38

GND-AUDIO LEFT-SPEAKER

GND-AUDIO

VIA VIA

GND-AUDIO

GND-AUDIO

VIA

GND-AUDIO

GND-AUDIO

VIA 1735 1D38 1 2 3 4 1 2 3 2041145-3

30 31 32 33

V_NOM 2D14

1D50

VIA

37 36 35 34

5D03

FD05 FD06

2D01

220R GND-AUDIO 3D06-3 FD07 3 100K 6 7 3D06-2 100K 2 4 RIGHT-SPEAKER ID33 GND-AUDIO RIGHT-SPEAKER 4 3D06-4 100K 2D02 5 10u GND-AUDIO 3 7D03-2 BC847BS(COL) 5 GND-AUDIO

10n 2D13

FD02

10n

LEFT-SPEAKER

8 3D06-1 1 100K

V_NOM

1D52

2D27 RES
2041145-4

2D26 RES

4K7

22K

2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521


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2011-Jul-15 back to

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Circuit Diagrams and PWB Layouts


DC/DC

Q552.2L LA

10.

EN 94

B03B

DC/DC

B03B
5U03 RES 30R 5U02

FU05

IU22 +12V

2U24

2U23

2U25

2U19

2U20

10u

10u

IU10

7 8 2

3U11

3R3

12V/1V8 CONVERSION
FU02 5U00 3u6

2U21 IU11 220p

10u

10u

1u0

7U02-1 SI4952DY

30R 0402 Jumper

FU03 +1V8

47R 3U23-3

3U23-4

3U23-2

47R 3U23-1

2U15

7U02-2 SI4952DY IU09 5 6 4

IU23

2U17

2U18

7U01 SI4778DY IU08 3U27 10R IU12 5 6 7 8 4 1 2 3

2U00

3U14

10u

3U04 IU05

3R3

3R3

2U22 IU06 2U02 100n IU07

3U28

2U01

100n

3R3

10R

IU13

220p

7U03 TPS53126PW 2 11 3 10 1 VBST 2 1 EN 2 1 VO 2 1 VFB 2 1 TRIP 2 VIN GND 1 2 1 2 1 2 1 2 1 2

3U05

7U04 SI4778DY IU16 IU14 5 6 78 4 1 2 3

IU24 ENABLE-1V8

DRVL

23 14 1 12 24 13 22 15 7 17 18 19 GND-SIG IU25 FU04

12V/1V1 CONVERSION
FU06 5U01 2u0 FU01 +1V1

DRVH

1n0 RES

2U03

3U24-4

47R 3U24-3

3U24-2

47R 3U24-1

3U20

2U12

47R

47R

RES 7U00 BC847BW IU03 1 2 +3V3-STANDBY 3U00 10K 3U01 2U06 3

GND-SIG 3U02 22K GND-SIG GND-SIG +1V1 12K 3U03

IU01

21 16 20

TEST

IU02

2U11

2U04

2U05

100n

10u

1u0

10K

IU18

GND-SIG

1n0

V5FILT VREG5

IU17

2U09

2U10

1n0

GND-SIG

1u0

47u

22u

PGND

2U13

10R RES

5 8

3U21 IU19 100R 1%

FU00

1% 330R

3U17

RES 2U29

IU20

100p RES

2U08

3U19

3U18

5K6

3U08 +1V8 330R 1%

3U22 1K0 1%

IU04

FU09

CU00 CU01 CU02 CU03 CU04 CU05

FU08 IU21

RES 100p

1K0 1%

3U09

3U10

2U07

22K

GND-SIG

GND-SIG

GND-SIG

GND-SIG

GND-SIG

GND-SIG

GND-SIG

1% 1K0

100n

RES 100u 2.0V


SENSE+1V1

SW

STPS2L30A

+1V1 +1V8

4 9

1n0

1n0

IU15

2U16

47R

47R

47u

22u

6U00

2U14

2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 65213


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2011-Jul-15 back to

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Circuit Diagrams and PWB Layouts


DC/DC

Q552.2L LA

10.

EN 95

B03C

DC/DC
+3V3 LED-2 RES 10K RES 10K 3U74 3U75 +3V3-STANDBY

B03C
**
Items Optional table for Ambilight Emmy ( +24V AL) yes yes no yes no Sundance / Infinity ( +12V AL) no no yes yes yes BlockBuster (For non-Amblight sets) no no no yes no

+5V +3V3-STANDBY

***

Optional table for Styling 2U44 3U43 open 100R 1M95 13 POLE 14 POLE

9U41 RES 10K 3U68 3U69 10K

IU43

IU44 IU45 9U42 RES 7U42 RES BC847BW IU47

3U41 10K RES

* *

optionally 1M99 is a 9 pin connector

LED2

LED2

3U59 10K RES

4U00 4U01 1M99 1M95 2U56

Dream Catcher Core Range

0R 100p

LED-1

+3V3 LED1 LED1 3U53 10K

7U43 BC847BW

3U70 10K

1M99 1 2 3 4 5 6 7 8 9 10 11 12 13 1-2041145-3 RES 2U57 2U56 1n0 1n0 GND_AL GND_AL GND_AL FU77 +12VIN FU56 FU57 FU74 FU68 100p 100p 100p 100p 100p RES 3U66 RES 3U67 RES 3U84 RES 3U76 RES 2U48 RES 2U72 RES 2U51 RES 2U52 RES 2U43 100R 4 100R 100R 100R BL-SPI-SDO BL-SPI-CSn BL-SPI-CLK FU48 FU49 FU50 FU54 RES 3U44 100R FU07 3D-LR +12V_AL +3V3 RES 3U56 10K 4 3U82 1K0 RES 3U83-4 5 7U48-1 BC857BS(COL) 1 ENABLE-3V3-5V IU64

3U83-1 2 1

8 2U71 +3V3-STANDBY 3 100n 5 7U48-2 BC857BS(COL) 3U83-2 100K 6 IU40 7 100K 2

100K IU41

MAINS-OK

**

3U71

100R

STANDBY 5 7U40-2 BC847BPN(COL) IU48 5 3 3U62-3 3 IU61 7 10K 3 3U60-3 6 22K FU73 RES 10K 3U61 10K 4 3U83-3 100K

2U68 1u0 2U47 BZX384-C6V2 1M95 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1-2041145-4

3U62-4 4

10K

***
FU58 FU59 FU60 FU61 FU63 FU75 FU67

6U40

10n 2U54 +12VIN T 3.0A 32V 3U72 2U50 +24V-AUDIO-POWER 1K0 1U40 +12V

22K

IU51

1u0 RES

10n

2U55

2U49

3U80

100n

4K7

FU62 FU76 2U58 100n

3U63

10K FU51 FU52 FU53 3U45 100R 100R 100R FU55 3U64 IU55 POWER-OK 100p 3U42 3U43 LAMP-ON BACKLIGHT-PWM_BL-VS BACKLIGHT-BOOST

***

** **

4U01 4U00 1K0 3U65 2U53 100K 1n0 10n

GND_AL +12VIN

1n0

*** 2U44

+12VD

2U45

2U46

RES 10K

+24V

GND-AUDIO

+3V3

3U81

IU56

+3V3-STANDBY 3K3

6 1 7U41-1 BC847BS(COL) 1 10K

3U73

3U62-1

IU62 IU50

3U60-4

22K

**
10n +3V3-STANDBY FU66

ENABLE-1V8

IU49 6 7U40-1 BC847BPN(COL) 1 IU63

3U62-2

FU72 7U41-2 BC847BS(COL) 5 4 IU52 8 3U60-1 22K IU57 1

3U60-2

DETECT2

ENABLE-3V3n

2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521


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Circuit Diagrams and PWB Layouts


DC/DC

Q552.2L LA

10.

EN 96

B03D

DC/DC
+3V3 7UC0 LF25ABDT 1 IN OUT COM 3

B03D
*
+12V

2UA4

3UA0

2K2

*
FUA0 +2V5-REF

1u0

1 7UA0 TS2431

FUA4 +2V5

IUB6 +5V5-TUN +5V-TUN

CUA0

+2V5-LVDS

+12V

+2V5-REF

3UB6-4 4 5 1K0 3UB7-4 4 5 470R

330R 1%

5 7UA7-2 4 BC847BS(COL)

7UA7-1 BC847BS(COL) 3U13 IUB4

2UB0

1u0

6 1K0 IUB2 3UB6-2 2 7 6 1K0 3UB6-1 1 8 1K0 IUB5 3 1

3UB6-3

7UA6 BC817-25W 3U12 IUB3

330R 1%

+1V8 +5V IU26 7UA3 PHD38N02LT 3UB0 22R FUA3 4 +1V2 IUA5 2 1

*
3U15-1 100R 3U15-2 100R 3U15-3 100R 3U15-4 100R 7 8

+3V3 +5V

3U16-1 100R

+3V3

3U16-2 100R 3U16-3 100R 3U16-4 100R

2 470R 3UB7-3 3 3UB7-1470R 8 1

3UB7-2

2UB8

470R

22u

2UB1

RES 1u0

2UB2

1u0

NOT FOR 5000 SERIES

ENABLE-1V8 4 3U25-4 5 3UB1 SENSE+1V2

100K RES

100K RES 3 3U25-3 6

IUA6

1K0

RESERVED 5UA0 30R

3U25-2

100K RES

3U29-1 470R 3U29-2 470R

RES

+12V

7UA5 LDS3985M50 +5V5-TUN 1 3 IN INH OUT BP 5 4 IUB1 +5V-TUN

100K RES

IU29

RES 7UA4 TS431AILT 5 A


NC

3U25-1 3 RES 7U06-2 BC847BS(COL) 4

6 5 RES 7U06-1 BC847BS(COL) 1 IU30 2

+3V3

3 3U29-3 6 RES 470R 3U29-4 470R 1 3U26-1 8 RES 470R 3U26-2 470R RES 3UB5 +5V 6 RES 100K RES

3UB2 3

4K7

2UB7

2UB5

100n 2UB6

REF

3UB3

3UB4 1K0

IUB0

2UB3 1n0

+3V3

3U26-3 470R 3U26-4 470R

2UB4 RES 330p RES


3 2011-03-09 2010-12-23

4K7

NC

1u0

SPB SSB TV550 2K11 4DDR BR SD

1u0

COM

3139 123 6521


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Circuit Diagrams and PWB Layouts


DC/DC

Q552.2L LA

10.

EN 97

B03E

DC/DC
5UD0 +12V IUD0 +5V5-TUN 2UD0 2UD1 2UD2 10u 10u 10u 7UD0-1 ST1S10PH ENABLE-3V3-5V RES 1n0 2 5 INH SYNC A 4 1 A SW 6

B03E
*
30R 0402 Jumper 7 3 IUD3 5UD1 3u6 2UD4 22u 2UD5 22u IUD7 6UD0 SS36 2UD6 FUD3 +5V RES 2U27 RES 2UE9 220u 16V +1V1 100n

VIN

SW

2UD3

VFB GND P HS 8 9

6 7U05-1 BC847BS(COL) RES 1 2

IU27

IUD6 7UD0-2 ST1S10PH 10 11 14 13 15

2UD7 4n7 3UD2 120K

1% 3UD0

68K 3UD1

* *
+12V

5UD3

IUD1 7UD1-1 ST1S10PH ENABLE-3V3-5V 2 5 INH SYNC A 4

2UD8

2UD9

2UE0

10u

10u

10u

30R 0402 Jumper

SW

VIN

SW

7 3

IUD4

5UD2 3u6

FUD2 +3V3 220u 16V +1V1 RES 2U28 100n 2UE1 1% 100K 4n7 3UD3 2UE2 22u 2UE3 2UE4

VFB GND P HS 8 9

22u

3 7U05-2 RES 4

BC847BS(COL) 5

RES

VIA

12

33K 1%

3U06

IUD2 7UD1-2 ST1S10PH 10 11 14 13 15

3UD4

1M0 3UD5

*
+5V

7UD2 LD1117DT25 6UD1 S1D 2UE5 100n IUD5 3 IN OUT COM 1 2UE6 2 22u 16V +2V5

(*) FOR 5000 SERIES ONLY (**) NOT FOR 5000 SERIES

7UD3 LD1117DT33 3 IN OUT COM 2UE7 1 2UE8 100n 2 22u 16V +3V3

RES

VIA

12

33K 1%

3U07

10K

10K

IU28

22u

2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521


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Circuit Diagrams and PWB Layouts


Temperature sensor & AmbiLight

Q552.2L LA

10.

EN 98

B03F

Temperature sensor & AmbiLight

B03F

5UM1 +3V3 30R

IUM0

1UM0 T 1.0A 63V

FUM0

V-AMBI

2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 65213


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Circuit Diagrams and PWB Layouts


Fan control

Q552.2L LA

10.

EN 99

B03G

Fan control

B03G
+12V +3V3 1 3US4-1 8 10K +12V

3US5-2

+12V 3 7US1-1 LM339P 14

10K 7

2US3 IUS6 7US2 BC807-25W IUS7 3US9 22R BC807-25W 7US3 IUS9 3US6 47R

3US2

FAN-CTRL1

1K0 IUT1

IUS3 3US5-1 8 1 10K

8 12

+12V +3V3 3US5-3 6

11 IUT2 FAN-CTRL2 10

IUS4 3US5-4 5 4 10K IUS8

12

FAN-DRV +3V3 +12V 10K +12V 7US1-3 LM339P 2 3US4-4 IUS5 3US4-3 6 10K 5

5 4

TACH01

+12V 9US0 RES +12V 3US4-2 7 10K 7US1-4 LM339P 1

7 6

12

TACH02

FUS0

TACHO

12

3US3

10K

7US1-2 LM339P 13

10K

+12V

3US7

100n

10K

2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521


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Circuit Diagrams and PWB Layouts


Vdisp switch

Q552.2L LA

10.

EN 100

B03H

Vdisp switch

B03H

1 9UU0-1 RES 2 9UU0-2 RES 3 9UU0-3 RES 4 9UU0-4 RES 1 9UU1-1 RES 2 9UU1-2 RES 3 9UU1-3 RES 4 9UU1-4 RES

8 7 6 5 8 7 6 5 FUU0

RES 7UU0 SI4835DDY +12VD RES 7UU2-2 PUMD12 8 4 5 IUU0 6 RES 3UU0-4 +3V3-STANDBY 5 47K 4 2 RES 7UU2-1 PUMD12 1 3 RES 3UU1

RES 7UU1 SI3441BDV RES 2UU2 22n

+VDISP-INT

3UU3-1

1 3UU3-2 IUU3 7

47K RES RES 2UU1 1u0 IUU2

47R IUU1 RES 3UU0-1 8 1 47K

47K RES RES 7UU3 BC847BW

RES 3UU0-2 7 2

3 47K

IUU4 3UU3-3 IUU5 3UU3-4 4 5 6 3 47K RES 2UU0 RES 100n 47K RES

+3V3

VDISP-SWITCH

FUU1 3UU2 4K7 RES

+3V3

LCD-PWR-ONn

2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521


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Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 101

10-4 B04 313912365213


Analogue externals A

B04A

Analogue externals A

B04A

IE22 AUDIO-IN1-R 1 2E06 100p

3E07-1 CDS4C12GTA 12V 1K0 8 RES 6E03 1E31 2E88

FE71

AUDIO-IN1-L

FE23 4 2E04

3E07-4 1K0 5 CDS4C12GTA 12V 6E09 1E54 2E91 1n0

100p

1n0

RES

** ** 4E01
RES

1E02-1 MSP-8032SH-01-NI-FE-RF-PBT-BRF RED 1 2 1E02-2 MSP-8032SH-01-NI-FE-RF-PBT-BRF WHITE 3 4

AV1-STATUS

IE18

3E32 AV2-STATUS IE05 3E17 3E44 IE48 AV1-BLK 3E73 IE51 AV2-BLK CVBS-MON-OUT1 3E07-2 2 1K0 3E07-3 3 1K0 6 7 18p

YPBPR1-PB EU 3E74 18R FE73

** 4E02
RES

AV1-B

IE53

5E73 1u8

BEC3

3E75 18R CDS4C12GTA 12V

2E80

2E79

RES 6E23

1E12

2E15

150p

150p

100p

RES

FE74

YPBPR1-SYNCIN1 EU 3E76 18R

** 4E05
AV1-G FE86 2E83 150p 5E74 2E84 150p 1u8 3E77 18R RES 6E26 CDS4C12GTA 12V RES FE80

1E01-3 MSP-8033SH-02-NI-FE-RF-PBT-BRF GREEN 5 6

+3V3

1E18

2E14

RES
YPBPR1-PR EU 3E78 18R BEC5 3E79 2E86 150p 18R

100p

**
FE81 CDS4C12GTA 12V

AV1-R

IE55 2E85 150p

5E76 1u8

4E03 RES

1E01-1 MSP-8033SH-02-NI-FE-RF-PBT-BRF RED 1 2

RES 6E28

1E19

2E12

FE85

RES

GND_A

2E98

100p

4K7

4K7

**

4E04 RES

1E01-2 MSP-8033SH-02-NI-FE-RF-PBT-BRF BLUE 3

+3V3

4K7

4K7

2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521


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2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts


Analogue externals B

Q552.2L LA

10.

EN 102

B04B

Analogue externals B

B04B
SPDIF out EU
CDS4C12GTA 12V RES 6E40 9E29 IE71 3E87 18R YPBPR1-SYNCIN1 FE72 AV3-Y SPDIF-OUT IE15 RES 5E06 30R RES 2E22 10p RES 1E44 RES 6E46 FE59 CDS4C12GTA 12V RES 1E07 MTJ-032-68B-46-NI-FE 1 2 FE41

YPBPR
2 1E08-1 * MSP-8033SH-05-NI-FE-RF-PBT-BRF 1 2E27 YELLOW 1E43 100p FE54

**

4E20 RES

AP

9E04

3E88 27R

IE73

AV2-CVBS

GND_A
MTJ-032-21B-45 NI FE (PBT) 1E03 2 1

FE51 CDS4C12GTA 12V

EU
RES 6E51

9E57

IE74

3E89 18R

IE75

AV3-PB YPBPR1-PB

2E67

100p

** 4E21

RES

GND_A
MTJ-032-21B-42 NI FE 2 1E04 2E68 100p 1 FE48

1E28

EU
CDS4C12GTA 12V RES 6E52

9E58

IE76

3E90 18R

IE77

AV3-PR YPBPR1-PR

** 4E22

RES

FE42

GND_A

1E39

YPBPR AUDIO
MSP-8033SH-05-NI-FE-RF-PBT-BRF 6 CDS4C12GTA 12V 3E97 FE50 1E29 RES 6E06 2E39 1n0 1K0 2E72 100p IE31 AV3-Y AV1-CVBS

Provision for Dreamcatcher


+3V3 AUDIO-IN3-R 9E15 9E16 RES RES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 RES 1E32

1E08-3 RED

** 4E23
RES

FE43

AV3-PR RXD1-MIPS 3E96 IE29 AUDIO-IN3-L AV3-PB TXD1-MIPS 2E71 100p

9E19 9E12

RES RES

GND_A
4 1E08-2 3 * MSP-8033SH-05-NI-FE-RF-PBT-BRF RES WHITE 4E24

FE49

CDS4C12GTA 12V

1K0

9E17 9E14

RES RES

2E40

1E42

**

RES 6E38

1n0

GND_A

AUDIO-IN3-R AV1-B

9E11 9E18

RES RES

AUDIO-IN3-L AV1-G

9E13 9E20

RES RES

VGA ( OR DVI ) AUDIO


AV1-R 1E09 MSJ-035-69A-B-RF-PBT-BRF 2 3 1 2E36 1n0 1E37 FE02 CDS4C12GTA 12V 3E21 1K0 2E35 100p IE09 AUDIO-IN4-L AV1-STATUS AUDIO-IN1-R AV1-BLK AUDIO-IN1-L 9E24 9E25 9E26 9E28 RES RES RES RES 9E22 RES

V_NOM

RES 6E19

31

FE01 IE10 AUDIO-IN4-R 2E38

DF50-30DP

FE03 CDS4C12GTA 12V

3E20 1K0 100p

V_NOM

+3V3

3E9C

1E10 3150-831-030-H1 2 VCC VIN GND MT 7 6 5 4 1 3 FE44

1R0

RES 6E20

2E37

1n0 1E38

SPDIF-OPT

RES 2E77

RES 6E53

CDS4C12GTA 12V

V_NOM

2E73

100p 1E80

100n

* SOC Cinch V 3P 1L3 YEWHRDY at 1E08 for Brazil ** Provision for ESD
SPB SSB TV550 2K11 4DDR BR SD
3139 123 6521
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3 2 2011-03-09 2010-12-23

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts


Ethernet & Service

Q552.2L LA

10.

EN 103

B04C

Ethernet & Service


TXD1-MIPS 7 RXD1-MIPS 5E08 +3V3 30R 2E62 10u 2E63 100n 2E66 100n IE07 +3V3-ET-ANA 6

3E53-2 47R 3E53-3 47R

IE49 2 IE50 3 BZX384-C5V1 BZX384-C5V1 4 1

3E53-1 47R 3E53-4 47R

8 FE57

FE56 2 3 1 1E06

6E43

6E44

1E85

1E86

MSJ-035-69A-B-RF-PBT-BRF FE58

UART SERVICE CONNECTOR

B04C

+3V3-ET-ANA +3V3

+3V3

PROVISION FOR iTV


IE32 3E30 IE33 2E52 100n 2E53 2E49 2E48 100n 4n7 10u RES 1E71 TXD RXD 2E54 10p 7E10-1 LAN8710A-EZK 27 12 6 1 +3V3 1 2 3 5 IE38 IE06 1M0 1E70 NX3225GA 25M 10p

10K 10K 10K 10K

3E66 3E67 3E81 3E82

3E33

10K

RES RES RES RES

2E55

CR 5 4 CLKIN 1 XTAL 2 RST

1A 2A VDD

IO

502382-0370 31 30 29 28 20 26 13 IE63 3E64 7 IE64 3E65 3 10K 2 10K 14 32 12K1 1% 3E40 IE39 RXD1-MIPS 3 1 X1 7 9E42 3E72 3E34 3E68 RES 3E35 RES RES 10K 10K +3V3
ETH-INTSEL

RESET-ETHERNETn ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3)

IE26

RES 2E70

10p 19 11 10 9 8

RX

RES 6E48

P N P N

BAS316

ETH-RXP ETH-RXN ETH-TXP ETH-TXN ETH-TXCLK

provision for iTV

RES 2E69

ETH-COL

3E70 RES

3E69 RES 10K

10K 15 RES 3E71 RES 3E80 10K 10K +3V3 21 22 23 24 25 18

RXDV RXER RXD4 0 PHYAD 1 RXCLK REGOFF 1 LED 2 INTSEL CRS RBIAS

ETH-RXDV ETH-RXER

14

RES 3E9D

RES 3E9E

10K

ETH-RXCLK

ETH-TXEN ETH-TXD(0) ETH-TXD(1) ETH-TXD(2)

TXEN 0 1 2 TXD 3 4 INT TXER MDC MDIO

10K

+3V3 RXD-UP
ETH-REGOFF

1 1 X1 7

13 RES 7E12 PDTC144EU RES 7E13 PDTC144EU AV2-BLK

ETH-TXD(3)
ETH-TXER

+3V3 14
ETH-CRS

ETH-MDC ETH-MDIO

17 16 3E51 1K5 +3V3

RES 7E11-2 74HC4066PW 4 5

VSS 33 7E10-2 LAN8710A-EZK 34 35 36 40 41 42

VIA VIA 37 38 39

VIA

TXD-UP

1 1 X1 7

RES 7E11-3 74HC4066PW 8 6

14

TXD1-MIPS

10

1 1 X1 7

RES 7E11-4 74HC4066PW 11 12

+3V3-ET-ANA

+3V3-ET-ANA

CONFIGURATION RESISTOR SETTINGS


49R9 1% 49R9 1% 49R9 1% 49R9 1% 3E22 3E25 3E95 3E99 3E26 22R 3E98 22R

Resistor ETHERNET CONNECTOR


ETH-TXP ETH-TXN FE27 FE28 1E87 3 ACM2012 2 FE60 4 1 FE30 FE61 1E88 3 ACM2012 2 4 1 CDA5C16GTH 16V RES CDA5C16GTH 16V RES CDA5C16GTH 16V RES CDA5C16GTH 16V 6E47-3 6E47-1 6E47-2 6E47-4 9 11 10 12 2E60 22n FE34 8 6 7 5 1N00 1 2 3 4 5 6 7 8

POP

14

EMPTY

3E64 (RES) 3E65 (RES) 3E66 (RES) 3E67 (RES) 3E68 (RES) 3E69 (RES)

PHYADD(0) = 1 PHYADD(1) = 1 PHYADD(2) = 1 RMII mode selected Internal 1.2V reg. disabled MODE(0) = 0 MODE(1) = 0 MODE(2) = 0 INTERRUPT FUNCTION DISABLED ON nINT/TXER/TXD4 SIGNAL

PHYADD(0) = 0 PHYADD(1) = 0 PHYADD(2) = 0 MII mode selected Internal 1.2V reg. enabled MODE(0) = 1 MODE(1) = 1 MODE(2) = 1 INTERRUPT FUNCTION ENABLED ON nINT/TXER/TXD4 SIGNAL

ETH-RXP ETH-RXN

FE29 FE31

5E01

5E03

5E02

5E04

RES 27n

RES 27n

RES 27n

RES 27n

RES

5450-323-183-H3

2E08

2E05

2E07

2E09

RES 15p

RES 15p

RES 15p

RES 15p

2E57

2E58

2E56

15p 3E39

2E59

0 ohm

15p

0 ohm

15p

0 ohm

3E27

3E28

3E29

0 ohm

15p

3E70 (RES) 3E71 (RES)


FE32

RES

RES

RES

RES

RES

RES

RES

RES

ETH-INTSEL ETH-REGOFF

3E72

FE33

10K

COL CRS_DV MODE2

10K RES

100n

0 MODE 1 RMIISEL PHYAD2 RXD<0:3>

TX

TXCLK

+3V3

RES 7E11-1 74HC4066PW 1

2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

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2011-Jul-15 back to

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Circuit Diagrams and PWB Layouts


HDMI

Q552.2L LA

10.

EN 104

B04D
1P04 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FEC6 21 23

HDMI
I2C Address
5EC0 2EC0 RES 2EC1 FEC0 2ECV 100n 10u 1u0 FEC3 2EC2 MICOM-VCC33 220u 16V 3ECH 10K 30R

B04D

SII9187B = 0xB2

HDMI CONNECTOR 3
ARX2+ ARX2ARX1+ ARX1ARX0+ ARX0ARXC+ ARXCPCEC-HDMI FEC1 FEC2 FEC4 47K FEC5 20 22 AIN-5V ARX-HOTPLUG ARX-DDC-SCL ARX-DDC-SDA ARX-DDC-SCL ARX-DDC-SDA 1 ARX-HOTPLUG AIN-5V
ARX-DDC-SDA ARX-DDC-SCL

+3V3

FECB

AIN-5V +3V3-HDMI RES 2ECW 2EC6 100n 2EC7 100n 2EC8 100n 10u

FEC7 2EC3

RES 5EC3 100n 30R

+3V3

3EC1-3

47K

7EC1 SII9187B

9 27 64

37 MICOM_VCC33

VCC33 3EC1-1 4 3ECM-4 10R 5 1 3ECN-1 1u0 8 100K 2ECM IE42 31 32 29 30 65 66 67 68 69 70 71 72 35 36 33 34 1 2 3 4 5 6 7 8 41 42 39 40 11 12 13 14 15 16 17 18 45 46 43 44 19 20 21 22 23 24 25 26 (CBUS) HPD0 R0PWR5V DSDA0 DSCL0 N R0XC P N R0X0 P N R0X1 P N R0X2 P (CBUS) HPD1 R1PWR5V DSDA1 DSCL1 N R1XC P N R1X0 P N R1X1 P N R1X2 P (CBUS) HPD2 R2PWR5V DSDA2 DSCL2 N R2XC P N R2X0 P N R2X1 P N R2X2 P (CBUS) HPD3 R3PWR5V DSDA3 DSCL3 N R3XC P N R3X0 P N R3X1 P N R3X2 P

SBVCC33

38

+5V-EDID 8 3ECP-1 10K 3ECP-3 1 3 6 10K

R4PWR5V DSCL4 DSDA4 CEC_D

49 48 47 51

1P03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FECG 21 23

HDMI CONNECTOR 2
BRX2+ BRX2BRX1+ BRX1BRX0+ BRX0BRXC+

AIN-5V

ARXCARXC+ ARX0ARX0+ ARX1ARX1+

VGA-SCL-EDID-HDMI VGA-SDA-EDID-HDMI 9EC2 RES CEC-HDMI

BIN-5V BRX-HOTPLUG BIN-5V BRX-DDC-SDA BRX-DDC-SCL 3 3ECM-3 10R 6 2 3ECN-2 1u0

ARX2ARX2+ 7 100K 2ECN IE43

TX2

N P N P N P N P

57 56 59 58 61 60 63 62 3ECJ RES

HDMIA-RX2HDMIA-RX2+ HDMIA-RX1HDMIA-RX1+ HDMIA-RX0HDMIA-RX0+ HDMIA-RXCHDMIA-RXC+ RES 3ECK 4K7 9EC3 RES PCEC-HDMI 3ECL RES 4K7 MICOM-VCC33

3ECA-2

47K

BRXCPCEC-HDMI FECC FECD FECE FECF 20 22 BIN-5V BRX-DDC-SCL BRX-DDC-SDA BRX-DDC-SCL BRX-DDC-SDA

TX1

BRXCBRXC+ 8 3ECA-1 BRX0BRX0+ BRX1BRX1+ BRX2BRX2+ CRX-HOTPLUG CIN-5V 2 3ECM-2 10R 7 3 3ECN-3 1u0 6 100K 2ECP IE44

TX0

TXC

47K

BRX-HOTPLUG

TPWR_CI2CA

55 IE12 FECR

4K7

CEC_A

50

BIN-5V

HDMI CONNECTOR 1
1P02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 23 CRX2+ CRX2CRX1+ CRX1CRX0+ CRX0CRXC+ CRXCPCEC-HDMI ARC-eHDMI+ CRX-DDC-SCL CRX-DDC-SDA 47K CIN-5V CRX-DDC-SDA CRX-DDC-SCL

INT

52

FECY

+3V3

CRXCCRXC+ CRX0CRX0+ CRX1CRX1+ CRX2CRX2+ DRX-HOTPLUG 6 DIN-5V DRX-DDC-SDA DRX-DDC-SCL eHDMI+ 5EC2 30R CIN-5V ARC-eHDMI+ 2ECC 1 3ECM-1 10R 8 4 3ECN-4 1u0 5 100K 2ECQ IE45

CSCL CSDA

54 53

3EC3 3EC5

100R 100R

SCL-SSB SDA-SSB

RES 2ECX

FECJ FECA FECK FECL FECM FECN 20 22 RES 7E02 BC847BW CIN-5V

CRX-DDC-SCL CRX-DDC-SDA 3ECA-3

3ECA-4

FECP

47K

CRX-HOTPLUG 3E23 22K RES +3V3-STANDBY

DRXCDRXC+ DRX0DRX0+ 10p DRX1DRX1+ DRX2DRX2+

VIA

PCEC-HDMI

3ECD 100R IEC4

7EC0 BC847BW IEC5

IEC6 9EC0 CEC-HDMI

74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

EPAD IEC7 22K FECW +3V3-STANDBY 73

3ECE

6EC1 +5V BAT54 IE11 4R7 IE65 2 3ECU-2 10K 2ECU 1u0 DDCA-SCL IE66 4 3ECU-4 5 10K 7 +3V3 +5V-VGA

10p

RSVDL

10p RES 2ECY

10 28

7EC1 NON-INSTAPORT INSTAPORT 9187B 9287B

3ECN 4X 100K 4X 100K

3ECF 100K 100K BLOCKBUSTER SUNDANCE

3ECG 3ECF 100K

DDCA-SDA

FECZ

2011-03-09 2010-12-23

+5V-EDID

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521


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Circuit Diagrams and PWB Layouts


Headphone

Q552.2L LA

10.

EN 105

B04E

Headphone

B04E

+3V3-STANDBY

4 PUMD12 7EE0-2 A-PLOP 3

6 FEE0 RESET-AUDIO 2 7EE0-1 PUMD12 1

A-STBY

2EE0 47p 3EE1-1 22K 4 3EE1-4 22K 2EE5 47p +3V3 5

8 7 3EE1-2 3EE1-3 3 22K 6 22K

2EE1

7EE1 TPA6111A2DGN

100n

IEE0 ADAC(3) IEE2 ADAC(4)

2EE3 1u0

IEE1 2EE4 1u0

3EE0-1 10K

IEE3 1 5 3EE0-4 10K 4 IEE4 2EE2 1u0 IEE6 IEE5 2 6 5 3 1 2

AMPLIFIER
INVO

3 2EE6 4V 100u 7 10 11 2EE7 4V 100u 1 IEE8 2 IEE7

VDD 1 1 4

3EE2-3 33R 3EE2-4 33R 3EE2-2 33R 3EE2-1 33R

6 FE36 5 AMP1

FE35 7 AMP2

SHUTDOWN BYPASS 4

VIA GND GND_HS 9

A-PLOP

3 3EE0-3 6 RES 3EE3 22K 10K

2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521


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2011-Jul-15 back to

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Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 106

10-5 B05 313912365213


DDR

B05A

DDR

+1V8

DDR2-VREF-DDR

+1V8

DDR2-VREF-DDR

B05A

2B40

47u 2B00

100n 2B02

100n 2B03

100n 2B01

100n 2B04

100n 2B05

100n 2B06

100n 2B07

100n

2B36 100p 2B08 100n

100n 2B13

47u 2B09

100n 2B10

100n 2B14

2B41

100n 2B11

100n 2B12

100n 2B15

100n 2B16

A1 E9 L1 H9

A9 C1 C3 C7 C9 VDDQ

E1

AT T-POINT
3B22 240R DDR2-CLK_N 3B27 240R DDR2-CLK_N 3B28 240R DDR2-CLK_P DDR2-CLK_N DDR2-CLK_P DDR2-CLK_P

DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-BA0 DDR2-BA1
DDR2-BA2

H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1 3B01 RES 240R F9 E8 F8 F2 G8 F7 G7 F3 B3

VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13 0 1 BA 2 ODT CK CKE CS RAS CAS WE DM|RDQS VSS A3 E3 J1 K9

VDDL

VDDQ

VREF 3B00-2 DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-BA0 DDR2-BA1
DDR2-BA2

SDRAM
DQ

0 1 2 3 4 5 6 7

C8 3 C2 D7 1 D3 D1 D93B00-4 4 B1 B9 3B00-11

2 6 3B02-3 33R 3 8 3B02-1 33R 2 3B02-2 5 R 333 B02-4 4 8 33R

7 33R 6 3B00-3 33R 7 33R 5 33R

DDR2-D16 DDR2-D17 DDR2-D18 DDR2-D19 DDR2-D20 DDR2-D21 DDR2-D22 DDR2-D23

DQS

B7 A8 2B44 RES

3B13 2p2 33R

3B12 33R

DDR2-DQS2_P DDR2-DQS2_N

H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1 3B03 RES 240R F9 E8 F8 F2 G8 F7 G7 F3 B3

VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13 0 1 BA 2 ODT CK CKE CS RAS CAS WE DM|RDQS VSS A3 E3 J1 K9

VDDL

VREF 3B04-2 2 7 6 33R 6 33R 33R 7 3B05-2 33R 2 1 8 3B05-1 33R 5 5 3B05-4 33R 4 8 33R 33R 3B14 33R 33R

SDRAM
DQ

E2

7B02 EDE1108AGBG-1J-F

A1 E9 L1 H9

A9 C1 C3 C7 C9

E1

E2

7B03 EDE1108AGBG-1J-F

100n

2B17 100n 2B37 100p

0 1 2 3 4 5 6 7

C8 3B05-3 C2 D7 3B04-3 D3 D1 D93B04-4 B1 B93B04-1

3 3

4 1

DDR2-D24 DDR2-D25 DDR2-D26 DDR2-D27 DDR2-D28 DDR2-D29 DDR2-D30 DDR2-D31

DQS

B7 A8 2B45

NU|RDQS

A2

3B15 RES 2p2

DDR2-DQS3_P DDR2-DQS3_N

DDR2-ODT DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM2

NU|RDQS

A2

DDR2-ODT DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM3

NC

L3 L7

DDR2-A14

NC

L3 L7

DDR2-A14

3B23 33R

VSSDL E7

VSSQ A7 B2 B8 D2 D8

3B24 33R

VSSDL E7

VSSQ A7 B2 B8 D2 D8 DDR2-VREF-DDR

+1V8

+1V8

DDR2-VREF-DDR

100n 2B22

100n 2B23

2B42

47u 2B18

100n 2B24

100n 2B19

100n 2B20

100n 2B21

100n 2B25

100n

2B26 100n 2B38 100p

2B43

47u 2B27

100n 2B30

100n 2B32

100n 2B33

100n 2B28

100n 2B31

100n 2B29

100n 2B34

A1 E9 L1 H9

A9 C1 C3 C7 C9 VDDQ

E1

DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-BA0 DDR2-BA1
DDR2-BA2

H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1 3B06 RES 240R F9 E8 F8 F2 G8 F7 G7 F3 B3

VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13 0 1 BA 2 ODT CK CKE CS RAS CAS WE DM|RDQS VSS A3 E3 J1 K9

VDDL

VDDQ

VREF 3B07-2 DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-BA0 DDR2-BA1
DDR2-BA2

SDRAM
DQ

0 1 2 3 4 5 6 7

C8 C23B08-4 4 D7 D3 3B08-2 2 D1 D9 3B07-4 4 B1 B9 3B07-1 1

2 5 33R 7 33R 5 33R 8 33R 3 1 3

7 33R 6 3B07-3 33R 8 3B08-1 33R 6 3B08-3 33R

DDR2-D0 DDR2-D1 DDR2-D3 DDR2-D2 DDR2-D4 DDR2-D5 DDR2-D6 DDR2-D7

DQS

B7 A8 2B46

3B17 RES 2p2

3B16 33R 33R

DDR2-DQS0_P DDR2-DQS0_N

H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1 3B09 RES 240R F9 E8 F8 F2 G8 F7 G7 F3 B3

VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13 0 1 BA 2 ODT CK CKE CS RAS CAS WE DM|RDQS VSS A3 E3 J1 K9

VDDL

VREF 2 3B10-2 7 33R 7 3B11-2 8 33R 33R 5 3B11-4 33R

SDRAM
DQ

E2

7B00 EDE1108AGBG-1J-F

A1 E9 L1 H9

A9 C1 C3 C7 C9

E1

E2

7B01 EDE1108AGBG-1J-F

100n

2B35 100n 2B39 100p

0 1 2 3 4 5 6 7

C8 C2 3B11-3 3 3B10-3 33R 3 D7 D3 D1 D93B10-4 4 B1 B9 3B10-1 1

6 6 33R

2 1 5 3B11-1 33R 4 8 33R

DDR2-D8 DDR2-D14 DDR2-D10 DDR2-D11 DDR2-D12 DDR2-D13 DDR2-D9 DDR2-D15

DQS

B7 A8 2B47

NU|RDQS

A2

3B19 RES 2p2

3B18 33R 33R

DDR2-DQS1_P DDR2-DQS1_N

+1V8

DDR2-ODT DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM0

NU|RDQS

A2

DDR2-ODT DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM1

180R 1%

3B20

NC

L3 L7

DDR2-A14

NC

L3 L7

DDR2-A14

3B25 33R

FB00 DDR2-VREF-DDR 180R 1%

VSSDL E7

VSSQ A7 B2 B8 D2 D8

3B26 33R

VSSDL E7

VSSQ A7 B2 B8 D2 D8

3B21

1X20 HOOK1

1X21 HOOK1

1X22 HOOK1

1X23 HOOK1

1X24 HOOK1

2011-03-09 2010-12-23

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div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 107

10-6 B06 313912365213


Display interfacing-Vdisp

B06A

Display interfacing-Vdisp

B06A

1G03 T 3.0A 32V

5G01 +VDISP-INT 30R RES 5G02 30R RES 2G44 22u RES

1G00 2G43 100n T 3.0A 32V RES

FG0H

+VDISP

RES 3G28 2K2

IG11

RES 6G00 LTST-C190KGKT

For Development use only

2010-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


Video out - LVDS

Q552.2L LA

10.

EN 108

B06B

Video out - LVDS

B06B
+3V3

10K

+VDISP
RES

10K

10K

47p

47p

47p

47p

47p

47p

47p

47p 2G26

2G7A

2G77

2G75

2G79

47p

2G76

2G24

2G78

2G25

RES 3G33

RES 3G34

RES 3G35

2G27

47p

FI-RE51S-HF 60 61 58 59 56 57 54 55 52 53

4 3 2 1

9G0K-4 9G0K-3 9G0K-2 9G0K-1

5 6 7 8

2G92 2G93 2G94 2G95

100n 100n 100n 100n FG2J FG30 FG31 FG32 FG33

CTRL-DISP

FI-RE41S-HF 51 50 48 49 46 47 44 45 42 43 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1G50

SDA-DISP SCL-DISP

RES 3G32 3G2W 3G2Y RES 3G38 RES 3G37 RES 3G2Z FG04 RES 3G30 RES 3G31 RES 3G36

100R 100R 100R 100R 100R 100R 100R 100R 100R

FG34 FG2H FG2G FG35 FG2R FG2K FG2L FG2M FG2E FG2F FG1Y FG1Z FG20 FG21 FG22 FG23 FG24 FG25 FG26 FG27 2G28 2G29 10p 10p

CTRL-DISP

BACKLIGHT-BOOST 3D-LR CTRL-DISP CTRL-DISP 3D-VS-DISP


PX1APX1A+ PX1BPX1B+ PX1CPX1C+ PX1CLKPX1CLK+ PX1DPX1D+ PX1EPX1E+

2G96 2G99 2G97 2G98


PX3APX3A+ PX3BPX3B+ PX3CPX3C+ PX3CLKPX3CLK+ PX3DPX3D+ PX3EPX3E+

47p 47p 47p 47p FG1C FG1D FG1E FG1F FG1G FG1H FG11 FG1J FG1K FG1L FG1M FG1N

PX4APX4A+ PX4BPX4B+ PX4CPX4C+ PX4CLKPX4CLK+ PX4DPX4D+ PX4EPX4E+

FG12 FG13 FG14 FG15 FG16 FG17 FG18 FG19 FG1A FG1B FG1Q FG1P

PX2APX2A+ PX2BPX2B+ PX2CPX2C+ PX2CLKPX2CLK+ PX2DPX2D+ PX2EPX2E+

FG28 FG29 FG2A FG2B FG2C FG2D FG1R FG1S FG1T FG1U FG1W FG1V FG2P 2G91 100n

+VDISP

RES 9G0G

FG2N

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

TO DISPLAY

1G51

TO DISPLAY
1X05 REF EMC HOLE

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


AmbiLight CPLD

Q552.2L LA

10.

EN 109

B06C
5GA0 +3V3 30R

AmbiLight CPLD

B06C
FGA0 VINT 100n

2GA0

2GA1

100n 2GA2

1u0

DEBUG ONLY

5GA1 +3V3 30R 2GA3 2GA5 100n 1u0

FGA1 VIO +3V3

RES 1G37 3GA4 10K RES +3V3 1 2 3 4 5 6 SD51022

2GA6

GCK3 GTS1 GTS2 GSR


10p RES

3GA5-4 3GA5-3 3GA5-2 3GA5-1

4 3 2 1

5 6 7 8

100R 100R 100R 100R

RES RES RES RES

VINT

VIO

7GA0 XC9572XL-10VQG44C0100 PXCLK54 GCK2 GCK3 43 44 1 2 3 39 40 41 42 36 34 33 29 30 31 32 37 38 11 9 24 10

15 35

VCCINT IXO1_43|GCK1 IXO1_44|GCK2 IXO1_1|GCK3 IXO1_2 IXO1_3 IXO1_39 IXO1_40 IXO1_41 IXO1_42 IXO2_36|GTS1 IXO2_34|GTS2 IXO2_33|GSR IXO2_29 IXO2_30 IXO2_31 IXO2_32 IXO2_37 IXO2_38 TCK TDI TDO TMS GND 4 17 25

VCCIO

26

AMBI-SPI-CLK-OUT-R AMBI-SPI-SDI-OUT_G1-R AMBI-SPI-SDO-OUT-R

IGA1 CPLED2 IGA2 CPLED3

PNX-SPI-CS-BLn PNX-SPI-SDO PNX-SPI-SDI PNX-SPI-CLK

3GA3

33R

GTS1 GTS2 GSR AMBI-SPI-CS-OUTn_R2-R AMBI-PWM-CLK_B2 AMBI-SPI-CS-OUTn_R2 AMBI-LATCH1_G2 AMBI-TEMP CPLED3 CPLED2

IXO3_5 IXO3_6 IXO3_7 IXO3_8 IXO3_12 IXO3_13 IXO3_14 IXO3_16 IXO3_18 IXO4_19 IXO4_20 IXO4_21 IXO4_22 IXO4_23 IXO4_27 IXO4_28

5 6 7 8 12 13 14 16 18 19 20 21 22 23 27 28

9GA1 RES

3GA1

RES 47R 5 33R 3 7 3G10-3 33R 3G13 1 10R 5 3G10-1 33R

PNX-SPI-CSBn BACKLIGHT-PWM 3D-LR 3D-VS-DISP BL-SPI-SDO BL-SPI-SDI BL-SPI-CSn BACKLIGHT-PWM_BL-VS BL-SPI-CLK AMBI-PROG_B1 AMBI-BLANK_R1 AMBI-SPI-CS-EXTLAMPSn AMBI-SPI-CLK-OUT AMBI-SPI-SDI-OUT_G1 AMBI-SPI-SDO-OUT AMBI-LATCH2_DIS

IGA3 GCK2 +3V3 3 GCK3 5 RES 7GA1-2 BC847BS(COL) 4

8 3G11-1

3G14 1 6 33R 3G11-3

33R 3 33R

4 3G10-4 2 3G10-2 3G12 4 3G11-4

+3V3 6 GTS1 2 RES 7GA1-1 BC847BS(COL) 1

6 33R 33R 8 33R

+3V3 3 10p 2G15 10p 2G17 2G13 10p 2G18 10p 2G16 10p 2G14 10p 2G19 10p GTS2 5 RES 7GA2-2 BC847BS(COL) 4

10p 2G11

10p 2G12

2G10

10K

3G15 +3V3

10p

+3V3 6 GSR 2 RES 7GA2-1 BC847BS(COL) 1 7 330R 2 5 330R 4 8 330R 1 6 330R 3 LTST-C190KGKT RES 3GA6-2 RES 3GA6-1 RES 3GA6-4 RES 3GA6-3 RES 6GA3

DEBUG ONLY
RES 1G35 1 2 3 4 5 6 7 8 2GA4 RES 3GA2-1 RES 3GA2-2 RES 3GA2-3 RES 3GA2-4 1 2 3 4 8 7 6 5 100R 100R 100R 100R RES 1G36 1 2 3 4 5 6 FGA6 FGA4 FGA5 FGA3 FGA2

LTST-C190KGKT

LTST-C190KGKT

100n RES

+3V3

SD51022

BACKLIGHT-PWM

9GA0

BACKLIGHT-PWM_BL-VS

LTST-C190KGKT

RES 6GA0

RES 6GA1

RES 6GA2

2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


SPI buffer

Q552.2L LA

10.

EN 110

B06D

SPI buffer

B06D

RES
+3V3 +3V3

RES 2GE0

100n

RES 7GE1 PDTC114EU

RES 3GE2 RES 7GE0 74LVC245A 1 19 2 2 3 4 5 6 7 8 9 IGE0 3 3GE0-3 47R 3GE1-3 6 3 RES 47R 3GE3 47R 47R

10K

20

PNX-SPI-CSBn

3EN1 3EN2 G3 PNX-SPI-CLK 18 17 16 15 14 13 12 11 10 1

6 RES 1 5 RES 3GE0-1 8 RES 47R 4 3GE1-4 47R RES

BL-SPI-CLK BL-SPI-SDO AMBI-SPI-CLK-OUT-R AMBI-SPI-SDO-OUT-R PNX-SPI-SDI

PNX-SPI-SDO AMBI-SPI-SDI-OUT_G1-R BL-SPI-SDI

3GE4 RES

PNX-SPI-CLK

RES 9GE0-1

BL-SPI-CLK

PNX-SPI-SDO

RES 9GE0-2

BL-SPI-SDO

BL-SPI-SDI

RES 9GE1 RES 9GE2 RES 5 9GE0-4

PNX-SPI-SDI

PNX-SPI-CS-BLn

IGE1

* ** 4

BL-SPI-CSn

* **

Buffer Direct

2011-03-09 2010-12-23

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3139 123 6521


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Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 111

10-7 B09 313912365213


Connectors comp

B09A

Connectors comp
5C55 30R FC67 1M59 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 3C74 100K RES +3V3

B09A
FC70 FC71 FC72 FC73 V-AMBI FC74 FC75 V-AMBI FC76 FC78 3C70 100R FC79 FC81 2C70 100n FC77

AMBI-SPI-CLK-OUT AMBI-SPI-SDO-OUT AMBI-SPI-SDI-OUT_G1 AMBI-PWM-CLK_B2 AMBI-SPI-CS-OUTn_R2 AMBI-LATCH1_G2 AMBI-BLANK_R1 AMBI-PROG_B1 AMBI-LATCH2_DIS AMBI-TEMP

2C76 FC87 LIGHT-SENSOR 2C93 RC 47n RES IC73 LED-2 IC74 3C75 100R 3C76 100R 3C77 100R +3V3-STANDBY 2C79 LED-1 IC75 3C78 100R 100p 2C80 100p 28 KEYBOARD FC95 3C79 BZX384-C5V6 BZX384-C5V6 100p 2C82 6C03 RES 10R RES FC93 FC94 +5V 2C81 100n 100p 2C77

6C02

2C78 100p

RES BZX384-C5V6

FC88 FC89 FC90 FC91 FC92

1M19 1 2 3 4 5 6 7 8

GND_AL

*
FC83 +24V T 2.0A 63V 1C86 AMBI-POWER

FC82

FC84 +12V_AL

* 1C87
T 2.0A 63V

2C94

2C95

100n

100n RES

2C96 100n RES GND_AL GND_AL

Option table for Ambilight BLOCKBUSTER N N EMMY Y N SUNDANCE / INFINITY N Y


SCL-SET C90 * RES 310K SDA-SET C91 * RES 3 100R RES 3C80 100R RES3C81 100R RES 3C82 100R RES 3C83 100R FAN-CTRL2 FC64 RES 1M71 FC97 1 2 3 4 9C00 RES 9C01 RES 3C94 3C95

+3V3-STANDBY +T 1 2 3 4 +5V 47R RES RES 47R +T 0R3 FC65 FC66 0R3 9C02-1 9C02-2 9C02-3 9C02-4 3C97 8 7 6 5

ITEMS 1C86 1C87

FAN-CTRL1

+3V3 FC61

iTV

FH52-11S-0.5SH 2C86 RES 10p 2C87 RES

TACH01

FC62

2C90

1u0 2C91

10p

SCL-BL TACH02

FC85 FC63

FC96 FC98

100p RES 2C84

RES 2C83

100p

SDA-BL

FC86

2041145-4

* RES 3C92 * RES 3C93


10K RES 5C54 +3V3 30R T 1.0A 63V RES 1C85 100R

TEMPERATURE SENSOR
FC99 RES 2C85

+3V3 FAN-DRV

**

Option table for Leading Edge BlockBuster / Emmy Yes No Sundance / Infinity No Yes

Items 1M19 1M20

RES 5C53 +12V 30R

1u0

IC78

RESERVED
SPB SSB TV550 2K11 4DDR BR SD
3139 123 6521

**

**

1u0

2011-Jul-15 back to

div. table

**

RES 3C96

6C05

FH34SRJ-26S-0.5SH(50)

1M20

1 2 3 4 5 6 7 8 9 10 11 12

**

100p

TO LED PANEL

3 2

2011-03-09 2010-12-23

19110_048_110415.eps 110415

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 112

10-8 313912365213 SSB Layout


Overview top side

1M95
2U58 2U53 3U65 4U01 4U00 3U64 2U49 3U45 3U43 2U44 2U45 2U46 3U81 3U76 2U48 2U72 3U84 3U71 2U54 2U68 2U47 3U42

1M99
2U51 2U50 2U43 3U67 3U66 2U52 3U44 3U56 2U56

1F24 1M71
1C85
2C84 3C83

1M59
3G10

3US6 3US9

2C95

3C93

3C91

5C53

3C80

2C83

1UM0

3C90

2C70

2U24

2U23

2U25

2U19

2U20

5U03

5U02

3GA1

9GA0

IUT1

2C94

5C54

3G11
3C70 2C96

1C86 1C87

2C85

3G13

2G16

3G12

3G14

3C82

3C92

3C81

5C55

6GA0

IU15

2U17

2U18

IUS9

7US3

7US2

5UM1 3US2

IUS5
3US3

3US7

3U23

7GA2

7U01 7U04 7U02


IU18

IUS4

IUS3

3US5 IUS6

2US3

IU23

3US4

IUT2

7US1

9US0

3GA6

6U00

2U11 2U09

3U24

5U00

7GA0
2UB2 2UB1

6GA3

6GA1

1G37
3GA5

6GA2

7GA1

IU17

2U16

2U15

1G36
3GA2

1G50

3B11

2UE8

5U01
2S4P

3B26

7B01
2G98 2G97 2G99 2G96

2UB0 2B47 3B18 3B19

7UA4

2UE6

7UA3
2UB4 2UB3 3UB4 3UB5 3UB1

IGA3 IGA2 IGA1

1G35
2GA4

3UB0

3UB2

3UB3

2UE3 2UE2

2D19

2D05

3B07

7B00

2UE0
3UD4 3B16 3UD5 3B17 2UE1 3UD3 2U28 3U07

IUD1

5D08

3B25

7UD1
IUD2

IUD4

5UD2

2UD8 2UD9
5UD3

2UE9

7U05

3F11

9S00

3F08

3U06 2U27

2D20

3S3Y

6UD0
IUD0

3F10

9F28

7B02
2D07

2UD5

3UD2 2UD7

2S4E 3B23 3B12 3B13

3S1K

3S1J
3S3R 3S2A 3S3T 3S3N

3S1B 3UD1 2S4D 3S1L 3UD0

2B44

9F27
3S1C 3S3L

2UD1 2UD2
5UD0

5D07

3B00

1D50

3B05

3S6K

1735 1D38

2D17

IF62
3S81 3S6N 3S80 2S4F 3S3F BS15 DS50 2S4G 3S54 3S50 3S52

2D08

2D24

2D23

3B24

2S2W

2S2Z

2S30

2S33

3S27

2D09

2S2R
2S2T

IS13 2S34
4S14

3E17

3S3W

3S42

7D10
2D10 2D06

3B04

3S3G
3S2M

7S00

1D52

3S3H

3S00

3S3U

9S06

3S44

7B03

2B45

3B15 3B14

1S02

3S43

3S3M

DBS8

3S6H

2S2V

2S32

7S08

2S31

2S2Y

3S26

3S6J

2S7K

2S7H

2S7R

2S7E

2S7M

BS10

3S4J 2S7J

2S77 2S8G 2S7U 2S7N 2S87 2S78

2S2S

2F40
3S84 3S83

2S7P

3S4L

3S4K

9S21

9S19

2S7L

3S4R

3S4P

3S4T

9S18

9S20

3S53

3S13 3S12
BS13

2S41

3S59

2D12 2D11

5D02 5D01

2S4M
9E20 9E18

1F10

2F58

7F58

3F59 3F60

IF61

2UD4

7S00

3F09

3S28

3S29

3B02

3S3Q

3S62 3S21 3S3S

3S23

3S24

2UD0
2UD3

7UD0

5UD1

1P09

2UD6
9FLH 9FLC 9FLD

7F20

3B10

9S92

9S90

2B46

3B08

9S91

9S93

2UE4

9FLJ

3F58

9E24 4E03

1E06 1E71

5D04

3E32

4E02

1F75
6F72
3F78 2F92 2F94 2F90 3F71

9E22

7F70
2F91 3F72

3FLE

1FL5
2FL6 2FL7

1E31 1E19 1E86

IF89

5F70

1G51

1E54

1E12

1E18

1P08
7FL5
9FLG

5D05

2G29 2G28

9F00 9F01

9F05 9F06

1E02
3E97

2F9D

3FL7

9F04
2F9C

9FLE

2E48

3E69

3E70

3E67

3E66

9E43

3E71

9E42

2E49

3E64

3E65

2F93

4E04

4E05

3E87 3E88 9E29 9E04

4E01

2G7A 2G79

2E53 2G24 2E52 9E11 2E72 2G25 2G26 3G38 3E33 2G78 2G27 2G76 2G75

5F72

6E06

3E96

6E38

4E22

3E51

1E70

2E27

3F64

3F65

2E54 3E21

2E35

2E38

6E19

IE10
2E37 3E20

2F86 3F75

7E10
IE07
3E40 2E66

2F9A

2G77

3E34 3E35

3E68

2F99

1E29

3E72 3C74

6FD3

3C75

2E63

2E62

6FD2

3E28 2E05

1E28

2C77

3C76

2C93

1E39

2E07

5E02

5E01

IE11

1M19

1M20

1E88

1E87

2C80 2C78

3C78 3C77

IC75

6E51

2C82

3C79

IC74

2EE6

3EC3 2E67 3EC5

3ECF

6C03 6C05
2C91 2C90 2C86 2C87 3C95 3C94

6E47

3E27

5E08

3E98

2E60

3E26

9E15

6EC1

2ECU 3ECP

2F98

1T01
2E73 3E9C

1FD2

3ECG

4E21

9E57

9E17

3E89

3EE3

2EE4

IEE5

2EE3

IEE4

IEE6

3ECN IE42

1329
2F60 2F97 2F81
2E77

4E20

1F52
3F62 3F63 6FC7 6FC5
3FC4

4E24

2FDC

3FDG

6C02

2E57

2E56

7EE0

1E38

1FD3

2FDD

3E25 3E22

6E20

2C76

1E08
2EE2

1E42

1E43

1E03 1E04
2EC1
9EC3 5EC2

1328

1E09

1E37

3FL2

2E55 3E30

2E39

1E32

2F88

3FL4

IE09

9F71

6E40

4E23

1F51

2F9B

9FL3

3F34

9FLL

3FLC

9FLK

1P07

9E13

2E71

2E40

2E36

2EE0

3EE1

2E22

2C81

5E06

2EE5

2EE7
6E46 3EE2

7EE1
2EE1

7EC1
2ECC

3EE0

2ECP

2ECN 2ECM

1P05

3ECM

6FC3 6FC4

3U68

6E53 1E80

3FC3

IEE3

3U70

7U43
9U42 9U41 3U41

1E44
3FC7 9FC5 3FC6 3FC5 9FC3 9FC6 2FC3 2FC5

6FC2 6FC1 6FC6

3U69 3U75

3U53 3U59 3U74

1E10

1E07

1P04

1P03

1P02

1FC5

1E05
2 2011-03-07

1FC1

7U42

1N00

2FC4

2FC2

2FC1

2FC6

3FC1

2FC7 3FC2 9FC4

6FC8
2FC8

1FC6

1FC3 1FC4 1FC2

9FLF

1E01

1E85 IF86

5F73

SSB Layout Top

3139 123 6521


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div. table

Circuit Diagrams and PWB Layouts


Overview bottom side

Q552.2L LA

10.

EN 113

CXXX

FC81 FC67

FC96

FC82

FC78

FC71 FC79

9FL1

FL38

9FL2

2G13

2G14

FC76

FC77

FC75

FC99

2G11

2G19

2G15

2G12

3U01

3U00

FU48

FU50

FU49

FU54

FU77

FU63

FU75

FU56

FU57

FU74

FU68

FU09

FU08

CU00

FC73

2G18

2G10

2G17

FC97 FC70 FC72

FC98

IC78 FU58 FU59 FU60 FU61 IU56 FU66 FU67 FU51 FU52 FU53 FU55 FU62 FU76

FC84 FC83

3UU0
FS2W
IU20 3U17 IU06

FC74

3U08

3U22

2U07

3U10

3U72

2U57

FC64

FC62 FUM0

FC61

FC63

6U40

FU01

FS2Y

FU07

1U40
IU22 IU49 IU48

2U06

IU03

IU55

7UU2

3U09

3U18

2U03

2U08

3U19

IU04

IUU3

FUU1 3UU2

7U40

2GA2

3GE1

3GE0
FGA5

IU05 IU24 3U04 2U21 2U01 IU11 IU16

3U27

IU51

7U00

IU08

IU13

2U02 IU07

IUU0

IUM0 IUS7

7UU3
3UU3

IUU4

2U55 IU63 3U73

3U11

3U28

7GE0

2GA5

2GA3

FU05

3U62

FUS0 2UA4 IU50

9GE0
9GA1 9GE2 IGE1

FGA1

FU72 IU62 FU73 FU02

5GA1

3U80

FU06 IU09 FU04 IU14 IU25 2U05 FU00

7UU1

IU10

7U03
2U00
3U02 IU02 IU01

3U05

2U22

3U14

3GA4

2GA6

3UU1 IUU1 2UU1 FG2J 2UU0

IUS8

IU12

IUU5
IUU2

FUD2

7U41

3U60
IU61

2GE0

3U26

FGA0

7UC0
FUA3 IUA5 CUA0

FG1P

FG1Q

5GA0

3G15

3U63 3U82 3U61

IU52 IU57

IU19

IS17

2U04
CU04
IU21

3U20 2U10

3U21 2U29

2GA0

3U03 IU64 CU05

7UU0
FG17

FG1B

3U29

CU03

FG1A

CU01

CU02

FG19

FG18 FG16

3GA3

3GE4

6UD1

7GE1
FGA4 FGA6
FGA2 FGA3 IS40

9GE1

3GE2

2GA1 FUA4

7U48

3U83
IUD5 IU41 2U71

3GE3

2U13 2U12
FU03

FG13

7UD3

IGE0

IU40

2UE5

1G00

1G03

FC85

7UD2
2UE7

2U14
3S66 3S68
FC86 FS31

2B32

FB00

2B34

9S95

9S94

2G44
5G01 5G02

2B27

2B35

2B33

FG1N

FG1M

FG1K

FG1L

IUA6

FG11

FG1J

2B29

6G00
FG1H IG11 FG1E FG1F FG1G

IUB0 IF08

2B28

IF04

2G43

7S01

3F21

9S10

3F23
IF21 IF23

9S11 3S65

2S12

IS08

2B31

3G28

3F24

2B30

3B09

FG33 FG1C FG0H 2G92 2G93 FG1D

9S97

9S13

FF08

3F22

3F12 2F21

9S12 IS09

3F20

IF22

9C01 9C00

3S6B 3S6C IS00

2S89

3S58 3S5W

2G95

3F19

2B22

FG30

3U16

3U15

2B42
2B25 3S06
2B24 FS01

9G0K

3S67

9S96

2F20

2G94

FG32

3B27

2B23

FG31

2B38

FL31 IF87 3S61

9S08 2S4N

2S25

2S61

2B19

2B21

3S60 IF88 FUD3 IU30 IU29 IU28 3S5Z 3S6D 3S5Y FF07 3S57 3S2G IUB3 3S6A 3S6W 3S6V 3S69 3S2F 3S56 3S6E 3S6F

3S15

3B06 2B18

IS26

7U06

2S6P

3U25

IS25 5S85 3S1W

2S5M

IS3K

2S62

2S5H

2S64

2S4W 2S4Y

2S5P

2S57

5S94

2S4S

2S26

5S88

2S63

2S67

3B20

3S6G

3S07

2S17

2S66 3S1V

2B20

2B26

3B21

2S5J

3S1X

2S6F

2S60

7UA0
FUA0 3UA0

IU27 FF09 3S1E

FF05

IS3Q 5S80

3B22

5S92

IS58

5S89

5S93

2S5A

2S5G
5S87

3S6P

2S27

3S30 3S33

3D01

5S83

2S21

3S6Q

3F07

FF06

2D03

ID35

7D11
ID34

5S81

3UB7

3UB6
IS3S

2S23

2S5D

2S6M

3S1R

3S1U

3S1S

3S1T

2S59

2S58

2S28

IUD3

2UB8

3S82

5S82

2S5K
5S95

2S6E 2B10 2S6D 2S65 3S0V

3D15

2B14

2B16

2S5C

IUB4 IUB2

2S6L

2S43

IS42

ID12

2S6H

3D09

5S04

5S90

2S53

IUB5

2S55

2S56

IS10

2S68

3D16

7UA7
IU26

2B37 2B15

7D03

IS04

2S6K

3S20

2S2E

7UA6

FS64

FS02 2B13

3S64

ID11

2S4V

IS01

2S6B

2S37

2S6N 3S22

2S11

2UB7

9FD2

3FD7

9FD5

3FD2

2S6C

2S4T

2S51

2S6G 2S46

2B11

IF55

2B12

2SHW

2D02
ID14 3B01 2B09

3D06

3U13

3U12

IUD6

3S0W

2S5B
2S6A

2S52

2S20

2S24

2B17

FD07

ID33

3S45

2S15

2S4Z

3S40

IFD3

IFD5

FC95 3S41 3S1P 3S2K 3S55

IS16

DS52

7FD1

7F54

3FD1

2F53

3F69

3S1F

2S4K

IF57

7S20

2FD1

2S4Q

7UA5
IUB1 2UB5 2UB6

7F53
9CH0

IS4Z

IS5F

2B40

2S45

FD01

FD08

3D02

IS3L

2S4R

IUD7

5UA0

3F66 3F54

2S50

FF58

3F53

3F67

IS05

9S09

2S4U

2D28

2D29
FD03 ID15

7D15

2S13

5S84

3S2H

2S3G

IF51 FF04

IS5E 2S76 3S5S 2S75 3S76 IS4W

IS1A 2S36

3S2V

6FD1

FS0Z

9S0E

IUB6 IFD1

IS2U

2S10 FS45 FS51

IS3B

3S09

IF56

C001

IS50

2S29

3FD6

9FD1

9S0D

2S3H

3S5V

2S3L

3S75

2B03

2B02

2S2L

3FD3

3FD4

IFD2

IFD4

2S19

CD10

IS1L

2S84

3S46 3S2S

IS2Z IS5J

2S40

3S08

7S09
2S3K
2S3Q 3S19 IS1E IS1G

2S18

IS1B

2S3E

FS11

3S10

FS10

3S1G 3S1H

IS5D 3S2L

ID37 ID19 FD09 ID27

2D16

3F68

IS19

3B28

2B01

ID18

ID30

2S14

2B04

2B08

2B36

IS3D

2S86

IS5H

2S3F

2S85

IS1N

ID29

ID28

3S5T

IS1M

FS08

2S16

2B07

IS4V

IS1S

3S6M

3S11

2B06

IS5G IS3F 9S24 IS3E IS20

2B05

2S3D

2S3C

2S3B

2S3A

2S38

IS2V

2S3M

3S25

IS1K

3F44

3F42

IS06

3S72

FF43

FF50

3S5B

3S18
FS44

FS49

IS5C

2S8A

2S39

3B03

2B00

2S2J

FF44

3S05

2S22

FS50 IE05 IS44

2S2K

3S6L

3S37

3S34

FF47

3S32

IS03 IS07

2B41
ID09 ID31

FD10 FD05 ID32 2D01 2D14

FF49

IF47

3S47

FF45

3F40
3F41 3F43

3S16 3S17
IS1J

IS0V FF48

7S05
2S2G 2S2H
IS02

2S3J

3F45
FE86

IS12 FD14

3S51

5D03
ID10 2D13

FD06

FS03

IS1Q IF16

2S42

FD02

C000

FF46

5F76
2F62 2F70

6E48

3S39

3S5E IS1H IS0R IS1P

3S36
3S38

3S0Z

3S3P

3S49

FF41

3E9E

FF42 IF53

AF72 FF56

5F74

3E9D

FF55

FL39 IFLF

7F52

IF58

FL30

3F52
IF54

3F79
IF80

IF50

2E69

FL32

5F71

7E11

2F73 2F80 2F72 2F82 2F77 2F76 AF73

FS52

FF29

FS57

IS11

2F95

FS53

3S1D

2F65 3F82

7E13 7E12

IS1D

IF79 FL37 IFL2

2D27

2D21

IE15

9E14

9E12

2F52

2E83

IFL1

IF72

9F25 9F26
FL36

6E43

2F49
IF59
FF57

IE50

3D10
ID07

BEC5 BEC3

IF52

2F96

5E74
2E14 FE80

3E77

2E84

2E80 2E98

3E75 2E15

5E73
FE74

2E86 3E74 IE53 2E79 IE55 2E85 3E78

IE18 FE23 9E28 2E04 9E25 IE22

ID05

5E76
2E12 FE81

3E79

FE57 IFLG IFL4 IF81 IF90 IF75

3E53
FE56

6E44
IE49

IU43 3E76

6E26

6E23

6E28 6E09

3E07
2E91 2E88 FE71

2E06

FE73

6E03
2G91

IU45

9G0G

2F78 2F74

FG1V

FG1W

IF77

IFLC 2FLA

FF75 FF71

FG2N IF73 FE58

2F71

2FLD

3FLA

2FL9

2FL5
2FLB

FF01

7F75

2F85

FG2P

FG1U

FG1T

IF76

IF11

3D14
ID08

FG2D

2FL4 2FL8 2FL1 2FL3


2FLC IFLE AF71 IF13

IF10

9F03 9F02
IF12

2D26

2D22

FG2C

FG1S

FG1R

FG2A FG2B

2F75
IF74
ID06

5F66

IF78

2F66

2F63 2F64

IF14

3F80 3F81
IF28 3FE5

2F79 3F77
IF27 IF82

FG27

FG28

FG29

3FLF

IFLA

IF15 2FH8 FG26 FG25 FG24

2FL2
3FLD
3FLH 3FLB IFLD

2FE5

3FG4
IF29

3FE7

3FG2

3FE6

2FF3

FG23 FG2M

FG22

5FG2

AF70 IFL3 3FLG

5FG0

IF64

3F32

1FE0

IFLB

2FF6
5FE4 FF00

IF66

3G31 3G33 3G34 IE26 IE73 3FG7 FE50 IE64 IE38 IE29 IE31 FE54 IE51 IE06 2FE4 IE32 FG2K IE63 3G30 3G36 3G2Z FG2R FG2L

FG21

FG20

2FG2

FL43 IF63 FF64 IF48

9E16

2FF5 2FF0

FG1Y

FG1Z

FL33

2FG3

FE72

FG2E

FG2F

3E44

IE48 FE42

9E26

IE71

FFDC

FF66

FF65

5FE0 FF82 5FE3

2FH5

BFE3

FL41

IF65 2FG9

2FE6

FL40

2FH6

5FE7

2FH7 BFE2 2FG8

7FE0
DFE9
IF18 DFF2 IF49

3E73

2FE0

3FG6

FE43

FE85

FE49

3G37 FG2G

DFE8

3G2Y 3G2W

FG35

DFE7 IE33

3G32 3G35

FG34

FG04

FG2H

DFE6

IE39 FE31

2FG7

2FG6 2FG4 IF17

FC89 FE33 FE29 FE34 FC87

2F84 3F76

2FE8
2FF7 2FF2 2FE3 2FG0 3FE8
FF62

3FE9

FF03

2FF8 IF68

2FF4

FF81

5FE5

IF67

FE32

DFF1

3E95
3E29 FE27 FE28 2E58

3E99
2E59

7FE3

2FH2

2FH4

FF61

5FA4

2FF1

2FA4

5FE8

IF69

2FG1

2FF9

5E03

5E04

FE01 IC73

IEE8

2E09

2E08

5FE9

2FH3

FF63 5FA3 2FA3 FFAF

IEE7

FC90 FE30

FL42

IEE0

FE59

FC91

2E68

FFB5

FFDB

FE02 FECZ

6E52

FE61 FC92 IE77 FE51 IE74 IE75 FC65 FE60 9E19

2F59

FE03 FF76 FFA2

FECB

FE48 IE44

FC93

2ECY

FFB6

FFDA

FF74

3FBF

FFC9

FFB1

7FA3
2FA2
FE44

2F61

2ECW

2EC2

2ECQ
3ECH
IE43

FEC7 5EC3

2EC3

IE76

2EC7

3ECJ

FEC3

3ECL

IE12 9EC2 FE41

IEE1 FC66 IEE2 IU47

FFB2

2ECV

2EC6

2EC0

FFB3 FFC5 FFB4

FFC3 FFC7

FFC4

5EC0 IE66 FEC0 IE65

FC94

FECY

9E58

IE45

2ECX

3E90

FECR

3ECK

FEE0

2C79

FC88

3E39

IU44

9FC2

2EC8

9FC1

3ECU
FE36

FFC1

FFC2

FFC6 FFC8

FECW

FECA IEC6 IEC5

IEC7

3ECE

9EC0

7EC0 7E02
3ECD
IEC4

3E23 FEC2 FECE FEC4 FEC5 FEC1

FECM

3ECA
FECF FECD FEC6

3EC1

FECK FECP FECN FECL FECC

FECG

FE35

FECJ

FG12

2B39

2UU2

FUU0

9UU1 9UU0

2B43

FG15

FG14

2011-03-07

SSB Layout Bottom

3139 123 6521


19110_002_110307.eps 110307

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 114

10-9 B01 313912365214

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts


Common Interface

Q552.2L LA

10.

EN 115

B01A

Common Interface

B01A

CA-CD1n CA-CD2n

FF05 FF06

3 4

6 10K 5 10K 3F07-1 1 8 10K 3F07-2 2 7 10K 3F07-4 1 3F08-1

3F07-3

+3V3

CA-MOCLK CA-MOVAL CA-MOSTRT

8 10K 5 FF07 10K 3F08-3 3 6 10K 3F08-2 2 7 10K 4 3F08-4 RES 1 3F09-1 8 10K RES 2 3F09-2 7 10K RES 3 3F09-3 6 10K RES 4 3F09-4 5 10K RES 4 3F10-4 5 10K RES 3 3F10-3 6 10K RES 2 3F10-2 7 10K RES 1 3F10-1 8 10K 3F12 10K 2 3F11-2 7 10K 3 3F11-3 6 10K 4 3F11-4 5 10K 8 3F11-1 1 10K

+3V3

CA-MDO0 CA-MDO1 CA-MDO2 CA-MDO3

IF04

CA-MDO4 CA-MDO5 CA-MDO6 CA-MDO7

CA-RDY

FF08

+3V3

IF08

FF09 CA-VS1n

+3V3

1X07 REF EMC HOLE

1X04 EMC HOLE

1X08 REF EMC HOLE

1X01 REF EMC HOLE

2011-05-10 2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521

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div. table

Circuit Diagrams and PWB Layouts


Flash

Q552.2L LA

10.

EN 116

B01B

Flash

B01B

+3V3

2F20

100n 2F21

7F20 NAND04GW3B2DN6F

100n 12

[FLASH] 4G 16
XIO-D00 XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07 3F20-1 1 3F20-3 3 3F21-1 1 3F21-3 3 8 6 8 6 100R 3F20-2 100R 3F20-4 100R 3F21-2 100R 3F21-4 2 4 2 4 7 5 7 5 100R 100R 100R 100R IF21 3F22-2 +3V3 XIO-OEn XIO-WEn NAND-WPn +3V3 NAND-RDY1n 2K2 IF23 10K 3F19 VSS 13 36 2 100R 3F22-3 3 10K 3F22-1 1 5 100R 3F24 7 16 17 9 8 18 19 7 29 30 31 32 41 42 43 44 0 1 2 3 IO 4 5 6 7

37

VCC

NC

NAND-CE1n NAND-CLE NAND-ALE

6 8

100R 100R IF22

3F23 3F22-4 4

CLE ALE CE RE WE WP R B

1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 27 28 33 34 35 38 39 40 45 46 47 48

+3V3

2011-05-11 2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521

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div. table

Circuit Diagrams and PWB Layouts


USB Hub

Q552.2L LA

10.

EN 117

B01C

USB Hub

B01C
+3V3

USB-OVR1 3FL2 +5V 100n 100n 100n 100n 1u0 10n 10n 10n 2FLB 1n0 2FLC 1n0 2FLA 1n0 +T 0R3 4 3FL4-4 5 100K 3 3FL4-3 100K +3V3 3 7 11 15 19 23 27 33 39 55 7FL5 CY7C65621-56LTXCT IFL4 IFLG +3V3 +5V 3FLD 1 3FLE-1 100K 2 3FLE-2 100K 4 3FLE-4 5 100K 3 3FLE-3 100K +3V3 RESET-USBn USB1-DM USB1-DP USB-DM USB-DP USB2-DM USB2-DP USB-WIFI-DDn USB-WIFI-DDp 3FLF 9FLF 9FLG 9FLH 9FLJ 10K 6 9 10 7 9F26 9F25 9FLC 9FLD IFL1 IFL2 17 18 13 14 10K 8 IFLA 21 22 45 26 46 XIN XOUT SELFPWR VBUSPOWER RESET DD+ DD1DD1+ DD2DD2+ PWR2 OVR2 SPI_CS SPI_SCK SPI_SD GREEN2 AMBER2 PWR1 OVR1 12p 1 3FL4-1 8 100K 2 3FL4-2 100K USB-16-PBT-B-30-CU1-BRF 9FL3 3FL7 10K 3F32 +5V 4 3F34-4 100K 3F34-3 100K +3V3 +3V3 2 3F34-2 100K 1 3F34-1 8 100K +3V3 RES RES RES RES 1 2 3 4 1 2 3 4 9FL1-1 9FL1-2 9FL1-3 9FL1-4 9FL2-1 9FL2-2 9FL2-3 9FL2-4 8 7 6 5 8 7 6 5 USB-16-PBT-B-30-CU1-BRF 7 +T 0R3 +5V-USB1 +5V-USB2 6 USB2-DM USB2-DP FL42 FL40 FL41 FL32 7 6 +5V-USB1 USB1-DM USB1-DP FL43 FL36 FL37 1 2 3 4 5 FL33 +5V-USB2

2FL2

2FLD

2FL5

2FL3

1FL5

2FL8

2FL9

2FL4

2FL1

USB1
1P08

2FL6

4 2 12p

24M 2FL7

VCC GREEN1 AMBER1

6 IFLF

35 36 37 38 29 30 31 32 25 48 49 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 IFLC IFLD IFLE 3FLA 3FLB 3FLC 10K 15K 10K IFLB

USB2
1P07 1 2 3 4 5

9FLE

+5V

IFL3

53 51 5 6 42 41 54 1 2 44 43 52

RES

VIA

RES 3FLJ +T 0R3 USB-WIFI-DDn USB-WIFI-DDp FL31 FL38 FL39 FL30

(WIFI)
RES 1F24 1 2 3 4 5 6

USB2-DM USB2-DP +3V3 USB-OVR1 +3V3

9FLK 9FLL 3FLG 10K 3FLH 10K

NC

502386-0570

GND 4 8 12 16 20 24 28 34 40 47 50 56 SCENARIO 1x USB 1x USB + WIFI 2x USB 2x USB + WIFI 1P07 N N Y Y 1P08 Y Y Y Y 1F24 N Y N Y 3FLG N Y Y N 3FL2 N N Y Y 3FL4 N N Y Y 3FL7 N Y N Y 3F32 Y Y Y Y 3F34 N Y Y Y 7FL5 CY7C65621 CY7C65621 CY7C65631 9FLE 9FLC/D 9F25/6 9FL2 N N N Y Y N N N Y Y N N N N N Y 9FL3 N N N Y

GND HS 57

9FLF/G 9FLH/J 9FLK/L N N N N Y N Y N N N Y Y

2011-05-10 2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521

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Circuit Diagrams and PWB Layouts


SD Card

Q552.2L LA

10.

EN 118

B01D

SD-Card

B01D

3F40 +3V3 +T 22u 16V 2F40 0R3

FF45

+3V3-SD

+3V3

3F41-4 47K

5 3 3F41-3 47K

IF47 SDIO-DAT3 6 SDIO-CMD SDIO-DAT3 SDIO-CMD

3F44-2 100R

7 3 3F43-3 100R 6

FF47 1P09-1 FF48 1 2 3 4 5 6 7 8 9

3F45 RES 10K 2 3F41-2 7 47K 1 3F42-1 8 47K 1 3F41-1 8 47K

SDIO-CLK

SDIO-CLK

3F44-1 100R

+3V3-SD 8 FF49 FF41 1 3F43-1 8 100R FF42 FF43 13 15

SDIO-DAT0 SDIO-DAT1 SDIO-DAT2

SDIO-DAT0 SDIO-DAT1 SDIO-DAT2

2 3F43-2 7 100R 3 3F44-3 6 100R

14 16

FF46

SCDA7A0200

2 3 3F42-3 6 47K

3F42-2 47K

1P09-2 7 SDIO-CDn SDIO-CDn FF44 10 11 12 SCDA7A0200

SDIO-WP

SDIO-WP

FF50

2011-05-10 2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 6521

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Circuit Diagrams and PWB Layouts


PNX85500 Control

Q552.2L LA

10.

EN 119

B01E

PNX85500 Control

B01E

+3V3-STANDBY

+3V3-STANDBY

+3V3-STANDBY 2F49 100p 2F52 100n RES

+3V3

+3V3

+3V3

3F52

3F67

10K

7F52 M25P05-AVMN6 IF50 D C S W 5 IF52 6 IF53 1 IF54 3 7 +3V3-STANDBY

10K

3F66

10K RES

BACKLIGHT-BOOST 7F53 RES PDTA114EU +5V

VCC PNX-SPI-SDI IF51 2 Q

512K FLASH

PNX-SPI-SDO PNX-SPI-CLK PNX-SPI-CSBn PNX-SPI-WPn BOOST-PWM IF55

3F68 RES 7F54-2 RES BC847BPN(COL) IF57

HOLD VSS 4

7F54-1 RES BC847BPN(COL) 6 IF56 4 2 1

FF29

IF61 SPI-PROG

FF04

IF62 SDM

5 3 3F53 RES RES 10K 2F53

47K

9CH0

FF58

3F69

3F54

1u0

+3V3

MAIN NVM DEBUG ONLY


IF58 2F58 RES 100n 8 7F58 SCL-SSB SDA-SSB FF63 7 6 5 3F59 100R 3F60 100R FF55 FF56 SCL-UP-MIPS SDA-UP-MIPS 3F63 100R FF61 3F62

10K

1K0 RES

RES 1F52 100R FF62 4 1 2 3 5

SCL SDA

3F58 IF59

1 2 3

(8K 8) EEPROM
0 1 2 ADR

10K

WC SCL

SDA 4 FF57

DEBUG / RS232 INTERFACE


FF65 FF66 3F64 100R 3F65 100R 7 6 FF64 RES 1F51 1 2 3 4 5

LEVEL SHIFTED UP FOR DEBUG USE ONLY

TXD-UP RXD-UP RESET-STBYn SPI-PROG

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Circuit Diagrams and PWB Layouts


Tuner

Q552.2L LA

10.

EN 120

B01F
FF71

Tuner
IF10

B01F
IF11 4MHZ_REF

1T01 15 RF_AGC B+_LNA RF_IO TUN 16

TUNER
I2C_ADR I2C_SDA I2C_SCL B+_TUN

14 IF_OUT1 IF_OUT2 9F00 9F01 9F02 13 NC +5V-TUN-PIN 10n 7F75 UPC3221GV-E1 1F75 IF75 O1 O2 5 4 IF81 2F74 10n 2F78 10n GND1 GND2 4 VAGC 10n
AGC CONTROL

9F03

2F71

PNX-IF-P

2F72

*
VCC OUTPUT1 7 IF78 2F79 IF74 2F75 10n IF76 1 3F79-1 RES 2F76 5F71 220R IF80 4 3F79-4 220R AF72 2p2 2F77

*
2F70 RES

2F65 RES 1p0

10

11

12

2F73

IF73 2 IF77 3 INPUT2 INPUT1

5F74

2F62

6p8

6p8

6p8

6p8

6p8

6p8

6p8

1 2 3

OUTPUT2

RES 2F9C

RES 2F9D

RES 2F9A

RES 2F9B

RES 2F98

RES 2F97

RES 2F99

X7251M 36M17

AF73 2F80 2F82

*
FF74 TUN-P1 100n 4n7 4n7 FF00 FF75 RES 2F81 2F59 2F60 2F61 FF76 AF71 AF70 TUN-IF-N TUN-IF-P IF-AGC PNX-IF-AGC IF82 3F77 4K7 IF-AGC 100p 100p FF01 IF72 9F05 9F06 BA591 2F85 3F71 6F72 3F72 1K0 2F92 +5V-TUN-PIN 4K7 10n IF79 3F80 220R 3F81 220R IF86 2F90 3F78 3K3 10n 5F70 +5V-TUN-PIN TUN-IF-N TUN-IF-P 470n 3 4 ATB2012 10n IF89 2F84 15p 2F86 15p 3F76 47R TUN-P6 3F75 47R TUN-P7 IF88 SDA-TUNER IF87 SCL-TUNER SELECT-SAW RES IF90 7F70 PDTC114EU 5F73 2 1 IF14 IF12 2F63 10n 2F64 10n

*
PNX-IF-N

IF13 IF5F66 680n 2F66 15p

9F04

47n

*
FF81 FF82

RES 2F95

RES 2F96

2F93

100n

IF15

RES 5F76

820R IF+
4

GND

TUN-P6 TUN-P7

* For BR NIM Tuner only

2F91 RES

* For EU Hybrid Tuner Only


9F71 5F72 RES +5V-TUN 30R +5V-TUN-PIN 2F88

* Remarks
Item No. 1T01 2F61 2F62 9F02 9F03 9F04 9F05 9F06 2F73 2F82 2F72 2F80 2F77 5F71 5F74

Component Europe Brazil FA23X7 TH26X3 RES 4u7 5p6 10p Used RES Used RES Used RES Used RES Used RES RES 1p0 RES 1p0 12p 15p 12p 15p 18p 22p 560n 680n 680n 820n

22u

2F94

10n

330n 3F82 RES

I ISWI

IF16

15p

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Circuit Diagrams and PWB Layouts


Toshiba Supply

Q552.2L LA

10.

EN 121

B01G

Toshiba supply

B01G

+3V3

+1V2-BRA-DR1 +1V2-BRA-VDDC

5FA3

5FA4 2FA4

30R

7FA3 LD1117DT12 3 IN OUT COM 2FA2 2 FFAF

2FA3

100n

100n

FFA2

10u

30R

2011-05-10 2010-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


HDMI

Q552.2L LA

10.

EN 122

B01H

HDMI

B01H

HDMI CONNECTOR SIDE


1P05 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FFB5 21 23 DRX2+ DRX2DRX1+ DRX1DRX0+ 1 3FBF-1 8 DRX-DDC-SCL DRX-DDC-SDA DRX0DRXC+ DRXCPCEC-HDMI FFB1 FFB2 FFB3 FFB4 20 22 FFB6 DIN-5V DRX-HOTPLUG DRX-DDC-SCL DRX-DDC-SDA DIN-5V

47K 2 3FBF-2 7 47K

DIN-5V

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Circuit Diagrams and PWB Layouts


VGA

Q552.2L LA

10.

EN 123

B01I

VGA

B01I
FFC1 CDS4C12GTA 12V 3FC5 18R R-VGA RES 2FC1 1FC1 RES 6FC1 100p

FFC2 CDS4C12GTA 12V

3FC6 18R

G-VGA

RES 2FC2

1E05 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FFC6 1216-02D-15L-2EC FFC7

RES 6FC2

1FC2

100p

3FC7 CDS4C12GTA 12V FFC3 RES 2FC3 RES 6FC3 1FC3 100p 18R

B-VGA

VGA CONNECTOR

FFC4 FFC5

9FC5 RES 6FC4 CDS4C12GTA 12V 2FC4 1FC4

H-SYNC-VGA

3FC3

17

4K7

47p

9FC6 CDS4C12GTA 12V RES 6FC5 2FC5 1FC5 3FC4

V-SYNC-VGA

47p

4K7

RES 3FC1 10K

9FC1 FFC8 CDS4C12GTA 12V 9FC2 RES RES 6FC6

VGA-SDA-EDID-HDMI VGA-SDA-EDID

2FC6

47p

RES 3FC2 10K

9FC3 FFC9 CDS4C12GTA 12V 9FC4 RES

VGA-SCL-EDID-HDMI VGA-SCL-EDID

2FC7

RES 6FC7

47p

+5V-VGA RES 6FC8 CDS4C12GTA 12V 2FC8 1FC6

47p

2011-05-10 2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


Temp sensor & headphone

Q552.2L LA

10.

EN 124

B01J

Temp sensor & headphone

B01J

+3V3 9FD1 RES 9FD2 RES RES 3FD1

1K0

2FD1

3FD2 IFD5 9FD5 1K0

100n

LTST-C190KGKT

RES

6FD1

7FD1 LM75BDP 3 1 2 OS SDA

+VS

A0 A1

7 6 5

IFD1 IFD3

SDA-SSB SCL-SSB 3FD4 100R

3FD3 100R

IFD2 IFD4

GND

SCL

A2

3FD6

1K0 3FD7

RES

1K0

RES 1329 1 2 3

502382-0370 1328 2MSJ-035-69A-B-RF-PBT-BRF AMP1 AMP2 CDS4C12GTA 12V 1FD3 CDS4C12GTA 12V 2FDC FFDB 22n 2FDD 22n FFDC 7 8 3FDG-2 1K0 3FDG-1 1 FFDA 3

1FD2

RES

6FD2

RES

6FD3

1K0

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Circuit Diagrams and PWB Layouts


Tuner Brazil

Q552.2L LA

10.

EN 125

B01K

Tuner Brazil

B01K

5FE0 +2V5-BRA 30R

IF63

IF64 +1V2-BRA-VDDC 2FE3 100n 2FE4

2FE0

100n 2FE5

100n 2FF0

100n 2FF1

1 u0

1u 0

AGND 5FE3 30R 2FE6 2FF2 100n 2FF3 100n 2FF5 100n 2FF4 100n 2FF6 1u 0 1u0 IF65 IF66 +3V3-BRA-FLT

+3V3-BRA-FLT

5FE4 +3V3-BRA 30R

AGND 5FE5 30R 2FE8 100n 2FF8 2FF7 100n 2FF9 1u0 1u0 +3V3 30R IF67 IF68 +1V2-BRA-DR1 5FE7 IF48 +3V3-BRA

IF69

5FE8 +2V5-BRA 30R 2FG0 1u 0 7FE3 LD3985M25 5FE9 +5V 30R 1 3 IN INH OUT BP 5 4 FF03 +2V5-BRA

25M4 2FG2 2FG3 18p 18p 4 2

100n 2FG1

1FE0

COM 2FH2 2FH3 2FH4 1u0 10n AGND AGND AGND 1u 0 2 7FE0 TC90517FG 19 18 3 2 IF+ IF2FG4 10n 2FG6 2FG7 AGND 100n 2FG8 100n 2FH6 2FH7 10n IF17 IF18 BFE2 BFE3 100n 100n 30 29 28 27 24 25 26 39 +3V3-BRA-FLT 40 8 3FE6 10K 1 41 10K IF29 7 11 SCL-SSB SDA-SSB 3FE8 100R 3FE9 IF49 100R 45 46 I X O 16 36 56 63 13 35 49 64 34 48 DR1VDD 32 22 20 43 DR2VDD

AD_DVDD

AD_AVDD

PLLVDD

VDDC

VDDS

FIL

21 58 53 54 55 59 52 61 60 38 9 10 51 42 6 5 12 14

2FH5 1n5 DFE6 DFE7 DFE8 3FG6-3 DFE9 3 6 33R TS-BR-SOP 2 AGND 3FG6-4 4 5 33R TS-BR-VALID 1

* To be drawn near PNX85500

PBVAL RERR RLOCK

9F27-1

TS-FE-VALID

0 XSEL 1 P ADI_AI N P ADQ_AI N P AD_VREF N AD_VREF DTCLK DTMB S_INFO 0 TSMD 1 AGCI CKI AD_DVSS AD_AVSS PLLVSS SCL SDA

RSEORF SBYTE SLOCK SRCK SRDT STSFLG1 AGCCNTI AGCCNTR STSFLG0 SYRSTN SLADRS 0 1

9F27-2

TS-FE-SOP 5FG0

100n

2FG9

3FG7 3FG6-2 DFF1 2

33R 7

TS-BR-CLOCK 4

9F28 9F27-4 5

* *

TS-FE-CLOCK TS-FE-DATA

30R 5FG2 30R

AGND

33R TS-BR-DATA

AGND

IF27

3FE5 18K

IF28 IF-AGC 2FH8 10n

AGND

DFF2

3FE7

3FG2-1 10K 3FG4-2 4K7 3FG4-1 4K7 3FG2-2 10K +3V3-BRA-FLT

RESET-SYSTEMn

TN VSS 4 15 33 37 44 47 50 57 62

SCL SDA

23

31

AGND

AGND

17

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Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 126

10-10 B02 313912365214


NANDflash - conditional access

B02A

PNX85500: NANDflash - conditional access

+3V3

B02A
XIO-D00 XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07

3S1W

7S00-5 PNX85500

FLASH

NAND-ALE NAND-CLE

D22 ALE C21 NAND CLE J25 J26 H21 H22 H23 H24 H25 H26 G21 G22 G23 G24 G25 G26 F22 F23 00 01 02 03 04 05 06 07 XIO_A 08 09 10 11 12 13 14 15

00 01 02 03 04 05 06 07 XIO_D 08 09 10 11 12 13 14 15 XIO

D25 D26 C24 D23 C23 B23 A22 E22 F24 F25 F26 E23 E24 E25 E26 D24

10K XIO-D10 3S15 10K

INPACK

INPACK

IS26

B22 OE_ C22 WE_ B21

XIO-OEn XIO-WEn +3V3


NAND-CE1n

CLK_BURST

IS25

E21 CE1_ D21 CE2_ A20 NAND RDY2 F21 RDY1 A21 WP_

3S1V

9S08 IS00

NAND-RDY1n NAND-WPn

+3V3

3S1X

7S00-11 PNX85500 P21 P22 P23 P24 P25 P26 N21 N22 J22 K25 K26 N23 CA-MOCLK L25 N24 N25 CA-MOSTRT CA-MOVAL L22 L23 J21
CA-RDY

0 1 2 3 MDI 4 5 6 7

VIDEO_STREAM

0 1 2 3 MDO 4 5 6 7

N26 M21 M22 M23 M24 M25 M26 L21

10K

10K RES

CA-MDO0 CA-MDO1 CA-MDO2 CA-MDO3 CA-MDO4 CA-MDO5 CA-MDO6 CA-MDO7

ADD_EN DATA_DIR DATA_EN I MCLK O MISTRT MIVAL MOSTRT MOVAL OOB_EN RDY RST VCCEN VPPEN T21 DATA T23 ERR T22 TNR_SER1 MICLK R23 MIVAL R22 SOP
TS-FE-DATA TS-FE-ERR TS-FE-CLOCK TS-FE-VALID TS-FE-SOP

VS

K23 1 K24 2 K21 1 K22 2

9S00

CA-VS1n CA-MOCLK CA-CD1n CA-CD2n

CD

CA
3S1R 3S1S 3S1T 3S1U RES RES TS-FE-DATA TS-FE-CLOCK TS-FE-VALID TS-FE-SOP 3S23 470R 3S24 470R 3S28 470R 3S29 RES RES 470R 560R 560R 560R 560R

+3V3

TS-FE-DATA TS-FE-CLOCK TS-FE-VALID TS-FE-SOP

L24 L26 J23 J24

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Circuit Diagrams and PWB Layouts


SDRAM

Q552.2L LA

10.

EN 127

B02B

PNX85500: SDRAM

B02B

7S00-8 PNX85500 DDR2-BA0 DDR2-BA1


DDR2-BA2

H1 H2 G1 D1 D5 R3 T5 F3 C2 F2 C3 B4 F1 C1 E1 F4 B2 E5 C5 A4 G5 B3 F5 U3 P2 U2 P3 N1 U1 P1 T1 V4 R5 U5 P5 N3 V3 R4 V5

0 1 BA 2

MEMORY

DDR2-DQM0 DDR2-DQM1 DDR2-DQM2 DDR2-DQM3 DDR2-D0 DDR2-D1 DDR2-D3 DDR2-D2 DDR2-D6 DDR2-D5 DDR2-D4 DDR2-D7 DDR2-D8 DDR2-D9 DDR2-D10 DDR2-D11 DDR2-D12 DDR2-D13 DDR2-D14 DDR2-D15 DDR2-D16 DDR2-D17 DDR2-D19 DDR2-D18 DDR2-D22 DDR2-D23 DDR2-D20 DDR2-D21 DDR2-D24 DDR2-D30 DDR2-D26 DDR2-D25 DDR2-D28 DDR2-D31 DDR2-D27 DDR2-D29

0 1 DM 2 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DQ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

M0

+1V8

0 1 2 3 4 5 6 7 A 8 9 10 11 12 13 14 N P N P N P N P N P

J1 J3 K1 G4 L3 G3 L2 H5 L1 J5 J2 M3 J4 M2 K5 N5 N4 E2 E3 D3 D4 R1 R2 T3 T4 K3 K4 L5 M4 M1 M5 H3 A2 V1 DDR2-VREF-CTRL2 DDR2-VREF-CTRL3 100p 2S20 100n 2S17 2S24 100n 2S25 100p 1% IS42 261R 3S30 10R 3S33 10R

DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-A14 DDR2-CLK_N DDR2-CLK_P DDR2-DQS0_N DDR2-DQS0_P DDR2-DQS1_N DDR2-DQS1_P DDR2-DQS2_N DDR2-DQS2_P DDR2-DQS3_N DDR2-DQS3_P DDR2-CAS DDR2-CKE DDR2-CS DDR2-ODT DDR2-RAS DDR2-WE 3S6Q 10K 3S6P 10K RES

100u 2.0V

180R 1%

180R 1%

CLK

3S06

3S20

2S12

FS02 DDR2-VREF-CTRL3 180R 1% DDR2-VREF-CTRL2 180R 1% 3S22 FS01

DQS0

DQS1

3S07

DQS2

DQS3

CASB CKE CSB ODT PCAL RASB WEB 1 VREF 2

DDR2-CKE

DDR2-ODT

3S0V

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Circuit Diagrams and PWB Layouts


Digital video in

Q552.2L LA

10.

EN 128

B02C

PNX85500: Digital video in

B02C

7S00-6 PNX85500 HDMIA-RX2+ HDMIA-RX2HDMIA-RX1+ HDMIA-RX1HDMIA-RX0+ HDMIA-RX0HDMIA-RXC+ HDMIA-RXC+3V3 3S0W 12K RES 2S2E 10u IS01 W24 RREF T25 T26 P RX0_A N

HDMI_DV

U25 P U26 RX1_A N

Y26 SCL Y25 DDC_A SDA V25 P V26 T24 RX2_A N HOT_PLUG_A W25 P W26 RXC_A N

DDCA-SCL DDCA-SDA IS10

2011-05-10 2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


Audio

Q552.2L LA

10.

EN 129

B02D

PNX85500: Audio

B02D
3S0Z 3S53-1 100R 3S53-2 7S08 LD3985M25 FS08 IS12 4 2S2R 10u 5 OUT BP IN INH 1 10u RES 3 IS13 1u0 RES 4S14 +2V5 ADAC(1) IS02 12 13 11 +2V5-AUDIO +3V3 2S3J 220n +24V-AUDIO-POWER 4R7 +24V-AUDIO-VDD

1 AUDIO-IN1-L

3S12-1 22K

IS1H 8

1 3S16-1 8 10K 2 3S16-2

2S2W 1u0

100R 3S53-3 100R 3S53-4

FS03 4 7S05-4 LM324 14

2S2T

3S16-3 3

6 10K

2S2Z IS1M 1u0 100u 4V 3S51 4R7 2S42 2S41 IS0V 1u0 2S2Y 1u0 2S31 1u0 7S00-2 PNX85500

2S34

22K

1u0

100n

AUDIO-IN1-R

2 3S12-2

IS1J 7

7 10K

2S2S

3S38 100R

2S2V 100R

+AUDIO-L

COM

3S36-2 10K

7 8

10K 3S36-1 2S2G 47p +24V-AUDIO-VDD 1

3S16-4 5 4 10K 3S13-4 4 22K 3S13-3 6 22K 3S13-1 1 22K 3S13-2 22K 7 8 IS1Q 3S17-2 2 7 10K IS1P 1 3S17-1 8 10K 5 3 3S17-3 6 10K IS0R 4 3S17-4 5 10K

AUDIO-IN3-L

AUDIO-IN3-R

2S30 1u0 2S33 1u0 2S32 1u0 3S10 100R IS1B

AUDIO AE10 AC7 L P AIN1 ADACL AF10 AB7 R N


AD10 L AIN2 AC10 R AE9 L AIN3 AF9 R AD9 L AIN4 AC9 R AF8 L AE8 AIN5 R ADACR AC6 P AB6 N AD7 AE7 AF7 AD6 AE6 AF6

2S36 1u0 IS1N

1 3S3G-1 8 33R 3 3S3G-3 33R 6

ADAC(1) ADAC(2) ADAC(2) IS03 10 9 11 ADAC(3) ADAC(4) 4 7S05-3 LM324 8 3S39 100R

-AUDIO-R

AUDIO-IN4-L

AUDIO-IN4-R

1 2 3 ADAC 4 5 6

3S3G-2 2 7 4 IS1S 3S3G-4 33R 5 33R

2S2L IS19 1u0

I2S_OUT AB9 POS VR_AADC AB8 NEG AD8

AD4 OSCLK AD1 SCK AD2 WS

3 3S3H 33R 3S3U 33R


ADAC(6) ADAC(5)

3S36-3 10K

6 5

10K 3S36-4 2S2H 47p +24V-AUDIO-VDD 4

IS1A 3S3F 56R 10u 2S3G 100n 2S3H 10u 2S3E 2S3F 100n 9S06 RES DBS8

AE1 1 AF2 2 VREF_AADC AE3 I2S_OUT_SD 3 AF3 AC8 VCOM_AADC 4 AF5 AE5 SPDIF_OUT SPDIF_IN1

2S3D

1n0 2S3C

1n0 2S3B

1n0 2S3A

1n0 2S39

1n0 2S38

1n0

IS07 ADAC(5) 3 2

7S05-1 LM324

AUDIO-OUT-L

11

3S37 10K

3S6L 22K 2S2K 47p +24V-AUDIO-VDD

+3V3 +3V3-ARC

3S11 1R0 2S3Q

IS1L

100n

ADAC(6) IS06

5 6

7S05-2 LM324 7

AUDIO-OUT-R

SPDIF-OUT-PNX

SPDIF-OUT-PNX

IS1D

7S09-1 74LVC00APW 1 2

3S6N 14

SPDIF-OPT

11

&
3

RES 2S3K 100n

47R IS1G 1 3S18-1 8 RES 3S18-2 RES 3S18-3 220R RES 7 6


SPDIF-OUT

3S34 220R 10K

3S32 22K 2S2J 47p

+3V3

220R

+3V3

+3V3-ARC 3S19 10K 7S09-2 74LVC00APW 4 IS1E 5 7 +3V3 10 7 +3V3-ARC 14 7S09-3 74LVC00APW 9

&
6

14

&
8

SEL-HDMI-ARC

2S3L 100n

180R 3S6M

IS1K

2S3M 100n 3S25 68R

IS44
eHDMI+

+3V3-ARC 7S09-4 74LVC00APW 12 +3V3 13 7

14

&
11

2011-05-10 2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


MIPS

Q552.2L LA

10.

EN 130

B02E
3S45 +3V3 10K +3V3 3S40 10K 3S82 +3V3 +3V3 +3V3 +3V3 10K 3S62 +3V3 10K 3S80 3S81 10K 10K 10K

PNX85500: MIPS

B02E
7S00-3 PNX85500 +3V3

CONTROL
IS05
BOOTMODE BOOTMODE 3D-LR RXD1-MIPS TXD1-MIPS RXD2-MIPS TXD2-MIPS

1 Y21 IS16 Y22 Y23 Y24 W21 W22 W23 V22 V23 U23 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_10 GPIO_11

C25 SDA C26 SCL

1 100R

3S56

2 1 100R 1 100R 1 100R 1 100R 2 3S57

SDA-UP-MIPS SCL-UP-MIPS SDA-SET SCL-SET SDA-SSB SCL-SSB SDA-TUNER SCL-TUNER EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TDI-PNX85500

SDA-UP-MIPS SCL-UP-MIPS SDA-SET SCL-SET SDA-SSB SCL-SSB SDA-TUNER SCL-TUNER EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TDI-PNX85500

3S69 3S6A 4K7 3S6B 3S6C 4K7 3S6D 3S6E 2K2 3S6F 3S6G 2K2 3S6K 1 10K 8 3S6H-1 10K 3 6 3S6H-3 2 10K 10K +3V3-STANDBY 7 3S6H-2 5 3S6H-4 4 10K FS57 +3V3 2K2 2K2 EJTAG-DETECTn FS53 4K7 4K7 EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDI-PNX85500 FS44 FS49 FS50 FS51 FS52

RES 1F10 1 2 3 4 5 6 7 8

3D-LR

IS17

9S09

B26 SDA 2 A25 SCL 3 B25 SDA A24 SCL

3S58 1 2 100R 1 3S5Y 2 100R 1 100R 3S60 2

2 3S5W

DS52 BOOST-PWM FS10 TXD2-MIPS FS11 RXD2-MIPS IS04 GPIO6

FOR FACTORY USE ONLY

3S5Z

GPIO6
PNX-SPI-CS-BLn BOOST-PWM SELECT-SAW USB-DM USB-DP

B24 SDA 4 A23 SCL TRSTN TMS TCK TDO TDI AA25 AA24 AA23 AB26 AB25 AE4 AD5 AC5

10 9

3S61

RES 3S21

PNX-SPI-CS-BLn

R26 DN R25 USB IS4Z R24 DP RREF 5K6 1% 3S55

BM08B-SRSS-TBT

3S00 33R

RESET_SYS BL_PWM CLK_54_OUT

RESET-SYSTEMn BACKLIGHT-PWM

3S64 +3V3 10K

FS64

SELECT-SAW

3S26

3S27

3S6J

RES 10K

3S83 +3V3 10K 3S84 +3V3 10K

RXD1-MIPS

+3V3 TXD1-MIPS 3S72 47R

10K

+3V3 IS40
PXCLK54

10K

RES

+3V3 2S89 100n 7S01 PCA9540B 3 +3V3 3S65 3S66

VDD

SC0 SC1

5 8 4 7

SCL-DISP SCL-BL SDA-DISP SDA-BL

SCL-DISP SCL-BL SDA-DISP SDA-BL

SCL-SET SDA-SET

1 2

SCL SDA
INP FIL

I2 C -BUS CTRL

SD0 SD1

1 4K7 1 4K7 3S67 2 1 4K7 3S68 2 1 4K7 2

VSS 6 FS31 9S10 IS08


SCL-SET

SCL-BL

9S11 9S12

FS2W FS2Y

SCL-DISP SDA-DISP SDA-BL

SDA-SET

IS09

9S13

7S00-4 PNX85500
ETH-RXCLK ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3) ETH-RXDV ETH-RXER SDIO-DAT3 SDIO-CLK SDIO-CMD SDIO-DAT0 SDIO-DAT1 SDIO-DAT2 SDIO-CDn SDIO-WP

AA3

RXCLK

ETHERNET
TXCLK AA2 AA1 AA4 AB1 AB2 AA5 AB3 AC3 Y2 Y3 Y1
ETH-TXCLK ETH-TXD(0) ETH-TXD(1) ETH-TXD(2) ETH-TXD(3) ETH-TXEN ETH-TXER ETH-COL ETH-CRS ETH-MDC ETH-MDIO

IS50

Y5 0 Y6 1 AB4 RXD ETH 2 AC1 3

0 1 AC2 TXD 2 RXDV Y4 RXER 3 ETH TXEN W2 TXER CC_DAT3 W1 COL CLK W6 CRS CMD W5 0 MDC W4 SDIO 1 DAT MDIO W3 2 U6 SDCD V6 SDWP

2011-05-10 2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


Video out - LVDS

Q552.2L LA

10.

EN 131

B02F

PNX85500: Video out - LVDS

B02F

7S00-7 PNX85500 PX1APX1A+ PX1BPX1B+ PX1CLKPX1CLK+ PX1CPX1C+ PX1DPX1D+ PX1EPX1E+ PX2APX2A+ PX2BPX2B+ PX2CLKPX2CLK+ PX2CPX2C+ PX2DPX2D+ PX2EPX2E+ 9S92 9S93 9S90 9S91 A7 B7 C8 B8 N A P N B P

LVDS
A

N P N P

D7 E7 E8 D8 9S94 9S95

PX3APX3A+ PX3BPX3B+ PX3CLKPX3CLK+ PX3CPX3C+ PX3DPX3D+ PX3EPX3E+ PX4APX4A+ PX4BPX4B+ 9S96 9S97 PX4CLKPX4CLK+ PX4CPX4C+ PX4DPX4D+ PX4EPX4E+

C10 N CLK B10 P A9 B9 N C P LOUT1 LOUT3

CLK

E10 N D10 P N P D9 E9

A11 N D B11 P C12 N E B12 P A14 N A B14 P C15 N B B15 P C17 N CLK B17 P A16 B16 N C P A18 B18 N D P C19 B19 N E P LOUT2 LOUT4

D11 N E11 P E12 N D12 P D14 N E14 P E15 N D15 P E17 N D17 P D16 N E16 P D18 N E18 P E19 N D19 P

CLK

2011-05-10 2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

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Circuit Diagrams and PWB Layouts


Standby controller

Q552.2L LA

10.

EN 132

B02G

PNX85500: Standby controller

B02G
+1V1 POL IS3B RES 5S04 30R

1u0 2S10

2S13 2S37 9S24 RES 1u0 2S11 100n

IS20

100n

DS50 AC17 1 7S00-9 PNX85500 XTAL_IN XTAL_OUT RESET_IN EA ALE PSEN MC AE17 AF17 AA26 AB24 AB23 AC26 3S2F 100R 3S2H 100R 100R

3 1S02 2 4 1 54M

2S4G 10p 2S4F 10p +3V3-STANDBY

AA17 VDDA_1V1_DCS

VDDA_ADC2V5

AF26

+3V3-STANDBY 3S1C 3S1E 10K +3V3-STANDBY 3S3M 10K 3S3P 10K RES 3S3S 10K 3S3T +3V3-STANDBY 3S1H 10K 10K RES 10K RES 3S1F 3S3L

3S1B 10K 3S1D 27K 10K

RC TACHO CEC-HDMI BACKLIGHT-PWM-ANA-DISP SDM LCD-PWR-ONn EJTAG-DETECTn LAMP-ON STANDBY FAN-CTRL1 FAN-CTRL2 POWER-OK ENABLE-3V3n RXD-UP TXD-UP DETECT2

2S4D 1n0

RC TACHO CEC-HDMI BACKLIGHT-PWM-ANA-DISP SDM LCD-PWR-ONn EJTAG-DETECTn LAMP-ON STANDBY FAN-CTRL1 FAN-CTRL2 POWER-OK ENABLE-3V3n RXD-UP TXD-UP DETECT2

AD19 0 AE19 1 AF19 2 P1 AA20 3 AB20 7 AC20 0 AD20 1 AE20 2 AF20 3 AA21 P2 4 AB21 5 AC21 6 AD21 7 AE21 0 AF21 1 AA22 2 AB22 P3 3 AC22 4 AD22 5 AD23 0 AE26 1 AE25 P5 2 AE24 3

VDD_XTAL

RESET-STBYn IS3F EA ALE PSEN SDA-UP-MIPS SCL-UP-MIPS LED1 LED2 PNX-SPI-SDO PNX-SPI-SDI PNX-SPI-CLK PNX-SPI-CSBn IS2V IS2Z CTRL-DISP RESET-DVBS RESET-USBn RESET-ETHERNETn SEL-HDMI-ARC RESET-AVPIP RESET-AUDIO AUDIO-MUTE-UP CTRL-DISP RESET-DVBS RESET-USBn RESET-ETHERNETn SEL-HDMI-ARC RESET-AVPIP RESET-AUDIO AUDIO-MUTE-UP RES 10K RES 3S3Y 10K 10K 3S2S RES 3S3W 4K7 3S2L RES 10K RES 10K 10K 4K7 3S46 3S47 3S2M RES 3S49 +3V3-STANDBY EA ALE PSEN
SDA-UP-MIPS SCL-UP-MIPS

RES 10K 3S3N RES 10K 3S3Q RES 10K 3S3R 10K RES

STANDBY

3S44 10K 10K 3S42 3S6V 4K7 RES 3S1P 10K 10K 4K7 3S43 10K

IS3E IS3D RES

AC23 SDA AC24 SCL

3S2G

3S6W RES

3S1G 10K 3S2A 10K RES

AD26 0 PWM AC25 1 AE23 SDO AF25 SDI AF24 SPI CLK AF23 CSB AB17 0 AA18 1 AD18 2 AE18 3 AF18 P0 4 AA19 5 AB19 6 AC19 7

100R

LED1 LED2

3S2K

3S41

3S1K 10K RES

RESET-SYSTEMn 3S1J 100K RES 3S1L 10K 2S4E 100n SPI-PROG KEYBOARD

VSS_XTAL

RESET-SYSTEMn AV2-BLK AV1-BLK KEYBOARD LIGHT-SENSOR AV1-STATUS AV2-STATUS SPI-PROG PNX-SPI-WPn

AF22 4 AE22 P6 5

AD17

+3V3-STANDBY

+3V3-STANDBY

1 3S2V 2

9S0E

1K0

FS45 1

7S20 NCP303LSN28 2 IS2U 5

FS0Z

RESET-STBYn

INP OUTP CD NC GND 3

9S0D

2S4K

100n

RES

2011-05-10 2010-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

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Circuit Diagrams and PWB Layouts


Power

Q552.2L LA

10.

EN 133

RES 10u

B02H

PNX85500: Power

IS3Q 2

5S80 +1V1 30R 2S6A 2S5A 100n

B02H

5S81 +2V5 RES 10u 30R 2S5B 100n 2 +1V8 100n 2S65 100u 2S60 100n 2S61 2S62 2S26 100n 2S63 100n 2S64 100n 2S66 100n 2S67 100n 2S68 100n 100n IS3S 2 RES 10u 1 2S6B

5S82 +3V3 30R 2S5C 2S5D 100n

SENSE+1V1

c001 7S00-10 PNX85500 L6 L7 R6 R7 U7 A5 A6 B5 B6 C6 D6 E6 F6 G6 F7 G7

5S93 2 30R 100n 2S6E 2 220u 6.3V 2S4M 100n +2V5

+1V1 6 5 8 8 7 2S5G-1 100n 2S5G-2 100n 2S5G-4 100n 2S5G-3 100n 2S5H-1 2S4Q 22u 2S4R 2S43 2S28 2S27 100n 100n 100n

7S00-12 PNX85500 A1 A10 A12 A15 A17 A19 A26 A3 A8 B1 B20 C20 C4 D2 D20 E13 E20 E4 F10 F12 F14 F16 F18 F20 F8 G10 G12

VSSA

VSS

VSS

VSS

VSSA_1V1_LVDS_PLL

VSSA_2V5_LVDS_BG

2S46

VSS G14 G16 G18 G2 G20 G8 H4 H6 H7 J20 K10 K12 K14 K16 K18 K2 K6 K7 L20 L4 M10 M12 M14 M16 M18 M6

+1V1

30R 2S4S 10u RES

VDD_1V1_DDR

VSSA_USB

J7

VDDA_2V5_VDAC VDDA_3V3_USB

Y10 R21

2S5P

2S21

100n

1u0

C13

R20

A13

100n

5S94

U24 V24 HDMI_AGND

M7 N2 N20 P10 P12 P14 P16 P18 P4 P6 P7 T10 T12 T14 T16 T18 T2 T6 T7 U4 V10 V12 V14 V16 V18 V2 Y20

AF1 AE2 AD3 AC4 AB5 H20 F11 G11 F13 G13 F15 G15 F17 G17 F19 G19 J9 J11 J13 J15 J17 L9 L11 L13 L15 L17 N9 N11 N13 N15 N17 R9 R11 R13 R15 R17 U9 U11 U13 U15 U17 J6 AA6 Y7 W7 F9 G9

HDMI_VDDA_1V1

V20 V21 U20 U21 U22 N6 N7 C7 C9 C11 C14 C16 C18 W20 P20 M20 K20 V7 Y8 Y19 Y18 IS3K B13

100n 2S5H-2

100n 2S5H-3

100n 2S5H-4

2S23

100n

100u

22u

VDD

2S6D

VDD_1V8

HDMI_VDDA_2V5 HDMI_VDDA_3V3_TERM VDD_2V5

+2V5-LVDS 2S4N 2S4P

100n

2S5K-1

100n 2S5K-3

100n 2S5K-2

100n 2S5K-4

100n 2S5J-3

100n 2S5J-1

100n 2S5J-2

100n 2S5J-4

100n

220u 2.5V

2S29

10u

VDD_2V5_LVDS

5S85 100n 1 2S6G 2 100n 2S6N 100n 2S6C 2S6P 2S6F 100n 10u 30R +3V3 2 2 2 1

AA16 AA8 Y11 Y14 Y16 Y9

VDD_3V3

+3V3-STANDBY 10u 2S4U 2S4V 100n 5S83 +1V1 RES 1u0 2S4W 2S4Y 100n IS3L 30R 5S84 6.3V 30R 2S4Z 2S50 100n 10u 30R c000
SENSE+1V2

VDD_1V1 VDD_3V3_SBY VDDA_1V1_LVDS_PLL

AA15 Y15 VDDA_1V2 AA13 VDDA_2V5 VDDA_2V5_AADC VDDA_2V5_ADAC VDDA_2V5_DCS VDDA_2V5_LVDS_BG VDDA_2V5_USB VDDA_2V5_VADC Y12 AA9 2S51 AA7 Y17 D13 T20 Y13 2S52 100n

5S95

+2V5

+1V2

10u

POL +2V5-AUDIO

+2V5-AUDIO 2S45 100n

5S87 +2V5 30R 2S55 2S56 100n 1u0 5S88 +2V5-LVDS 2S5M 100n 2S57 10u 30R 5S89 +2V5 100n 2S58 10u 30R 2 2S6H 100n 2S6K 1 2 5S90 +2V5 30R 2S4T 2S53 100n 10u 5S92 +3V3 100n 2S59 1u0 30R
4 2011-05-10 2011-03-09 2010-12-23

2SHW IS58

100n

2S6M

100n 2S6L

SPB SSB TV550 2K11 4DDR BR SD

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Circuit Diagrams and PWB Layouts


Analog video

Q552.2L LA

10.

EN 134

B02I
Connectivity

PNX85500: Analog video


AV1-CVBS 22n 2S87

B02I
3S59
2S8A 22n Y-SVHS

47R

AV1-R 22n

2S7J 2S22 22n C-SVHS

3S4J

56R

3S05

EU: SCART1
3S5E
22n

56R

3S5B

47R

CVBS-MON-OUT1

3S4L

56R

IS4V

2S7H AV1-G

3S4K

56R

22n IS4W

3S09
YPBPR1-SYNCIN1 2S7M 10n 2S7L AV3-Y

3S4P

56R

22n

2S7N AV3-PR

56R

EU: AP:

3S4R

YPBPR1 YPBPR1
AV3-PB

22n 7S00-1 PNX85500 2S7P

ANALOG_VIDEO
AB15 AC13 AD13 AE13 CVBS_Y1 ATV_CVBS_Y3 C3 R B AV1 CVBS_Y7 G C7 SYNCIN1 CVBS1_OUT Y_G1 CVBS2_OUT PR_R_C1 PB_B1 RESREF CURREF CVBS_Y2 SYNCIN2 1 Y_G2 2 PR_R_C2 3 PB_B2 REF 4 5 R 6 G VGA B IF_AGC HSYNC_IN RF_AGC IN VSYNC OUT P SCL VGA_EDID TUNER N SDA AGND

2S19

2S18 22n

2S16 22n

2S15 22n

3S4T

56R

22n

AD11 AC11 AF11 AE11 AB10 AA11 AC16 AB16 AB13 AB12 AA12 AA10 AD12 AB11 AE12 AF12 BS13

AV2-CVBS 22n

2S8G

9S18

AF15 AE15 AC15 AD15 AB14 AF14 AE14 AC14 AD14 AF16 AD16 AE16 AB18 AC18 AF4 AD24 AD25

IS5E IS5D IS5F IS5G IS5H IS5J

3S5S 10K

22n

IS5C

3S75

2S14

22n

AC12 AF13

8K2

560R

2S40

3S08

47p

560R

AP:

AV1-B

2S7K

PNX-IF-AGC

AV4-Y

AP:

9S19

EU:

SCART2 YPBPR2

22n

BS10

10n

2S7R

BS15

2S75

10K

3S76

IS11 PNX-RF-AGC

+CVBS
2S76
AV4-PR 22n 2S7U

9S20

AA14

10n

47K

2S77 10n

PNX-IF-P

AV4-PB

2S7E

9S21

22n

2S78 10n

PNX-IF-N

2S84 R-VGA

3S50 3S52 3S54

56R

22n

2S85 G-VGA

56R

22n

2S86 B-VGA

3S5V-4

100R

H-SYNC-VGA

3S5T-1 100R

100R

100R

V-SYNC-VGA

3 3S5T-3 6 100R RES 3 3S5V-3 100R 3S5V-1 100R


4 2011-05-10 2011-03-09 2010-12-23

* 319803104790 - RST SM0402 47R PMS Col R at 9S18 for BRZ


6

VGA-SCL-EDID

VGA-SDA-EDID

RES

100R

AP: VGA

3S5V-2

3S5T-4

3S5T-2

EU: VGA

56R

22n

SPB SSB TV550 2K11 4DDR BR SD

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Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 135

10-11 B03 313912365214


Audio

B03A

Audio
+AVCC

B03A
6 +24V-AUDIO-POWER 4R7 2D06 220n 1 3D09 7D03-1 BC847BS(COL) +24V-AUDIO-POWER FD14

3D16 ID11 22K

ID12 10u 35V

220R 5D08

220R

5D07

2D05

GND-AUDIO

-AUDIO-R

FD01

2D28 1u0

ID14 4 6 7 3D02-2 2 4K7 2 7D15-1 BC847BS(COL) 1

2D24 2D07 2D20 47n 4K7 220u 35V

ID27

ID28 220u 35V

2D19

2D08

220n

220n

3D02-4

3D14-4 22K

3D14-3 22K

3D14-2 22K

3D14-1 220n

A-PLOP

FD08

GND-AUDIO

GND-AUDIO 7D10-1 TPA3123D2PWP

19 20

+AUDIO-L

1 3

3 6 3D02-3 4K7 3 5 7D15-2 BC847BS(COL) 4

3D02-1 1 8

1u0

47n 4K7 ID19 ID18 6 5 18 17

AVCC

10 12

FD03

2D29

ID15

2D23

R PVCC BSR R OUT L 16 15 22 21 ID31 2D09 220n ID32 2D10 ID10 220n 22u ID09 5D01 22u ID05 5D02 ID06 5D05 220R 5D04 220R ID08 ID07 2D12 35V 220u 2D11 35V 220u LEFT-SPEAKER RIGHT-SPEAKER

R IN L 0 GAIN 1 VCLAMP BYPASS MUTE SD

CLASS-D AUDIO AMP

BSL

GND-AUDIO 2D17 1u0 AUDIO-MUTE-UP A-STBY +3V3-STANDBY 6

2D16 1u0

ID29

ID30

11 7 4 2

ID37 FD09

PGND AGND 8 9 L 23 24 R 13 14 GND_HS 25

3D15

3D01-3

4K7

3D10-2 22K

3D10-4 22K

3D10-3 22K

3D10-1 220n

2D21 220n 10n

2D22 220n

47K

MAINS SWITCH DETECT

CD10

FD10

7D11-1 BC847BS(COL) 1

3 7D11-2 BC847BS(COL) 4

ID34 ID35 5 4 3D01-4 47K 2D03 100p 5 DETECT2

+3V3-STANDBY

GND-AUDIO

22K

GND-AUDIO

7D10-2 TPA3123D2PWP 26 27 28 29

40 39 38

GND-AUDIO LEFT-SPEAKER V_NOM 2D14 1D50 37 36 35 34

GND-AUDIO

VIA VIA

GND-AUDIO

GND-AUDIO

VIA
VIA

VIA

GND-AUDIO

GND-AUDIO

2D27 RES

2D26 RES

22K

1735 30 31 32 33 5D03 2D01 220R GND-AUDIO 3D06-3 FD07 3 100K 6 7 3D06-2 100K 2 4 RIGHT-SPEAKER ID33 GND-AUDIO RIGHT-SPEAKER 4 3D06-4 100K 2D02 5 10u GND-AUDIO V_NOM 1D52 3 7D03-2 BC847BS(COL) 5 GND-AUDIO 10n 2D13 FD05 FD06 FD02 10n 1 2 3 4

1D38 1 2 3 2041145-3

2041145-4

LEFT-SPEAKER

8 3D06-1 1 100K

2011-05-10 2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


DC/DC

Q552.2L LA

10.

EN 136

B03B

DC/DC

B03B
5U03 RES 30R 5U02

FU05

IU22 +12V

2U24

2U23

2U25

2U19

2U20

10u

10u

IU10

7 8 2

3U11

3R3

12V/1V8 CONVERSION
FU02 5U00 3u6

2U21 IU11 220p

10u

10u

1u0

7U02-1 SI4952DY

30R 0402 Jumper

FU03 +1V8

3U23-4

47R 3U23-3

3U23-2

47R 3U23-1

2U15

7U02-2 SI4952DY IU09 5 6 4

IU23

2U17

2U18

7U01 SI4778DY IU08 3U27 10R IU12 5 6 7 8 4 1 2 3

2U00

3U14

10u

3U04 IU05

3R3

3R3

2U22 IU06 2U02 100n IU07

3U28

2U01

100n

3R3

10R

IU13

220p

7U03 TPS53126PW 2 11 3 10 1 VBST 2 1 EN 2 1 VO 2 1 VFB 2 1 TRIP 2 VIN GND 1 2 1 2 1 2 1 2 1 2

3U05

7U04 SI4778DY IU16 IU14 5 6 78 4 1 2 3

IU24 ENABLE-1V8

DRVL

23 14 1 12 24 13 22 15 7 17 18 19 GND-SIG IU25 FU04

12V/1V1 CONVERSION
FU06 5U01 2u0 FU01 +1V1

DRVH

1n0 RES

2U03

3U24-4

47R 3U24-3

3U24-2

47R 3U24-1

3U20

2U12

47R

47R

RES 7U00 BC847BW IU03 1 2 +3V3-STANDBY 3U00 10K 3U01 2U06 3

GND-SIG 3U02 22K GND-SIG GND-SIG +1V1 12K 3U03

IU01

21 16 20

TEST

IU02

2U11

2U04

2U05

10u

100n

1u0

10K

IU18

GND-SIG

1n0

V5FILT VREG5

IU17

2U09

2U10

1n0

GND-SIG

1u0

47u

22u

PGND

2U13

10R RES

5 8

3U21 IU19 100R 1%

FU00

1% 330R

3U17

RES 2U29

IU20

100p RES

2U08

3U19

3U18

3U08 +1V8 330R 1%

3U22 1K0 1%

IU04

FU09

CU00 CU01 CU02 CU03 CU04 CU05

FU08 IU21

RES 100p

1K0 1%

3U09

3U10

2U07

22K

GND-SIG

GND-SIG

GND-SIG

GND-SIG

GND-SIG

GND-SIG

GND-SIG

1% 1K0

5K6

100n

RES 100u 2.0V


SENSE+1V1

SW

STPS2L30A

+1V1 +1V8

4 9

1n0

1n0

IU15

2U16

47R

47R

47u

22u

6U00

2U14

2011-05-10 2011-03-09 2010-12-23

SPB SSB TV550 2K11 4DDR BR SD

3139 123 65213

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Circuit Diagrams and PWB Layouts


DC/DC

Q552.2L LA

10.

EN 137

B03C

DC/DC
+3V3 LED-2 RES 10K RES 10K 3U74 3U75 +3V3-STANDBY

B03C
**
Items Optional table for Ambilight Emmy ( +24V AL) yes yes no yes no Sundance / Infinity ( +12V AL) no no yes yes yes BlockBuster (For non-Amblight sets) no no no yes no

+5V +3V3-STANDBY

***

Optional table for Styling 2U44 3U43 open 100R 1M95 13 POLE 14 POLE

9U41 RES 10K 3U68 3U69 10K

IU43

IU44 IU45 9U42 RES 7U42 RES BC847BW IU47

3U41 10K RES

* *

optionally 1M99 is a 9 pin connector

LED2

LED2

3U59 10K RES

4U00 4U01 1M99 1M95 2U56

Dream Catcher Core Range

0R 100p

LED-1

+3V3 LED1 LED1 3U53 10K

7U43 BC847BW

3U70 10K

1M99 1 2 3 4 5 6 7 8 9 10 11 12 13 1-2041145-3 RES 2U57 2U56 1n0 1n0 GND_AL GND_AL GND_AL FU77 +12VIN FU56 FU57 FU74 FU68 100p 100p 100p 100p 100p RES 3U66 RES 3U67 RES 3U84 RES 3U76 RES 2U48 RES 2U72 RES 2U51 RES 2U52 RES 2U43 100R 4 100R 100R 100R BL-SPI-SDO BL-SPI-CSn BL-SPI-CLK FU48 FU49 FU50 FU54 RES 3U44 100R FU07 3D-LR +12V_AL +3V3 RES 3U56 10K 4 3U82 1K0 RES 3U83-4 5 7U48-1 BC857BS(COL) 1 ENABLE-3V3-5V IU64

3U83-1 2 1

8 2U71 +3V3-STANDBY 3 100n 5 7U48-2 BC857BS(COL) 3U83-2 100K 6 IU40 7 100K 2

100K IU41

MAINS-OK

**

3U71

100R

STANDBY 5 7U40-2 BC847BPN(COL) IU48 5 3 3U62-3 3 IU61 7 10K 3 3U60-3 6 22K FU73 RES 10K 3U61 10K 4 3U83-3 100K

2U68 1u0 2U47 BZX384-C6V2 1M95 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1-2041145-4

3U62-4 4

10K

***
FU58 FU59 FU60 FU61 FU63 FU75 FU67

6U40

10n 2U54 +12VIN T 3.0A 32V 3U72 2U50 +24V-AUDIO-POWER 1K0 1U40 +12V

22K

IU51

1u0 RES

10n

2U55

2U49

3U80

100n

4K7

FU62 FU76 2U58 100n

3U63

10K FU51 FU52 FU53 3U45 100R 100R 100R FU55 3U64 IU55 POWER-OK 100p 3U42 3U43 LAMP-ON BACKLIGHT-PWM_BL-VS BACKLIGHT-BOOST

***

** **

4U01 4U00 1K0 2U53 3U65 100K 1n0 10n

GND_AL +12VIN

1n0

*** 2U44

+12VD

2U45

2U46

RES 10K

+24V

GND-AUDIO

+3V3

3U81

IU56

+3V3-STANDBY 3K3

6 1 7U41-1 BC847BS(COL) 1 10K

3U73

3U62-1

IU62 IU50

3U60-4

22K

**
10n +3V3-STANDBY FU66

ENABLE-1V8

IU49 6 7U40-1 BC847BPN(COL) 1 IU63

3U62-2

FU72 7U41-2 BC847BS(COL) 5 4 IU52 8 3U60-1 22K IU57 1

3U60-2

DETECT2

ENABLE-3V3n

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Circuit Diagrams and PWB Layouts


DC/DC

Q552.2L LA

10.

EN 138

B03D

DC/DC
+3V3 7UC0 LF25ABDT 1 IN OUT COM 2UA4 3UA0 2K2 3

B03D
*
+12V 1u0

*
FUA0 +2V5-REF

1 7UA0 TS2431 K

2 A

FUA4 +2V5

IUB6 +5V5-TUN +5V-TUN

CUA0

+2V5-LVDS

+12V

+2V5-REF

3UB6-4 4 5 1K0 3UB7-4 5 4 470R

330R 1%

5 7UA7-2 4 BC847BS(COL)

7UA7-1 BC847BS(COL) 3U13 IUB4

2UB0

1u0

6 1K0 IUB2 3UB6-2 2 7 6 1K0 3UB6-1 1 8 1K0 IUB5 3 1

3UB6-3

7UA6 BC817-25W 3U12 IUB3

330R 1%

+1V8 +5V IU26 7UA3 PHD38N02LT 3UB0 22R FUA3 4 +1V2 2UB1 RES 1u0 2UB2 IUA5 2 1

*
3U15-1 100R 3U15-2 100R 3U15-3 100R 3U15-4 100R 7 8

+3V3 +5V

3U16-1 100R

+3V3

3U16-2 100R 3U16-3 100R 3U16-4 100R

1 2 470R 3UB7-3 3 3UB7-1470R 8 1

3UB7-2

2UB8

470R

22u

1u0

NOT FOR 5000 SERIES

ENABLE-1V8 4 3U25-4 5 100K RES 7 IUA6 3UB1 1K0 SENSE+1V2

100K RES 3 3U25-3 6

RESERVED 5UA0 30R

3U25-2 2

100K RES

1 100K RES IU29

3U29-1 470R 3U29-2 470R

RES

+12V

7UA5 LDS3985M50 +5V5-TUN 1 3 IN INH OUT BP 5 4 IUB1 2UB5 100n 2UB6 1u0 +5V-TUN

RES 7UA4 TS431AILT 5 A


NC

3U25-1 3 RES 7U06-2 BC847BS(COL) 4 8 6 5 RES 7U06-1 BC847BS(COL) 1 IU30 2

+3V3

3 3U29-3 6 RES 470R 3U29-4 470R 1 3U26-1 8 RES 470R 3U26-2 470R RES 3UB5 +5V 6 RES 100K RES

3UB2 3

4K7

2UB7

REF

3UB3 4

3UB4 1K0

IUB0

2UB3 1n0

+3V3

3U26-3 470R 3U26-4 470R

2UB4 RES 330p RES


4 2011-05-10 2011-03-09 2010-12-23

4K7

NC

1u0

COM

SPB SSB TV550 2K11 4DDR BR SD

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Circuit Diagrams and PWB Layouts


DC/DC

Q552.2L LA

10.

EN 139

B03E

DC/DC
5UD0 +12V IUD0 +5V5-TUN 2UD0 2UD1 2UD2 10u 10u 10u 7UD0-1 ST1S10PH ENABLE-3V3-5V RES 1n0 2 5 INH SYNC A 4 1 A SW 6

B03E
*
30R 0402 Jumper 7 3 IUD3 5UD1 3u6 2UD4 22u 2UD5 22u IUD7 6UD0 SS36 2UD6 FUD3 +5V RES 2U27 RES 2UE9 220u 16V +1V1 100n

VIN

SW

2UD3

VFB GND P HS 8 9

6 7U05-1 BC847BS(COL) RES 1 2

IU27

IUD6 7UD0-2 ST1S10PH 10 11 14 13 15

2UD7 4n7 3UD2 120K

1% 3UD0

68K 3UD1

* *
+12V

5UD3

IUD1 7UD1-1 ST1S10PH ENABLE-3V3-5V 2 5 INH SYNC A 4

2UD8

2UD9

2UE0

10u

10u

10u

30R 0402 Jumper

SW

VIN

SW

7 3

IUD4

5UD2 3u6

FUD2 +3V3 220u 16V +1V1 RES 2U28 100n 2UE1 1% 100K 4n7 3UD3 2UE2 22u 2UE3 2UE4

VFB GND P HS 8 9

22u

3 7U05-2 RES 4

BC847BS(COL) 5

RES

VIA

12

33K 1%

3U06

IUD2 7UD1-2 ST1S10PH 10 11 14 13 15

3UD4

1M0 3UD5

*
+5V

7UD2 LD1117DT25 6UD1 S1D 2UE5 100n IUD5 3 IN OUT COM 1 2UE6 2 22u 16V +2V5

(*) FOR 5000 SERIES ONLY (**) NOT FOR 5000 SERIES

7UD3 LD1117DT33 3 IN OUT COM 2UE7 1 2UE8 100n 2 22u 16V +3V3

RES

VIA

12

33K 1%

3U07

10K

10K

IU28

22u

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Circuit Diagrams and PWB Layouts


Temperature sensor & AmbiLight

Q552.2L LA

10.

EN 140

B03F

Temperature sensor & AmbiLight

B03F

5UM1 +3V3 30R

IUM0

1UM0 T 1.0A 63V

FUM0

V-AMBI

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Circuit Diagrams and PWB Layouts


Fan control

Q552.2L LA

10.

EN 141

B03G

Fan control

B03G
+12V +3V3 1 3US4-1 8 10K +12V

3US5-2

+12V 3 7US1-1 LM339P 14

10K 7

2US3 IUS6 7US2 BC807-25W IUS7 3US9 22R BC807-25W 7US3 IUS9 3US6 47R

3US2

FAN-CTRL1

1K0 IUT1

IUS3 3US5-1 8 1 10K

8 12

+12V +3V3 3US5-3 6

11 IUT2 FAN-CTRL2 10

IUS4 3US5-4 5 4 10K IUS8

12

FAN-DRV +3V3 +12V 10K +12V 7US1-3 LM339P 2 3US4-4 IUS5 3US4-3 6 10K 5

5 4

TACH01

+12V 9US0 RES +12V 3US4-2 7 10K 7US1-4 LM339P 1

7 6

12

TACH02

FUS0

TACHO

12

3US3

10K

7US1-2 LM339P 13

10K

+12V

3US7

100n

10K

2011-05-10 2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


Vdisp switch

Q552.2L LA

10.

EN 142

B03H

Vdisp switch

B03H

1 9UU0-1 RES 2 9UU0-2 RES 3 9UU0-3 RES 4 9UU0-4 RES 1 9UU1-1 RES 2 9UU1-2 RES 3 9UU1-3 RES 4 9UU1-4 RES

8 7 6 5 8 7 6 5 FUU0

RES 7UU0 SI4835DDY +12VD RES 7UU2-2 PUMD12 8 4 5 IUU0 6 RES 3UU0-4 +3V3-STANDBY 5 47K 4 2 RES 7UU2-1 PUMD12 1 3 RES 3UU1

RES 7UU1 SI3441BDV RES 2UU2 22n

+VDISP-INT

3UU3-1

1 3UU3-2 IUU3 7

47K RES RES 2UU1 1u0 IUU2

47R IUU1 RES 3UU0-1 8 1 47K

47K RES RES 7UU3 BC847BW

RES 3UU0-2 7 2

3 47K

IUU4 3UU3-3 IUU5 3UU3-4 4 5 6 3 47K RES 2UU0 RES 100n 47K RES

+3V3

VDISP-SWITCH

FUU1 3UU2 4K7 RES

+3V3

LCD-PWR-ONn

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Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 143

10-12 B04 313912365214


Analogue externals A

B04A

Analogue externals A

B04A

IE22 AUDIO-IN1-R 1 2E06 100p

3E07-1 CDS4C12GTA 12V 1K0 8 RES 6E03 1E31 2E88

FE71

AUDIO-IN1-L

FE23 4 2E04

3E07-4 1K0 5 CDS4C12GTA 12V 6E09 1E54 2E91 1n0

100p

1n0

RES

** ** 4E01
RES

1E02-1 MSP-8032SH-01-NI-FE-RF-PBT-BRF RED 1 2 1E02-2 MSP-8032SH-01-NI-FE-RF-PBT-BRF WHITE 3 4

AV1-STATUS

IE18

3E32 AV2-STATUS IE05 3E17 3E44 IE48 AV1-BLK 3E73 IE51 AV2-BLK CVBS-MON-OUT1 3E07-2 2 1K0 3E07-3 3 1K0 6 7 18p

YPBPR1-PB EU 3E74 18R FE73

** 4E02
RES

AV1-B

IE53

5E73 1u8

BEC3

3E75 18R CDS4C12GTA 12V

2E80

2E79

RES 6E23

1E12

2E15

150p

150p

100p

RES

FE74

YPBPR1-SYNCIN1 EU 3E76 18R

** 4E05
AV1-G FE86 2E83 150p 5E74 2E84 150p 1u8 3E77 18R RES 6E26 CDS4C12GTA 12V RES FE80

1E01-3 MSP-8033SH-02-NI-FE-RF-PBT-BRF GREEN 5 6

+3V3

1E18

2E14

RES
YPBPR1-PR EU 3E78 18R BEC5 3E79 2E86 150p 18R

100p

**
FE81 CDS4C12GTA 12V

AV1-R

IE55 2E85 150p

5E76 1u8

4E03 RES

1E01-1 MSP-8033SH-02-NI-FE-RF-PBT-BRF RED 1 2

RES 6E28

1E19

2E12

FE85

RES

GND_A

2E98

100p

4K7

4K7

**

4E04 RES

1E01-2 MSP-8033SH-02-NI-FE-RF-PBT-BRF BLUE 3

+3V3

4K7

4K7

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Circuit Diagrams and PWB Layouts


Analogue externals B

Q552.2L LA

10.

EN 144

B04B

Analogue externals B

B04B
SPDIF out EU
CDS4C12GTA 12V RES 6E40 9E29 IE71 3E87 18R YPBPR1-SYNCIN1 FE72 AV3-Y SPDIF-OUT IE15 RES 5E06 30R RES 2E22 10p RES 1E44 RES 6E46 FE59 CDS4C12GTA 12V RES 1E07 MTJ-032-68B-46-NI-FE 1 2 FE41

YPBPR
2 1E08-1 * MSP-8033SH-05-NI-FE-RF-PBT-BRF 1 2E27 YELLOW 1E43 100p FE54

**

4E20 RES

AP

9E04

3E88 27R

IE73

AV2-CVBS

GND_A
MTJ-032-21B-45 NI FE (PBT) 1E03 2 1

FE51 CDS4C12GTA 12V

EU
RES 6E51

9E57

IE74

3E89 18R

IE75

AV3-PB YPBPR1-PB

2E67

100p

** 4E21

RES

GND_A
MTJ-032-21B-42 NI FE 2 1E04 2E68 100p 1 FE48

1E28

EU
CDS4C12GTA 12V RES 6E52

9E58

IE76

3E90 18R

IE77

AV3-PR YPBPR1-PR

** 4E22

RES

FE42

GND_A

1E39

YPBPR AUDIO
MSP-8033SH-05-NI-FE-RF-PBT-BRF 6 CDS4C12GTA 12V 3E97 FE50 1E29 RES 6E06 2E39 1n0 1K0 2E72 100p IE31 AV3-Y AV1-CVBS

Provision for Dreamcatcher


+3V3 AUDIO-IN3-R 9E15 9E16 RES RES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 RES 1E32

1E08-3 RED

** 4E23
RES

FE43

AV3-PR RXD1-MIPS 3E96 IE29 AUDIO-IN3-L AV3-PB TXD1-MIPS 2E71 100p

9E19 9E12

RES RES

GND_A
4 1E08-2 3 * MSP-8033SH-05-NI-FE-RF-PBT-BRF RES WHITE 4E24

FE49

CDS4C12GTA 12V

1K0

9E17 9E14

RES RES

2E40

1E42

**

RES 6E38

1n0

GND_A

AUDIO-IN3-R AV1-B

9E11 9E18

RES RES

AUDIO-IN3-L AV1-G

9E13 9E20

RES RES

VGA ( OR DVI ) AUDIO


AV1-R 1E09 MSJ-035-69A-B-RF-PBT-BRF 2 3 1 2E36 1n0 1E37 FE02 CDS4C12GTA 12V 3E21 1K0 2E35 100p IE09 AUDIO-IN4-L AV1-STATUS AUDIO-IN1-R AV1-BLK AUDIO-IN1-L 9E24 9E25 9E26 9E28 RES RES RES RES 9E22 RES

V_NOM

RES 6E19

31

FE01 IE10 AUDIO-IN4-R 2E38

DF50-30DP

FE03 CDS4C12GTA 12V

3E20 1K0 100p

V_NOM

+3V3

3E9C

1E10 3150-831-030-H1 2 VCC VIN GND MT 7 6 5 4 1 3 FE44

1R0

RES 6E20

2E37

1n0 1E38

SPDIF-OPT

RES 2E77

RES 6E53

CDS4C12GTA 12V

V_NOM

2E73

100p 1E80

100n

* SOC Cinch V 3P 1L3 YEWHRDY at 1E08 for Brazil ** Provision for ESD
SPB SSB TV550 2K11 4DDR BR SD
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Circuit Diagrams and PWB Layouts


Ethernet & Service

Q552.2L LA

10.

EN 145

B04C

Ethernet & Service


TXD1-MIPS 7 RXD1-MIPS 5E08 +3V3 30R 2E62 10u 2E63 100n 2E66 100n IE07 +3V3-ET-ANA 6

3E53-2 47R 3E53-3 47R

IE49 2 IE50 3 BZX384-C5V1 BZX384-C5V1 4 1

3E53-1 47R 3E53-4 47R

8 FE57

FE56 2 3 1 1E06

6E43

6E44

1E85

1E86

MSJ-035-69A-B-RF-PBT-BRF FE58

UART SERVICE CONNECTOR

B04C

+3V3-ET-ANA +3V3

+3V3

PROVISION FOR iTV


IE32 3E30 IE33 2E52 100n 2E53 2E49 2E48 100n 4n7 10u RES 1E71 TXD RXD 2E54 10p 7E10-1 LAN8710A-EZK 27 12 6 1 +3V3 1 2 3 5 IE38 IE06 1M0 1E70 NX3225GA 25M 10p

10K 10K 10K 10K

3E66 3E67 3E81 3E82

3E33

10K

RES RES RES RES

2E55

CR 5 4 CLKIN 1 XTAL 2 RST

1A 2A VDD

IO

502382-0370 31 30 29 28 20 26 13 IE63 3E64 7 IE64 3E65 3 10K 2 10K 14 32 12K1 1% 3E40 IE39 RXD1-MIPS 3 1 X1 7 9E42 3E72 3E34 3E68 RES 3E35 RES RES 10K 10K +3V3
ETH-INTSEL

RESET-ETHERNETn ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3)

IE26

RES 2E70

10p 19 11 10 9 8

RX

RES 6E48

P N P N

BAS316

ETH-RXP ETH-RXN ETH-TXP ETH-TXN ETH-TXCLK

provision for iTV

RES 2E69

ETH-COL

3E70 RES

3E69 RES 10K

10K 15 RES 3E71 RES 3E80 10K 10K +3V3 21 22 23 24 25 18

RXDV RXER RXD4 0 PHYAD 1 RXCLK REGOFF 1 LED 2 INTSEL CRS RBIAS

ETH-RXDV ETH-RXER

14

RES 3E9D

RES 3E9E

10K

ETH-RXCLK

ETH-TXEN ETH-TXD(0) ETH-TXD(1) ETH-TXD(2)

TXEN 0 1 2 TXD 3 4 INT TXER MDC MDIO

10K

+3V3 RXD-UP
ETH-REGOFF

1 1 X1 7

13 RES 7E12 PDTC144EU RES 7E13 PDTC144EU AV2-BLK

ETH-TXD(3)
ETH-TXER

+3V3 14
ETH-CRS

ETH-MDC ETH-MDIO

17 16 3E51 1K5 +3V3

RES 7E11-2 74HC4066PW 4 5

VSS 33 7E10-2 LAN8710A-EZK 34 35 36 40 41 42

VIA VIA 37 38 39

VIA

TXD-UP

1 1 X1 7

RES 7E11-3 74HC4066PW 8 6

14

TXD1-MIPS

10

1 1 X1 7

RES 7E11-4 74HC4066PW 11 12

+3V3-ET-ANA

+3V3-ET-ANA

CONFIGURATION RESISTOR SETTINGS


49R9 1% 49R9 1% 49R9 1% 49R9 1% 3E22 3E25 3E95 3E99 3E26 22R 3E98 22R

Resistor ETHERNET CONNECTOR


ETH-TXP ETH-TXN FE27 FE28 1E87 3 ACM2012 2 FE60 4 1 FE30 FE61 1E88 3 ACM2012 2 4 1 CDA5C16GTH 16V RES CDA5C16GTH 16V RES CDA5C16GTH 16V RES CDA5C16GTH 16V 6E47-3 6E47-1 6E47-2 6E47-4 9 11 10 12 2E60 22n FE34 8 6 7 5 1N00 1 2 3 4 5 6 7 8

POP

14

EMPTY

3E64 (RES) 3E65 (RES) 3E66 (RES) 3E67 (RES) 3E68 (RES) 3E69 (RES)

PHYADD(0) = 1 PHYADD(1) = 1 PHYADD(2) = 1 RMII mode selected Internal 1.2V reg. disabled MODE(0) = 0 MODE(1) = 0 MODE(2) = 0 INTERRUPT FUNCTION DISABLED ON nINT/TXER/TXD4 SIGNAL

PHYADD(0) = 0 PHYADD(1) = 0 PHYADD(2) = 0 MII mode selected Internal 1.2V reg. enabled MODE(0) = 1 MODE(1) = 1 MODE(2) = 1 INTERRUPT FUNCTION ENABLED ON nINT/TXER/TXD4 SIGNAL

ETH-RXP ETH-RXN

FE29 FE31

5E01

5E03

5E02

5E04

RES 27n

RES 27n

RES 27n

RES 27n

RES

5450-323-183-H3

2E05

2E07

2E08

2E09

RES 15p

RES 15p

RES 15p

RES 15p

2E58

2E56

2E57

15p 3E39

2E59

0 ohm

15p

0 ohm

15p

3E27

3E28

3E29

0 ohm

0 ohm

15p

3E70 (RES) 3E71 (RES)


FE32

RES

RES

RES

RES

RES

RES

RES

RES

ETH-INTSEL ETH-REGOFF

3E72

FE33

10K

COL CRS_DV MODE2

10K RES

100n

0 MODE 1 RMIISEL PHYAD2 RXD<0:3>

TX

TXCLK

+3V3

RES 7E11-1 74HC4066PW 1

2011-05-10 2011-03-09 2010-12-23

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Circuit Diagrams and PWB Layouts


HDMI

Q552.2L LA

10.

EN 146

B04D
1P04 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FEC6 21 23

HDMI
I2C Address
5EC0 2EC0 RES 2EC1 FEC0 2ECV 100n 10u 1u0 FEC3 2EC2 MICOM-VCC33 220u 16V 3ECH 10K 30R

B04D

SII9187B = 0xB2

HDMI CONNECTOR 3
ARX2+ ARX2ARX1+ ARX1ARX0+ ARX0ARXC+ ARXCPCEC-HDMI FEC1 FEC2 FEC4 47K FEC5 20 22 AIN-5V ARX-HOTPLUG ARX-DDC-SCL ARX-DDC-SDA ARX-DDC-SCL ARX-DDC-SDA 1 ARX-HOTPLUG AIN-5V
ARX-DDC-SDA ARX-DDC-SCL

+3V3

FECB

AIN-5V +3V3-HDMI RES 2ECW 100n 2EC7 100n 2EC8 2EC6 100n 10u

FEC7 2EC3

RES 5EC3 100n 30R

+3V3

3EC1-3

47K

7EC1 SII9187B

9 27 64

37 MICOM_VCC33

VCC33 3EC1-1 4 3ECM-4 10R 5 1 3ECN-1 1u0 8 100K 2ECM IE42 31 32 29 30 65 66 67 68 69 70 71 72 35 36 33 34 1 2 3 4 5 6 7 8 41 42 39 40 11 12 13 14 15 16 17 18 45 46 43 44 19 20 21 22 23 24 25 26 (CBUS) HPD0 R0PWR5V DSDA0 DSCL0 N R0XC P N R0X0 P N R0X1 P N R0X2 P (CBUS) HPD1 R1PWR5V DSDA1 DSCL1 N R1XC P N R1X0 P N R1X1 P N R1X2 P (CBUS) HPD2 R2PWR5V DSDA2 DSCL2 N R2XC P N R2X0 P N R2X1 P N R2X2 P (CBUS) HPD3 R3PWR5V DSDA3 DSCL3 N R3XC P N R3X0 P N R3X1 P N R3X2 P

SBVCC33

38

+5V-EDID 8 3ECP-1 10K 3ECP-3 1 3 6 10K

R4PWR5V DSCL4 DSDA4 CEC_D

49 48 47 51

1P03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FECG 21 23

HDMI CONNECTOR 2
BRX2+ BRX2BRX1+ BRX1BRX0+ BRX0BRXC+

AIN-5V

ARXCARXC+ ARX0ARX0+ ARX1ARX1+

VGA-SCL-EDID-HDMI VGA-SDA-EDID-HDMI 9EC2 RES CEC-HDMI

BIN-5V BRX-HOTPLUG BIN-5V BRX-DDC-SDA BRX-DDC-SCL 3 3ECM-3 10R 6 2 3ECN-2 1u0

ARX2ARX2+ 7 100K 2ECN IE43

TX2

N P N P N P N P

57 56 59 58 61 60 63 62 3ECJ RES

HDMIA-RX2HDMIA-RX2+ HDMIA-RX1HDMIA-RX1+ HDMIA-RX0HDMIA-RX0+ HDMIA-RXCHDMIA-RXC+ RES 3ECK 4K7 9EC3 RES PCEC-HDMI 3ECL RES 4K7 MICOM-VCC33

3ECA-2

47K

BRXCPCEC-HDMI FECC FECD FECE FECF 20 22 BIN-5V BRX-DDC-SCL BRX-DDC-SDA BRX-DDC-SCL BRX-DDC-SDA

TX1

BRXCBRXC+ 8 3ECA-1 BRX0BRX0+ BRX1BRX1+ BRX2BRX2+ CRX-HOTPLUG CIN-5V 2 3ECM-2 10R 7 3 3ECN-3 1u0 6 100K 2ECP IE44

TX0

TXC

47K

BRX-HOTPLUG

TPWR_CI2CA

55 IE12 FECR

4K7

CEC_A

50

BIN-5V

HDMI CONNECTOR 1
1P02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 23 CRX2+ CRX2CRX1+ CRX1CRX0+ CRX0CRXC+ CRXCPCEC-HDMI ARC-eHDMI+ CRX-DDC-SCL CRX-DDC-SDA 47K CIN-5V CRX-DDC-SDA CRX-DDC-SCL

INT

52

FECY

+3V3

CRXCCRXC+ CRX0CRX0+ CRX1CRX1+ CRX2CRX2+ DRX-HOTPLUG 6 DIN-5V DRX-DDC-SDA DRX-DDC-SCL eHDMI+ 5EC2 30R CIN-5V ARC-eHDMI+ 2ECC 1 3ECM-1 10R 8 4 3ECN-4 1u0 5 100K 2ECQ IE45

CSCL CSDA

54 53

3EC3 3EC5

100R 100R

SCL-SSB SDA-SSB

RES 2ECX

FECJ FECA FECK FECL FECM FECN 20 22 RES 7E02 BC847BW CIN-5V

CRX-DDC-SCL CRX-DDC-SDA 3ECA-3

3ECA-4

FECP

47K

CRX-HOTPLUG 3E23 22K RES +3V3-STANDBY

DRXCDRXC+ DRX0DRX0+ 10p DRX1DRX1+ DRX2DRX2+

VIA

PCEC-HDMI

3ECD 100R IEC4

7EC0 BC847BW IEC5

IEC6 9EC0 CEC-HDMI

74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

EPAD IEC7 22K FECW +3V3-STANDBY 73

3ECE

6EC1 +5V BAT54 IE11 4R7 IE65 2 3ECU-2 10K 2ECU 1u0 DDCA-SCL IE66 4 3ECU-4 5 10K 7 +3V3 +5V-VGA

10p

RSVDL

10p RES 2ECY

10 28

7EC1 NON-INSTAPORT INSTAPORT 9187B 9287B

3ECN 4X 100K 4X 100K

3ECF 100K 100K BLOCKBUSTER SUNDANCE

3ECG 3ECF 100K

DDCA-SDA

FECZ

2011-05-10 2011-03-09 2010-12-23

+5V-EDID

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Circuit Diagrams and PWB Layouts


Headphone

Q552.2L LA

10.

EN 147

B04E

Headphone

B04E

+3V3-STANDBY

4 PUMD12 7EE0-2 A-PLOP 3

6 FEE0 RESET-AUDIO 2 7EE0-1 PUMD12 1

A-STBY

2EE0 47p 3EE1-1 22K 4 3EE1-4 22K 2EE5 47p +3V3 5

8 7 3EE1-2 3EE1-3 3 22K 6 22K

2EE1

7EE1 TPA6111A2DGN

100n

IEE0 ADAC(3) IEE2 ADAC(4)

2EE3 1u0

IEE1 2EE4 1u0

3EE0-1 10K

IEE3 1 5 3EE0-4 10K 4 IEE4 2EE2 1u0 IEE6 IEE5 2 6 5 3 1 2

AMPLIFIER
INVO

3 2EE6 4V 100u 7 10 11 2EE7 4V 100u 1 IEE8 2 IEE7

VDD 1 1 4

3EE2-3 33R 3EE2-4 33R 3EE2-2 33R 3EE2-1 33R

6 FE36 5 AMP1

FE35 7 AMP2

SHUTDOWN BYPASS 4

VIA GND GND_HS 9

A-PLOP

3 3EE0-3 6 RES 3EE3 22K 10K

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Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 148

10-13 B05 313912365214


DDR

B05A

DDR

+1V8

DDR2-VREF-DDR

+1V8

DDR2-VREF-DDR

B05A

2B40

47u 2B00

100n 2B02

100n 2B03

100n 2B05

100n 2B01

100n 2B04

100n 2B06

100n 2B07

100n

2B36 100p 2B08 100n

100n 2B13

47u 2B09

100n 2B10

100n 2B14

2B41

100n 2B11

100n 2B12

100n 2B15

100n 2B16

A1 E9 L1 H9

A9 C1 C3 C7 C9 VDDQ

E1

AT T-POINT
3B22 240R DDR2-CLK_N 3B27 240R DDR2-CLK_N 3B28 240R DDR2-CLK_P DDR2-CLK_N DDR2-CLK_P DDR2-CLK_P

DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-BA0 DDR2-BA1
DDR2-BA2

H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1 3B01 RES 240R F9 E8 F8 F2 G8 F7 G7 F3 B3

VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13 0 1 BA 2 ODT CK CKE CS RAS CAS WE DM|RDQS VSS A3 E3 J1 K9

VDDL

VDDQ

VREF 3B00-2 DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-BA0 DDR2-BA1
DDR2-BA2

SDRAM
DQ

0 1 2 3 4 5 6 7

C8 3 C2 D7 1 D3 D1 D93B00-4 4 B1 B9 3B00-11

2 6 3B02-3 33R 3 8 3B02-1 33R 2 3B02-2 5 333 B02-4 R 4 8 33R

7 33R 6 3B00-3 33R 7 33R 5 33R

DDR2-D16 DDR2-D17 DDR2-D18 DDR2-D19 DDR2-D20 DDR2-D21 DDR2-D22 DDR2-D23

DQS

B7 A8 2B44 RES

3B13 2p2 33R

3B12 33R

DDR2-DQS2_P DDR2-DQS2_N

H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1 3B03 RES 240R F9 E8 F8 F2 G8 F7 G7 F3 B3

VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13 0 1 BA 2 ODT CK CKE CS RAS CAS WE DM|RDQS VSS A3 E3 J1 K9

VDDL

VREF 3B04-2 2 7 6 33R 6 33R 7 3B05-2 33R 33R 2 1 8 3B05-1 33R 5 5 3B05-4 33R 4 8 33R 33R 3B14 33R 33R

SDRAM
DQ

E2

7B02 EDE1108AGBG-1J-F

A1 E9 L1 H9

A9 C1 C3 C7 C9

E1

E2

7B03 EDE1108AGBG-1J-F

100n

2B17 100n 2B37 100p

0 1 2 3 4 5 6 7

C8 3B05-3 C2 D7 3B04-3 D3 D1 D93B04-4 B1 B93B04-1

3 3

4 1

DDR2-D24 DDR2-D25 DDR2-D26 DDR2-D27 DDR2-D28 DDR2-D29 DDR2-D30 DDR2-D31

DQS

B7 A8 2B45

NU|RDQS

A2

3B15 RES 2p2

DDR2-DQS3_P DDR2-DQS3_N

DDR2-ODT DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM2

NU|RDQS

A2

DDR2-ODT DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM3

NC

L3 L7

DDR2-A14

NC

L3 L7

DDR2-A14

3B23 33R

VSSDL E7

VSSQ A7 B2 B8 D2 D8

3B24 33R

VSSDL E7

VSSQ A7 B2 B8 D2 D8 DDR2-VREF-DDR

+1V8

+1V8

DDR2-VREF-DDR

2B42

100n 2B22

100n 2B23

100n 2B24

100n 2B19

100n 2B20

100n 2B21

47u 2B18

100n 2B25

100n

2B26 100n 2B38 100p

47u 2B27

2B43

100n 2B29

100n 2B28

100n 2B31

100n 2B30

100n 2B32

100n 2B33

100n 2B34

A1 E9 L1 H9

A9 C1 C3 C7 C9 VDDQ

E1

DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-BA0 DDR2-BA1
DDR2-BA2

H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1 3B06 RES 240R F9 E8 F8 F2 G8 F7 G7 F3 B3

VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13 0 1 BA 2 ODT CK CKE CS RAS CAS WE DM|RDQS VSS A3 E3 J1 K9

VDDL

VDDQ

VREF 3B07-2 DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-BA0 DDR2-BA1
DDR2-BA2

SDRAM
DQ

0 1 2 3 4 5 6 7

C8 C23B08-4 4 D7 D3 3B08-2 2 D1 D9 3B07-4 4 B1 B9 3B07-1 1

2 5 33R 7 33R 5 33R 8 33R 3 1 3

7 33R 6 3B07-3 33R 8 3B08-1 33R 6 3B08-3 33R

DDR2-D0 DDR2-D1 DDR2-D3 DDR2-D2 DDR2-D4 DDR2-D5 DDR2-D6 DDR2-D7

DQS

B7 A8 2B46

3B17 RES 2p2

3B16 33R 33R

DDR2-DQS0_P DDR2-DQS0_N

H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1 3B09 RES 240R F9 E8 F8 F2 G8 F7 G7 F3 B3

VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13 0 1 BA 2 ODT CK CKE CS RAS CAS WE DM|RDQS VSS A3 E3 J1 K9

VDDL

VREF 2 3B10-2 7 33R 7 3B11-2 8 33R 33R 5 3B11-4 33R

SDRAM
DQ

E2

7B00 EDE1108AGBG-1J-F

A1 E9 L1 H9

A9 C1 C3 C7 C9

E1

E2

7B01 EDE1108AGBG-1J-F

100n

2B35 100n 2B39 100p

0 1 2 3 4 5 6 7

C8 C2 3B11-3 3 D7 3B10-3 33R 3 D3 D1 D93B10-4 4 B1 B9 3B10-1 1

6 6 33R

2 1 5 3B11-1 33R 4 8 33R

DDR2-D8 DDR2-D14 DDR2-D10 DDR2-D11 DDR2-D12 DDR2-D13 DDR2-D9 DDR2-D15

DQS

B7 A8 2B47

NU|RDQS

A2

3B19 RES 2p2

3B18 33R 33R

DDR2-DQS1_P DDR2-DQS1_N

+1V8

DDR2-ODT DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM0

NU|RDQS

A2

DDR2-ODT DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM1

180R 1%

3B20

NC

L3 L7

DDR2-A14

NC

L3 L7

DDR2-A14

3B25 33R

FB00 DDR2-VREF-DDR 180R 1%

VSSDL E7

VSSQ A7 B2 B8 D2 D8

3B26 33R

VSSDL E7

VSSQ A7 B2 B8 D2 D8

3B21

1X20 HOOK1

1X21 HOOK1

1X22 HOOK1

1X23 HOOK1

1X24 HOOK1

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Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 149

10-14 B06 313912365214


Display interfacing-Vdisp

B06A

Display interfacing-Vdisp

B06A

1G03 T 3.0A 32V

5G01 +VDISP-INT 30R RES 5G02 30R RES 2G44 22u RES

1G00 2G43 100n T 3.0A 32V RES

FG0H

+VDISP

RES 3G28 2K2

IG11

RES 6G00 LTST-C190KGKT

For Development use only

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Circuit Diagrams and PWB Layouts


Video out - LVDS

Q552.2L LA

10.

EN 150

B06B

Video out - LVDS

B06B
+3V3

10K

+VDISP
RES

10K

10K

47p

47p

47p

47p

47p

47p

47p

47p 2G26

2G7A

2G77

2G79

2G75

2G24

47p

2G76

2G78

2G25

RES 3G33

RES 3G34

RES 3G35

2G27

47p

FI-RE51S-HF 60 61 58 59 56 57 54 55 52 53

4 3 2 1

9G0K-4 9G0K-3 9G0K-2 9G0K-1

5 6 7 8

2G92 2G93 2G94 2G95

100n 100n 100n 100n FG2J FG30 FG31 FG32 FG33

CTRL-DISP

FI-RE41S-HF 51 50 48 49 46 47 44 45 42 43 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1G50

SDA-DISP SCL-DISP

RES 3G32 3G2W 3G2Y RES 3G38 RES 3G37 RES 3G2Z FG04 RES 3G30 RES 3G31 RES 3G36

100R 100R 100R 100R 100R 100R 100R 100R 100R

FG34 FG2H FG2G FG35 FG2R FG2K FG2L FG2M FG2E FG2F FG1Y FG1Z FG20 FG21 FG22 FG23 FG24 FG25 FG26 FG27 2G28 2G29 10p 10p

CTRL-DISP

BACKLIGHT-BOOST 3D-LR CTRL-DISP CTRL-DISP 3D-VS-DISP


PX1APX1A+ PX1BPX1B+ PX1CPX1C+ PX1CLKPX1CLK+ PX1DPX1D+ PX1EPX1E+

2G96 2G99 2G97 2G98


PX3APX3A+ PX3BPX3B+ PX3CPX3C+ PX3CLKPX3CLK+ PX3DPX3D+ PX3EPX3E+

47p 47p 47p 47p FG1C FG1D FG1E FG1F FG1G FG1H FG11 FG1J FG1K FG1L FG1M FG1N

PX4APX4A+ PX4BPX4B+ PX4CPX4C+ PX4CLKPX4CLK+ PX4DPX4D+ PX4EPX4E+

FG12 FG13 FG14 FG15 FG16 FG17 FG18 FG19 FG1A FG1B FG1Q FG1P

PX2APX2A+ PX2BPX2B+ PX2CPX2C+ PX2CLKPX2CLK+ PX2DPX2D+ PX2EPX2E+

FG28 FG29 FG2A FG2B FG2C FG2D FG1R FG1S FG1T FG1U FG1W FG1V FG2P 2G91 100n

+VDISP

RES 9G0G

FG2N

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

TO DISPLAY

1G51

TO DISPLAY
1X05 REF EMC HOLE

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Circuit Diagrams and PWB Layouts


AmbiLight CPLD

Q552.2L LA

10.

EN 151

B06C
5GA0 +3V3 30R

AmbiLight CPLD

B06C
FGA0 VINT 100n

2GA0

2GA1

100n 2GA2

1u0

DEBUG ONLY

5GA1 +3V3 30R 2GA3 2GA5 100n 1u0

FGA1 VIO +3V3

RES 1G37 3GA4 10K RES +3V3 1 2 3 4 5 6 SD51022

2GA6

GCK3 GTS1 GTS2 GSR


10p RES

3GA5-4 3GA5-3 3GA5-2 3GA5-1

4 3 2 1

5 6 7 8

100R 100R 100R 100R

RES RES RES RES

VINT

VIO

7GA0 XC9572XL-10VQG44C0100 PXCLK54 GCK2 GCK3 43 44 1 2 3 39 40 41 42 36 34 33 29 30 31 32 37 38 11 9 24 10

15 35

VCCINT IXO1_43|GCK1 IXO1_44|GCK2 IXO1_1|GCK3 IXO1_2 IXO1_3 IXO1_39 IXO1_40 IXO1_41 IXO1_42 IXO2_36|GTS1 IXO2_34|GTS2 IXO2_33|GSR IXO2_29 IXO2_30 IXO2_31 IXO2_32 IXO2_37 IXO2_38 TCK TDI TDO TMS GND 4 17 25

VCCIO

26

AMBI-SPI-CLK-OUT-R AMBI-SPI-SDI-OUT_G1-R AMBI-SPI-SDO-OUT-R

IGA1 CPLED2 IGA2 CPLED3

PNX-SPI-CS-BLn PNX-SPI-SDO PNX-SPI-SDI PNX-SPI-CLK

3GA3

33R

GTS1 GTS2 GSR AMBI-SPI-CS-OUTn_R2-R AMBI-PWM-CLK_B2 AMBI-SPI-CS-OUTn_R2 AMBI-LATCH1_G2 AMBI-TEMP CPLED3 CPLED2

IXO3_5 IXO3_6 IXO3_7 IXO3_8 IXO3_12 IXO3_13 IXO3_14 IXO3_16 IXO3_18 IXO4_19 IXO4_20 IXO4_21 IXO4_22 IXO4_23 IXO4_27 IXO4_28

5 6 7 8 12 13 14 16 18 19 20 21 22 23 27 28

9GA1 RES

3GA1

RES 47R 5 33R 3 7 3G10-3 33R 3G13 1 10R 5 3G10-1 33R

PNX-SPI-CSBn BACKLIGHT-PWM 3D-LR 3D-VS-DISP BL-SPI-SDO BL-SPI-SDI BL-SPI-CSn BACKLIGHT-PWM_BL-VS BL-SPI-CLK AMBI-PROG_B1 AMBI-BLANK_R1 AMBI-SPI-CS-EXTLAMPSn AMBI-SPI-CLK-OUT AMBI-SPI-SDI-OUT_G1 AMBI-SPI-SDO-OUT AMBI-LATCH2_DIS

IGA3 GCK2 +3V3 3 GCK3 5 RES 7GA1-2 BC847BS(COL) 4

8 3G11-1

3G14 1 6 33R 3G11-3

33R 3 33R

4 3G10-4 2 3G10-2 3G12 4 3G11-4

+3V3 6 GTS1 2 RES 7GA1-1 BC847BS(COL) 1

6 33R 33R 8 33R

+3V3 3 2G13 10p 2G16 10p 2G18 10p 2G15 10p 2G17 10p 2G14 10p 2G19 10p GTS2 5 RES 7GA2-2 BC847BS(COL) 4

2G10

10p 2G11

10p 2G12

10K

3G15 +3V3

10p

+3V3 6 GSR 2 RES 7GA2-1 BC847BS(COL) 1 7 330R 2 6 330R 3 LTST-C190KGKT 8 330R 1 5 330R 4 RES 3GA6-2 RES 3GA6-1 RES 3GA6-4 RES 3GA6-3 RES 6GA3

DEBUG ONLY
RES 1G35 1 2 3 4 5 6 7 8 2GA4 RES 3GA2-1 RES 3GA2-2 RES 3GA2-3 RES 3GA2-4 1 2 3 4 8 7 6 5 100R 100R 100R 100R RES 1G36 1 2 3 4 5 6 FGA6 FGA4 FGA5 FGA3 FGA2

LTST-C190KGKT

LTST-C190KGKT

100n RES

+3V3

SD51022

BACKLIGHT-PWM

9GA0

BACKLIGHT-PWM_BL-VS

LTST-C190KGKT

RES 6GA0

RES 6GA1

RES 6GA2

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Circuit Diagrams and PWB Layouts


SPI buffer

Q552.2L LA

10.

EN 152

B06D

SPI buffer

B06D

RES
+3V3 +3V3

RES 2GE0

100n

RES 7GE1 PDTC114EU

RES 3GE2 RES 7GE0 74LVC245A 1 19 2 2 3 4 5 6 7 8 9 IGE0 3 3GE0-3 47R 3GE1-3 6 3 RES 47R 3GE3 47R 47R

10K

20

PNX-SPI-CSBn

3EN1 3EN2 G3 PNX-SPI-CLK 18 17 16 15 14 13 12 11 10 1

6 RES 1 5 RES 3GE0-1 8 RES 47R 4 3GE1-4 47R RES

BL-SPI-CLK BL-SPI-SDO AMBI-SPI-CLK-OUT-R AMBI-SPI-SDO-OUT-R PNX-SPI-SDI

PNX-SPI-SDO AMBI-SPI-SDI-OUT_G1-R BL-SPI-SDI

3GE4 RES

PNX-SPI-CLK

RES 9GE0-1

BL-SPI-CLK

PNX-SPI-SDO

RES 9GE0-2

BL-SPI-SDO

BL-SPI-SDI

RES 9GE1 RES 9GE2 RES 5 9GE0-4

PNX-SPI-SDI

PNX-SPI-CS-BLn

IGE1

* **

BL-SPI-CSn

* **

Buffer Direct

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Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 153

10-15 B09 313912365214


Connectors comp

B09A

Connectors comp
5C55 30R FC67 1M59 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 3C74 100K RES +3V3

B09A
FC70 FC71 FC72 FC73 V-AMBI FC74 FC75 V-AMBI FC76 FC78 3C70 100R FC79 FC81 2C70 100n FC77

AMBI-SPI-CLK-OUT AMBI-SPI-SDO-OUT AMBI-SPI-SDI-OUT_G1 AMBI-PWM-CLK_B2 AMBI-SPI-CS-OUTn_R2 AMBI-LATCH1_G2 AMBI-BLANK_R1 AMBI-PROG_B1 AMBI-LATCH2_DIS AMBI-TEMP

2C76 FC87 LIGHT-SENSOR 2C93 RC 47n RES IC73 LED-2 IC74 3C75 100R 3C76 100R 3C77 100R +3V3-STANDBY 2C79 LED-1 IC75 3C78 100R 100p 2C80 100p 28 KEYBOARD FC95 3C79 BZX384-C5V6 BZX384-C5V6 100p 2C82 6C03 RES 10R RES FC93 FC94 +5V 2C81 100n 100p 2C77

6C02

2C78 100p

RES BZX384-C5V6

FC88 FC89 FC90 FC91 FC92

1M19 1 2 3 4 5 6 7 8

GND_AL

*
FC83 +24V T 2.0A 63V 1C86 AMBI-POWER

FC82

FC84 +12V_AL

* 1C87
T 2.0A 63V

2C94

2C95

100n

100n RES

2C96 100n RES GND_AL GND_AL

Option table for Ambilight BLOCKBUSTER N N EMMY Y N SUNDANCE / INFINITY N Y


SCL-SET C90 * RES 310K SDA-SET C91 * RES 3 100R RES 3C80 100R RES3C81 100R RES 3C82 100R RES 3C83 100R FAN-CTRL2 FC64 RES 1M71 FC97 1 2 3 4 9C00 RES 9C01 RES 3C94 3C95

+3V3-STANDBY +T 1 2 3 4 +5V 47R RES RES 47R +T 0R3 FC65 FC66 0R3 9C02-1 9C02-2 9C02-3 9C02-4 3C97 8 7 6 5

ITEMS 1C86 1C87

FAN-CTRL1

+3V3 FC61

iTV

FH52-11S-0.5SH 2C86 RES 10p 2C87 RES

TACH01

FC62

2C90

1u0 2C91

10p

SCL-BL TACH02

FC85 FC63

FC96 FC98

100p RES 2C84

RES 2C83

100p

SDA-BL

FC86

2041145-4

* RES 3C92 * RES 3C93


10K RES 5C54 +3V3 30R T 1.0A 63V RES 1C85 100R

TEMPERATURE SENSOR
FC99 RES 2C85

+3V3 FAN-DRV

**

Option table for Leading Edge BlockBuster / Emmy Yes No Sundance / Infinity No Yes

Items 1M19 1M20

RES 5C53 +12V 30R

1u0

IC78

RESERVED
SPB SSB TV550 2K11 4DDR BR SD
3139 123 6521

**

**

1u0

2011-Jul-15 back to

div. table

**

RES 3C96

6C05

FH34SRJ-26S-0.5SH(50)

1M20

1 2 3 4 5 6 7 8 9 10 11 12

**

100p

TO LED PANEL

4 3 2

2011-05-10 2011-03-09 2010-12-23

19112_040_110628.eps 110628

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 154

10-16 313912365214 SSB Layout


Overview top side

1M95
2U46 3U64 2U58 3U65 2U44 2U45 2U49 3U45 2U53 4U01 4U00 3U43 3U81 2U48 3U76 2U72 3U84 3U71 2U54 2U68 2U47 3U42

1M99
2U51 2U52 2U43 2U50 3U44 3U67 3U66 3U56 2U56 5U02

1F24 1M71
1C85
2C84 3C83 2G16 3G13 3G12

1M59
3G10

3US6 3US9

2C95

2C85

3C93

2C83

3C91

5C53

3C80

1UM0

3C90

2C70

2U24

2U23

2U25

2U19

2U20

5U03

3GA1

9GA0

IUT1

2C94

5C54

3G11
3C70 2C96

1C86 1C87

3G14

3C92

3C82

3C81

5C55

6GA3

6GA0

IU15

2U17

2U18

IUS9

7US3

7US2

5UM1 3US2

IUS5
3US3

3US7

3U23

7GA2

7U01 7U04 7U02


IU18

IUS4

3US5 IUS6

2US3

IU23

IUS3

3 US 4

IUT2

7US1

6GA1

9US0

3GA6

1G37
3GA5

6U00

2U11 2U09

3U24 IU17

5U00

7GA0
2UB2 2UB1

6GA2

7GA1

2U16

2U15

1G36
3GA2

1G50

3B11

2UE8

5U01
2S4P

3B26

7B01
2G98 2G97 2G99 2G96

2UB0 2B47 3B18 3B19

7UA4

2UE6

7UA3
2UB4 2UB3 3UB4 3UB5 3UB1

IGA3 IGA2 IGA1

1G35
2GA4

3UB0

3UB3

3UB2

2UE3 2UE2

2D19

2D05

3B07

7B00

2UE0
3UD4 3B16 3UD5 3B17 2UE1 3UD3 2U28 3U07

IUD1

5D08

3B25

7UD1
IUD2

IUD4

5UD2

2UD8 2UD9
5UD3

2UE9

7U05

3F11

9S00

3F08

3U06 2U27

2D20

3S3Y

6UD0
IUD0

3F10

3F09

3S28

3S29

3B02

3S3Q

3S62 3S21 3S3S

3S23

3S24

2UD0
2UD3 3UD2 2UD7

9F28

7B02
2D07

2S4E 3B23 3B12 3B13

3S1K

3S1J
3S3R 3S2A 3S3T 3S3N

3S1B 3UD1 2S4D 3S1L 3UD0

2B44

9F27
3S1C 3S3L

2UD1 2UD2
5UD0

5D07

3B00

1D50

3B05

3S6K

1735 1D38

2D17

IF62
3S81 3S6N 3S80 2S4F 3S3F BS15 DS50 2S4G 3S54 3S50 3S52

2D08

2D24

2D23

3B24

2S2W

2S2Z

2S33

2S30

3S27

2D09

2S2R
2S2T

IS13 2S34
4S14

3E17

3S3W

3S42

7D10
2D10 2D06

3B04

3S3G
3S2M

7S00

1D52

3S3H

3S00

3S3U

9S06

3S44

7B03

2B45

3B15 3B14

1S02

3S43

3S3M

DBS8

3S6H

2UD5

2S2V

2S32

7S08

2S31

2S2Y

3S26

3S6J

2S7K

2S7H

2S7R

2S7E

2S7M

BS10

3S4J 2S7J

2S77 2S8G 2S7U 2S7N 2S87 2S78

2S2S

2F40
3S84 3S83

2S7P

3S4L

3S4K

9S21

9S19

2S7L

3S4R

3S4P

3S4T

9S20

3S53

3S13 3S12
BS13

2S41

9S18

3S59

2D12 2D11

5D02 5D01

2S4M
9E20 9E18

1F10

7F58

2F58

3F59 3F60

IF61

2UD4

7UD0

5UD1

1P09

2UD6
9FLH 9FLC 9FLD

7F20

3B10

9S90

9S91

9S92

2B46

3B08

9S93

2UE4

9FLJ

3F58

9E24 4E03

1E06 1E71

5D04

3E32

4E02

1F75
6F72
3F78 2F92 2F94 2F90 3F71

9E22

7F70
2F91 3F72

3FLE

1FL5
2FL6 2FL7

1E31 1E19 1E86

IF89

5F70

1G51

1E54

1E12

1E18

1P08
7FL5
9FLG

5D05

2G29 2G28

9F00 9F01

9F05 9F06

1E02
3E97

2F9D

3FL7

9F04
2F9C

9FLE

2E48

3E66

3E69

3E70

3E80

9E42

3E71

2E49

3E64

3E67

3E65

2F93

4E04

4E05

3E87 3E88 9E29 9E04

4E01

2G7A 2G79

2E53 2G24 2E52 9E11 2E72 2G25 2G26 3G38 3E33 2G78 2G27 2G76 2G75

5F72

6E06

3E96

6E38

4E22

3E51

1E70

2E27

3F64

3F65

2E35

2E54 3E21

2E38

6E19

IE10
2E37 3E20

2F86 3F75

7E10
IE07
3E40 2E66

2F9A

2G77

3E34 3E35

3E68

2F99

1E29

3E72 3C74

6FD3

3C75

2E63

1M19

2E62

6FD2

3E28 2E05

1E28

2C77

3C76

2C93

1E39

2E07

5E02

5E01

IE11

1M20

1E88

1E87

2C80 2C78

3C78 3C77

IC75

3C96

6E51

2C82

3C79

IC74

2EE6

3EC3 2E67 3EC5

3ECF

6C03 6C05
2C91 2C90 3C94 2C86 2C87 3C95

6E47

3E27

5E08

3E98

2E60

3E26

9E15

6EC1

2ECU 3ECP

2F98

1T01
2E73 3E9C

1FD2

3ECG

4E21

9C02

9E57

9E17

3E89

3EE3

3ECN IE42

3C97

2EE4

IEE5

2EE3

IEE4

IEE6 2EE2

1329
2F60 2F97 2F81
2E77

4E20

1F52
3F62 3F63 6FC7 6FC5
3FC4

4E24

2FDC

3FDG

6C02

2E57

2E56

7EE0

1E38

1FD3

2FDD

3E25 3E22

6E20

2C76

1E08

1E42

1E43

1E03 1E04
2EC1
9EC3 5EC2

1328

1E09

1E37

3FL2

2E55 3E30

2E39

1E32

2F88

3FL4

IE09

9F71

6E40

4E23

1F51

2F9B

9FL3

3F34

9FLL

3FLC

9FLK

1P07

9E13

2E71

2E40

2E36

2EE0

3EE1

2E22

2C81

5E06

2EE5

2EE7
6E46 3EE2

7EE1
2EE1

7EC1
2ECC

3EE0

2ECP

2ECN 2ECM

1P05

3ECM

6FC3 6FC4

3U68

6E53 1E80

3FC3

IEE3

3U70

7U43
9U42 9U41 3U41

1E44
3FC7 9FC5 3FC6 3FC5 9FC3 9FC6 2FC3 2FC5

6FC2 6FC1 6FC6

3U69 3U75

3U53 3U59 3U74

1E10

1E07

1P04

1P03

1P02

1FC5

1E05
4 2011-05-10

1FC1

7U42

1N00

2FC4

2FC2

2FC1

2FC6

3FC1

2FC7 3FC2 9FC4

6FC8
2FC8

1FC6

1FC3 1FC4 1FC2

9FLF

1E01

1E85 IF86

5F73

SSB Layout Top

3139 123 6521


19112_041_110628.eps 110628

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts


Overview bottom side

Q552.2L LA

10.

EN 155

CXXX

FC81 FC67

FC96

3FLJ
FL38

FC78 FC82 FC79

FC71

9FL1
FC99 2G11 2G18 2G10 2G17 FC73

9FL2

2G13

2G14

FC76

FC77 2G19 2G15

FC75 FC97 FC70 FC72 FC74 FC64 FC62 FUM0 FC61 FC63 FC98 2G12

CU00

FU48

FU50

FU49

FU54

FU77

FU63

FU75

FU56

FU57

3U01

3U00

FU74

FU68

FU09

FU08

FU58

FU59

FU60

FU61

IU56

IC78

FU66

FU67

FU51

FU52

FU53

FU55

FU62

FU76

FC84 FC83

3UU0
IU55 FS2W FS2Y

3U22

2U07

FU07

3U10

3U08

3U72

2U57 2U03

6U40
IU51

1U40
IU22 IU49 IU48

2U06 FU01

IU03

IU20

3U17 IU06 3U27 IU13

7UU2

3U18

2U08

3U09

3U19

IU04

IUU3

FUU1 3UU2

7U40

7U00
IU05 IU24 3U04 2U21 2U01 IU11 3U11 IU16 3U28

IU08

2GA2

3GE1

3GE0
FGA5

2U02 IU07

IUM0 IUS7

7UU3
3UU3

IUU0

IUU4

2U22

IUS8

2U55 IU63 3U73

7GE0

2GA3

2GA5

3U62

FUS0 2UA4 IU50

5GA1

IU62

FU73 3U80

FU02

9GE0
9GA1 9GE2 IGE1 IS17

FGA1

FU72

FU06 IU09 FU04 IU14 IU25 2U05 FU00 3U02 3U20 IU01 CU02 IU19 2U10 2U29 3U21

7UU1

IU10

7U03
IU02

3U05

3U14

3GA4

2GA6

3UU1 IUU1 2UU1 FG2J 2UU0

IU12 FU05

IUU5

FUD2

7U41

IUU2

3U60
IU61

2GE0

3U26

FGA0

FUA3

7UC0
IUA5 CUA0

FG1P

FG1Q

5GA0

3G15

3U63 3U82

IU52 IU57 IU64

2U04
IU21 CU04 CU01

2U00

2GA0

3U03 CU05

3U61

7UU0
FG17 2B39

FG1B

3U29

CU03

FG1A

FG19

FG18 FG16

3GA3

3GE4

6UD1

7GE1
FGA2 FGA3 FGA4 FGA6 IS40

9GE1 3GE3

3GE2

2GA1 FUA4

7U48

3U83
IUD5 IU41 2U71

2U13 2U12
FU03

7UD3

IGE0

2UU2
FB00 2B34

FUU0

9UU1 9UU0

2B43
2B32 2B27 2B33 9S95 9S94

FG15

FG14

IU40

FG13

FG12

2UE5

1G00

1G03

7UD2
2UE7

2U14
3S66 3S68 FC86 FS31

2G44
5G01 5G02

2B35

FG1N

FG1M

FG1K

FG1L

IUA6 2B29

FG11

FG1J

6G00
FG1H IG11 FG1E FG1F FG1G

IUB0 IF08

2B28

IF04

7S01

3F21

9S10

3F23
IF21 IF23

9S11 3S65

2S12

IS08

2B31

2G43

3G28

3F24

FC85

2B30

3B09

FG33 FG1C FG0H 2G92 2G93 2G94 FG32 FG1D

9S97

9S13

FF08

3F22

3F12 2F21

9S12 IS09

3U16

3U15 3F20

IF22

2B42
2B25 3S06 2B24 FS01

3B27 2G95 2B22 2B23 2B38 FG30

3F19

9C01 9C00

3S6B 3S6C IS00

2S89

3S58 3S5W

9G0K

3S67

9S96

2F20

FG31

FL31

IF87 3S61

9S08 2S4N

2S25

2S61

2B19

2B21

3S60 IF88 IU30 FUD3 3S6E 3S5Z 3S6D IU29 IU28 3S5Y FF07 3S57 3S2G IUB3 3S6A 3S6W 3S6V 3S69 3S2F 3S56 3S6F

3S15

3B06 2B18

IS26 5S88 2S63

7U06

2S6P

3U25

IS25 5S85 3S1W

2S5M

IS3K

2S62

2S5H

2S64

2S4W 2S4Y

2S5P

2S57

5S94

2S4S

2S26

2S67

3B20

3S6G

3S07

2S17

2S66 3S1V

2B20

2B26

3B21

2S5J

3S1X

2S6F

2S60

7UA0
FUA0 3UA0

IU27 FF09 3S1E

FF05

IS3Q 5S80

3B22 5S93

5S92

IS58

5S89

2S5A

2S5G
5S87

3S6P

2S27

3S30 3S33

3D01

5S83

2S21

3S6Q

3F07

FF06

2D03

ID35

7D11
ID34

5S81

3UB7 3UB6 2S5D


2S6M 3S1R 3S1U 3S1S 3S1T

2S23

2S58

2S28

2UB8

3S82 IS04

5S82

IS3S

2S59

2S5K
5S95 5S90

2S6E 2B10 2B16 2B14 2S6D 2S65 2S68 3S0V IS42

3D15

2S5C

IUB4 IUB2

IUD3

2S6L

2S43

ID12

2S6H

2S6K

3D09

5S04

2S53

IUB5

2S55

2S56

IS10

3D16

7UA7
IU26 3U12

2B37 2B15 3S20 2S24 2B17 FS02 2B13 2B12 2B11 ID14 3B01 2B09 FD01

7D03
2D02

FD07

2S2E

7UA6

2S4V

2S6B

2S37

2S6N 3S22

2S11

2UB7

IF55 9FD2 3FD7 9FD5 3FD2 2S6C 3S45 FF58

2S4T

2S51

2S6G 2S46

IUD7

IS16

IFD3 5UA0

IFD5

DS52

2S45

7FD1

7F54

IS5F

3FD1

2F53

3F69

3S1F

2S4K

IF57 9CH0 IF51 FF04

3S1P 3S2H 3S2V 9S0E

7S20

2FD1

2S4Q

7UA5
IUB1 2UB5 2UB6

7F53

3S41

3S2K 3S55 9S0D

2B40

3D02

3S40

FD08

IS3L

2S4R

3F66 3F54

2S50

3F53

3F67

IS05

9S09

2S4U 2S15 2S4Z

FC95

2D28

IS4Z

2D29
FD03 ID15

7D15

2S13

5S84

2S3G

IS5E 2S76 3S5S 2S75 3S76 3S75 IS4W

IS1A 2S36 C001

IUB6 IFD1

6FD1

IS2U

2S10 FS45 FS51

IS3B

3S09

IF56

FS0Z

IS50

2S29

3FD6

9FD1

2S3H

3S5V

2S3L

2B03

2B02

2S2L

3FD3

3FD4

IFD2

IFD4

2S40

2S19

CD10

IS1L

2S84 2S3K 3S2S

3S46

IS2Z IS5J

3S08

7S09
2S3Q 3S6M 3S11 3S19 IS1E IS1G

2S18

IS1B

2S3E

FS11

3S10

FS10

3S1G 3S1H 3S2L

ID37 ID19 FD09 ID27

2D16

3F68

IS19

3B28 2B08 2B36

2B01

ID18

ID30

IS5D

2S14

2B04

IS3D 2S86 IS5H

2S3F

2S85

ID29

IS1N

ID28

3S5T

IS4V

IS1M

FS 0 8 2B07 IS 1S 2B05

2B06

IS5G IS3F 9S24 IS3E IS20

2S16

2S3D

2S3C

2S3B

2S3A

IS2V

2S3M

3S25

IS1K

3F44

3F42

IS06

3S72

FF43

FF50

3S5B

3S18
FS44

FS49

IS5C

2S8A

2S39

2S38

3B03

2B00

2S2J

3S05

2S22

2S2K

3S6L

3S37

3S34

3S32

IS07

FS50 IE05 IS44

IS0 3

FF44

FF47

2B41
ID09 ID31

FD10 FD05 ID32 2D01 2D14

FF49

IF47

3S47

FF45

3F40
3F41 3F43

FD14

FE86

3S16 3S17
IS1J

IS0V FF48

7S05
IS02 2S2G 2S2H 3S39

2S3J

3F45

IS12

3S51

ID33

2SHW

3D06

3U13

IUD6 3S0W FS64 3S64

IS01

2S6A

ID11

2S5B

2S52

2S20

5D03
ID10 2D13

FD06

IS1Q IF16

2S42

F S 03

FD02

C000

FF46

5F76
2F62 2F70

6E48 7E13 7E12


3S3P 3S49 3S1D

3S5E IS1H IS0R IS1P

3S36
3S38

3S0Z

FF41

2F65 3F82
FF56 AF72

3E9E

FF42 IF53

5F74

IS11

2F95

F S 53 FS57 FS52

IS1D

FF55

FL39 IFLF

7F52

FF29

IF58

FL30

3F52
IF54

3F79
IF80

IF50

2E69

FL32

5F71

7E11

2F73 2F80 2F72 2F82 2F77 2F76 AF73

3E9D

2D27

FL37

IF79 IFL2

2D21

IE15 9E14 9E12

2F52

2E83

9F25 9F26
FL36

6E43

2F49
FF57 IF59

IE50

3D10
ID07

BEC5 BEC3

IF52 IFL1 IF72

2F96

5E74
2E14 FE80

3E77

2E84

2E80 2E98

3E75 2E15

5E73
FE74

2E86 3E74 IE53 2E79 IE55 2E85 3E78

IE18

FE23 9E28 2E04 9E25 IE22

ID05

5E76
2E12 FE81

3E79

FE57 IFLG IF90 IF75 IF81

3E53
FE56

6E44
IE49

IU43 3E76

6E26

6E23

6E28 6E09

3E07
2E91 2E88 FE71

2E06

FE73

6E03
2G91

IU45

IFL4

9G0G

2F78 2F74

FG1V

FG1W

FF71

IFLC 2FLA 2FLD 3FLA

FF75

FG2N IF73 FE58

IF77

2F71

2FL9

2FL5
2FLB

FF01

7F75

2F85

FG2P

FG1U

FG1T

2D26

2FL4
IF11

IF10

9F03 9F02
IF12

IF76

2D22

FG2C

FG1S

FG1R

3D14
ID08

FG2D FG2A FG2B

5F66

2F66

2FL8 2FL1 2FL3


IFLA 2FLC IFLE 3FLF

AF71 IF13

2F75
IF74 ID06

IF78

2F63 2F64

IF14

3F80 3F81
IF28 3FE5

2F79 3F77
IF27 IF82

FG27

FG28

FG29

IF15 2FH8 FG26 FG25 FG24

2FL2
3FLD 3FLH 3FLB IFLD

3FE7

3FG4
IF29

3FG2

3FE6

2FE5

2FF3

FG23 FG2M

FG22

5FG2

AF70 IFL3 3FLG

5FG0

IF64

3F32

1FE0

IFLB

2FF6
5FE4 FF00

IF66 2FG2

3 G3 1 3G33 3 G3 4 IE26 IE73 2FF0 3FG7 FE50 FE72 FE85 IE71 3E73 FE54 IE51 IE06 2FE4 IE32 2E70 DFE7 IE33 FG04 IE39 FE31 3 G3 2 3 G3 5 FG34 FG2K FE43 IE29 IE31 FE49 IE38 3E81 IE64 3E82 IE63 3 G3 0 3 G3 6 3G2Z FG2R FG2L

FG21

FG20

FL43

9E16

2FF5

FG1Y

FG1Z

IF63 FL33 FF64 IF48

2FG3

FG2E

FG2F

FFDC

FF66

FF65

5FE0 FF82 5FE3

2FE0
2FH5

IF65 2FG9 2FH6

2FE6

BFE3

FL40 5FE7 2FH7 BFE2 2FG8 2FG7 2FG6

7FE0
DFE9 IF18 DFF2 IF49 2FF7 2FF2 2FE3 2FG0 3FE8 3FE9 FF62 2FF8 IF68 FF61 2FF4 DFF1 5FA4

3FG6

FE42

3E44

IE48

9E26

3 G3 7 FG2G

FL41

DFE8

3G2Y 3G2W FG2H

FG35

DFE6 FC89 FE33 FE29 FE34 FC87 IF17

2F84 3F76

2FG4

2FE8
FF81 FF03 5FE5 IF67

3E95
3E29 2E08 FE27 FE28 2E58

3E99
2E59 2E09 3E39 FC88

7FE3

2FH2

2FH4

FE32

2FF1

2FA4

5FE8

IF69

2FG1

2FF9

5E03

5E04

FE01 IC73 IEE7 IEE8 FE30 FE59 FC91 FE61 FC92 IE77 FE60 9E19 FE51 IE74 IE75 FC65 FEE0 FC93 FC94 IE12 9EC2 FE41 FC66 FE44 IEE2 IU47 IEE1 2C79 3E90 IE66 FEC0 IE65 IU44 IEE0 FC90

5FE9

2FH3

5FA3

2FA3

FL42

FFAF

FF63

2E68 FECZ FE48 IE44 2ECY IE45 2ECX

FFB5

FFDB

FE02

2F59

FE03 FF76 FFA2

FECB

FFB6

FFDA

FF74

3FBF

FFC9

FFB1

7FA3
2FA2

2F61

2ECW

2EC2

2ECQ
3ECH IE43

FECY

FEC7 5EC3

2EC3 3ECL

IE76 2EC7 3ECJ FECR 3ECK

2ECV

FFB2

FFC5 9FC2 FFB4 9FC1 FFC2

FFC7 2EC8

2EC6

2EC0

FFB3

FFC3

FFC4

FEC3

5EC0

9E58

6E52

3ECU
FE36 IEC7 IEC6 IEC5 3ECE

FFC1 FFC6 FFC8 FECW FECA

9EC0

7EC0 7E02
3ECD IEC4

FECJ FE35 FEC2

3E23

FECE

FEC4 FEC5 FEC1

FECM

3ECA
FEC6 FECF FECD

3EC1

FECK

FECP FECN

FECL

FECC

FECG

2011-05-10

SSB Layout Bottom

3139 123 6521


19112_042_110628.eps 110628

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 156

10-17 E 27221719026x IR/LED/Key Board


Leading Edge Module

E
BZ1 B A BUZZER

Leading Edge Module


+3.3V +3.3V 2 1 C6 104 R11 100R Q1 R9 1K 2SC8050 VDDHI JP1 10 9 BUZZER ANALOG_VOUT ZD1 5.6V C2 105 R1 1K C3 105 PWM SCL 11 12 13 14 8 L1 100uH C1 VDD R2 10K VPP C4 104 U1 1 2 3 4 5 6 7 JP2 R3 VPP/M CLR/RE3 SEG12/Vcap(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0 SEG7/C12IN1-/AN1/RA1 COM2/DACOUT/VREF-/C2IN+/AN2/RA2 SEG15/COM3/VREF+/C1IN+/AN3/RA3 SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4 SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5 VSS VDD SEG1/VCAP(2)/CLKOUT/OSC2/RA6 SEG2/CLKIN/OSC1/RA7 P2B(1)/T1CKI/T1OSO/RC0 P2A(1)/CCP2(1)/T1OSI/RC1 SEG3/P1A/CCP1/RC2 SEG6/SCL/SCK/RC3 VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA 19 18 17 16 15 RB7/ICSPDAT RB6/ICSPCLK RB5/AN13/CPS5/T1G RB4/AN11/CPS4 RB3/AN9/CPS3/CCP2(1) RB2/AN8/CPS2 RB1/AN10/CPS1 RB0/AN12/CPS0/INT 28 ICSPDAT 27 ICSPCLK 26 25 24 23 22 21 VDD 20 C5 104 100R R4 100R R5 100R R6 100R R7 100R R8 100R CPS0 CPS1 CPS2 CPS3 CPS5

E
PIC16LF1933

MCU

Proxim ity

4.7uF/16V

CH+ CHHOM E AL VOL+ VOL-

BUZZER

1 1 CPS4 1 1 1 1

SDA

CONNECTOR
J1 8 7 6 5 4 3 2 1 2.0- 8pin +5V ANALOG_VOUT LED1 LED2 IR LIGHT +3.3V

J2 1 2 3 4 5 6 7 8 9 10 11 12 13 HEADER13 SDA SCL +5V +3.3V IR

IR
+3.3V TVS1 RES ZD4 5.6V

R17 10 R18 100R C10 4.7uF/6.3V

U2 3 2 4 1 OUT VDD GND GND TSOP75236

Proximity Sensor
1 1 2 Proxim ity3 OUT CX 6 5 4 C7 1u R27 2K VDDHI VSSVDDHI VREG IQS127D

IR ANALOG_VOUT LED2 LED1 LIGHT

CAP TOUCHSENCE
CX ANTENNA C8 1u C9 104 LIGHT ZD5 3.3V

+5V R10 4.7k / 100

+3.3V R15 47

WHITE LED
WHITE

+5V

D2 RED 1 3

D1

TEMT6200FX01 G1 5 6 LM358 Q3* BC847 2 B C12 R21 100k C11 104 104 R23 15k R24 18k 1 U3B 7 R22 470 3 2

8 U3A 1 LM358 4 R26 100R R20 22k R25 100k C13 104
Leading Edge Module
2722 171 9026
19100_815_110217.eps 110217

RED LED

LIGHT Sensor

+5V

LED1

R12 10k

2 R13 10k

B E

Q2 BC847

LED2

R14 10k

Q3 BC857 2

B E ZD3 5.6V E

R19 47k

R16 10k

8 9

2010-07-15 2010-07-15

VSS

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 157

10-18 E 27221719027x IR/LED/Key Board


Leading Edge Module

Leading Edge Module

E
U1 PIC16F1827 RA0/AN0/CPS0/C12IN0RB0/SRI/T1G/CCP1(1)/P1A(1)/INT/FLT0 RA1/AN1/CPS1/C12IN1RB1/AN11/CP S11/RX(1)/DT(1)/SDA1/SDI1 RA2/AN2/VREF-/DACOUT/CPS2/C12IN2-/C12IN+ RB2/AN10/CP S10/M DMIN/TX(1)/CK(1)/RX(1)/DT(1)/SDO(1) RA3/AN3/CPS3/C12IN3-/C1IN+/Vref+/C1OUT/CCP3(2)/SRQ RB3/AN9/CPS9/MDOUT/CCP1(1)/P1A(1)/Vcap RA4/AN4/CPS4/C2OUT/T0CKI/CCP4(2)/SRNQ RB4/AN8/CPS8/SCL1/SCK1/MDCIN2 RA5/M CLR/VPP/SS1 RB5/AN7/CPS7/P1B/TX(1)/CK(1)/SS1(1) RA6/OSC2/CLKOUT/CLKR/P1D(1)/SDO1(1) RB6/AN5/CPS5/T1OSI/T1CKI/PGC/P1C(1) RA7/OSC1/CLKIN/P1C(1) RB7/AN6/CPS6/T1OSO/PGD/P1D(1)/MDCIN1 VSS VSS VDD VDD 7 8 9 10 11 12 13 14 16 15 PWM 1 R1 SDA 1K IN4 IN5 PWM 2-SCL R27 BUZZER 1K ICSPCLK ICSPDAT VDD C5 104 KEYBOARD C2 105 VDD C3 105 ZD2 5.6V R16 3.9k IN0 19 IN6 20 IN1 1 IN2 2 IN3 3 MCLR 4 17 18 5 6

CPS6 +3.3V

L1 100uH C1 C4 10uF 104

VDD R2 103

NOT USED TV CONNECTOR J7


1 2 3 4 5 6 7 8 2.0-8pin LIGHT IR LED2 LED1 KEYBOARD +5V ESD +3.3V +3.3V R18 100R ZD4 5.6V C10 10uF/6.3V 2 4 1 VDD L2 100uH R11 100R C7 105 C6 104 BZ1

IN5 R3

CAP touchsence J1
CPS5 3.9K 1 J2 CPS4 1 J3 CPS3 1 J4 CPS2 1 J5 CPS1 1 J6 CPS0 1

IR
IR

R17 10

U2 3 OUT VDD GND GND TSOP75236

C8 10uF/6.3V

BUZZER
BUZZER R9 1K

BUZZER Q1 BC847

test VDD
ICSPCLK

T1 T2 T3 T4

IN4 R4 3.9K IN3 R5 3.9K IN2 R6 3.9K IN1 R7 3.9K IN0 R8 3.9K

ICSPDAT T5 MCLR +3.3V +5V R15 47/15 +5V TEMT6200 D1 RED C E G1 5 6 Q3 LED1 R12 10k 2 R13 10k B E Q2 BC847 LED2 R14 10k C B C E B C BC857 C 3 ZD3 5.6V E B BC847 R28 10k C11 104 C13 104 Q4 B R19 47k R20 22k LM358 LM358 C12 R21 100 k 104 R23 15k R24 18k R25 4 +5V 8 3 2 U3A

White LED
WHITE 1

R10 4.7k / 100 D2

Red LED

LIGHT Sensor
U3B 7 R22 470

R26 100R ZD1 3.3V

LIGHT

100 k

2010-08-23

Leading Edge Module

2722 171 9027


19101_057_110505.eps 110624

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 158

10-19 E 27221719028x IR/LED/Key Board


Leading Edge Module

Leading Edge Module

2010-08-24

Leading Edge Module

2722 171 9028


19101_058_110505.eps 110505

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 159

10-20 E 27221719029x IR/LED/Key Board


Leading Edge Module

Leading Edge Module


U1 CPS6 +3.3V R16 3.9k L1 100uH C1 C4 10uF 104 KEY2 SCL C16 ZD5 5.6V 105 C17 105 R2 103 VDD IN0 19 IN6 20 IN1 1 IN2 2 IN3 3 MCLR 4 17 18 R29 1K 5 6 PIC16F1827 RA0/AN0/CPS0/C12IN0RB0/SRI/T1G/CCP1(1)/P1A(1)/INT/FLT0 RA1/AN1/CPS1/C12IN1RB1/AN11/CP S11/RX(1)/DT(1)/SDA1/SDI1 RA2/AN2/VREF-/DACOUT/CPS2/C12IN2-/C12IN+ RB2/AN10/CP S10/M DMIN/TX(1)/CK(1)/RX(1)/DT(1)/SDO(1) RA3/AN3/CPS3/C12IN3-/C1IN+/Vref+/C1OUT/CCP3(2)/SRQ RB3/AN9/CPS9/MDOUT/CCP1(1)/P1A(1)/Vcap RA4/AN4/CPS4/C2OUT/T0CKI/CCP4(2)/SRNQ RB4/AN8/CPS8/SCL1/SCK1/MDCIN2 RA5/M CLR/VPP/SS1 RB5/AN7/CPS7/P1B/TX(1)/CK(1)/SS1(1) RA6/OSC2/CLKOUT/CLKR/P1D(1)/SDO1(1) RB6/AN5/CPS5/T1OSI/T1CKI/PGC/P1C(1) RA7/OSC1/CLKIN/P1C(1) RB7/AN6/CPS6/T1OSO/PGD/P1D(1)/MDCIN1 VSS VSS VDD VDD 7 8 9 10 11 12 13 14 16 15 PWM 1 R1 SDA 1K IN4 IN5 PWM 2-SCL R27 BUZZER 1K ICSPCLK ICSPDAT VDD C5 104 KEYBOARD C2 105 VDD C3 105 ZD2 5.6V

VDD VDD

L2 100uH

R11 100R C7 105 C6 104 BZ1

IN5 R3

CAP touchsence J1
CPS5 3.9K 1 J2 CPS4 1 J3 CPS3 1 J4 CPS2 1 J5 CPS1 1 J6 CPS0 1

TV CONNECTOR JP1
1 2 3 4 5 6 7 8 9 10 11 12 13 HEADER13 +5V SDA KEY2 SCL +5V IR KEYBOARD LED2 LED1 LIGHT +3.3V C15 101

R30 1K

C8 10uF/6.3V

C14 101

IR
IR +3.3V

R17 10

U2 3 2 OUT VDD GND GND TSOP75236

BUZZER
BUZZER R9 1K

BUZZER Q1 BC847

test VDD
ICSPCLK

T1 T2 T3 T4

IN4 R4 3.9K IN3 R5 3.9K IN2 R6 3.9K IN1 R7 3.9K IN0 R8 3.9K

R18 100R ESD ZD4 5.6V C10 10uF/6.3V

4 1

ICSPDAT T5 MCLR

+3.3V R15 47/15 +5V TEMT6200 D1 RED E C G1 5 6 Q3 Q4 C E B C ZD3 5.6V E BC847 R28 10k C11 104 C13 104 B R19 47k R20 22k LM358 LM358 C12 R21 100 k 104 R23 15k R24 18k R25 4 +5V 8 3 2 U3A

White LED
WHITE 1

R10 4.7k / 100 D2

Red LED

LIGHT Sensor
U3B 7 R22 470

R26 100R ZD1 3.3V

LIGHT

LED1 R12 10k

2 R13 10k

B E

Q2 BC847

LED2 R14 10k

B BC857 C

100 k

2010-08-27

Leading Edge Module

2722 171 9029


19101_059_110505.eps 110505

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 160

10-21 AL1 820400091394


LiteOn 5 LED RGB Master 24V

AL1A
1M83 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

LiteOn 5 LED RGB Master 24V


FB01 +24V

AL1A
CLK-BUFFER
PWM-CLOCK 1 3B01-1 8 150R 2B00 100p 7B26-1 TLC5946RHB BLANK PWM-CLOCK-BUF 2 3B00-2 7 150R 1K3 3B18 FB35 31 24 26 3 1 2 23 22 25 32 12 13 28 29 BLANK GSCLK IREF MODE SCLK SIN SOUT XERR XHALF XLAT 27 FB28 PWM-CLOCK-BUF +3V3 2B11 100n

VCC 0 1 2 3 4 5 6 7 OUT 8 9 10 11 12 13 14 15 GND_HS 33 7B26-2 TLC5946RHB VIA 34 35 VIA VIA 36 VIA 37 38 39 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 PWM-R1 PWM-G1 PWM-B1 PWM-B2 PWM-R2 PWM-G2

FB07 FB06 FB05 +3V3 FB10 FB11 FB12 +3V3 FB13 FB15 FB16 28 27

PROG BLANK LATCH SPI-CSn SPI-CLOCK PWM-CLOCK SPI-DATA-RETURN SPI-DATA-IN SPI-CLOCK 2

3B01-2 150R

FB29

PROG SPI-CLOCK-BUF SPI-DATA-IN-BUF SPI-DATA-IN SPI-CLOCK-BUF LATCH

1 3B00-1 8 150R 4 3B00-4 3 3B00-3 150R 5 150R +3V3 6

2B04

100p 2B05

2B06

2B07

NC

100p

100p

100p

PWM-G4 PWM-R4 PWM-B4 PWM-G3 PWM-R3 PWM-B3 DATA-SWITCH 3B31 +3V3 1K43 42 41 40

2B01

100p

+3V3

EEPROM
2B20 SPI-DATA-IN-BUF SPI-CLOCK-BUF 7B07 M95010-WDW6 8 +3V3 5 5 7B06 74LVC1G32GW SPI-CSn DATA-SWITCH 1 4 2 3 +3V3 1 3 6 D C S HOLD W GND 4 7 VCC 100n

30

FH34SRJ-26S-0.5SH(50)

GND

7004 LTW-008RGB2 Q 2 BLUE GREEN +3V3 RED 5 1 3 BLUE GREEN RED 6 2 4 5 1 3 BLUE GREEN RED

7003 LTW-008RGB2 6 2 4 5 1 3 BLUE GREEN RED

7002 LTW-008RGB2 6 2 4 5 1 3 BLUE GREEN RED

7001 LTW-008RGB2 6 2 4 5 1 3 BLUE GREEN RED

7000 LTW-008RGB2 6 2 4 +24V

2B03 SPI-DATA-RETURN +24V 6 3B50-3 3 3 3B07-3 6 10K +24V 7B50-1 BC847BS(COL) 6 2 2 3B51-2 7 1 10K 7B23-1 BC847BS(COL) 6 2 7 3B13-2 2 1 RES 9B01-4 FB30 10K +24V 5 3B50-4 4 7B51 BC847BW 3 1 4 3B51-4 5 2 9B50-1 8 FB62 PWM-R3_C 10K 10K

PWM-B3
+24V

FB50 7

RES 9B50-2 2

FB60

PWM-B3_C

PWM-B1

FB61

PWM-G3_C

1 3B07-1 8

7B23-2 BC847BS(COL) 3 5

BLUE-R RED-R GREEN-R

10K

6 3B13-3 3

RES

10K

4 10K RES 9B01-3 FB31 7 3B50-2 2 10K

PWM-G3
+24V

FB51

PWM-R1 +24V

7B50-2 BC847BS(COL) 3 5 RES 9B50-3

4 3B07-4 5

FB40

FB41

FB04

FB20

1 3B51-1 8

7B25 BC847BW 3 1

10K

4 10K

8 3B13-1 1

RES 9B01-2 FB32

PWM-G1

10K

PWM-R3

FB52

B010

B011

B012

100n

2010-11-15 2010-11-04 2010-09-23 2010-07-12

AL 2K11 LiteOn 5 LED RGB 24V Master

8204 000 9139

2 1

19111_002_110517.eps 110517

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 161

10-22 AL1 820400091574


LiteOn 5 LED 12V 50%

AL1A
1M83 FB01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

LiteOn 5 LED 12V 50%


+3V3 2B11 100n 7B26-1 TLC5946RHB BLANK PWM-CLOCK-BUF 1 3B00-1 8 150R 1K3 3B18 FB35 31 24 26 3 1 2 23 22 25 32 12 13 28 29 BLANK GSCLK IREF MODE SCLK SIN SOUT XERR XHALF XLAT

AL1A
0 1 2 3 4 5 6 7 OUT 8 9 10 11 12 13 14 15 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 PWM-R1 PWM-G1 PWM-B1 PWM-B2 PWM-R2 PWM-G2

VCC +3V3

+12V

PROG SPI-CLOCK-BUF SPI-DATA-IN-BUF SPI-DATA-IN SPI-DATA-OUT LATCH FB04 FB07 FB06 FB05 +3V3 FB10 FB11 FB12 +3V3 FB13 FB15 FB16 28 27 SPI-DATA-RETURN SPI-DATA-IN SPI-CLOCK TEMP-SENSOR PROG BLANK LATCH SPI-CSn PWM-CLOCK

4 3B00-4 5 150R 3 3B00-3 6 150R FB20 +3V3

27

2B12 PWM-G4 PWM-R4 PWM-B4 PWM-G3 PWM-R3 PWM-B3 DATA-SWITCH 3B31 1K43 +3V3 42 41 40 37 38 39

2 3B00-2 7 150R

3B21 33R

2B04

100p 2B05

2B06

2B07

NC

100p

1p0

1p0

GND 30

GND_HS 33 7B26-2 TLC5946RHB 34 VIA 35 VIA VIA 36 VIA

FH34SRJ-26S-0.5SH(50)

+3V3 +3V3 2B20 100n

1u0

EEPROM CLK-BUFFER
SPI-DATA-IN-BUF SPI-CLOCK-BUF 7B07 M95010-WDW6 5 5 7B06 74LVC1G32GW SPI-CSn DATA-SWITCH 1 4 2 3 +3V3 1 3 6 D C S HOLD W GND 4 7 7B20-1 74LVC2G17 Q 2 PWM-CLOCK 2 3B01-2 7 33R 2B00 2 33p 1 8

TEMP SENSOR
2B17 100n +3V3 +3V3

2B08 100n 3B34 100K RES

1K5 1%

+3V3

VCC

1K5 1%

+3V3 7B30 1 5 4 9B10 6B10 BAT54 COL TEMP-SENSOR

3B39

1 3B30-1 8 150R

FB28

PWM-CLOCK-BUF

FB41 1K5 1%

3B40

3 FB40 RES 2 -T 10K 3B11 3B05 10K

2B02

2B09

100n

+3V3

7B20-2 74LVC2G17 +3V3 5

SPI-DATA-RETURN

3B22 33R

SPI-CLOCK

3B01-4 33R

3B30-3 150R

FB29

SPI-CLOCK-BUF

2B01

33p

2B10

7000 LTW-008RGB2-PH1 PWM-B1 PWM-G1 PWM-R1 5 1 3 BLUE GREEN RED 6 2 4

3B35 22R cb01 9B01 3 3B03-3 6 220R 2 3B03-2 7 220R 5 1 3 BLUE GREEN RED

33p

7001 LTW-008RGB2-PH1 6 2 4 5 1 3 BLUE GREEN RED

7002 LTW-008RGB2-PH1 6 2 4 2B03 2B13 100n 100n +12V

FB30

FB31

FB32

FB50

FB51

FB52

FB60

FB61

FB62

B010

B011

B012
3 2010-12-02 2010-10-05 2010-07-15

3B41

33p

LMV331IDCK

AL 2K11 LiteOn 5 LED 12V 50%

8204 000 9157

19050_008_110418.eps 110418

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts


LiteOn 5 LED 12V 50%

Q552.2L LA

10.

EN 162

AL1B

LiteOn 5 LED 12V 50%

AL1B

7100 LTW-008RGB2-PH1 PWM-B2 PWM-G2 PWM-R2 5 1 3 BLUE GREEN RED 6 2 4 5 1 3

7101 LTW-008RGB2-PH1 BLUE GREEN RED 6 2 4 PWM-B2-R PWM-G2-R PWM-R2-R

2011-01-21 2010-12-02 2010-10-05 2010-07-15

AL 2K11 LiteOn 5 LED 12V 50%

8204 000 9157

2 1

19050_009_110418.eps 110418

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 163

10-23 AL3 820400091353


LiteOn 1 LED RGB Master 24V

AL3A

LiteOn 1 LED RGB Master 24V

AL3A

7005 LTW-008RGB2 1 3C01-1 8 220R 2 3C01-2 7 220R 5 3C02 13R 1 3C03-1 8 1K0 2 3C03-2 7 1K0 3C03-3 1K0 1 3 BLUE GREEN RED 6 2 4

BLUE GREEN RED

BLUE-R GREEN-R RED-R

4 3C03-4 5 1K0

1M85 FH34SRJ-18S-0.5SH(50) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

PWM-G3_C PWM-R3_C PWM-B3_C

+24V B013 FC12 19 20

2010-11-22 2010-09-29 2010-07-12

AL 2K11 LiteOn 1 LED 24V

8204 000 9135

19111_003_110517.eps 110517

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 164

10-24 AL3 820400091373


LiteOn 4 LED RGB Master 24V

AL3A

LiteOn 4 LED RGB Master 24V

AL3A
+24V

3C21-1 10K 2K0 3C21-2 2K0 1 3C01-1 8 2K0 2 3C01-2 7 2K0 3 3C01-3 6 2K0 BLUE-R 4 3C01-4 5 2K0 GREEN-R 1 3C02-1 8 470R 2 3C02-2 7 470R 3 3C02-3 6 470R 3C02-4 470R RED-R 1 3C03-1 8 3K0 2 3C03-2 7 3K0 3C03-3 3K0 4 3C03-4 5 3K0 8 3C16-1 1 10K 1 3C04-1 8 3K0 2 3C04-2 7 3K0 3 3C04-3 6 3K0 4 3C04-4 5 10K 3K0 6 3C15-3 3 7C05-2 BC847BS(COL) 3 5 6 3C16-3 3 4 10K 9C00-4 RES FC52 +24V PWM-G4 +24V RED PWM-R4 FC16 BLUE 7 3C15-2 2 7C05-1 BC847BS(COL) 6 2 RES 9C00-2 7 3C16-2 2 1 10K PWM-G4-C PWM-R4-C PWM-B4-C PWM-G3_C PWM-R3_C PWM-B3_C

FC50

PWM-R4-C 1M85 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

GREEN

8 3C15-1 1

7C06 BC847BW 3 1

10K

FC51

PWM-G4-C

+24V

RES 9C00-1

19 PWM-B4-C 1 3C09-1 8 3K6 2 3C09-2 7 3K6 3 3C09-3 6 3K6 3C09-4 3K6 1 3C10-1 3K6 2 3C10-2 7 8 5 1 3 5 BLUE GREEN RED 6 2 4 7102 LTW-008RGB2

20

FH34SRJ-18S-0.5SH(50)

FC17

PWM-B4

FC18

+24V 1 3C07-1 8 7 3C05-2 7C01-1 BC847BS(COL) 6 2 7 3C06-2 1 10K RES 9C01-4 FC10 1 3C17-1 8 +24V 7100 LTW-008RGB2 5 7C02 BC847BW 3 RES 9C01-2 1 8 2 3C06-1 10K 1 3 BLUE GREEN RED 6 2 4 5 1 3 7101 LTW-008RGB2 BLUE GREEN RED 6 2 4 4 4K3 2 3C17-2 7 8 3C05-1 4K3 3 3C17-3 6 4K3 3C17-4 4K3 10K 4K3 3C07-2 4K3 3 3C07-3 6 4K3 4 3C07-4 5 4K3

1 3C08-1 8 1K0 2 3C08-2 7 1K0 3 3C08-3 6 1K0 4 3C08-4 5 1K0

PWM-B2

7103 LTW-008RGB2 5 1 3 BLUE GREEN RED 6 2 4 2C01 100n

+24V

10K

PWM-G2 +24V

FC11

3K6 3 3C10-3 6 7C01-2 BC847BS(COL) 3 RES 9C01-1 5 3K6 4 3C10-4 5 3K6 4

3C05-4 3C06-4 4 5 4

5 10K 10K

PWM-R2

FC12

B013

B014

FC20
3 2010-11-15 2010-11-04 2010-09-28

AL 2K11 LiteOn 4 LED 24V Master

8204 000 9137

19111_004_110517.eps 110517

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 165

10-25 AL3 820400091413


LiteOn 7 LED RGB Master 24V

AL3A

LiteOn 7 LED RGB Master 24V


+24V 7 3C15-2 2

AL3A
7C05-1 BC847BS(COL) 6 2 FC50

10K

PWM-R4-C
1M85

7 3C16-2 2

RES 9C00-3

1 10K

PWM-G4-C PWM-R4-C PWM-B4-C PWM-G3_C PWM-R3_C PWM-B3_C

3C01-3 220R 3C01-4

PWM-R4
7005 LTW-008RGB2

FC16

+24V

BLUE GREEN RED

6 2 4

8 3C15-1 1

BLUE-R GREEN-R RED-R

220R

BLUE
1 3

3C02 13R

GREEN RED

7C06 BC847BW 3 1

FC51

PWM-G4-C
+24V

8 3C16-1 1

RES

10K

3C03-1 1K0 3C03-2 1K0 3C03-3 1K0 3C03-4 1K0

9C00-4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

10K

PWM-G4

FC17

FH34SRJ-18S-0.5SH(50)

+24V

6 3C15-3 3

7C05-2 BC847BS(COL) 3 5

10K

5 FC52

PWM-B4-C

6 3C16-3 3

4 10K

PWM-B4

FC18

+24V 1 3C07-1 8 2 3C05-2 7 7C01-1 BC847BS(COL) 6 2 2 3C06-2 7 1 RES 9C01-2 7 FC10 1 3C09-1 8 +24V 7100 LTW-008RGB2 5 7C02 BC847BW 3 8 RES 9C01-1 1 1 3C06-1 8 2 10K 1 3 BLUE GREEN RED 6 2 4 5 1 3 7101 LTW-008RGB2 BLUE GREEN RED 6 2 4 3C12 13R 4 1K0 2 3C09-2 7 1 3C05-1 8 1K0 3 3C09-3 6 1K0 3C09-4 1K0 5 1 3 5 2C01 100n
3

10K

10K

220R

4 3C07-4 5 2 220R

PWM-B2

RES 9C00-1 8

7102 LTW-008RGB2 BLUE GREEN RED 6 2 4 5 1 3

7103 LTW-008RGB2 BLUE GREEN RED 6 2 4 5 1 3

7104 LTW-008RGB2 BLUE GREEN RED 6 2 4 5 1 3

7105 LTW-008RGB2 +24V BLUE GREEN RED 6 2 4

10K

PWM-G2
+24V

FC11

4 3C05-4 5

7C01-2 BC847BS(COL) 3 5 5 RES 9C01-4

4 3C06-4 5

10K

4 10K

B013

B014

B015

B016

FC20

FC21

PWM-R2

FC12

2010-11-22 2010-09-23 2010-07-02

AL 2K11 LiteOn 7 LED 24V Master

8204 000 9141

19111_005_110517.eps 110517

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 166

10-26 AL3 820400091583


LiteOn 4 LED 12V 50%

AL3A

LiteOn 4 LED 12V 50%

AL3A

1M84 SPI-CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FH34SRJ-26S-0.5SH(50)

PWM-B4 PWM-G4

SPI-DATA-OUT SPI-DATA-RETURN +3V3 PWM-CLOCK

PWM-R4
SPI-CSn LATCH +3V3 BLANK PROG TEMP-SENSOR

+12V

B013

B014

FC10

FC20

FC11

FC50

FC12

FC51

FC52

2010-12-02 2010-10-05 2010-07-15

AL 2K11 LiteOn 4 LED 12V 50%

8204 000 9158

19050_010_110418.eps 110418

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts


LiteOn 4 LED 12V 50%

Q552.2L LA

10.

EN 167

AL3B

LiteOn 4 LED 12V 50%

AL3B

7200 LTW-008RGB2-PH1 PWM-B3 PWM-G3 PWM-R3 5 1 3 BLUE GREEN RED 6 2 4

3C11 22R cc10 9C10 5 1 3

7201 LTW-008RGB2-PH1 BLUE GREEN RED 6 2 4 5 1 3

7202 LTW-008RGB2-PH1 BLUE GREEN RED 6 2 4 +12V

1 3C13-1 8 220R 2 3C13-2 7 220R

2C10

2C11

100n

100n

2010-12-02 2010-10-05 2010-07-15

AL 2K11 LiteOn 4 LED 12V 50%

8204 000 9158

19050_011_110418.eps 110418

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts


LiteOn 4 LED 12V 50%

Q552.2L LA

10.

EN 168

AL3C

LiteOn 4 LED 12V 50%

AL3C

3C31 22R PWM-B2-R PWM-G2-R PWM-R2-R cc30 9C30 5 1 3

7102 LTW-008RGB2-PH1 BLUE GREEN RED 6 2 4 +12V

1 3C33-1 8 220R 2 3C33-2 7 220R

2C30

2C31

100n

100n

2010-12-02 2010-10-05 2010-07-15

AL 2K11 LiteOn 4 LED 12V 50%

8204 000 9158

19050_012_110418.eps 110418

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 169

10-27 AL3 820400091592


LiteOn 7 LED 12V 50%

AL3A

LiteOn 7 LED 12V 50%

AL3A

7300 LTW-008RGB2-PH1 5 1 3 BLUE GREEN RED 6 2 4 1

3C03 22R 9C04 cc04 3C01-1 220R 2 3C01-2 7 220R 5 1 3 8

7301 LTW-008RGB2-PH1 BLUE GREEN RED 6 2 4 5 1 3

7302 LTW-008RGB2-PH1 SPI-CLOCK BLUE GREEN RED 6 2 2C01 2C02 100n 100n PWM-CLOCK SPI-CSn LATCH +3V3 BLANK PROG TEMP-SENSOR 4 +12V SPI-DATA-OUT SPI-DATA-RETURN +3V3

1M84 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FH34SRJ-26S-0.5SH(50)

PWM-B4 PWM-G4 PWM-R4

+12V

B013

B014

B015

B016

FC10

FC20

FC11

FC21

FC12

2010-12-02 2010-10-07

AL 2K11 LiteOn 7 LED 12V 50%

8204 000 9159


19101_054_110505.eps 110505

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts


LiteOn 7 LED 12V 50%

Q552.2L LA

10.

EN 170

AL3B

LiteOn 7 LED 12V 50%

AL3B

7200 LTW-008RGB2-PH1 PWM-B3 PWM-G3 PWM-R3 5 1 3 BLUE GREEN RED 6 2

3C14 22R 9C12 1 cc12 4 3 3C13-3 6 220R 4 3C13-4 5 220R 3 5

7201 LTW-008RGB2-PH1 BLUE GREEN RED 6 2 4 5 1 3

7202 LTW-008RGB2-PH1 BLUE GREEN RED 6 2 4 +12V

2C10

100n 2C04

100n

2010-12-02 2010-10-07

AL 2K11 LiteOn 7 LED 12V 50%

8204 000 9159


19101_055_110505.eps 110505

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts


LiteOn 7 LED 12V 50%

Q552.2L LA

10.

EN 171

AL3C

LiteOn 7 LED 12V 50%

AL3C

3C15 PWM-B2-R PWM-G2-R PWM-R2-R 22R 9C32 cc32 3 3C33-3 6 220R 4 3C33-4 5 220R 5 1 3

7102 LTW-008RGB2-PH1 BLUE GREEN RED 6 2 4 +12V

2C30

2C05

100n

FC17 FC18 FC16

FC50 FC51 FC52

100n

2010-12-02 2010-10-07

AL 2K11 LiteOn 7 LED 12V 50%

8204 000 9159


19101_056_110505.eps 110505

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 172

10-28 AL 310431364803 AmbiLight Layout


9 LED 50% 12 V LiteOn

Layout Top
7000
3B35
FB40 Cb01 9B01

cc3 9C 30 0

B010

B011

B012

3C31

B013

2B03

FB06

FB10

3C33

B014

2B13

FB41

7001
3B34
FB12

FB07

2C30

FB16

2B09

7B30

2B08
FB15

3B00

3B03

1M83

3C11

FB30

FB29

FB20

FB52 FB50 FB04 FB13 FB61 FB11 FC12 FC11

3C13
FC17

FB05

2B01

2B102B02

FB28

3B22

FC16

FB31

Layout Bottom

cc10 9C10

3B11

7B20

7B07

3B01

2B00

2B06 2B07 2B04 2B05

3B30

FB01

FC10

2C10

FC18

3B39

3B05

FC50

FB51

1M84

2C31

FC51

FC52

FB35

2C11

2B12 2B17

2B20

3B31

7002

7B06

3B18 2B11

7100

FB32

7101

FB60

FB62

7102

7200

7201

7202
FC20

7B26

3B21

2010-12-02 2010-10-05

AL 2K11 LITEON 9 LED 50%

3104 313 6480


19050_069_110506.eps 110506

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 173

10-29 AL 310431364812 AmbiLight Layout


12 LED 50% 12 V LiteOn

Layout Top
B010
7000
3B35
FB40 C b01 9B01 FB41

Layout Top
B012 B014 B015 B011
2B03
2B13 FB06 FB10

B013

FC20

2C05

2B00

FB12 3B34

2B09

7B30

2B08
FB16 FB15

3B00

FB29

FB20

FB05

2B01

2B102B02

FB28

3B22

FB31

FB50

FB04

FB13

FB61

FB11

FC12

FC11

FC16 FC17

Layout Bottom

Layout Bottom

2C04

3B03

1M83

3B05

2C10

2C01

FB52

FB30

2C02

7B20

FB51

3C14

3C13

9C12 cc12

3B11

7B07

3B01

3B30

2C30

3C15

9C 32 2 cc3

7B06
FB01

2B06 2B07 2B04 2B05

3B39

7B26

FB35

3B21

3C33

FC10

FC18

FC50

FC51

FC52

FC21

3C01

1M84

B016

7001

FB07

3C03

9C04 Cc04

2B12 2B17

2B20

3B31

7002

3B18 2B11

7100

FB32

7101

FB60

FB62

7102

7200

7201

7202

7300

7301

7302

2010-12-02 2010-10-05

AL 2K11 LITEON 12 LED 50%

3104 313 6481


19050_070_110506.eps 110506

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 174

10-30 AL 310431364833 AmbiLight Layout


6 LED 24V LiteOn ECO RGB Master

FB60

3B00

B010

B011

2B07

2B06

3B18

2B11

2B03

7B06

3C01

2B20

1M83

FB30

FB51

3B01

2B00

3B31 FB16 FB15

2B01

FB29

FB20

FB52

FB05

FB28

FB31

9B50

FB50

FB04

FB13

FB61

FB11

1M85

3B13

FC12

3C03

FB12

FB01

FB40

7B07

7B26

7B23

3B51

FB35

3B50

7B25

7B51

3C02

FB06

7B50

FB10

9B01

2B04

B012

B013

7000

FB41

7001

FB07

7002

7003

3B07

FB32

7004

FB62

7005

2B05

2011-05-17

AL 2K11 ECO RGB M 6LED 24V LITEON

3104 313 6483


19110_057_110517.eps 110517

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 175

10-31 AL 310431364853 AmbiLight Layout


9 LED 24V LiteOn ECO RGB Master

3B00

B011

B012

B010

FB06

7B50

FB10

B013

B014

3B18 2B11

9B01

FB07

2B07

7000
2B03
FB40

FB41

7001
FB12

2B06 2B05

2B04

7002

7003

3B07

FB32

7004
3B50
FB51 FB30 FB52

FB60

FB62

7100
3C02 9C01

3C03 3C04

3C01 3C21
FC10

7101
FC18

3C08

3C09

3C10 3C15
FC51

3C07 3C17
FC52

7102

7103
FC20

7B06

1M83

2B20 3B31

FB01

7B23
3B13

7C01

3C06

3C05

2B00

3B01

2B01

FB29

FB20

3C16

7C05
FC16

FB16

FB15

FB05

FB28

FB31

9B50

FB50

FB04

FB13

FB61

FB11

FC12

FC11

FC17

7C06

9C00

7B51

7C02

7B07

7B26

3B51

FB35

7B25

FC50

1M85

2C01

2011-05-17

AL 2K11 ECO RGB M 9LED 24V LITEON

3104 313 6485


19110_059_110517.eps 110517

2011-Jul-15 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2L LA

10.

EN 176

10-32 AL 310431364873 AmbiLight Layout


12 LED 24V LiteOn ECO RGB Master

3B00

B013

B010

B011

B012

3C02

FB06

7C02

2B03

FC50

7B06

FB12

1M83

FB51

3B13

3C06

3C05

2B00

3B01

2B01

FB29

FB20

3C16

3B31
FB16 FB15

FB30

FB52

3C01
FB61 FB11 FC12

7C01

3C03

7C05
FC16

FB05

FB28

FB31

9B50

FB50

FB04

FB13

FC11

FC17

7C06

9C00

2B20

FB01

7B23

7B51

FC10

FC51

FC52

FC18

FC21

FB40

7B07

7B26

3C15

3B51

FB35

3B50

7B25

7B50

FB10

B014

FC20

9C01

B015

1M85

B016

3B18 2B11

9B01

FB07

2B07

7000

FB41

7001

2B06 2B05

2B04

7002

7003

3B07

FB32

7004

FB60

FB62

7005

7100

3C09

3C07

7101

7102

7103

7104

7105

3C12

2C01

2011-05-17

AL 2K11 ECO RGB M 12LED 24V LITEON

3104 313 6487


19110_061_110517.eps 110517

2011-Jul-15 back to

div. table

Styling Sheets

Q552.2L LA

11.

EN 177

11. Styling Sheets


11-1 Blockbuster/Emmy 32"

BLOCKBUSTER / EMMY 32"

1150

5213 5216

0011

1005

5216 0260
Pos No. 0004 0011 0029 0260 1004 1005 1085 1108 1150 1161 1162 5213 5216 8191 8308 8G50 8G51 Description Front Cabinet Back Cover Hard Switch bracket Stand Display panel Power Supply Unit Remote Control Keyboard + IR assy Board SSB AmbiLight AmbiLight Loudspeaker box Tweeter Mainscord 1.8m Main (power) switch Cable LVDS FFC Cable LVDS FFC Remarks

0029 8308

Not displayed

Not displayed Not displayed

1004 1108 0004

Not displayed Not displayed Not displayed


19110_049_110420.eps 110420

2011-Jul-15 back to

div. table

Styling Sheets

Q552.2L LA

11.

EN 178

11-2 Blockbuster/Emmy 40" - 46"

BLOCKBUSTER / EMMY 40"- 46"

1150

1005 5216

0011

5213

0260 5216
POS. NO. 0004 0011 0040 0260 1004 1005 1085 1108 1150 1161 1162 5213 5216 8191 8308 8G50 8G51 DESCRIPTION. Front Cabinet Back Cover Hard Switch bracket Stand Display panel Power Supply Unit Remote Control Keyboard + IR assy Board SSB AmbiLight AmbiLight Loudspeaker box Tweeter Mainscord 1.8m Main (power) switch with cable Cable LVDS FFC Cable LVDS FFC REMARKS

0040 1004 8308

Not Displayed

Not Displayed Not Displayed

1108

0004

Not Displayed Not Displayed Not Displayed


19110_050_110420.eps 110420

2011-Jul-15 back to

div. table

Styling Sheets

Q552.2L LA

11.

EN 179

11-3 Sundance 42" - 47"

SUNDANCE 42" - 47"

1150

1005 0050 0051

1163

0035

5217 0011 0050 0051 0050 0257 5213

1163
Pos No. 0004 0011 0029 0035 0050 0051 0257 0258 0270 1004 1005 1027 1085 1108 1150 1163 5213 5216 5217 8191 8308 8G50 8G51 Description Front Cabinet Back Cover Main Switch Bracket Swivel bracket Ambilight Clip Ambilight Clip Stand neck Stand base 3D glasses Display panel Power Supply Unit Temperature sensor board Remote control Keyboard assy (touch control) Board SSB Ambilight module Loudspeaker box Tweeter Tweeter Mainscord Main Switch with cable LVDS (FFC) Cable LVDS (FFC) Cable Remarks

0258

8308 0029 1004

5216

42 47

Not displayed

Not displayed

0004 1108

Not displayed Not displayed Not displayed


19110_064_110711.eps 110711

2011-Jul-15 back to

div. table