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I

Cascade two-port models of differential ampliÞer with current-mirror supply (input stage) and common-source ampliÞer with current supply (second gain stage)

vi+

+ vd Gm1vd

+ Rout1 vi 2 − Gm2vi 2 Rout

+ vo −

vi−

I

−

First stage: polarity of Gm1 is inverted to reßect reversal of input terminals ... which is done to make the overall gain positive for vd > 0 Gm1 = gm1 Rout1 = ro2 || ro4

I

Second stage: Gm2 = gm5 Rout = ro5 || ro6 a vdo = ( Ð G m 1 R out 1 ) ( Ð G m 2 R out )

a vdo = g m 1 ( r o 2 r o 4 ) g m 5 ( r o 5 r o 6 )

EE 105 Spring 1997 Lecture 37

4 I D7 100 µ A Therefore (W/L)3.= 1 2 ( W ⁄ L ) 3.5 V and V .set Wmax = 150 µm (for minimize channel-length modulation. I Initial Transistor Sizing: Make (W/L)1 = (150 µm / 3 µm) in order to maximize Gm1 and maximize common-mode input voltage range DC currents: assume IREF = 50 µA Set DC bias current of differential ampliÞer = DC bias of common-source stage = 100 µA each as a Þrst-cut --> total current drawn is 250 µA --> power spec. set Lmin = 3 µm) Set DC power budget at 1.= -----------------.4 = 75 µm since we use Lmin to save area.4 = (W/L)5 /2 = 25 --> W3. we also set (W/L)7 = (150 µm / 3 µm) EE 105 Spring 1997 Lecture 37 .2.Two-Stage CMOS Design Example I Design constraints Typical situation for an internal op amp: area and power are both limited. we set (W/L)6 = (W/L)5 = (150 µm / 3 µm) To maximize common-mode input range.= .5 V. SimpliÞed area constraint -. For symmetrical output swing. is just met Transistor dimensions: (W/L)5 = (150 µm / 3 µm) to maximize gm5 ÐI D6 ( W ⁄ L )5 100 µ A ---------------------------.= ----------.25 mW (including reference current) for case where we have symmetrical supplies: V+ = 2.

5 V M8 (75/3) 1 M7 (150/3) 2 M6 (150/3) _ vI− 50 µA M3 (75/3) 3 M4 (75/3) M1 (150/3) M2 (150/3) + vI+ 4 Cc M5 (150/3) + CL v O − −2.5 mjswp = 0.1 fF/µm2 Cjswno = 0.5 fF/µm Cjno = 0.8 V Cov = 0.33 p-channel MOSFET µpCox = 25 µA V2 VTOp = −1.1(µm/V) L 2φn = 0.8 V Cov = 0.5 fF/µm Cjpo = 0.First-Cut CMOS Two-Stage Op Amp +2.0 V γp = 0.95 V mjp = 0.5 mjswn = 0.6 V1/2 tox = 15 nm λp = 0.95 V mjn = 0.1(µm/V) L 2φp = −0.5 fF/µm φBn = 0.5 V n-channel MOSFET µA V2 VTOn = 1.0 V µnCox = 50 γn = 0.6 V1/2 tox = 15 nm λn = 0.33 EE 105 Spring 1997 Lecture 37 .3 fF/µm2 Cjswpo = 0.35 fF/µm φBp = 0.

min = Ð 2.5 V Ð ( Ð 1 V ) Ð 1.5 V Ð 0.1 V V O . I Output voltage swing V O .possible at the expense of increased area (W/L) ratios must be increased.4 V = 2. min = Ð 2.5 V + 1.4 V = 0.DC Bias Solution I Assume that the DC input voltages are VI+ = VI.22 V output range in nearly symmetrical and adequate EE 105 Spring 1997 Lecture 37 .28 V Ð 1.28 V = Ð 2.= 0 V and VO = 0 V I Input common-mode voltage range V IC .5 V + 0.28 V + ( Ð 1 V ) = Ð 2.22 V room for improvement in the upper limit -.82 V V IC . max = 2. max = 2.

15 ×10 in decibels. 4 EE 105 Spring 1997 Lecture 37 .Small-Signal Performance I Small-signal parameters: gm1 = gm2 = 357 µS gm5 = 2 gm1 = 714 µS ro2 = ro4 = 600 kΩ ro5 = ro6 = 300 kΩ I Differential voltage gain: a vdo = ( 0. |avdo|dB = 81 dB.357 ) ( 600 600 ) ( 714 ) ( 300 300 ) = 1.

.Stability -..terminals to be reversed! . then the output is destabilized if the input is perturbed..A Brief Introduction I Non-inverting. unity gain conÞguration + vs(t) + _ Op Amp _ vo(t) vs(t) = vssin(ωst) Feedback is to negative terminal of op amp.. the sign of avd is ßipped! Consider + and . EE 105 Spring 1997 Lecture 37 . which tends to stabilize the output voltage vo(t) to be nearly equal to vs(t) I What happens when the phase of avd(jωs) = 180o? . if |avd(jωs)| > 1.

then the unity-gain non-inverting configuation (worst-case) will be stable One solution: locate the second pole of the op amp ω2 at approximately the unity gain frequency ω 2 ≈ a vdo ω 1 The second gain stage is responsible for both poles C'c + Vi 2 − + R1 Gm2Vi 2 Rout C'L Vo − I I Is C1 Device capacitances are lumped together in the circuit: C 1 = C gs 5 + C gd 4 + C db 4 + C gd 2 + C db 2 C L ′ = C L + C db 5 + C db 6 + C gd 6 C c ′ = C c + C gd 5 The compensation capacitor Cc sets the dominant pole ω1 by the Miller effect: ω 1 ≈ R 1 C 1 + R 1 ( 1 + G m 2 R out ) C c ′ where R1 = Rout1 Ð1 EE 105 Spring 1997 Lecture 37 .Ensuring Stability I If the gain of the op amp is less than 1 (in magnitude) when the phase is 180o.

Second Pole Location I Direct factoring of transfer function --> ÒexactÓ expression for ω2 For the case when C 1 Ç C c ′ .≈ --------------------------------------------------------ω 2 ≈ ---------C L ′ R 1 C 1 + R 1 ( 1 + G m 2 R out ) C c ′ Gm 2 R1 R Cc ′ out since Gm2Rout >> 1 G m 1 - C c ′ ≈ C L ′ ---------G m 2 EE 105 Spring 1997 Lecture 37 . C L ′ 1 ω 2 ≈ G m 2 ⁄ C L ′ = ------------------------------( 1 ⁄ Gm 2 ) C L ′ I Interpretation: At frequencies around ω2 (>> ω1). the impedance Zc = (1 / jω2 Cc) is small enough that M5 can be considered diode-connected Load capacitance sees a ThŽvenin resistance of 1 / gm5 --> ω2 is set by the load capacitance in parallel with 1 / gm5 I Adjusting compensation and load capacitors to satisfy ω 2 ≈ a vdo ω 1 Gm 2 ( G m 1 R out 1 ) ( G m 2 R out ) ( G m 1 R out 1 ) ( G m 2 R out ) .≈ -----------------------------------------------------------------------.

C c ′ = 5.3 krad/s ω 2 = 10.5 pF with parasitic capacitances --> C L ′ = C L + 350 fF = 7.85 pF The compensation capacitor is approximately 357 µ S ..2 Mrad/s SPICE: must increase Cc to 20 pF in order to have ω 2 ≈ a vdo ω 1 ω 1 = 1.9 pF C c ′ ≈ ---------------- 714 µ S L the ÒexactÓ result is signiÞcantly higher .3 pF Area requirement with a 500 • thick oxide is less than 100 x 100 µm2 --> not a signiÞcant addition to the op amp area I I I Pole locations: ω 1 = 5.4 Mrad/s I EE 105 Spring 1997 Lecture 37 .8 krad/s ω 2 = 67.Capacitor Sizing I The load capacitor is set by system speciÞcations: CL = 7.C ′ = 3..

EE 105 Spring 1997 Lecture 37 .

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