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FirststepswithUVMWebinarFridayAugust2nd201310.

30amGMTQ&ALog

Audience Question: Q: Can UVM be used for SoC verification? Many of the companies use complete C based verification approach for ARM based SoC verification. Your comment would be useful A: Yes, UVM is typically used for SoC verification (depending what you mean by that). Many companies use UVM in a SystemVerilog verification environment combined with software-based verification (e.g. using an ARM instruction-set simulator) Audience Question: Q: Is SV ARM instruction-set simulator available? A: There are several ISSs available, typically provided by ARM themselves, and at different levels of detail. None of them are written in SystemVerilog, but that does not stop you using an ARM ISS alongside your SV/UVM verification environment Audience Question: Q: What is factory automation? How is it different in building a conventional SV testbench A: The factory is a mechanism that gives you more flexibility when instantiating components in the verification environment or generating stimulus. The factory allows you to override the types of objects that are created by existing verification code without needing to modify the original source code. Audience Question: Q: what is the super class of the current class? A: The super-class is the class that the current class "extends". So the superclass of my_test is uvm_test Audience Question: Q: what we can pass in the argument parent? A: A reference to the parent component Audience Question: Q: Is there is any free ISS compatible with UVM? A: If you want a "free" ISS, you should check out OVP at www.ovpworld.org. There really is no issue with "compatibilty" with UVM (in other words, yes, they are compatible) Audience Question: Q: how we do pass user defined constructor to factory method A: When using the factory (and you should always use the factory for components, transactions, and sequences) your class has to have a constructor with a fixed set of arguments (as shown on the slides) Audience Question: Q: why we have to register the declared class with uvm factory ? A: So that we can use the factory to create instances (objects) of this class, which is a good thing, because it is one of the main ways to achieve reuse in UVM Audience Question: Q: what will happen if i am not registering the component using "`uvm_component_utils()" A: Bad things will happen! More specifically, you will get obscure (hard to debug) error messages when you try to instantiate those components (using the factory method create(), which is how you should always instantiate components) Audience Question: Q: why to register factory setting when my_test uses the parent uvm_test. uvm_test should be already registered to factory ? A: It doesn't work like that. A new class is a new type, and each type needs to be registered with the factory. When you create an object of type my_test, you don't want an object of type uvm_test instead! Audience Question: Q: why function new has two arguments? A: That's how it is. The first argument is the name, the second the parent. Audience Question: Q: what's the impact if the class is not registered in the UVM factory? A: Obscure, hard-to-debug error messages whenever you try to instantiate the component/object! Audience Question: Q: what is the parent class for the test? A: Good question. There is a special pseudo-component uvm_top that instantiates the top-level test.

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FirststepswithUVMWebinarFridayAugust2nd201310.30amGMTQ&ALog
Audience Question: Q: Why a constructor is needed ? is it optional ? A: A constructor is an essential feature of object-oriented programming. In the case of UVM components, transactions, sequences, and objects, the constructor is NOT optional, and moreover, it has to have the correct number and type of arguments. Audience Question: Q: are you sure that OVP has free A: I'm not up-to-date with OVP's commercial model these days. I suggest you check out their website.

Audience Question: Q: what is raise_objection and drop_objection in run_phase A: This is the mechanism to end the test. A piece of UVM code raises an objection whenever it is busy (so the test does not end too soon) and drops the objection again when it is ready to end. Audience Question: Q: why we can not print any statement and raise objection in build phase ? A: You can print stuff in build_phase. It does not make sense to raise objections in build_phase, because objections are only meaningful in run-time phases where simulation time is passing. Audience Question: Q: as build_phase and run_phase uses uvm_phase, can i write the run_phase task in the build_phase ? A: No. These are pre-defined "common" phases that have to be used for predefined purposes. build_phase builds the UVM component hierarchy, run_phase in effect "runs simulation", i.e. simulation time passes Audience Question: Q: what is the advantage of create over new? A: When you call new, you get an object of a type that is determined at compile-time according to the type of the variable the reference is assigned to. The point of the factory mechanism is to allow you to override the type of the object being created at run-time. Audience Question: Q: May I know what is #10 in the run_phase task ? A: #10 pauses the execution of the SV process for a procedural delay of 10 time units. Audience Question: Q: What is the difference between new() and create? How to decide which one to be used? A: When you call new, you get an object of a type that is determined at compile-time according to the type of the variable the reference is assigned to. The point of the factory mechanism is to allow you to override the type of the object being created at run-time. Audience Question: Q: At what time user should call drop_objection. How user will know that "life" of raise_objection is over and need to call drop_objection. A: Depends what your code is doing. For example, if you are generating some stimulus, you would call raise_objection before the simulus and drop_objection after a stimulus. Audience Question: Q: can we use modport inside generate block? A: Yes, this is standard SystemVerilog. The only caveat is that some SystemVerilog RTL synthesis tools might not support it. Audience Question: Q: Why do we need to include uvm_macros, and import uvm_pkg separately? A: Just a technicality of SV. "import" is used to import names from a package, "include" is including the contents of a text file that contains some macro definitions. In other words, "import" cannot be used to make macros available Audience Question: Q: whu macros lib called outside package and uv_pkg call inside the package, as both are library file ? A: Because include is just copying text around, whereas import is manipulating the names in some "namespace". With import, you want to restrict the scope of the imported names. When including macros, you don't have that luxury because macro definitions are compiler directives. Audience Question: Q: is it necessary to import uvm_pkg in both top module and my_pkg? A: uvm_pkg contains all the UVM definitions (except for macros), so you need to import it wherever you use any UVM definitions.

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FirststepswithUVMWebinarFridayAugust2nd201310.30amGMTQ&ALog
Audience Question: Q: how to pass the test in run_test when there are multiple tests? A: You can only have one top-level test. You could make a "super-test" that runs all the other tests, then start that. Audience Question: Q: what happens to the new constructor in my_test when run_test(:my_test") is called ? A: run_test("my_test") uses the UVM factory to locate the actual test object, which it then starts as the top-level test.

Audience Question: Q: what if i don't give a drop objection at the end? A: The test only ends when all objections have been dropped. However, you can also set a time-out, or you can "crash out" of the test by causing a fatal error (`uvm_fatal(...)) Audience Question: Q: is it necessary to import uvm_pkg in both top module and my_pkg? A: uvm_pkg contains all the UVM definitions (except for macros), so you need to import it wherever you use any UVM definitions. Audience Question: Q: Is it compulsory to write run_phase and build phase tasks seperately or we can make it in single task A: No. These are pre-defined "common" phases that have to be used for predefined purposes. build_phase builds the UVM component hierarchy, run_phase in effect "runs simulation", i.e. simulation time passes Audience Question: Q: How do see the object in waveform. lets say in VCS or ncsim A: You can do that using UVM transaction recording combined with proprietary features of your particular simulator. VCS and NCSIM both support this kind of transaction viewing. Audience Question: Q: what is mean by UVM_Drain_Time? A: The drain time is an extra bit of time allowed after all objections are dropped before simulation ends. Audience Question: Q: Questa does not need to UVM_HOME to run uvm test A: All the current simulators can either be run using the standard UVM base class library that you download from www.accellera.org, or have their own built-in implementation of UVM (which may be one version out-of-date) that does some tool-specific optimisations. So if you are not using UVM_HOME, you are probably using the build-in version of UVM in your simulator Audience Question: Q: Is it compulsory to write run_phase and build phase tasks seperately or we can make it in single task A: No, you cannot make it a single task. That would defeat the object of the standard phase methods. You need build_phase...connect_phase... ... run_phase .. ... ... Audience Question: Q: is this DUT example is synthesisable ? as it uses uvm_info ? A: The example on the slide is just a dummy DUT so you can play with UVM. It is not meant to be RTL code Audience Question: Q: Any example of uvm component path hierarchy for scope? A: E.g. "*.m_env.m_agent.m_driver" Audience Question: Q: How is UVM different from OVM? A: The very first version of UVM was created by taking OVM 2.0.1 and replacing the string "ovm" with "uvm" (literally). Since that time, UVM has moved on a lot. Today, UVM is the dominant standard. Unless you have legacy OVM code to support, you should probably forget OVM and concentrate on UVM Audience Question: Q: Is drop objection a blocking kind of a statement? e.g i have raised two objections in the order of objection1 followed by objection2 but i drop the objection in the order of objection 2 followed by objection 1 A: No, drop_objection is not blocking.

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FirststepswithUVMWebinarFridayAugust2nd201310.30amGMTQ&ALog
Audience Question: Q: why is the interface declared virtual ? A: An "interface" is the definition of a structural component, much like a module. A virtual interface is, in effect, a reference to an interface instance. Think of a virtual interface as a fancy variable that happens to point to an interface. Audience Question: Q: can we use uvm_info is the synthesizable RTL code ? A: I doubt the situation would ever arise. The simple answer is that `uvm _info is (probably) unsynthesizable. Audience Question: Q: can uvm_config_db be used to retrive parameters in object class instead of component class ? A: The VALUE that is stored in the config db can be of any type at all (bit, int, string, uvm_object, uvm_component, ...). The SCOPE in the config db is a test string that represents a path through the UVM component hierarchy.

Audience Question: Q: how are the characteristics of the interface signals conveyed to the driver? A: Through the virtual interface, which is just a reference from the driver to the SV interface instance. The driver can "see" the variables and wires in the interface through the virtual interface Audience Question: Q: Why is it bad to generate the clock from within a class? A: It badly breaks the SystemVerilog scheduler. Don't go there! Audience Question: Q: If i don't raise an onobjection but still give a drop objection, will the simulation hang? A: I'm not 100% sure what would happen, but it is definitely something you would not want to do. Always make sure every call to raise_objection has exactly one corresponding drop_objection Audience Question: Q: what is finish_on_completion? A: Just a flag to indicate whether or not UVM will call $finish at the end of the test (after the final UVM phase has executed) Audience Question: Q: Can we pass command line arguments to a config variable? A: Yes, the command line processor makes this very convenient Audience Question: Q: can uvm_top.finish_on_completion be called from any other place other than module top? A: Yes, it is irrelevant where you call it from. And it is not very important. Audience Question: Q: Can we set any variable (like : int x) from top level hierarchy to get in low level hierarchy? A: Yes, through a straightforward object reference (obj1.obj2.obj3.property). But this is often really bad practice, because it hurts re-use. So this is where you would use the configuration database instead Audience Question: Q: how will we generate a clock in class A: Never, ever! Always generate the clock in a module. Audience Question: Q: The raise/drop can be done only in test..? A: raise/drop would typically be called from a test, from a sequence, or from a driver. They can be called from anywhere. Audience Question: Q: Does monitor only checks the OUT ports of DUT ? or IN ports can also be checked by monitor ? A: The monitor can check whatever you want. Audience Question: Q: Can i use a global_stop_request instead of raise objection and drop objection? A: global_stop_request is OVM. UVM is (almost) backward-compatible with OVM, but there are some legacy features of OVM that you should not be using in UVM. global_stop_request is one of those. In UVM, use objections. Audience Question: Q: What happens if finish_on_completion == 1 A: $finish is called on completion of the test

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FirststepswithUVMWebinarFridayAugust2nd201310.30amGMTQ&ALog
Audience Question: Q: how driver know when to pull the transactions from the sequencer ? A: The driver will try to grab the next transaction just as soon as it is finished with the previous transaction (or even before that if dealing with pipelined transactions) Audience Question: Q: How it will differ uvm_sequence and uvm_sequence_item A: A sequence is best thought of as a sequence of transactions. A sequence_item can be a single transaction (or another sequence)

Audience Question: Q: Can i use a global-stop_request instead of raise objection and drop objection in test? A: global_stop_request is OVM. UVM is (almost) backward-compatible with OVM, but there are some legacy features of OVM that you should not be using in UVM. global_stop_request is one of those. In UVM, use objections. Audience Question: Q: what is difference between uvm_test_done.raise_objection and phase.raise_objection ? A: uvm_test_done is obsolete, and should no longer be used. Audience Question: Q: For constrained random variables, is it possible to use a seed to obtain many times the same random sequence? A: Yes, definitely. UVM has random stability (the ability to generate the same random sequences after making changes to the code) built-in. You would just set the SV seed on the command line. Audience Question: Q: why is transaction registered in factory using `uvm_object_utils? A: See the previous discussion on the purpose of the factory. Bottom line: always register all components, sequences, and transactions using the factory. Audience Question: Q: what is difference between uvm_component_utils and uvm_component_utils_begin followed by uvm_component_utils_finish A: The *_begin and *_end forms bracket a bunch of field macros, which perform some automation on the fields within the component. Please don't use them unless and until you FULLY understand what they are doing. Audience Question: Q: What happens if finish_on_completion == 0 ? A: $finish is not called at the end-of-test (that was easy ;-) Audience Question: Q: what is the difference between uvm_transaction, uvm_sequence and uvm_sequence_item....and which one should be used to build the transaction class? A: Always extend uvm_sequence_item to define new transactions. There is no reason ever to use uvm_transaction directly. (Think of uvm_transaction as being internal to the UVM library) Audience Question: Q: Should we write individual Score boards for the every module of a SOC or only one is enough for overall SOC? Which is the best practice? A: The answer depends on your application. Scoreboards are generally concerned with end-to-end tests, e.g. sending packets to the DUT through one interface and getting them back through another interface, but in general a scoreboard can do whatever you want it to do. This is a challenging subject, because it is very difficult to give general guidelines. Audience Question: Q: Can we randomize and provide constraint in sequencer/sequence as in sequence_item ? A: Yes, sure. Audience Question: Q: Why we are dropping raise_objection and drop_objection as it is already done in test ? A: The whole point of UVM is re-use, so it is best to make each component as self-contained as possible. Audience Question: Q: drop_objection is similar like a flag ? A: Yes.

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FirststepswithUVMWebinarFridayAugust2nd201310.30amGMTQ&ALog
Audience Question: Q: why to raise and drop the objection in the sequence task body as well as doing in the my_test run phase ? A: The whole point of UVM is re-use, so it is best to make each component as self-contained as possible. Audience Question: Q: what is the difference btn sequencer and sequence A: A sequencer is a UVM component, built during the build_phase. A sequence generates a bunch of transactions during the run phase Audience Question: Q: Why we are dropping raise_objection and drop_objection in sequence as it is already done in test ? A: The whole point of UVM is re-use, so it is best to make each component as self-contained as possible. Audience Question: Q: How we will connect driver and sequencer, if both class driver and sequencer is extended by uvm_component class? A: When you connect components, you are connecting individual objects, not classes. So you connect one instance of uvm_component (the driver) to another (the sequencer) Audience Question: Q: Is a sequence similar to a scenario in VMM? A: Yes.

Audience Question: Q: What is the difference between analysis port and Imp ports? A: A port is used to call functions up/out of a component. An imp is a variation on an export, used to receive incoming function calls. Audience Question: Q: already addr, data are decalred as rand then why need to use seq.randomize ? A: It is the call object.randomize that actually randomizes any variables within the object that are declared with the rand keyword. Audience Question: Q: what is the difference between seq_item_port ,analysis port and tlm port A: A regular TLM port must be connected to EXACTLY on TLM export. An analysis port is like a broadcast mechanism, so one analysis port can be connected to any number of exports, including zero. Audience Question: Q: How do we setup multiple sequences to run? is there a UVM schedular? A: Call the start method of each sequence, in series (begin...end) or in parallel (fork...join). It's easy! Audience Question: Q: Can you explain 2 types of sequencer A: Which 2 types of sequencer? Audience Question: Q: how to access rand variables declared in object class in test case A: object_name.object_name.rand_variable. You do not need to do anything special Audience Question: Q: Does it require to learn OVM for getting expertise in UVM? A: No. UVM was based on OVM. Unless you have a OVM code to maintain, just learn UVM. Audience Question: Q: Can we define more than one sequencer component in an env? If so how it will be useful? A: Yes. Most designs have more than one interface (bus, network, serial, ...), and you would have one sequencer per interface. Audience Question: Q: so you wouldn't recommend starting with OVM now? A: The only reason to start with OVM now is if your company has a bunch of OVM code to maintain. Otherwise, everyone is focussing on UVM Audience Question: Q: What does super.new means? A: It means calling the constructor (new) of the base class (the one the current class is extended from)

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FirststepswithUVMWebinarFridayAugust2nd201310.30amGMTQ&ALog
Audience Question: Q: Is it possible to get a transcript of this webinar? A: I'm sorry we don't produce a transcript, however you can review the webinar through the recorded version. We'll send a link to you on Monday evening next week. Audience Question: Q: What is $cast(tx, rhs) ?what is the purpose ? is it an UVM construct or SV syntax ? A: This is a dynamic cast. It is attempting to cast the type of rhs to the type of tx. It will either work or crash. Audience Question: Q: what is the difference between copy and clone? A: Copy copies the contents of some other object over the top of the current object. Clone creates a brand new object and copies its contents from an existing object. Copy works best in SV (because of some technical limitations of OOP in SV) Audience Question: Q: Sorry i dont have idea about cast or casting A: Cast just means converting from one data type to another data type Audience Question: Q: when to use sformatf , psprintf, psdisplay ? A: Non-issue, really. The standard SystemVerilog call is $sformatf(). Use that. Anything else is just an example. Audience Question: Q: What would be title of next uvm webinar ? A: We will keep you informed by email of forthcoming titles in the EasierUVM webinar series. Thanks for your interest! Audience Question: Q: difference b/w uvm_component and uvm_object? A: Components are organised into a component hierarchy. uvm_object is the base class for (almost) everything in UVM

Audience Question: Q: In my DUT, at the deep level in assertion code $finish gets called due to fatel condition. So the UVM test will stop executing due to this. So in this case how UVm do the reporting mechanism. I think UVM can not prints any report due to $finish in DUT ( fatel error) Is my assumption is correct. A: Yes. If the DUT calls $finish, that will "pull the carpet out beneath the feet of the UVM test bench". Audience Question: Q: The sequence body code you showed did a check for the sequence phase not being null using an 'if' statement. If the result of the check is 'null', then how does this hold off the rest of the sequence code from beign executed ? A: This is recommended practice in UVM. starting_phase is a variable that is optionally set by the parent if it want the child sequence to raise/drop objections. If a parent sequence is dealing with objections itself it would not set starting_phase, in which case the test if(starting_phase != null) in the child sequence would clearly do nothing. Audience Question: Q: Will you also provide Q&A document with the link to the webinar as you always do after every webinar? A: Yes, you can either download the Q&A log now yourself - it is an option in the File drop-down-list. We will also send you a link to it along with a link to the presentation video recording on Monday evening next week. Audience Question: Q: For example I want to create 8 sewuence items and in that want to randomize the address and data fields. Now at the sequencer would it be possible to batch the requests and schedule it before sending it to the driver??? A: Yes, that would be possible. Just put your 8 transactions into an array, randomize them in advance, then pick them out one-by-one within the sequence Audience Question: Q: can i start multiple agents parallely A: Yes, that is the normal way things work. All UVM components run in parallel, and all UVM components can do things. Audience Question: Q: what is the use of $cast? A: $cast is just a dynamic type cast (looking at the value in some variable as if it were of a different type) Audience Question: Q: several uvm_env can be instantiated under a testcase ? A: Yes, if you wanted, although the norm would be to have one top-level env.

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FirststepswithUVMWebinarFridayAugust2nd201310.30amGMTQ&ALog
Audience Question: Q: thanks then is there any mechanism in UVM to report such thing A: No, because that behavior is built into SystemVerilog. Audience Question: Q: What do you suggest if the test needs to control the clock ? i.e. pause it for example A: Just add an enable to the clock generator (which should always be module-based), and wiggle the enable from the UVM test (which you can do) Audience Question: Q: is it possible to see the timing waveforms of transactions in the simulator wave window ? A: Yes. Check out "transaction recording" Audience Question: Q: So in verification using UVM do we create constraint random verification suit (sequencer, driver, checker, etc.) over each and every design module in a system.? A: You could do if you wanted to do block-level tests on each module before integrating them. Or you could hold off and only start verification at the chip level. Audience Question: Q: is it necessary to raise an objection and drop an objection in the pre body or post-nody of a sequence? Can it controlled from the run task in the tests? A: Either or both. The number one thing to understand is that UVM is about re-use, so you try to make each component as re-usable as possible. You've got to understand that first! Audience Question: Q: how do you constrain random()? Maybe an SV question. A: object.randomize() with { a == b; c > d; } Audience Question: Q: why main_phase task in testcase is declared as virtual A: All the standard phase tasks and functions are virtual methods Audience Question: Q: If transaction is yet not ready then what 'get_next_item ' will do?? A: Wait until the transaction is ready Audience Question: Q: is it necessary to raise an objection and drop an objection in the pre body or post-nody of a sequence? Can it contorlled from the run task in the tests? A: Can work either way. Audience Question: Q: why run phase is a task while build and connect phase are functions? A: Because run_phase is the only common phase method that consumes simulation time. Audience Question: Q: I see the benefits of structuring the testbench into functions/classes of sequence, sequencer, driver, monitor etc. Still, this can be easily done without UVM. Same holds for assertions and constraint randomization (right?). So what new feature does OVM brings really to the picture ? A: Re-use, re-use, and re-use. You are absolutely correct that you can do constrained random verification in any language without something like UVM. The point of UVM is to have a standard way to build re-usable verification components, test benches, and tests. Audience Question: Q: what happens with void'(seq.randomize()); where seq represents my sequence object A: seq.randomize() returns 1 if the worked and 0 if it fails (if there is a constraint conflict). void'(...) just discards the returned value. Audience Question: Q: build and connect are called in which simulation phase? A: Uh? build_phase and connect_phase are two UVM phases. They both occur "during simulation" as opposed to during compilation or elaboration.

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FirststepswithUVMWebinarFridayAugust2nd201310.30amGMTQ&ALog
Audience Question: Q: what happens with void'(seq.randomize()); where seq represents my sequence object. What if I remove void casting while randomizing ? A: seq.randomize() returns 1 if the worked and 0 if it fails (if there is a constraint conflict). void'(...) just discards the returned value. Audience Question: Q: Is it recommended to use a global_stop_request instead of raise_objection ,drop_objection in the run task of the test? A: global_stop_request is a relic from OVM and is deprecated in UVM. If you are starting with UVM, you should definitely use objections and forget global_stop_request Audience Question: Q: how the phases in UVM are different from OVM? A: Phases in UVM have been renamed and the semantics considerably extended. Objections (to phases ending) have been made non-optional Audience Question: Q: Is it necessary to call super.new? A: Generally, yes. Audience Question: Q: In uvm_config_db, the type of parameter passed has to be virtual always ? A: Only in the case where we are passing virtual interfaces through the config db, not for any other parameter type. Audience Question: Q: if we use the start and drop objection in the sequence task, then dont need to use in the my_test ? A: You can do either. The objective is to make the verification components and the test self-contained. Audience Question: Q: for $cast , it would be better to use if($cast( ) ) , so that you can break gracefully. A: Yes, that would be good practice. Audience Question: Q: can you please give one example of overriding the type of the object using factory? A: old_object_type::type_id::set_type_override(new_object_type::get_type()); Audience Question: Q: Since the main object of UVM is re-use. It means company can use UVM component in multiple project with little modification if required. So does it mean in future the demand for verification gets declined as verification time gets reduced. A: No, verification demands just keep increasing faster and faster! Audience Question: Q: my_env::type_id::create("my_env",this). Is this the only syntax allowed to instantiate any class before using it in UVM ? A: This is the syntax you should always use to create components, transaction, and sequences. m_env = new ("my_env, this); would work, but is REALLY BAD PRACTICE! Audience Question: Q: is the randomization part of UVM or part of SystemVerilog ? A: Randomization is part of SystemVerilog. UVM uses randomization in a particular way to help ensure random stability (repeatability of tests) Audience Question: Q: is there ia way to convert vmm/ovm to uvm. any script available A: Yes. There is lots of guidance on the web. Audience Question: Q: would it be possible to batch and schedule the sequence items based on first cum first serve basis A: Yes, but the default approach in UVM is not to batch the sequence items, but to generate them just-in-time. But there is nothing to prevent you from batching and using whatever selection algorithm you like. Audience Question: Q: Typically SoC have several peripherals & hence several agents. In this scenario does it makes sense to have a separate scoreboard for each agent ? A: Whatever makes sense for your application. A scoreboard often receives transactions from several agents, but it doesn't have to.

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FirststepswithUVMWebinarFridayAugust2nd201310.30amGMTQ&ALog
Audience Question: Q: What is the use of sequencer? A: A sequencer is a component that is used to generate test stimulus. Audience Question: Q: Why we are dropping raise_objection and drop_objection in sequence as it is already done in test ? A: To make the sequence code self-contained and thus more re-usable. Audience Question: Q: yep but question is at what time drop_objection should be called. User should know when to call & for that he must know when "life" of raise_obejction is over. A: Right. You only raise/drop objections in circumstances when you know when you are busy and when you are waiting on someone else (and prepared to let the test end) Audience Question: Q: why in the slide 14 uvm_macros pkg declaration is missing ? A: The slide is just showing the important bits. You would need to include the macros to get it to compile Audience Question: Q: Why in the slide 14 uvm_macros pkg declaration is missing ? A: The slide is just showing the important bits. You would need to include the macros to get it to compile Audience Question: Q: Is ther any mechanism other than 'uvm_config_db' to set virtual inteface in UVM? A: Yes, do it however you like, but using the config db is best practice. Audience Question: Q: in the example with the driver, there was code to check the values driven. I didn't catch the purpose of this. What is it checking? A: I can't find an example like that. But in principle, for example, the driver could include some low-level protocol checks to make sure that the DUT was setting the right pins at the right times. Audience Question: Q: For one of the above questions, you have answered "A sequencer is a component that is used to generate test stimulus", then what is the sequence an how it differs from sequencer? A: A sequencer is a component (think of a processor), a sequence is a set of stimulus (think of a software program running on that processor) Audience Question: Q: what is the alternate if I am not using set & get methods in environment? A: Just poke values into a variable directly

Audience Question: Q: In my experience, the use of verbose macro-language on top of a language brings confusion and doesn't help re-use. Do you think it is possible to build a simpler class/function library in a company that would be equaly (or better) re-usable even though it wouldn't be industry-standard A: I agree. Some macros in UVM are bad for this reason, and it is better not to use them. But all the macros shown on these slides are unavoidable because they deal with SystemVerilog language issues (typically the need to define a new type and an equivalent text string at the same type). Audience Question: Q: what is the guarantee that clock(slide 24) synchronize to the and other uvm components operation ? A: That's back-to-front. The UVM components should all be synchronized to some clock (or other sync signal) that is ultimately generated in an SV module (like this one) Audience Question: Q: what does "finish_on_completion=1" will do ? What will happen if we are not using it in our top file ? A: It merely means that the UVM library will call $finish at the end of the test. Not a big deal. If you don't use it, $finish will not get called. Audience Question: Q: We are looking for training on introduction to UVM REG ? A: You can check out further information on www.doulos.com, or contact us to buy training (www.doulos.com/contacts).

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