A

B

C

D

AN0

BN0

DN0

CN0

TP1996 RXINDN0 1 PAD PAD PAD PAD 1 1 1 RXINBN0 RXINCN0 RXINAN0

TP2010

PI_EVEN_RIN0N1 PAD PAD

PI_ODD_RIN0N 1

PI_EVEN_RIN0P 1 PAD AP0 BP0 DP0 CP0 RXINDP0 1 PAD PAD PAD PAD 1 1 1 RXINBP0 RXINCP0 RXINAP0 PAD

TP1995 PI_ODD_RIN0P 1

TP2009

PI_EVEN_RIN1N1 PAD AN1 BN1 DN1 CN1 RXINDN1 1 PAD PAD PAD PAD 1 1 1 RXINBN1 RXINCN1 RXINAN1 PAD

TP1986 PI_ODD_RIN1N 1

TP2008

TP1985

TP2007

PI_EVEN_RIN1P 1 PAD AP1 BP1 DP1 CP1 RXINDP1 1 PAD PAD PAD PAD 1 1 1 RXINBP1 RXINCP1 RXINAP1 PAD

PI_ODD_RIN1P 1

NC

TP1988

TP2002

PI_EVEN_RIN2N1 PAD PAD

PI_ODD_RIN2N 1

R0036

AN2

BN2

DN2

CN2

NCR0063

NCR0038

TP1987 RXINDN2 VCOMF 1 PAD R0037 R0064 GND PAD PAD PAD 1 1 1 RXINBN2 RXINCN2 RXINAN2

TP2001

PI_EVEN_RIN2P 1 PAD PAD

PI_ODD_RIN2P 1

01.Gamma

GND AVDD AVDD VCOMF

PI_EVEN_RINCLKN 1 PAD AP2 BP2 DP2 CP2 RXINDP2 1 PAD HAVDD R0091 RXCLKDN 1 PAD VGHC YV1C YV1C R0092 SCL_I SDA_I SCL_GA SDA_GA SCL_GA SDA_GA V1D2 V3D3 PAD PAD PAD CLKAN CLKBN CLKDN CLKCN RXCLKBN 1 RXCLKCN 1 RXCLKAN 1 VGL V3D3 V3D3 VCOMF2 PAD PAD PAD 1 1 1 RXINBP2 RXINCP2 RXINAP2 PAD AVDD

Close to J4

TP1992 PI_ODD_RINCLKN 1

TP2006

NC

PI_EVEN_RINCLKP 1 PAD PAD
5

PI_ODD_RINCLKP 1

5

XVCC

Close to J4

M_VCOMI2

TP1991

TP2005

R0022

R0021

VGMA[1..22]

PANEL_VCC

NCNC

TP1990

TP2004

PI_EVEN_RIN3N1 PAD RXCLKDP 1 PAD VGL VGHC YDIOD YOE 1 1 YCLK YDIOU PAD PAD PAD RXCLKBP 1 RXCLKCP 1 RXCLKAP 1 PAD

PI_ODD_RIN3N 1

U_DB

CLKAP

CLKBP

CLKDP

CLKCP

TP1989

TP2003

PI_EVEN_RIN3P 1 PAD PAD

PI_ODD_RIN3P 1

AN3

BN3

DN3

CN3

PANEL_VCC

TP1994 RXINDN3 1 PAD PAD PAD SCL_GA1 SDA_GA1 PAD PAD PAD 1 1 1 RXINBN3 RXINCN3 RXINAN3

TP2000

PI_EVEN_RIN4N1 PAD PAD

PI_ODD_RIN4N 1

M_VCOMI2 YDIOD YOE U_DB YCLK YDIOU XVCC VGL VGHC VCOMF VCOMF2

PI_EVEN_RIN4P 1 PAD AP3 BP3 DP3 CP3 RXINDP3 1 PAD HAVDD PAD PAD PAD 1 1 1 RXINBP3 RXINCP3 RXINAP3 PAD

TP1993 PI_ODD_RIN4P 1 V3D3 AVDD AN4 BN4 DN4 CN4 M_VCOMI2 U2810 SCL 1 PAD PAD PAD PAD PAD 1 1 1 1 RXINDN4 RXINBN4 RXINCN4 RXINAN4

TP1999

C0003

C0002

C0001

PVCC 1 PAD AP4 BP4 DP4 CP4 RXINDP4 1 PAD YOE YCLK YDIOD YDIOU PAD PAD PAD 1 1 1 RXINBP4 RXINCP4 RXINAP4 PAD VCOMF2 1

SDA

XVCC VGMA[1..22]

XSTB XPOL XDIOB

B0004

B0001

B0002

U2811

TP1978

TP2820

TP2818

M_CHECK 1 PAD PAD 1

WP_E

AG 1 PAD C0006 C0005 C0004 PAD 1

HSYNC_F

VGL

Close to J3,J4

TP2821 TP1979 LVDS_FORMAT 1 PAD C0009 C0008 C0007 XAVDD SCL_E 1 PAD XVCC VGL YV1C V1D2 V3D3 VGHC TP1982 XHAVDD FRC_RST 1 PAD TP1981 TP1983 SDA_E 1 PAD YV1C_S XSTB_S XPOL_S PAD PAD PAD 1 1 1 XIN_S SCL_I SDA_I

TP2819

XVCC

VGHC

VCOMF2 VGMA[1..22] XAVDD XPOL XSTB XHAVDD T1_RVP[4..6] T1_RVN[4..6]

VGMA22 VGMA21 VGMA19 VGMA17 VGMA15 VGMA13 VGMA12 VGMA11 VGMA10 VGMA8 VGMA6 VGMA4 VGMA2 VGMA1 XAVDD XHAVDD T1_RVP[4..6] T1_RVN[4..6] T1_RVP4 T1_RVN4 T1_RVP5 T1_RVN5 T1_RVP6 T1_RVN6

X-BACK/Right

T2_RVP[4..6] T2_RVN[4..6]

T1_RVCLKP T1_RVCLKN T2_RVP4 T2_RVN4 T2_RVP5 T2_RVN5 T2_RVP6 T2_RVN6

YV1C_S

XSTB_S

XPOL_S

B12V

4

4

CIS
GND EXSCL EXSDA R0047 RXINAN0 RXINAP0 RXINAN1 RXINAP1 R0046 RXINAN2 RXINAP2 R0048

03.TCON_S

C177

XIN_S

T1_RVP0 T1_RVN0 T1_RVP1 T1_RVN1 T1_RVP2 T1_RVN2 XSTB_S YV1C_S V3D3 V1D2 XPOL_S T1_RVCLKP T1_RVCLKN T1_RVP[4..6] T1_RVN[4..6] T1_RVP[0..2] T1_RVP[0..2] T1_RVN[0..2] T1_RVN[0..2] T2_RVCLKP T2_RVCLKN

CIS CIS
BD103 RXINAN[0..4] RXINAP[0..4] RXCLKAN RXCLKAP

C178

RXINAN[0..4] RXINAP[0..4]

SW_PVCC

RXCLKAN RXCLKAP T2_RVP[0..2] T2_RVN[0..2]

CIS
RXINAN3 RXINAP3 RXINAN4 RXINAP4 R0045

T2_RVP0 T2_RVN0 T2_RVP1 T2_RVN1 T2_RVP2 T2_RVN2

C106

G2 G1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RXINAN[0..4]

J4

CIS CIS
R101 R0044 2 3 R0049 4 RN001

RXINAP[0..4]

R105 2

NC

1 1 3

T1_LVP[4..6] T1_LVN[4..6]

T1_LVP[4..6] XPOL XSTB T1_LVN[4..6]

CIS
C107

CIS

Q101

CIS
RXINCN0 RXINCP0 R0043 1 2 3 4 RXINCN1 RXINCP1

R104

T1_LVCLKP T1_LVCLKN R0040 RXINCN[0..4] RXINCP[0..4] R0042 T1_LVP[0..2] T1_LVN[0..2] RXCLKCN RXINCN[0..4] RXCLKCP R0039 RXINCP[0..4]

T1_LVCLKP T1_LVCLKN

CIS
RXINCN2 RXINCP2 RXINCN[0..4] RXINCP[0..4] RXCLKCN RXCLKCP PANEL_VCC PAD RXINCN3 RXINCP3 RXINCN4 RXINCP4

IC101 1

S S S G D D D D 8 7 6 5

T1_LVP[0..2] T1_LVN[0..2]

CIS
2 1

PANEL_VCC

C111

R0041

3

R0050

NC

4

B12V

Close to U300

C0022 B0005 C0021 V12

RN002

LVDSORD AGBSEN

LVDSORD AGBSEN 1 PAD 1 YOE_S YOE4_S YOE3_S YCLK_S YDIO_S RST

U_DB

U_DF

YDIOD

YDIOU

XPOL XSTB PAD

U300

High Aging

Normal / Mirror Setting Table

Close to J1
F0002 12Vin1 1 PAD D0004 B3.3VD

Normal

3

3

X L H

O

YOE_S 1

YDIO_S 1

YCLK_S 1

YOE4_S

YOE3_S

RST

PAD

PAD

PAD YOE_S

NC

YDIO_S

YCLK_S

R0071

R0070

XPOL XSTB

O H L

X

Mirror

C0011 C0010

NC

YV1C PAD 1

R0014

R0013

Close to U401

CISCN2615
1 2 3 4 GND B3.3VD G1 G2 MGND1 MGND2 1 2 3 4 B12V

R0023

RXINCLKAP RXINCLKAN RXINAP[0..4] RXINAN[0..4]

RXINCLKCP RXINCLKCN RXINCP[0..4] RXINCN[0..4]

YV1C

R0015

T2_RVP[4..6] T2_RVN[4..6] XOUT_M

12Vin

J5

SCL_I SDA_I GND EXSCL EXSDA

YV1C_M V3D3 V1D2

T2_RVCLKP T2_RVCLKN XPOL_M XSTB_M 04.TCON_M

XSTB_M

YV1C_M V3D3 V1D2

XPOL_M

XOUT_M

T2_RVCLKP

T2_RVCLKN

T2_RVP[4..6]

T2_RVN[4..6]

RXINBN[0..4]

PI_ODD_RIN0N PI_ODD_RIN0P PI_ODD_RIN1N PI_ODD_RIN1P PI_ODD_RIN2N PI_ODD_RIN2P

RXINBP[0..4]

R0060

RXINBN0 RXINBP0 RXINBN1 RXINBP1 RXINBN2 RXINBP2 RXINBN[0..4] RXINBP[0..4] PI_ODD_RINCLKN PI_ODD_RINCLKP PI_ODD_RIN3N PI_ODD_RIN3P PI_ODD_RIN4N PI_ODD_RIN4P PI_EVEN_RIN0N PI_EVEN_RIN0P PI_EVEN_RIN1N PI_EVEN_RIN1P PI_EVEN_RIN2N PI_EVEN_RIN2P RXINBN[0..4] RXINBP[0..4] RXINCLKBN RXINCLKBP

T2_RVP[0..2] R0059 R0061 T2_RVN[0..2] RXINBN[0..4] RXINBP[0..4] RXCLKBN RXCLKBP RXINBN4 RXINBP4 R0058

T2_RVP[0..2] T2_RVN[0..2]

T1_LVP[4..6] T1_LVN[4..6] T1_LVP4 T1_LVN4 T1_LVP5 T1_LVN5 T1_LVP6 T1_LVN6 R0057 2 1 3 R0062

RXCLKBN RXCLKBP RXINBN3 RXINBP3

NC
RN003

4

T2_LVP[4..6] T2_LVN[4..6] RXINDP[0..4] PI_EVEN_RINCLKN PI_EVEN_RINCLKP PI_EVEN_RIN3N PI_EVEN_RIN3P PI_EVEN_RIN4N PI_EVEN_RIN4P WP_E R2764 WP RXINDN[0..4] RXINDP[0..4] RXINDN[0..4] RXINDP[0..4] RXINCLKDN RXINCLKDP RXINDN0 RXINDP0 RXINDN1 RXINDP1 RXINDN2 RXINDP2 RXCLKDN RXCLKDP RXINDN3 RXINDP3 R0056

T2_LVP[4..6] T2_LVN[4..6]

T1_LVCLKP T1_LVCLKN

RXINDN[0..4]

2

2

R0053 R0055

RXINDN[0..4] RXINDP[0..4] RXCLKDN RXCLKDP

T2_LVP4 T2_LVN4 T2_LVP5 T2_LVN5 T2_LVP6 T2_LVN6

T1_LVP0 T1_LVN0 T1_LVP1 T1_LVN1 T1_LVP2 T1_LVN2

NC
R0634

T1_LVP[0..2] R0052 I2C_SDA I2C_SCL RXINDN4 RXINDP4 HSYNC R0604 G S D R0615 R0633 T1_LVN[0..2] T2_LVCLKP T2_LVCLKN R0054 2 3 T2_LVCLKP T2_LVCLKN T2_LVP[0..2] T2_LVN[0..2] T2_LVP[0..2] T2_LVN[0..2]

SW_PVCC

Close to U401

FRC_NRESET

MAIN_CHECK

NC

R0051

NC

FRCBlock

1 HSYNC I2C_SDA I2C_SCL SW_PVCC

4 RN004

VGL

XVCC

SCL R2760_DE SDA R2761_DE FRC_RST CIS R657 PVCC CIS R2770 M_CHECK CIS R2765 HSYNC_F R2763 AG CIS R2766

VGHC

XHAVDD

VCOMF2

FRC_NRESET

M_VCOMI2

MAIN_CHECK

VGMA[1..22]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10

1 2 3 4 5 6 7 8 9 PI_ODD_RIN0N 10 PI_ODD_RIN0P 11 PI_ODD_RIN1N 12 PI_ODD_RIN1P 13 PI_ODD_RIN2N 14 PI_ODD_RIN2P 15 16 PI_ODD_RINCLKN 17 PI_ODD_RINCLKP 18 19 PI_ODD_RIN3N 20 PI_ODD_RIN3P 21 PI_ODD_RIN4N 22 PI_ODD_RIN4P 23 24 PI_EVEN_RIN0N 25 PI_EVEN_RIN0P 26 PI_EVEN_RIN1N 27 PI_EVEN_RIN1P 28 PI_EVEN_RIN2N 29 PI_EVEN_RIN2P 30 31 PI_EVEN_RINCLKN 32 PI_EVEN_RINCLKP 33 34 PI_EVEN_RIN3N 35 PI_EVEN_RIN3P 36 PI_EVEN_RIN4N 37 PI_EVEN_RIN4P 38 39 40 41 42 43 44 LVDS_FORMAT 45 46 47 48 49 50 51 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10

X-FRONT/Left

NC NC

XPOL XSTB

R0635

LVDSORD Q0602 SCL_E SDA_E EDID_WP AGBSEN

T2_LVP0 T2_LVN0 T2_LVP1 T2_LVN1 T2_LVP2 T2_LVN2 XAVDD

CIS

CIS

C502

U401

high Aging

R656CIS

MGND2 MGND1

YOE_M

YOE4_M

YOE3_M

YCLK_M

YDIO_M

LVDSORD

CIS CIS

I2C_SCL 4 3 2 1

RST

CIS
R658

I2C_SDA SCL_I SDA_I FRC_NRESET SW_PVCC MAIN_CHECK HSYNC AGING EDID_WP SCL_I SDA_I

CN901

AGBSEN

4 3 2 1

G2 G1

C0017

NC

RST

YCLK_M YOE_M

R0027

R555_DE

NC

YDIO_M R0066

YOE4_M

YOE3_M

VGMA22 VGMA21 VGMA19 VGMA17 VGMA15 VGMA13 VGMA12 VGMA11 VGMA10 VGMA8 VGMA6 VGMA4 VGMA2 VGMA1 YOE R0033 D0006 R0018 XAVDD D0002 V3D3 XHAVDD YDIOD YDIOU C0024 XVCC YCLK R544 R539_DE XDIOF XPOL XSTB D0003

Path balance between U300 &U401

R0025 AGING

NC

PAD

1

R0094

VCOMF2 V3D3 RST 1 PAD 1 R0010 B3.3VD C0026 PAD VGHC C0014 C0013 C0012 VGL

Path balance between U300 &U401

LVDS_FORMAT

NC NC C0015 NC

NC

R0001

XVCC PAD 1 R0028 R0095 YDIOU YCLK V3D3 YOE YDIOD M_VCOMI2 Date:
1

Close to U401

YDIOU YCLK U_DF YOE YDIOD M_VCOMI2 1 GH1 1 GH7 EDID_WP SCL_I SDA_I I2C_SCL I2C_SDA Model Name

G2 G1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

J3
1

1

1

1

1

<Variant Name>

U_DF

PAD

PAD

PAD

PAD

CIS

CIS

R15_OP

R14_OP

NC

8 7 6 5

1 GH6 1 GH11 U0106 1 GH2 VCC A0 WP A1 SCL A2 SDA GND

XVCC

YOE

Size Document Number Custom T315HW02 Wednesday, October 01, 2008 Sheet 1 of 10 Rev

Close to J3

Td(sec) = R(Ω) * C(F) * 0.79 =0.022u * 5.62M * 0.79 = 97mS

Top View
V3 Tcom\MEMC Board
EC02

YCLK

YDIOD

YDIOU

R0020

R0019

1 2 3 4 1 GH8 SCL_I SDA_I 1 GH9 1 GH3

T315HW02 V3 Tcom MEMC Board

1 R0093 1 GH5 GH10 1 GH4

友達光電電視顯示器產品研發處
A

B

C

D

5

4

3

2

1

D

D

AUO Confidential 80 J4 1 80 J3 1

T-CON_1(Slave) AUO-12401 B1

T-CON_2(Master) AUO-12401 B1

GAMMA
C

DC-DC

U0300 1

U0401 1

C

FRC PART [Page: FRC_IO, FRC_DDR and FRC_POWER]
DDR 1 4 1 4 1 J1
B

I2C Connector(4Pin)

IC500 DDR 51

CN901

Power Connector(4Pin)

LVDS Connector(51Pin)

CN2615
B

A

A

<Variant Name>

友達光電電視顯示器產品研發處
Model Name T315HW02 V3 Tcom MEMC Board

Placement
Size C Date:
5 4 3 2

Document Number

Rev

T315HW02 V3 Tcom\MEMC Board
Wednesday, October 01, 2008
1

EC02
of 10

Sheet

1

5

4

3

2

1

AVDD

Layout closely to IC, far from D201 and L201 TI65161: R201=127K; R203=10K; C206=120pF BD8160: R201=127K; R203=10.2K;C206=200pF SW
L0201 D0201

NC
S D
Q0201

15.73±0.08V 410mA(avg)/680mA(peak)
AVDD_F
R0225 AVDD

PANEL_VCC

Vo1

D

R0201 C0201 C0202 C0203 C0204 C0213

G

1

PAD

R0221

D

R0220 C0214 C0215 C0216 C0217 C0218

C0206 R0202

C209: AVDD soft-start time control TI65161: R213=0 ; C207=22n BD8160: R213=7.5K; C207=2.2n
C0207 R0213 U0201 C0209 R0212

C201, C202 put closed to L201

1

FB

SS

28

R0203

2

COMP

GD

27

GD

Vo1
C0208

3

OS

DLY2

26

C0210

C210: AVDD and VGH delay time control C211: VGL delay time control

4

SW

DLY1

25

C0211

Trace overlapping

SW

5

SW

REF

24

REF

C0256

6

D0207
C

NC NC NC

PGND

GND

23

C0212

7

D0206

PGND

AVIN

22
C

C109 put closed to Pin 8 Vo1
C0255 D0205 D0204 C0251 PANEL_VCC C0252 C0231

8

SUP

VINB

21

PANEL_VCC

R0230

9

EN2

VINB

20

C0230 V3D3

DRP

NC

1

PAD

R0231

C0261

C0258

C0257

VGL

J
C0254

11

K
R0211

DRN

SWB

18
C0232

L0202

1

VGL

D0203 R0223

A

C0253

C230 put closed to Pin 22

C231 put closed to Pin 20

PAD

R0224

10

19

VGH

1

Layout close to IC
PANEL_VCC

3.3V 1000mA(avg)/1200mA(peak)
V3D3_F
R0222

R207

PAD

12

FREQ

BOOT

17
D0202

V3D3

V3D3 V1D2

REF

R0208

13

FBN

EN1

16

PANEL_VCC

C0233

C234

R0204 C0235 U0302

PAD

Current limit R to reduce inrush current during YV1C switch

VGL

1.2V 1000mA(avg)
V1D2
V1D2

14

G1

Layout closely to Pin13 and far from D203, D204, D205,D206 and D207 TI65161: R207=49.9K; R208=10K BD8160: R207=61.2K; R208=10K
U0204

G1

Vin

GND

FBP

FBB

15 I Vout O
V1D2_F

R0262

R0205 C0236

G

C237

C238

12

11

GND

G1 VGH VGHM

GND

G1

R0209

GND Layout closely to pin15 and far from L202 and D202 TI65161: R204=191K; R205=110K; C235=10pF BD8160: R204=191K; R205=110K; C235=68pF

1

250mA(avg)
B

VGH
VGHM R0227

1 2 3

VFLK CD VDPM GND VD

10 9 8 7

GND

YV1C
B

VGHC

R0252

R0251

R0250

GND

NC

R0228 C0259

NC

SVGHM RE

R0210 C0275

4

C0260

C0270

NC
R0253 R0254 R0255

5

6

R0257 R0249 R0248 AVDD

R0258

AVDD

Layout close to Pin14 and far from D203, D204, D205,D206 and D207 TI65161: R209=226K; R210=10.2K BD8160: R209=226K; R210=10.2K

1/2 AVDD soft-start
U0208

close pin7
EN COMP FB G1 GND 8 7 6 5

1
C0263 PANEL_VCC C0626 C0264

SS BST VIN SW

close pin6
R0261

2 3 4

VFB=0.9V
R0260

R0259 C0271 C0268

G1

HAVDD

PAD

L0203

MAX : 3.2 mm
HAVDD_F R0256

7.02±0.1V 410mA(avg)/680mA(peak)
HAVDD HAVDD

D0208
A

C0265

NCC0266

C0267

1

A

<Variant Name>

友達光電電視顯示器產品研發處
Model Name T315HW02 V3 Tcom MEMC Board

DC-DC
Size Document Number Custom T315HW02 Date:
5 4 3 2 1

Rev

V3 Tcom\MEMC Board
Sheet 1 of 10

EC02

Wednesday, October 01, 2008

5

4

3

2

1

VGMA_REF PAD

AVDD
R0101 REFB1 R0107 C0125 R0106 C0101 VGMA1 1 VGMA[1..22] VGMA[1..22] R0171

R0156 MPVGMA1

1

R0100 AVDD AVDD VGMA_REF R0105 C0124 GND GND

NC
8 7 6 5

VGMA1

MPVGMA13 1 MPVGMA12 2 MPVGMA11 3 MPVGMA10 4

NC
RN108

8 7 6 5

VGMA13 VGMA12 VGMA11 VGMA10

NC
AVDD_MGA C0170 C0171 MPVGMA8 1 MPVGMA6 2 MPVGMA4 3 MPVGMA2 4

PAD

Close to U103 pin38

Close to U103 pin32
REFB2 REF_F11 R0115 C0117 C0102

C

R0108

REF_F1 CATH PAD 1 REF_F1 C0115 R0112 ANODE U0104

REF_F11 PAD 1

VG1 VGMA2 1

NC
RN107

VGMA8 VGMA6 VGMA4 VGMA2

MPVGMA21 1 MPVGMA19 2 MPVGMA17 3 MPVGMA15 4

NC
RN109

8 7 6 5

VGMA21 VGMA19 VGMA17 VGMA15

D

VZREF PAD 1 R0113 R REF

PAD

D

MPVGMA2

REFB4 4 3 2 1 5 6 7 8 RN104 C0103

MPVGMA1

VG2 VGMA4 1

R0157 R0172 MPVGMA22

NC

VGMA22

A

R0118

Close to U103 pin23 Close to U103 pin29
REF_F22 PAD 1 REF_F22 R0123 C0116 REF_F12 PAD 1 REF_F12 R0124 C0118 REFB8 R0126 R0127 REFB6

PAD

R0114

R0120

R0173

14

13

12

11

10

9

8

VG4 VGMA6 C0104 1

U0105 VDD_AMP VCOM_FB R0174 VCOM 7 6

NC NC

VCOMF2

GMA2

GMA1

GMA0

AGND

PAD

MPVGMA4 MPVGMA6 MPVGMA8 MPVGMA10 MPVGMA11 AVDD_MGA

15 16 17 18 19 20 21

GMA3 GMA4 GMA5 GMA6 GMA7 AVDD

AVDD

V3D3

Close to U103

VG6 VGMA8 C0105 1

GND_AMP DVDD A0 SDA SCL GMA10 GMA11 GMA12 GMA13 GMA14 GMA8 GMA9 GMA15 G1

R0175 5 R0176 4 3 2 1 MPVGMA22 R0180 R0181 V3D3_MGA C0174 C0173

NC

REFB1

Positive Gamma Value
R0103

REFB10 C0106

VG8 VGMA10 1

PAD

AGND

PAD

22

23

24

25

26

27

28

G1

Close to U103 pin30
REF2 PAD 1 R0110
C

MPVGMA12

MPVGMA13

MPVGMA15

MPVGMA17

MPVGMA19

REF_F2 AVDD C0119

REFB11 4 3 2 1 REFB12 C0108 5 6 7 8 RN105 C0107

VG10 VGMA11 1

MPVGMA21

SCL_GA

R0104

REF4 PAD 1

R0111 REF_F4 REF_F6 REF_F8 REF_F10 REF_F11 REF_F4 R0116 AVDD 36 35 34 33 32 31 30 29 28 27 26 25 REF_F12 REF_F13 REF_F15 REF_F17 REF_F19

VG11 VGMA12 1

PAD

R0177

SDA_GA R0178

C

Max9669 Programmable Gamma Buffer
R0169 VCOMF 11 G1 11 U108B 10 7 9 11 U108C 12 8 13 U108D

V3D3_MGA

11

U108A R0179 1 VCOMF2

REF6 PAD 1

R0117 R0146 REF_F6 R0144 R0121 VCOMF R0122 R0145 AVDD REF_F2 REF_F1 C0127 VCOMI

U0103

NC
R0170 AVDD_MGA

PAD

3 2

+ 4

Close to U103 pin22
24 23 22 21 20 19 18 17 16 15 14 13 REF_F21 REF_F22 AVDD C0126 REFB22 REFB21

Close to U103 pin43
REF_F8 C0123

REF8 PAD 1 R0125 VCOMF2 R0128 REF10 PAD 1 R0129 R0130 REF_F10 R0147

Mo Lo Ko Jo Io Ho VSS VDD Go Fo Eo Do

C0120

PAD

VCOMO REFB1

37 38 39 40 41 42 43 44 45 46 47 48

Li Ki Ji Ii Hi VSS VDD Gi Fi Ei Di Ci

REFB13 C0109

VG12 VGMA13 5 1 6 PAD

NC
C0163

Mi Ni Vcomi N.C. N.C. N.C. VDD VSS VDD VSS Vcomo No

Bi Ai VDD VSS Ao VSS Bo N.C. N.C. VDD N.C. Co

+ 4

+ 4

+ 4

14

REFB15 C0110 REFB19

VG13 VGMA15 1

AVDD_MGA

VCOMF R0148 V3D3 BANK_SEL R0161

C0122

REFB17 4 3 2 1 5 6 7 8 RN106 C0111

VG15 VGMA17 1 R0167

REFB2 REFB4 REFB6 REFB8 REFB10 REFB11

REFB12 REFB13 REFB15 REFB17

Close to U103 pin47
REFB11 AVDD C0121 REFB19 C0112

PAD

Close to U103 pin15

AVDD
R0166

NC
R0168

VG17 VGMA19 1

1

PAD

NCR0160 NC

1 2 3 4 5 6 7 8 9 10 11 12

AVDD_GA

C0162 R0162 R0159
B

NC
AVDD_GA R0163

B

PAD

C0161 V3D3 R0158 C0160 R0165 R0164 C0156 VCOMF2

REFB12

Negative Gamma Value
R0131

REFB21

VG19 VGMA21 C0113 1

Close to U103 pin8

NC

REF13 PAD 1

R0132 REF_F13 R0143 R0133

VG21 32 31 30 29 28 27 26 INNCOM REFB22 C0114 VGMA22 1 PVGMA1 PVGMA2 PVGMA4 PVGMA6 C0157 AVDD_GA 1 R0137 REF_F17 6 7 SDA_GA U0102 SCL_GA 8 G1 8 R0182 7 6 5 R0183 PVGMA8 25 OUTCOM

REF15 PAD 1

PAD

R0134 REF_F15 R0135 R0136

REF17 PAD

VG1 & VG22 => L255. VG2 & VG21 => L254 VG4 & VG19 => L223 VG6 & VG17 => L128 VG8 & VG15 => L32 VG10 & VG13 => L1 VG11 & VG12 => L0

PAD

BANK_SELECT

STD_REG

SET

INPCOM/DVROUT

REFIN

DVDD

1 2 3 4 5

OUT1 OUT2 OUT3 OUT4 GND AVDD OUT5

OUT18 OUT17 OUT16 OUT15 GND AVDD OUT14

24 23 22 21 20

PVGMA22 PVGMA21 PVGMA19 PVGMA17 C0159

VG22

U101

19 18 17

AVDD_GA

V3D3

OUT10

OUT11 PVGMA13 15

REF19 PAD
A

R0138 1 R0139 REF_F19 R0155 PVGMA22 R0154 VGMA22 PVGMA1 PVGMA13 PVGMA12 PVGMA11 PVGMA10 1 2 3 4 8 7 6 5 VGMA13 VGMA12 VGMA11 VGMA10 C0158 1 2 3 RN102 4 REF_F21 R0141 PVGMA8 PVGMA6 PVGMA4 PVGMA2 1 2 3 4 8 7 6 5 VGMA8 VGMA6 VGMA4 VGMA2 VDD PA5(HS) PA4(HS) PA3(HS) VSS PA0(HS) PA1(HS) PA2(HS)

G1

9

PVGMA10 10

PVGMA11 11

12

13

PVGMA12 14

NC

NC

VGMA1

NC

PVGMA15 16

OUT12

OUT6 OUT7 OUT8 OUT9 SDA SCL

OUT13

A

REF21 PAD 1

R0140

<Variant Name> PVGMA21 PVGMA19 PVGMA17 PVGMA15 1 2 3 4

NC
RN101

NC
RN103

PAD

PAD

PAD

R0142 REFB22

PAD

8 7 6 5

VGMA21 VGMA19 VGMA17 VGMA15

友達光電電視顯示器產品研發處 ISL24813 Programmable Gamma Buffer
Model Name T315HW02 V3 Tcom MEMC Board

1

1

1

1

Gamma
Size Document Number Custom T315HW02 Date: Rev

PA5_A

PA4_A

PA3_A

PA2_A

V3 Tcom\MEMC Board
Sheet 1 of 10

EC02

Wednesday, October 01, 2008
1

5

4

3

2

5

4

3

2

1

T2_lVCLKP

T2_RVCLKP

T2_RVCLKN

T2_LVCLKN

T2_LVP[4..6]

T2_RVP[4..6]

T2_RVP[0..2]

T2_LVN[4..6]

T2_LVP[0..2]

T2_RVN[4..6]

T2_RVN[0..2]

T2_LVN[0..2]

Data Mapping Setting Table PIX_SFT_EN MODE41 0 1 0 0 0 0 0 0 0 1 1
D

T2_LVCLKN

T2_LVCLKP

T2_RVCLKN

T2_RVCLKP

Closed to pin65 of U401
T2_LVN[0..2] T2_LVP[0..2] VDD_V3D3_M C0403 C0402 C0404 RN0401

D

FRVS1 FRVS2 BRVS CHPXF CHPXB

T2_RVN[4..6]

T2_RVN[0..2]

T2_RVP[4..6]

T2_RVP[0..2]

T2_LVN[4..6]

T2_LVP[4..6]

4 1

Close to U401
4 3

RN0400 VDD_V1D2_M

2

3

Close to U401

CHFB
C0406 C0407

1

2

C0405

CHML CHRB CHPN

For
VDD_V1D2_M

KME use
T2_RVP0 T2_RVN0 T2_RVP1 T2_RVN1 T2_RVP2 T2_RVN2 T2_LVP4 T2_LVN4 T2_LVP5 T2_LVN5 T2_LVP6 T2_LVN6 T2_LVP0 T2_LVN0 R0402 VDD_V3D3_M VDD_V1D2_M T2_LVP1 T2_LVN1 T2_LVP2 T2_LVN2

VDD_V3D3_M VDD_V1D2_M

G1

U0401
C

When ODEN is low or OPEN, OD_EN(Internal Register ) 0 : OD disable 1 : OD enable
R0403

120HZ Closed to pin56 of U401
L0401 V3D3 C0430 C0410 C0411
C

C0409 C0408

96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

NC
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 OSCSEL_M 126 127 128 RV2N RV2P GND VDDM RV1N RV1P RV0N RV0P LV7N LV7P LV6N LV6P GND VDDM LV5N LV5P LV4N LV4P GND VDDC12 LVCLKN LVCLKP LV3N LV3P LV2N LV2P GND VDDM LV1N LV1P LV0N LV0P G1 PV3P RV3N VDDWR PFCAP RVCLKP RVCLKN RV4P RV4N RV5P RV5N VDDM GND RV6P RV6N RV7P RV7N GND RMLVDS VDDIO REXT VDDC12 VDDC12 GND VDDIO GND GND VDDIO GND PWM OSCSEL XIN XOUT TEST SWAPL GOAEN SPDEN DCREN ODEN AGBSEN LVDSORD VDDIO GND VDDC12 VSEL XSTB XBDO XPOL YDIO YCLK YOE1 YOE2 VDDIO GND YOE3 YOE4 YV1C GND VDDC12 RSTN INSDA INSCL EPWP EXSDA EXSCL 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

When ODEN is high, OD_EN(Internal Register ) 0 : OD enable 1 : OD disable
R0405

R0404

NC
V1D2 V1D2 L0402 T2_RVN6 T2_RVP6 T2_RVN5 T2_RVP5

NC

VDD_V3D3_M

ODEN_M AGBSEN LVDSORD

AGBSEN LVDSORD

C0412 C0413

C0414

C0415

T2_RVN4 T2_RVP4

XSTB_M XPOL_M YDIO_M YCLK_M YOE_M

XSTB_M XPOL_M YDIO_M YCLK_M YOE_M

EPWP_M

VCCE_M

INSDA_M

GND

GND R0407

PAD

PAD

PAD

PAD

VDD_V1D2_M V3D3 V3D3 L0403 C0416 C0417
B

1

1

1

1

R0408 C0418 C0419 XIN_M

PAD

1

RXINO0N RXINO0P RXINO1N RXINO0P RXINO2N RXINO2P VDDL GND RXCLKON RXCLKOP RXINO3N RXINO3P RXINO4N RXINO4P VDDL GND VDDC12 VDDC12 GND RXINE0N RXINE0P RXINE1N RXINE1P RXINE2N RXINE2P VDDL RXCLKEN RXCLKEP RXINE3N RXINE3P RXINE4N RXINE4P

RST INSDA_M INSCL_M EPWP_M EXSDA EXSCL

RST

EXSDA EXSCL

U0402 5 SDA 6 SCL 7 WP 8 VCC R0401 R0409 R0410 R0411

GND A2 A1 A0

4 3 2 1

1

VDD_V3D3_M

PAD

T2

YOE3_M YOE4_M YV1C_M

YOE3_M YOE4_M YV1C_M

INSCL_M

GNDE_M

R0406

AUO12401 K1

On Bottom Layer

B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Closed to pin117 of U401
2 1
Y0401

PAD 1 XOUT_M
XOUT_M

D0401 VDD_V3D3_M GND VDD_V1D2_M VDD_V3D3_M C0420

VDD_V1D2_M VDD_V3D3_M RXINDN0 RXINDP0 RXINDN1 RXINDP1 RXINDN2 RXINDP2 RXINDN3 RXINDP3 RXINDN4 RXINDP4 RXINBN0 RXINBP0 RXINBN1 RXINBP1 RXINBN2 RXINBP2 RXINBN3 RXINBP3 RXINBN4 RXINBP4

C0421

R0412

VDD_V1D2_M C0422 C0401 C0423

Closed to pin8 of U402

3

4
R0413 RXINDP[0..4] RXCLKDN RXCLKDP RXCLKBN RXCLKBP RXINDN[0..4] RXINBN[0..4] RXINBP[0..4]

VDD_V3D3_M C0426 C0425 C0427
A

C0424
A

RXCLKBN

RXCLKBP

RXINBN[0..4]

RXINBP[0..4]

RXINDN[0..4]

RXINDP[0..4]

RXCLKDN RXCLKDP

Closed to pin127 of U401

<Variant Name>

Closed to pin33 of U401

友達光電電視顯示器產品研發處
Model Name T315HW02 V3 Tcom MEMC Board

Tcom(Master)
Size Document Number Custom T315HW02 Date: Rev

V3 Tcom\MEMC Board
Sheet 1 of 10
1

EC02

Wednesday, October 01, 2008

5

4

3

2

5

4

3

2

1

D

D

PI_ODD_RIN0N PI_ODD_RIN1N PI_ODD_RIN2N PI_ODD_RIN3N PI_ODD_RIN4N PI_ODD_RIN0P PI_ODD_RIN1P PI_ODD_RIN2P PI_ODD_RIN3P PI_ODD_RIN4P PI_ODD_RINCLKN PI_ODD_RINCLKP

PI_ODD_RIN0N PI_ODD_RIN1N PI_ODD_RIN2N PI_ODD_RIN3N PI_ODD_RIN4N PI_ODD_RIN0P PI_ODD_RIN1P PI_ODD_RIN2P PI_ODD_RIN3P PI_ODD_RIN4P

PI_ODD_RIN0N PI_ODD_RIN1N PI_ODD_RIN2N PI_ODD_RIN3N PI_ODD_RIN4N PI_ODD_RIN0P PI_ODD_RIN1P PI_ODD_RIN2P PI_ODD_RIN3P PI_ODD_RIN4P PI_ODD_RINCLKN PI_ODD_RINCLKP

RX1B_AN RX1B_BN RX1B_CN RX1B_DN RX1B_EN RX1B_AP RX1B_BP RX1B_CP RX1B_DP RX1B_EP RX1B_CLKN RX1B_CLKP RX3B_AN RX3B_BN RX3B_CN RX3B_DN RX3B_EN RX3B_AP RX3B_BP RX3B_CP RX3B_DP RX3B_EP RX3B_CLKN RX3B_CLKP RX2B_AN RX2B_BN RX2B_CN RX2B_DN RX2B_EN RX2B_AP RX2B_BP RX2B_CP RX2B_DP RX2B_EP RX2B_CLKN RX2B_CLKP RX4B_AN RX4B_BN RX4B_CN RX4B_DN RX4B_EN RX4B_AP RX4B_BP RX4B_CP RX4B_DP RX4B_EP RX4B_CLKN RX4B_CLKP

FRC_IO 05A.FRC_IO RXINAN0 RXINAN1 RXINAN2 RXINAN3 RXINAN4 RXINAP0 RXINAP1 RXINAP2 RXINAP3 RXINAP4 RXINCLKAN RXINCLKAP RXINCN0 RXINCN1 RXINCN2 RXINCN3 RXINCN4 RXINCP0 RXINCP1 RXINCP2 RXINCP3 RXINCP4 RXINCLKCN RXINCLKCP RXINBN0 RXINBN1 RXINBN2 RXINBN3 RXINBN4 RXINBP0 RXINBP1 RXINBP2 RXINBP3 RXINBP4 RXINCLKBN RXINCLKBP RXINDN0 RXINDN1 RXINDN2 RXINDN3 RXINDN4 RXINDP0 RXINDP1 RXINDP2 RXINDP3 RXINDP4 RXINCLKDN RXINCLKDP RXINDN[0..4] RXINBN[0..4] RXINCN[0..4] RXINAN[0..4]

Power B12V B3.3VD VREF B1.8V_DDR RXINAP[0..4] RXINCLKAN RXINCLKAP 05C.FRC_Power B12V B3.3VD VREF B1.8V_DDR GND

FRC_NRESET

FRC_NRESET

C

I2C_SCL I2C_SDA HSYNC MAIN_CHECK SW_PVCC

I2C_SCL I2C_SDA HSYNC MAIN_CHECK SW_PVCC

C

DDR RXINCP[0..4] RXINCLKCN RXINCLKCP

B1.8V_DDR

B1.8V_DDR

VREF

VREF

GND

PI_EVEN_RIN0N PI_EVEN_RIN1N PI_EVEN_RIN2N PI_EVEN_RIN3N PI_EVEN_RIN4N PI_EVEN_RIN0P PI_EVEN_RIN1P PI_EVEN_RIN2P PI_EVEN_RIN3P PI_EVEN_RIN4P
B

PI_EVEN_RIN0N PI_EVEN_RIN1N PI_EVEN_RIN2N PI_EVEN_RIN3N PI_EVEN_RIN4N PI_EVEN_RIN0P PI_EVEN_RIN1P PI_EVEN_RIN2P PI_EVEN_RIN3P PI_EVEN_RIN4P

PI_EVEN_RIN0N PI_EVEN_RIN1N PI_EVEN_RIN2N PI_EVEN_RIN3N PI_EVEN_RIN4N PI_EVEN_RIN0P PI_EVEN_RIN1P PI_EVEN_RIN2P PI_EVEN_RIN3P PI_EVEN_RIN4P PI_EVEN_RINCLKN PI_EVEN_RINCLKP

05B.FRC_DDR

RXINBP[0..4] RXINCLKBN RXINCLKBP
B

PI_EVEN_RINCLKN PI_EVEN_RINCLKP

B3.3VD

RXINDP[0..4] RXINCLKDN RXINCLKDP

GND

GND

B3.3VD

A

<Variant Name>

A

友達光電電視顯示器產品研發處
Model Name Size B Date:
5 4 3 2

T315HW02 V3 Tcom MEMC Board

FRC Top
Document Number Rev

T315HW02 V3 Tcom\MEMC Board
Wednesday, October 01, 2008 Sheet
1

EC02
of 10

1

5

4

3

2

1

PI_ODD_RIN4P PI_ODD_RIN4N

PI_ODD_RIN4P PI_ODD_RIN4N

R619

R611 PI_ODD_RIN3P PI_ODD_RIN3N PI_ODD_RIN2P PI_ODD_RIN2N PI_ODD_RIN3P PI_ODD_RIN3N PI_ODD_RIN2P PI_ODD_RIN2N

R603 IC500C R595

FRC
P_XA_CLK_N P_XA_CLK_P P_XA_RX0_N P_XA_RX0_P P_XA_RX1_N P_XA_RX1_P P_XA_RX2_N P_XA_RX2_P P_XA_RX3_N P_XA_RX3_P P_XA_RX4_N P_XA_RX4_P P_XB_CLK_N P_XB_CLK_P P_XB_RX0_N P_XB_RX0_P P_XB_RX1_N P_XB_RX1_P P_XB_RX2_N P_XB_RX2_P P_XB_RX3_N P_XB_RX3_P P_XB_RX4_N P_XB_RX4_P P_YA_CLK_N P_YA_CLK_P P_YA_TX0_N P_YA_TX0_P P_YA_TX1_N P_YA_TX1_P P_YA_TX2_N P_YA_TX2_P P_YA_TX3_N P_YA_TX3_P P_YA_TX4_N P_YA_TX4_P A16 B16 A13 B13 A14 B14 A15 B15 A17 B17 A18 B18 B22 B21 A19 B19 A20 B20 A22 A21 C22 C21 D22 D21 H22 H21 E22 E21 F22 F21 G22 G21 J22 J21 K22 K21
R501 R502 R503 R504 R505 R506 R507 R508 R509 R510 R511 R512 R513 R514 R515 R516 R517 R518 R519 R520 R521 R522 R523 U2849 R525 R526 R527 R528 R529 R530 R531 R532 R533 R534 R535 R536 RX1B_CLKN RX1B_CLKP RX1B_AN RX1B_AP RX1B_BN RX1B_BP RX1B_CN RX1B_CP RX1B_DN RX1B_DP RX1B_EN RX1B_EP RX2B_CLKN RX2B_CLKP RX2B_AN RX2B_AP RX2B_BN RX2B_BP RX2B_CN RX2B_CP RX2B_DN RX2B_DP RX2B_EN RX2B_EP RX3B_CLKN RX3B_CLKP RX3B_AN RX3B_AP RX3B_BN RX3B_BP RX3B_CN RX3B_CP RX3B_DN RX3B_DP RX3B_EN RX3B_EP RX2B_AN RX2B_AP RX2B_BN RX2B_BP RX2B_CN RX2B_CP RX2B_DN RX2B_DP RX2B_EN RX2B_EP

RX1B_CLKN RX1B_CLKP RX1B_AN RX1B_AP
D

D

PI_ODD_RIN1P PI_ODD_RIN1N PI_ODD_RIN0P PI_ODD_RIN0N

PI_ODD_RIN1P PI_ODD_RIN1N PI_ODD_RIN0P PI_ODD_RIN0N

R1 R579

PI_ODD_RINCLKP PI_ODD_RINCLKN PI_EVEN_RIN4P PI_EVEN_RIN4N PI_EVEN_RIN4P PI_EVEN_RIN4N R618 R610 PI_EVEN_RIN3P PI_EVEN_RIN3N PI_EVEN_RIN2P PI_EVEN_RIN2N PI_EVEN_RIN3P PI_EVEN_RIN3N PI_EVEN_RIN2P PI_EVEN_RIN2N

R602 RX4B_EP RX4B_EN RX4B_DP RX4B_DN RX4B_CP RX4B_CN RX4B_BP RX4B_BN RX4B_AP RX4B_AN RX4B_CLKP RX4B_CLKN

R594 PI_EVEN_RIN1P PI_EVEN_RIN1N PI_EVEN_RIN0P PI_EVEN_RIN0N PI_EVEN_RIN1P PI_EVEN_RIN1N PI_EVEN_RIN0P PI_EVEN_RIN0N

R586

R578
C

PI_ODD_RIN4P PI_ODD_RIN4N PI_ODD_RIN3P PI_ODD_RIN3N PI_ODD_RIN2P PI_ODD_RIN2N PI_ODD_RIN1P PI_ODD_RIN1N PI_ODD_RIN0P PI_ODD_RIN0N PI_ODD_RINCLKP PI_ODD_RINCLKN PI_EVEN_RIN4P PI_EVEN_RIN4N PI_EVEN_RIN3P PI_EVEN_RIN3N PI_EVEN_RIN2P PI_EVEN_RIN2N PI_EVEN_RIN1P PI_EVEN_RIN1N PI_EVEN_RIN0P PI_EVEN_RIN0N PI_EVEN_RINCLKP PI_EVEN_RINCLKN R537 R538 R539 R540 R541 R542 R543 U2850 R545 R546 R547 R548

M1 M2 L1 L2 J1 J2 H1 H2 G1 G2 K1 K2 F1 F2 E1 E2 C1 C2 B1 B2 A1 A2 D1 D2 T21 T22 R21 R22 N21 N22 M21 M22 L21 L22 P21 P22

PI_EVEN_RINCLKP PI_EVEN_RINCLKN

P_ZB_RX4_P P_ZB_RX4_N P_ZB_RX3_P P_ZB_RX3_N P_ZB_RX2_P P_ZB_RX2_N P_ZB_RX1_P P_ZB_RX1_N P_ZB_RX0_P P_ZB_RX0_N P_ZB_CLK_P P_ZB_CLK_N P_ZA_RX4_P P_ZA_RX4_N P_ZA_RX3_P P_ZA_RX3_N P_ZA_RX2_P P_ZA_RX2_N P_ZA_RX1_P P_ZA_RX1_N P_ZA_RX0_P P_ZA_RX0_N P_ZA_CLK_P P_ZA_CLK_N P_YB_TX4_P P_YB_TX4_N P_YB_TX3_P P_YB_TX3_N P_YB_TX2_P P_YB_TX2_N P_YB_TX1_P P_YB_TX1_N P_YB_TX0_P P_YB_TX0_N P_YB_CLK_P P_YB_CLK_N

RX1B_BN RX1B_BP RX1B_CN RX1B_CP RX1B_DN RX1B_DP RX1B_EN RX1B_EP RX2B_CLKN RX2B_CLKP

RX3B_CLKN RX3B_CLKP RX3B_AN RX3B_AP RX3B_BN RX3B_BP RX3B_CN RX3B_CP RX3B_DN RX3B_DP RX3B_EN RX3B_EP
C

RX4B_EP RX4B_EN RX4B_DP RX4B_DN RX4B_CP RX4B_CN RX4B_BP RX4B_BN RX4B_AP RX4B_AN

B3.3VD

B3.3VD C501

B3.3VD

RX4B_CLKP RX4B_CLKN B3.3VD

CIS
IC503 R627 R628 R629 R630 R631 R632 R5841_DE R5842_DE R584

R513_DE

NC

NC
IC500B

R633

FRC
SSDA SSCL MSDA MSCL V PWM H TRST_N TMS TDO TDI TCLK XOUT XIN N2 N1 M3 N3 A12 B11 B12 A3 A5 B5 A4 B4 P1 R1

I2C_SDA I2C_SCL EEPROM_SDA EEPROM_SCL

EEPROM_SCL EEPROM_SDA

8 7 6 5

VCC WP SCL SDA

NC A1 A2 GND

1 2 3 4

NC
R524

R634 R635 R636 R637_DE R638 R639_DE R640

B

MAIN_CHECK SW_PVCC

T_RST MAIN_CHECK SW_PVCC FRC_NRESET

R582 R590 R598 R606 R614 R622 R583 R591 R599 R607 R642 R615 R623 R644 GND R585_1 R585

FRC_NRESET

A11 B10 A10 B9 A9 B8 A8 B7 A7 P2 P3 R2 R3 B6 A6

B

GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 RESET_N TM

NC
HSYNC HSYNC

NC

HSYNC

1
R641_DE R643

PAD

TP501

NC
1 PAD
TP502

CIS
X501

1
B3.3VD

2

B3.3VD R588 IC589

/RESET

GND

1
C586_1
A

VDD

3
C586
A

2

<Variant Name>

友達光電電視顯示器產品研發處
Model Name T315HW02 V3 Tcom MEMC Board

FRC IO
Size C Date:
5 4 3 2

Document Number

Rev

T315HW02 V3 Tcom\MEMC Board
Wednesday, October 01, 2008
1

EC02
of 10

Sheet

1

5

4

3

2

1

L102 GND B12V B3.3VD B1.8V_DDR VREF GND B12V B3.3VD B1.8V_DDR VREF C122_1 B1.05V_DLL B3.3V_OSC B3.3VD B2.5V_VDDL_PLL B12V

CIS
IC104

TP_B1D05V

CIS
SS EN GND COMP FB 8 C130_OP 7 6 5 R108

PAD

1

B1.05V

CIS DE
BD109_DE V1.05VF NC

CIS BD108 CIS BD2007

CIS
BD129

R113_2

1 2

BS IN SW GND

C604

C605

C588

C589

C505

C506

C507

C508

C509

C503

C504

3

CIS
C156

CIS
C127 4

CIS
C145_1 C134

CIS
C2728

CIS
C2729

CIS
C2730

CIS
C2731

CIS
C2732

CIS
C2733

CIS
C2734

CIS
C2735

VREF
D

C129

MGND1

IC500E

FRC
VDD105_S VDD105DLL VDDLZ25PLL VDDLZ25 VDDLY25PLL VDDLY25 VDDLY25 VDDLX25PLL VDDLX25 VDDLX25 VDD33OSC VDD33 VDD33 VDD33 VDD18 VDD18 VDD18 VDD18 VDD18 VDD105PLL VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 J7 T13 H4 J4 K19 M19 H19 D14 D16 D12 P4 D8 D7 M4 P16 T15 T12 T8 P7 R4 T9 T16 R16 R9 P9 J16 J9 H16 H9 G16 G9 R15 B2.5V_VDDL

CIS

D

1

C688

C689

MGND1

C

W12 G7 G14 H7 H14 J10 J13 J14 P14 R7 R14 T7 T14 G8 G15 H8 H15 J8 J15 K9 K10 K13 K14 N9 N10 N13 N14 P8 P10 P13 P15 R8

DRAM_VREF VDD105 VDD105 VDD106 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105 VDD105

CIS
C157

CIS
C158 R118_1

R119_1 C148_1_OP C149_1_DE

D105_1

NC

C510

C511

C512

C513

C514

C515

C516

C517 C146_1

2

CIS

CIS

CIS

CIS

TP_B3D3V B1.8V_DDR

CIS
BD120

CIS
R113_OP

R157_DE

CIS
C518 B1.05V_MPLL B1.05V_PLL

CIS
C519

CIS
C520

CIS
C521

CIS
C522

CIS

PAD

NC
CIS
C122

1

CIS
BD2711

B3.3VD

CIS
BD2713

B3.3V_OSC

CIS L103 CIS
IC110

CIS
R114

CIS
C612

CIS
C613

CIS
C523

CIS
C524 R113_1 1 2

CIS CIS
C2788 SS EN GND COMP FB 8 C147_OP 7 6 5

CIS
C2789

BS IN SW GND

CIS
R115

C145

CIS
C159 B1.05V

CIS
C120

3

CIS
C121

4

CIS
C152

CIS
C153

CIS
C2736

CIS
C2737

CIS
C2738

CIS
C2739

CIS
C2740

CIS
C2741

CIS
C2742

CIS
C2743
C

CIS
R118 1

CIS

C525

CIS

C526

C527

CIS

CIS

C528

CIS

C529

C530

CIS

C531

CIS

CIS
C160

CIS
U2841

CIS
DE

CIS
R119

D105

CIS

CIS

CIS
IC500D

FRC
CIS 47NF/10%/16V/X7R/0603
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS105MPLL VSS105PLL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS33OSC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W19 W18 W17 W16 W15 W14 W13 W11 W10 W9 W8 W4 V19 V4 U22 U20 U19 U4 U3 U2 T20 T19 T11 T10 T4 T3 T2 R20 R19 R13 R12 R11 R10 P20 P19 P12 P11 N20 N19 N16 N15 N12 N11 N8 N7 N4 M20 M16 M15 M14 M13 M12 M11 M10 M9 M8 M7 L20 L19 L16 L15 L14 L13 L12 L11 L10 L9 L8

C146 2

C148_OP C149_DE

NC

B

A

C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D3 D4 D5 D6 D9 D10 D11 D13 D15 D17 D18 D19 D20 E3 E4 E19 E20 F3 F4 F19 F20 G3 G4 G10 G11 G12 G13 G19 G20 H3 H10 H11 H12 H13 H20 J3 J11 J12 J19 J20 K3 K4 K7 K8 K11 K12 K15 K16 K20 L3 L4 L7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS105_S VSS VSS VSS VSS VSS VSS VSS VSS VSS

CIS
C536

CIS
C537

CIS
C539

CIS
C541

CIS
C542

CIS
C543

CIS
C544 TP_B2D5V B3.3VD PAD

CIS
L116

B2.5V_VDDL

CIS 10NF/10%/50V/X7R/0603
CIS
U501

CIS
IC102 GND 1 3

CIS
U2842

CIS
C108

CIS
C538

CIS
C540

CIS
U502

CIS
U503

CIS
U504

CIS
U505

Vin

Vout

1

CIS
C112

2

CIS
L117

B2.5V_VDDL_PLL

CIS
C163

CIS
C183

CISBD160 CIS
C161

B1.05V_MPLL

CIS 100NF/10%/16V/X7R/0603
CIS
C162
B

B1.05V

CIS
C532

CIS
C533

CIS
C534

CIS
C535 B3.3VD

CIS
L111 1 IC109 IN GND /EN FB 4 OUT 5 V1.05VF

CISBD163 CIS CIS CIS
R140 C192_2 C190 C190_1 C190_2 R137 C164

B1.05V_DLL

CIS
C195

CIS
C194 C191

CIS
C196_1

CIS
C196

2

CIS
C165

CIS
C125 3

CIS

CIS
R125

CIS CIS
R141 C192

CISBD2712 CIS
C189 1

B1.05V_PLL

CIS
C2748

TP_B1D8V PAD

TP_B1D05V_PLL B1.8V_DDR

B3.3VD

CIS
IC107 ADJ 3 Vin Vout 2 R142 R138

L112

1

CIS

PAD

A

1

CIS

CIS
R139

CIS CIS CIS
C101

CIS
C102 <Variant Name>

CIS
C109

C103

CIS
R143 CIS

C014

CIS

C105

友達光電電視顯示器產品研發處
Model Name T315HW02 V3 Tcom MEMC Board

FRC Power
Size Document Number Custom T315HW02 Date: Rev

V3 Tcom\MEMC Board
Sheet 1 of 10
1

EC02

Wednesday, October 01, 2008

5

4

3

2

5

4

3

2

1

FRCD_DQS0_N

FRC_DM0 FRCD_DQS0_P

FRC_DQ10

FRC_DQ13

FRC_DQ6

FRC_DQ7

FRC_DQ1

IC500A FRCD_ADDR[0..12] FRCD_ADDR0 FRCD_ADDR1 FRCD_ADDR10 FRCD_ADDR11 FRCD_ADDR12 FRCD_ADDR2 FRCD_ADDR3 FRCD_ADDR4 FRCD_ADDR5 FRCD_ADDR6 FRCD_ADDR7 FRCD_ADDR8 FRCD_ADDR9 FRCD_BA0 FRCD_BA1 FRCD_BA2 FRCD_NCAS FRCD_CLK FRCD_NCLK FRCD_CLKE FRCD_NCS FRC_DM0 FRC_DM1 FRC_DM2 FRC_DM3 FRC_DQ[0..31] FRC_DQ0 FRC_DQ1 FRC_DQ10 FRC_DQ11 FRC_DQ12 FRC_DQ13 FRC_DQ14 FRC_DQ15 FRC_DQ16 FRC_DQ17 FRC_DQ18

FRC
W7 W6 W5 AA13 AB14 AA12 AB4 AA4 AA3 Y3 AA22 AB22 AA21 AB20 AA18 W20 W22 AA17 U21 AB16 AA5 Y1 AA20 Y6 W1 AA1 Y4 W2 Y5 AA6 W3 AB6 U1 V21 V3
FRCD_NWE FRCD_NRAS FRCD_ODT FRCD_DQS3_N FRCD_DQS3_P FRCD_DQS2_N FRCD_DQS2_P FRCD_DQS1_N FRCD_DQS1_P FRCD_DQS0_N FRCD_DQS0_P FRC_DQ9 FRC_DQ8 FRC_DQ7 FRC_DQ6 FRC_DQ5 FRC_DQ4 FRC_DQ31 FRC_DQ30 FRC_DQ3 FRC_DQ29 FRC_DQ28 FRC_DQ27 FRC_DQ26 FRC_DQ25 FRC_DQ24 FRC_DQ23 FRC_DQ22 FRC_DQ21 FRC_DQ20 FRC_DQ2 FRC_DQ19

B1.8V_DDR

FRC_DQ0

VTT_FRC

D

NC1 NC3 NC2 A12 [VDD] [VSS] A8 A11 A9 A7 A4 A6 A5 A3 [VSS] [VDD] A0 A2 A1 A10/AP /CS

AA9 AB8 AA15 AA16 Y16 AA8 Y9 Y8 AA7 Y7 AA14 Y14 Y15 AA11 Y11 Y10 Y13 AA10 AB10 Y12 AB12 Y20 Y19 AB1 Y2 V20 Y17 AB21 AA19 Y18 W21 AB18 Y21 AB2 V2 AA2

DRAM_A0 DRAM_TEST_D2 DRAM_A1 DRAM_TEST_D1 DRAM_A10 DRAM_TEST_ANALOG DRAM_A11 DRAM_WE_N DRAM_A12 DRAM_RAS_N DRAM_A2 DRAM_ODT DRAM_A3 DRAM_DQS3_N DRAM_A4 DRAM_DQS3 DRAM_A5 DRAM_DQS2_N DRAM_A6 DRAM_DQS2 DRAM_A7 DRAM_DQS1_N DRAM_A8 DRAM_DQS1 DRAM_A9 DRAM_DQS0_N DRAM_BA0 DRAM_DQS0 DRAM_BA1 DRAM_DQ9 DRAM_BA2 DRAM_DQ8 DRAM_CAS_N DRAM_DQ7 DRAM_CK DRAM_DQ6 DRAM_CK_N DRAM_DQ5 DRAM_CKE DRAM_DQ4 DRAM_CS_N DRAM_DQ31 DRAM_DM0 DRAM_DQ30 DRAM_DM1 DRAM_DQ3 DRAM_DM2 DRAM_DQ29 DRAM_DM3 DRAM_DQ28 DRAM_DQ0 DRAM_DQ27 DRAM_DQ1 DRAM_DQ26 DRAM_DQ10 DRAM_DQ25 DRAM_DQ11 DRAM_DQ24 DRAM_DQ12 DRAM_DQ23 DRAM_DQ13 DRAM_DQ22 DRAM_DQ14 DRAM_DQ21 DRAM_DQ15 DRAM_DQ20 DRAM_DQ16 DRAM_DQ2 DRAM_DQ17 DRAM_DQ19 DRAM_DQ18

[MDSD32M16B]

DQ10 [VSSQ] DQ13 [VDD] NC5 [VSS] [VSSQ] /LDQS [VDDQ] DQ6 [VSSQ] LDM LDQS [VSSQ] DQ7 [VDDQ] DQ1 [VDDQ] [VDDQ] DQ0 [VDDQ]

D7 D8 D9 E1 E2 E3 E7 E8 E9 F1 F2 F3 F7 F8 F9 G1 G2 G3 G7 G8 G9

IC301

R318 R319 R320 R321 R322 R323 R324 R317

R325

FRC_DQ11 FRC_DQ12 FRC_DQ8

R326

FRC_DQ9 FRC_DQ15 FRCD_DQS1_P FRC_DM1 FRC_DQ14 FRCD_DQS1_N

D3 D2 D1 C9 C8 C7 C3 C2 C1 B9 B8 B7 B3 B2 B1 A9 A8 A7 A3 A2 A1

DQ11 [VSSQ] DQ12 [VDDQ] DQ8 [VDDQ] [VDDQ] DQ9 [VDDQ] DQ15 [VSSQ] UDQS UDM [VSSQ] DQ14 [VDDQ] /UDQS [VSSQ] [VSS] NC4 [VDD]

DQ4 [VSSQ] DQ3 DQ2 [VSSQ] DQ5 [VDDL] [VREF] [VSS] [VSSDL] CK [VDD] CKE /WE /RAS /CK ODT BA2 BA0 BA1 /CAS

H1 H2 H3 H7 H8 H9 J1 J2 J3 J7 J8 J9 K2 K3 K7 K8 K9 L1 L2 L3 L7

FRC_DQ4 FRC_DQ3 FRC_DQ2 FRC_DQ5 VREF C301 C302 FRCD_CLK FRCD_CLKE FRCD_NWE FRCD_NRAS FRCD_NCLK FRCD_ODT FRCD_BA2 FRCD_BA0 FRCD_BA1 FRCD_NCAS C771 C773 C313 C314 C316 C317 C319 BD508 B1.8V_DDR

D

C325 VTT_FRC R357

C327

C329

C331

C332

C335

R8 R7 R3 R2 R1 P9 P8 P7 P3 P2 N8 N7 N3 N2 N1 M9 M8 M7 M3 M2 L8

R372_DE R358 R359 R360 R361 R362 R363 R364 R365 R366 R367 R368 R369 R370 R371

NC
FRCD_NCS FRCD_ADDR10 FRCD_ADDR1 FRCD_ADDR2 FRCD_ADDR0 FRCD_ADDR3 FRCD_ADDR5 FRCD_ADDR6 FRCD_ADDR4 FRCD_ADDR7 FRCD_ADDR9 FRCD_ADDR11 FRCD_ADDR8 FRCD_ADDR12 C344 C341 C340
C

C

B1.8V_DDR

FRCD_ADDR[0..12]

VREF R387 R388 R389 R390 R391 B1.8V_DDR R386 R385 R384 R383 R382 R381 R380 R379 R378 R377 R376 R375 R374 R373

VTT_FRC

IC108

VTT_FRC

1 2 3 4
C306 C307 C759 C760 C761 C762 C763 C169 C170 C167

NC VTT GND PVIN VSENSE AVIN VREF VDDQ

8 7 6 5
C168 U2839 U2840

VTT_FRC VTT_FRC BD509

C772 C348 C349 C351 C352 C354

GND

NC1 NC3 NC2 A12 [VDD] [VSS] A8 A11 A9 A7 A4 A6 A5 A3 [VSS] [VDD] A0 A2 A1 A10/AP /CS

R8 R7 R3 R2 R1 P9 P8 P7 P3 P2 N8 N7 N3 N2 N1 M9 M8 M7 M3 M2 L8

B

C305

C304

C303

C764

C765

C766

C767 FRCD_DQS3_N FRC_DQ30 FRC_DM3 FRCD_DQS3_P FRC_DQ31 FRC_DQ25

FRC_DQ24 FRC_DQ28 FRC_DQ27

A1 A2 A3 A7 A8 A9 B1 B2 B3 B7 B8 B9 C1 C2 C3 C7 C8 C9 D1 D2 D3

[VDD] NC4 [VSS] [VSSQ] /UDQS [VDDQ] DQ14 [VSSQ] UDM UDQS [VSSQ] DQ15 [VDDQ] DQ9 [VDDQ] [VDDQ] DQ8 [VDDQ] DQ12 [VSSQ] DQ11 DQ10 [VSSQ] DQ13 [VDD] NC5 [VSS] [VSSQ] /LDQS [VDDQ] DQ6 [VSSQ] LDM LDQS [VSSQ] DQ7 [VDDQ] DQ1 [VDDQ] [VDDQ] DQ0 [VDDQ]

/CAS BA1 BA0 BA2 ODT /CK /RAS /WE CKE [VDD] CK [VSSDL] [VSS] [VREF] [VDDL] DQ5 [VSSQ] DQ2 DQ3 [VSSQ] DQ4

L7 L3 L2 L1 K9 K8 K7 K3 K2 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 H1

R398 R399 R397 R394 R395

B

FRCD_BA2

C360

C362

C364

C366

C368

C370

C308 C309 VREF FRC_DQ21 FRC_DQ18 FRC_DQ19 FRC_DQ20 C379 C376 C375

D7 D8 D9 E1 E2 E3 E7 E8 E9 F1 F2 F3 F7 F8 F9 G1 G2 G3 G7 G8 G9

IC302

A

FRCD_DQS2_N FRC_DM2 FRC_DQ26 FRC_DQ29 FRC_DQ22 FRCD_DQS2_P FRC_DQ23 FRC_DQ17 FRC_DQ16

5

4

[MDSD32M16B]
A

CIS
<Variant Name>

友達光電電視顯示器產品研發處
Model Name T315HW02 V3 Tcom MEMC Board

FRC DDR
Size Document Number Custom T315HW02 Date:
3 2

Rev

V3 Tcom\MEMC Board
Sheet 1 of 10
1

EC02

Wednesday, October 01, 2008

5

4

3

2

1

T1_lVCLKP

T1_RVCLKP

T1_RVCLKN

T1_LVCLKN

T1_LVP[4..6]

T1_RVP[4..6]

T1_RVN[4..6]

T1_RVP[0..2]

T1_RVN[0..2]

T1_LVN[4..6]

T1_LVP[0..2]

T1_LVN[0..2]

Data Mapping Setting Table PIX_SFT_EN MODE41 0 1 0
D

T1_LVCLKN

T1_LVCLKP

T1_RVCLKN

T1_RVCLKP

Closed to pin65 of U300
T1_LVN[0..2] T1_LVP[0..2] VDD_V3D3_S C0322 C0321 C0323 RN0301

FRVS1 FRVS2 BRVS CHPXF CHPXB

T1_RVN[4..6]

T1_RVN[0..2]

T1_RVP[4..6]

T1_RVP[0..2]

T1_LVN[4..6]

T1_LVP[4..6]

D

4

3

0 0 0 0 0 0 1 1

Close to U300
4 3
RN0300

1

2

Close to U300
VDD_V1D2_S

1

2

CHFB
C0325 C0326

C0324

CHML CHRB CHPN

For
VDD_V1D2_S

KME use
T1_RVP0 T1_RVN0 T1_RVP1 T1_RVN1 T1_RVP2 T1_RVN2 T1_LVP4 T1_LVN4 T1_LVP5 T1_LVN5 T1_LVP6 T1_LVN6 T1_LVP0 T1_LVN0 R0310 VDD_V3D3_S VDD_V1D2_S T1_LVP1 T1_LVN1 T1_LVP2 T1_LVN2

VDD_V3D3_S VDD_V1D2_S

When ODEN is low or OPEN, OD_EN(Internal Register ) 0 : OD disable 1 : OD enable
R0309

120HZ Closed to pin56 of U300
C

G1

C0328
C

96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

C0327

RV2N RV2P GND VDDM RV1N RV1P RV0N RV0P LV7N LV7P LV6N LV6P GND VDDM LV5N LV5P LV4N LV4P GND VDDC12 LVCLKN LVCLKP LV3N LV3P LV2N LV2P GND VDDM LV1N LV1P LV0N LV0P

R0311

NC
T1_RVN6 T1_RVP6 T1_RVN5 T1_RVP5

V1D2

V1D2

L0300

C0301 C0302

C0303

C0304

T1_RVN4 T1_RVP4

R0312 GND GND R0313

VDD_V1D2_S V3D3 V3D3 L0302 VDD_V3D3_S R0342 C0305 C0306
B

C0307

C0308 XIN_S

PAD
XIN_S

1

RXINO0N RXINO0P RXINO1N RXINO0P RXINO2N RXINO2P VDDL GND RXCLKON RXCLKOP RXINO3N RXINO3P RXINO4N RXINO4P VDDL GND VDDC12 VDDC12 GND RXINE0N RXINE0P RXINE1N RXINE1P RXINE2N RXINE2P VDDL RXCLKEN RXCLKEP RXINE3N RXINE3P RXINE4N RXINE4P

97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 OSCSEL_S 126 127 128

PV3P RV3N VDDWR PFCAP RVCLKP RVCLKN RV4P RV4N RV5P RV5N VDDM GND RV6P RV6N RV7P RV7N GND RMLVDS VDDIO REXT VDDC12 VDDC12 GND VDDIO GND GND VDDIO GND PWM OSCSEL XIN XOUT

U0300 AUO12401 K1 T1

TEST SWAPL GOAEN SPDEN DCREN ODEN AGBSEN LVDSORD VDDIO GND VDDC12 VSEL XSTB XBDO XPOL YDIO YCLK YOE1 YOE2 VDDIO GND YOE3 YOE4 YV1C GND VDDC12 RSTN INSDA INSCL EPWP EXSDA EXSCL

When ODEN is high, OD_EN(Internal Register ) 0 : OD enable 1 : OD disable
R0308

G1

L0301

V3D3

NC VDD_V3D3_S
AGBSEN LVDSORD

C0330 C0319

C0320

ODEN_S AGBSEN LVDSORD

XSTB_S XPOL_S YDIO_S YCLK_S YOE_S

XSTB_S XPOL_S YDIO_S YCLK_S YOE_S

On Bottom Layer
EPWP_S VCCE_S INSDA_S INSCL_S GNDE_S U0301 5 SDA 6 SCL 7 WP 8 VCC R0303 R0304 R0305 R0306 D0300 VDD_V3D3_S

YOE3_S YOE4_S YV1C_S

YOE3_S YOE4_S YV1C_S

PAD

PAD

PAD

PAD

1

1

1

1

RST INSDA_S INSCL_S EPWP_S EXSDA EXSCL

RST

EXSDA EXSCL

GND A2 A1 A0

4 3 2 1

1

PAD

B

PAD

1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Closed to pin117 of U300
NC
2 1
Y0301

XOUT_S

VDD_V1D2_S VDD_V3D3_S RXINCN0 RXINCP0 RXINCN1 RXINCP1 RXINCN2 RXINCP2 RXINCN3 RXINCP3 RXINCN4 RXINCP4 RXINAN0 RXINAP0 RXINAN1 RXINAP1 RXINAN2 RXINAP2 RXINAN3 RXINAP3 RXINAN4 RXINAP4

GND VDD_V1D2_S VDD_V3D3_S

C0317

C0309

R0301

VDD_V1D2_S C0312 C0311 C0313

NC
3 4

NC

Closed to pin8 of U301

R0302

NC
C0310

VDD_V3D3_S RXINCP[0..4] RXCLKCN RXCLKCP RXCLKAN RXCLKAP RXINCN[0..4] RXINAN[0..4] RXINAP[0..4] C0315 C0314 C0316
A

NC
A

RXCLKAN

RXCLKAP

RXINCN[0..4]

RXINCP[0..4] RXCLKCN

RXINAN[0..4]

RXINAP[0..4]

RXCLKCP

Closed to pin127 of U300

<Variant Name>

Closed to pin33 of U300
Model Name

友達光電電視顯示器產品研發處
T315HW02 V3 Tcom MEMC Board

Tcom(Slave)
Size Document Number Custom T315HW02 Date:
5 4 3 2

Rev

V3 Tcom\MEMC Board
Sheet 1 of 10
1

EC02

Wednesday, October 01, 2008

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