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Tech Final Year Project (FYP) Proposal Department of Electronics and Communication Engineering Vardhaman College of Engineering (Autonomous) Shamshabad, Hyderabad - 501218

Student 1 : Student 2 : Student 3 : Student 4 :

Alekhya Dara Mounika Dubbaka Mounika Kondakalla Aparna Enukonda

10881A0462 10881A0480 10881A0481 11881A0414

Supervisor: Mr. Nagarjuna Batch No. : 10 - 03

Proposed Title of the Project: Advanced Peripheral Bus based Serial Peripheral Interface for SOC Abstract: SOC technology has become the main stream in IC design technology and the on-chip bus standards have promoted further development of SOC. Serial Peripheral Interface (SPI) is designed using an APB(Advanced Peripheral Bus) to interface low performance devices. SPI-APB bus can be configured under software to be a master or slave device. Reading and writing is done on AMBA APB bus interface. The core operates in 8 bit, 16 bit, 32 bit. The data is then serialized and transmitted from master to slave device using the standard 4-wire SPI bus interface. Being a single-master communication protocol it supports full duplex communication. The data is transmitted synchronously with MOSI (Master-Out Slave-In) relative to SCLK generated by the master. The master also receives the data on MISO (Master-In Slave-Out) signal in a full duplex model. The core is delivered as a synthesizable RTL Verilog model and task based test bench.

[1] AMBA 3 APB Protocol V1.0 Specifications, ARM Limited, 2004 [2] KeyStone architecture Serial Peripheral Interface, Texas Instruments, March 2012.