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Digital PDP8-L Users Handbook 1968

Digital PDP8-L Users Handbook 1968

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Published by kgrhoads
PDP8-L Users Handbook 1968
PDP8-L Users Handbook 1968

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Published by: kgrhoads on Feb 20, 2014
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Bits 3 through 8 of an lOT instruction serve as a device or subdevice select
code. Bus drivers in the processor buffer both the binary 1 and 0 output
signals of MB3-8 and distribute them to the interface connectors for bussed
connection to all device selectors. Each DS is assigned a select code and is
enabled only when the assigned code is present in the MB. When enabled, a
DS regenerates lOP pulses as lOT command pulses and transmits these
pulses to skip, input, or output gates within the device and/or to the proces-
sor to clear the AC.

Each group of three command pulses requires a separate DS channel (MI03
module), and each DS channel requires a different select code (or I/O device
address). One I/O device can, therefore, use several DS channels. Note that
the processor produces the pulses identified as lOP 1, lOP 2, and lOP 4 and
supplies them to all device selectors. The device selector produces pulses lOT
1, lOT 2, and lOT 4 which initiate a transfer or effect some control. Figure 25
shows generation of command pulses by several DC channels.

6 LINES FOR

>--

SELECT CODE

34

6 LINES FOR
SELECT CODE

33

12 /

IQP LINES

BMB

(BUSSED TO ALL

LiNES

DEVICE SELECTORS)

DEVICE

SELECTOR

34

DEVICE

SELECTOR

33

-

'---

-

-

r--
r--
r--

r--
r--

-
-

-
-

-

IOT 6341

JOT 6341

lOT 6342

JOT 6342

lOT 6344

lOT 6344

DEVICE 34 SELECTED

Figure 25. Generation of lOT Command Pulses by Device Selectors

93

The logical representation for a typical channel of the OS, using channel 34,
is shown in Figure 26. A 6-input NAND gate wired to receive the appropriate
signal outputs from the MB3-8 for select code 34 activates the channel. In the
OS module, the NAND gate contains 8 input terminals; 6 of these connect to
the complementary outputs of MB3-8, and 2 are open to receive subdevice or
control condition signals as needed. Either the 1 or the 0 signal from each MB
bit is connected to the NAND gate when establishing the select code. The
ground level output of the NAND gate indicates when the lOT instruction
selects the device, and can therefore enable circuit operations within the de-
vice. This output also enables three power NAND gates, each of which pro-
duces an output pulse if the corresponding lOP pulse occurs. The positive
output from each gate is an lOT command pulse identified by the select code
and the number of the initiating lOP pulse. Three inverters receive the positive
lOT pulses to produce complementary lOT output pulses. An amplifier module
can be connected in each channel of the DS to provide greater output drive.

BMB03 {OJ

BMB04 (1)

BMBOS (1)

BMB06 (1)

8M807 (0)

BMBOS (OJ

AVAILABLE FO"R {

SUB-DEVICE

ENCODING

634X

(DEVICE SELECT LINE

USED FOR BAC
INPUT GATING)

lOT 6344

0---+-----iOf""6344

lOT 6342

~-- -----ffiT<542

lOT 6341

Figure 26. Typical Device Selector (Device 34)

Input/Output Skip (105)

Generation of an lOT pulse can be used to test the condition or status of a·
device flag, and to continue to or skip the next sequential instruction based
upon the results of this test. This operation is performed by a 2-input AND
gate in the device connected as shown in Figure 27. One input of the skip gate
receives the status level (flag output signa!), the second input receives an lOT
pl,llse, and the output drives the computer skip (designated SKI P BUS) to
ground when the skip conditions are fulfilled. The state of the skip bus is
sampled at the end of each lOT. If the bus has been driven to ground, the
content of the program counter is incremented by 1 to' advance the program
count without executing the instruction at the current program count. In this
manner an lOT instruction can check the status of an 1[0 device flag and skip
the next instruction if the device requires servicing. Programmed testing in
this manner allows the routine to jump out of sequence to a subroutine that
services the device tested.

'

94

POP-B/l

BUILT-IN LOAD a RECEIVER

r-'------. "'-101623 SECTION
IPWR "AND" GATE

WIT H OPEN COllECTOR)

Figure 27. Use of lOS to Test the Status of an External Device

Assuming that a device is already operating, a possible program sequence
to test its availability follows:

Address

Instruction

Remarks

100,
101,
102,

6342
5100

5XXX

{SKIP IF DEVICE 34 IS READY
{JUMP .-1
{ENTER SERVICE ROUTINE FOR
{DEVICE 34

When the program reaches address 100, it executes an instruction skip with
6342. The skip occurs only if device 34 is ready when the lOT 6342 com-
mand is given. If device 34 is not ready, the flag signal disqualifies the skip
gate, and the Skip pulse does not occur. Therefore, the program continues
to the next instruction which is a jump back to the skip instruction. In this
example, the program stays in this waiting loop until the device_ is ready to
_ transfer data, at which time the skip gate in the device is enabled and the
. Skip pulse is sent to the computer lOS facility. When the skip occurs, the
instruction in . location 102 transfers program control to a subroutine to
service device 34. This subroutine can load the AC with data and transfer
it to device 34, or can load the AC from a register in device 34 and store
it in some known core memory address.

95

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