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All Programmable FPGAs, SoCs, and 3D ICs

Part III. Design Tools and Methodologies

12 December 2012 Clive Max Maxfield

The Good Old Days

The Good Old Days (cont.)

The Good Old Days (cont.)

Mixed-Level Design

Simulation and Synthesis

New Devices New Challenges

Yesterday: Programmable Logic Devices (PLDs) Today: All Programmable Devices (APDs)

These Arent Your Mothers FPGAs


Considerations with todays All Programmable FPGAs, SoCs, and 3D ICs
Humongous capacity Large numbers of hard cores (routing issues) Designs demand high-performance Designs are IP-Centric Designers need to manage IP Designers need to explore design space

Next-Gen Tools/Methodologies

Better Quality of Results (QoR)

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IP Packager and IP Integrator

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System Generator for DSP


Code Generation Modeling & Abstraction Vivado HLS Integration

QoR/IP Reuse

Debug & Verification

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C, C++ or SystemC

Vivado High-Level Synthesis (HLS)


Algorithmic Specification Micro Architecture Exploration

VHDL or Verilog

RTL Implementation

System IP Integration

Comprehensive Integration with the Xilinx Design Environment

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HLS Exploration and Optimization

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HLS Accelerates Productivity


Conventional HDL-based approach C-based Approach Seconds per iteration

Functional Verification Using HDL simulation

Functional Verification with C Compiler

Hours-days per iteration


RTL RTL
Final Validation

Verified RTL

Verified RTL

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Post-Synthesis Power Optimization


Before

After

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Conventional Methodology

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Modern Methodology

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Modern Methodology (cont.)

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Next Stop The 20nm Node

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Next Stop The 20nm Node

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Bugs Are Everywhere!

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Creating Rad-Tolerant Designs

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More Information / Further Reading


www.AllProgrammablePlanet.com

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