module fsm(hclk,hrst,hwrite,regwrite,acpt,write,sel,wdata,rdata,resp); input hclk,hrst

,hwrite,regwrite,acpt; output write,sel,wdata,rdata,resp; wire hclk,hrst,hwrite,regwrite,acpt; reg write,sel,wdata,rdata,resp; parameter size=3; parameter IDLE = 3'b000, WWAIT = 3'001, READ = 3'b010, WRITE = 3'011, PWRITE = 3'b100, READOK = 3'101, WRITEOK = 3'b110, PWRITEOK = 3'111; reg [SIZE-1:0] wire [SIZE-1:0] current_state; next_state;

assign next_state = fsm_function(current_state,hwrite,regwrite,acpt); function [SIZE-1:0] fsm_function; input [SIZE-1:0] current_state ; input hwrite,regwrite,acpt; case(current_state) IDLE: if (acpt == 1'b0) begin fsm_function= IDLE; end else if (acpt == 1'b1 && hwrite == 1'b0) begin fsm_function = READ; end else if (acpt == 1'b1 && hwrite == 1'b1) begin fsm_function = WWAIT; end WWAIT: if (acpt == 1'b0) begin fsm_function= WRITE; end else if (acpt == 1'b1) begin fsm_function = PWRITE;

end READ: if (acpt == 1'b0) begin fsm_function= READOK. end else if (acpt == 1'b0) begin fsm_function= IDLE. . end READOK: if (acpt == 1'b1 && hwrite == 1'b0) begin fsm_function = READOK. end else if (acpt == 1'b0) begin fsm_function= IDLE. end WRITEOK: if (acpt == 1'b1 && hwrite == 1'b0) begin fsm_function = READ. end else if (acpt == 1'b1 && hwrite == 1'b1) begin fsm_function = WWAIT. end PWRITE: if (acpt == 1'b0) begin fsm_function= PWRITEOK. end else if (acpt == 1'b1) begin fsm_function = PWRITE. end WRITE: if (acpt == 1'b0) begin fsm_function= WRITEOK. end else if (acpt == 1'b1 && hwrite == 1'b1) begin fsm_function = WWAIT.

end else begin current_state <= #1 next_state.end PWRITEOK: if (acpt == 1'b0 && regwrite == 1'b1) begin fsm_function = WRITE. endcase endfunction always @ (posedge hclk) begin : FSM_SEQ if (hrst == 1'b1) begin current_state <= #1 IDLE. . end default : fsm_function = IDLE. end end always @ (posedge clock) begin : OUTPUT_LOGIC if (hrst == 1'b0) begin write <= #1 1'b0. wdata <= #1 1'b0. sel <= #1 1'b0. end else if (acpt == 1'b1 && regwrite == 1'b1) begin fsm_function = PWRITE. end else if (regwrite == 1'b0) begin fsm_function= READ.

sel <= #1 1'b0. end else begin case(current_state) IDLE : begin write <= #1 1'b0. sel <= #1 1'b0. rdata <= #1 1'b0. resp <= #1 1'b0. end READ : begin write <= #1 1'b0. sel <= #1 1'b0. rdata <= #1 1'b0. rdata <= #1 1'b0. resp <= #1 1'b0. resp <= #1 1'b0. resp <= #1 1'b0. wdata <= #1 1'b0. wdata <= #1 1'b0. wdata <= #1 1'b0. end WWAIT : begin write <= #1 1'b0. .rdata <= #1 1'b0.

end WRITEOK : begin write <= #1 1'b0. wdata <= #1 1'b0. sel <= #1 1'b0. rdata <= #1 1'b0. end READOK : begin write <= #1 1'b0. sel <= #1 1'b0. wdata <= #1 1'b0. end PWRITE : begin write <= #1 1'b0. resp <= #1 1'b0. resp <= #1 1'b0. sel <= #1 1'b0. sel <= #1 <= 1'b0. rdata <= #1 1'b0.end WRITE : begin write <= #1 1'b0. . wdata <= #1 1'b0. resp <= #1 1'b0. rdata <= #1 1'b0.

rdata <= #1 1'b0. resp <= #1 1'b0. end endcase end end endmodule .rdata <= #1 1'b0. wdata <= #1 1'b0. resp <= #1 1'b0. sel <= #1 1'b0. end PWRITEOK : begin write <= #1 1'b0.