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S/36

CAMBRIDGE UNIVERSITY ENGINEERING DEPARTMENT



MICROPROCESSOR DATA

1986

Rl Oct 1984

List of Contents

Page

Section 1: General

Logic symbols

Hexadecimal/decimal conversion and 2s complement notation ASCII Character set

2 3 4

Section 2: Motorola 6800, 6809 and 68000

Programming model for 6800 and 6802 5
Instruction set for 6800 and 6802 6
Programming model for 6809 10
Instruction set for 6809 11
Programming model for 68000 17
Instruction set for 68000 18
Peripheral interface adaptor, 6821 20 Section 3: Synertek 6502 and EEC microcomputer

Programming model for 6502

Memory map for BBC microcomputer Block diagram of BBC microcomputer BBC microcomputer reference summary

23 24 25 26

1

LOGIC

A X !==CY- ~

COMPLEMENT: X =A AND:X = A. B NAND:X=A.B
=AA8
~ ~ ~
OR:X=A+8 NOR:X=A+B EXCLUSIVE OR:
=AvB X=A.8+A.B
=A @ 8
A X =A ¥ B 3-STATE BUFFER: E =1; X =A

E = a ; OUTPUT DISABLED (HIGH IMPEDANCE)

...
J Q
?CK

K Q J K Qn+1

o 0 o,

a 1 a

1 a 1

1 1 Gln

J -K FLIP-FLOP

0 Q
K

o
o Qn+1

a a

1 1

o FLIP - FLOP

2

16-BIT (2-BYTE) HEXADECIMAL/DECIMAL CONVERSION

More significant Less significant
BYTE BYTE
HEX DEC HEX DEC HEX DEC HEX DEC
0 0 0 0 0 0 0 0
1 4,096 1 256 1 16 1 1
2 8,192 2 512 2 32 2 2
3 12,288 3 768 3 48 3 3
4 16,384 4 1,024 4 64 4 4
5 20,480 5 1,280 5 80 5 5
6 24,576 6 1,536 6 96 6 6
7 28,672 7 1,792 7 112 7 7
8 32,768 8 2,048 8 128 8 8
9 36,864 9 2,304 9 144 9 9
A 40,960 A 2,560 A 160 A 10
B 45,056 B 2,816 B 176 B 11
C 49,152 C 3,072 C 192 C 12
D 53,248 D 3,328 D 208 D 13
E 57,344 E 3,584 E 224 E 14
F 61,440 F 3,840 F 240 F 15 2s COMPLEMENT NUMBER REPRESENTATION
(8-bit word)
2s complement binary Decimal

0000 0000 ) 0 )
0000 0001 ) Most significant + 1 ) Positive
) bit equals 0 )
0111 1111 ) + 127 )
1000 0000 ) - 128 )
1000 0001 ) Most significant - 127 ) Negative
) bit equals 1 )
1111 1111 ) 1 ) Number range for n-bit word:

n-1 n-1

-2 ~ x ~ 2 -1

and the negative of a number is represented by its complement +1.

3

ASCII CHARACTER SET

DEC HEX ASCII DEC HEX ASCII DEC HEX ASCII DEC HEX ASCII
0 00 ",@ 32 20 64 40 @ 96 60 \
1 01 "'A 33 21 65 41 A 97 61 a
2 02 "'8 34 22 " 66 42 8 98 62 b
3 03 "'C 35 23 # 67 43 C 99 63 c
4 04 "'0 36 24 $ 68 44 0 100 64 d
5 05 "'E 37 25 % 69 45 E 101 65 e
6 06 "'F 38 26 & 70 46 F 102 66 f
7 07 "'G 39 27 , 71 47 G 103 67 9
8 08 "'H 40 28 72 48 H 104 68 h
9 09 "" 41 29 73 49 , 105 69
10 OA ""J 42 2A * 74 4A J 106 6A j
11 08 ""K 43 28 + 75 48 K 107 68 k
12 OC ""L 44 2C 76 4C L 108 6C I
,
13 00 ""M 45 20 - 77 40 M 109 60 m
14 OE ""N 46 2E 78 4E N 110 6E n
15 OF ""0 47 2F / 79 4F 0 111 6F 0
16 10 "'p 48 30 0 80 50 P 112 70 p
17 11 ""0 49 31 1 81 51 0 113 71 q
18 12 "R ' 50 32 2 82 52 R 114 72 r
19 13 "S 51 33 3 83 53 S 115 73 5
20 14 "T 52 34 4 84 54 T 116 74 t
21 15 "U 53 35 5 85 55 U 117 75 u
22 16 "V 54 36 6 86 56 V 118 76 v
23 17 "W 55 37 7 87 57 W 119 77 w
24 18 "x 56 38 8 88 58 X 120 78 x
25 19 "'y 57 39 9 89 59 Y 121 79 Y
26 1A "'Z 58 3A 90 5A Z 122 7A z
27 18 .. [ 59 38 91 58 [ 123 78 {
28 lC "'\ 60 3C < 92 5C \ 124 7C I
29 10 ",] 61 3D = 93 50 ] 125 70 }
30 1E "' ... 62 3E > 94 5E " 126 7E IV
31 1F '" 63 3F ? 95 5F _ 127 7F DEL
It. @ means CTRL @ 4

MOTOROLA 6800 AND 6802 PROCESSOR PROGRAMMING MODEL

7 a
I Accumulator A I

7 a
I Accumulator B I
15 a
I x Index register I

15 0
I SP Stack pointer I

15 0
I PC Program counter I

Con d ition code

register Carry (from bit 7) Overflow

'----- Zero

Negaflve

I nterrupt mask

Half carry (from bit 3 )

Permanent memory assignments for interrupt vectors

Contents Address
RESET (low byte) FFFF
RESET (high byte) FFFE
NON-MAS KABLE INTERRUPT (low byte) FFFD
NON-MASKABLE INTERRUPT (high byte) FFFC
SOFTWARE INTERRUPT (low byte) FFFB
SOFTWARE INTERRUPT (high byte) FFFA
INTERRUPT REQUEST (low byte) FFF9
INTERRUPT REQUEST (high byte) FFF8 5

MOTOROLA 6800 INSTRUCTION SET

- -

C>:> U

co 00 co U

<D<D« = <..J CD U

z

::!

....

< a:: w Q.

o U

;:::

w

:iil ::

!::

a::

~

z < w ~ o o .:=

........... __ -- .

CI w

:::;

Q.

~

CI Z .... x w

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U~~~-------------------------------------------------------------------------------- ___

~ r-C>-+_U __ +-_- - __ - - - • __ • • • ~ __ a: a: - .. .. cn cn cn~~~~€1~I~~~~~€J~----.--.---.--.---.--?~?~?~-.---.---.---.--_:.~~.--_:.--.--

a: _ > .. _ .. __ ~ a:: ~ ~ ~ a: a: - .... a: a: a: eee.. .... ..... ~ ~ @C",@ ~ a: ~ ~ •••• w

Q NN -- ...... -- .... ~-~~~-~~ .... ~~_ .... _ .... ~- .... --~- .... ---- •••• o

u ... Z

.:t:t. - -_ - ~- --_

I N NN N NN NNN

CZl Z o

-

£-e

U :J

= en a.. co CD cnCD~~t.nr..nU. __ M Q <C cac:oU (Q(,Q <C~

E-- W Q a:au.. CO"",-CCu..c:au.,...... CCu..,....""" ,.... c:cu.,..... CCu... CXlu..

CZl gr-+--+-------------------------------------------------------------------------------

Z:E tt NN NNNNNNN NN N N

_",x

Z w C;; CI '" Z w

a:

g r--t--4-t--~--~------~---~---~---~---~---~-----------~---~--------------------------------------~---~------------~---~---~---~-------------

<

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M MMM MMMM

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i'MM MMMMMM MM

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Q. o

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MOTOROLA 6809 PROCESSOR PROGRAMMING MODEL

7 o 7 0
IAccumulator A II Accumulator B I

Accumulator 0
15 a
I x - In dex register I

15 , 0
I y - In d ex reg ister I

15 0
I U - User stack pointer I

15 a
I s - Hardware stack pointer I

15 0
I PC Program counter I 7 0

lOP-Direct page register I

Condition code register

7

a

Carry (from bit 7) L---_ Overflow ~-- Zero

L..-- Negative

IRQ interrupt mask '------- Half carry (from bit 3) ~------- Fast interrupt mask "---------- Entire state on stack

10

MOTOROLA 6809 INSTRUCTION SET

_.
Number of clock cycle
ADDRESSING MODES
..
E "0 'iii
.. ii "0 ..
e "0 .. .z
5 3 2 , 0 u c .. )( 'iii
INSTRUCTIONI .. e .. E ..
s: x .§ "0 -a;
FORMS DESCRIPTION E a UJ E a:
H N Z V C
ABX B + X - X • • • • • 3
(UNSIGNED)
ADC ADCA A+M+C-A ! I I I I 4 5 2 4+
ADCB B+M+C-B I I I I I 4 5 2 4+
ADD ADDA A+ M - A I I I I . 4 5 2 4+
.
ADDB B+ M - B I t t t t 4 5 2 4+
ADDD D + M:M + 1 -D · I I I I 6 7 4 6+

AND ANDA AAM - A • I I 0 • 4 5 2 4+
ANDB BAM - B • I I 0 • 4 5 2 4+
ANDCC CCAIMM - CC , 3
ASL ASLA A - a I t t I 2
ASLa B }o ·111111111 - 0 a I I I I 2
ASL M C b, bo a I I ! I 6 7 6+
ASR ASRA A}U - a t I • I 2
ASR a I I • I 2
B,IIIIIIIl-D
ASR M b, coC a ! I • I 6 7 6+
acc BCC Branch C=O • • • • •
LBCC Long Branch • • • • • 3
C=O 5(.)
BCS BCS Branch C = 1 • • • • • 3
lBCS long Branch • • • • • 5(.)
C = 1
BEQ BEQ Branch Z=O • • • • • 3
lBEQ long Branch • • • • • 5(.)
z=o
BGE BGE Branch ~ Zero • • • • • 3
LBGE Long Branch ~ • • • • • 5(.)
Zero
BGT BGT Branch > Zero • • • • • 3
LBGT Long Branch > • • • • • 5(.)
Zero
BHI BHI Branch Higher • • • • • 3
lBHI Long Branch • • • • • 5(6)
Higher
BHS BHS Branch Higher • • • • • 3
lBHS or Same
long Branch • • • • • 5(.)
Higher or Same
BIT BITA Bit Test A (M A A) • I I 0 • 4 5 2 4+
BITB Bit Test B (M II B) • I I 0 • 4 5 2 4+ -
BLE BLE Branch S Zero • • • • • 3
LBLE Long Branch S • • • • • 5(.)
Zero 11

Number of clock cycles
ADDRESSING MODES
.,
~ " 'c;;
., '0 " .,
5 3 2 1 0 ., u " ., .~
INSTRUCTIONI t e ., )( .0;
e ., E .,
DESCRIPTION J: x .s "0 0;
FORMS ..5 Ci L.U ..5 a:
H N Z V C
BLO BLO Branch Lower • • • • • 3
LBLO Long Branch • • • • • 5(.)
Lower
BLS BLS Branch Lower • • • • • 3
or Same
LBLS Long Branch • • • • • 5(.)
Lower or Same
BLT BLT Branch < Zero • • • • • 3
LBLT Long Branch < • • • • • 5(.)
Zero
BMI BMI Branch Minus • • • • • 3
LBMI Long Branch • • • • • 5(.)
Minus
BNE BNE Branch Z~O • • • • • 3
LBNE Long Branch • • • • • 5(.)
Z"O
BPL BPL Branch Plus • • • • • 3
LBPL Long Branch • • • • • 5(.)
. Plus
BRA BRA Branch Always • • • • • 3
LBRA Long Branch Always • • • • • 5
BRN BRN' Branch Never • • • • • 3
LBRN Long Branch Never • • • • • 5
BSR BRS Branch to • • • • • 7
Subroutine
LBSR Long Branch to • • • • • 9
Subroutine
BVC BVC Branch V=O • • • • • 3
LBVC Long Branch • • • • • 5(.)
V=O
BVS 8VS Branch V=1 • • • • • 3
LBVS Long Branch .'. • • • 5(.)
V=1
CLR CLRA O-A • 0 1 0 0 2
CLRB 0-8 • 0 1 0 0 2
CLR 0- M • 0 1 0 0 6 7 6+
CMP CMPA Compare M from A 8 I I I I 4 5 2 4+
CMP8 Compare M from B 8 I I I I 4 5 2 . 4+
CMPD Compare M:M + 1 • I I I I 7 8 5 7+
from D
CMPS Compare M:M + 1 • I I I I 7 8 5 7+
from S
CMPU Compare M:M + 1 • I I I I 7 8 5 7+
from U
CMPX Compare M:M + 1 • t I I I 6 7 4 6+
from X
CMPY Compare M:M + 1 • I I I I 7 8 5 7+
fromY 12

Number of clock cycles
ADDRESSING MODES
'"
E "0 ~
5 3 2 1 0 '" :.0 "0 '"
~ U "0 '" .2
INSTRUCTIONI e '" >< ~
'" ~ '" E '"
FORMS DESCRIPTION s: x .§ "0 q;
H N Z V C E a w .s a:
COM COMA A-A • I I 0 1 2
COMB 6-8 • I I 0 1 2
COM M-M • I I 0 1 6 7 6+
aNAl CC AIMM - CC; 1 20
Wait for Interrupt
DAA Decimal Adjust A • I I 0 I 2
DEC OECA A- 1 - A • I I I • 2
DECB B- 1 - B • I I I • 2
DEC M-l - M • I I I • 6 7 6+
EOR EORA A¥M - A • I I 0 • 4 5 2 4+
EORB B¥M - 8 • I I 0 • 4 5 2 4+
EXG R1. R2 R1 - R2' • • • • • 7
INC INCA A+l-A • I I I • 2
INCB 8 + 1 - 8 • I I I • 2
INC M+ 1 - M • ! I ! • 6 7 6+
JMP EA' - PC • • • • • 3 - 4 3+
JSR ~ump to Subroutine • • • • • 7. B 7+
LD LDA M-A • ! I 0 • 4 5 2 4+
LOB M - 8 • ! I 0 • 4 5 2 4+
LOO M:M + 1 - D • ! ! 0 • 5 6 3 5+
LDS M:M + 1 - S • ! I 0 • 6 7 4 6+
!
LOU M:M+ 1 -U • ! ! 0 • 5 6 3 5+
LDX M:M+ 1 -X • ! ! 0 • 5 6 3 5+
LDY M:M + 1 -Y • I I 0 • 6 7 4 6+
LEA LEAS EA~ - S • • • • • 4+
LEAU EA' - IJ • • • • • 4+
LEAX EN - X • • I • • 4+
LEAY EA' - Y • • I • • 4+
LSL LSLA At - • I 1 I t 2
LSLB B 0 -illIIIID - 0 • t t I t 2
LSL M c b, bo • 1 I 1 t 6 7 6+
LSR LSRA ~ io -[TI]]IIJ-O • 0 t • t 2
LSRB • 0 t • I 2
LSR M b, bo c • 0 I • I 6 7 6+
MUL Ax B - 0 • • I • 9 , 1
(Unsigned)
NEG NEGA A+ 1 - A 8 I I I ! 2
NEGB B+ 1 - B 8 ! I I I 2
NEG M+ 1 - M 8 I I I I 6 7 6+
NOP No Operation • • • • • 2
OR ORA AVM - A • I t 0 • 4 5 2 4+
ORB BVM - B • t ! 0 • 4 5 2 4+
ORee ee v IMM - ee 7 3
PSH PSHS Push Registers on • • • • • 5+4
S Stack
PSHU Push Registers on • • • • • 5+ 4
U Stack 13

NOTES:

1. Given in the table are the base cycles. To determine the total cycles add the values from the '6809' indexing modes' table.

2 Rl and R2 may be any pair of 8 bit or any pair of 16 bit registers.

The 8 bit registers are: A,B,CC,DP The 16 bit registers are: X,Y,U,S,D,PC

3. EA is the effective address.

4. The PSH and PU L instructions require 5 cycles plus 1 cycle for each byte pushed or pulled.

5. 5(6) means:5 cycles if branch not taken, 6 cycles if taken.

6. SWl sets 1& F bits. SW12 and SW13 do not affect I & F.

7. Conditions Codes set as a direct result of the instruction.

8. Value of half-carrv flag is undefined.
9. Special Case· Carry set if b7 is SET.
Number of clock cycles
ADDRESSING MODES
<ll
'0 OJ
c: <ll -0 '0 <ll
<ll U '0 <ll .:!
5 3 2 1 0 0; C <ll x OJ
INSTRUCTION/ ~ s E <ll
s: '0 Oi
.E 6 x .E .E CI:
FORMS DESCRIPTION w
H N Z V C
PUL PULS Pull Registers from • • • • • 5+
S Stack
PULU Pull Registers from • • • • • 5+
U Stack
ROL ROLA ~ }qJt-mmmJ • I t t I 2
ROLB • I t t t 2
ROL Me b,-bo • t I I I 6 7 6+
ROR RORA ~ } C[h-dITlJIDJ • I I • I 2
RORB • I I • I 2
ROR M c b, - bo • I I • t 6 7 6+
RTI Return From 7 '/'5
Interrupt
RTS Return From • • • • • 5
Subroutine
SBC SBCA A-M-C-A 8 I I I I 4 5 2 4+
SBCS B-M-C-S 8 t I I I 4 5 2 4+
SEX Sign Extend B • t I 0 • 2
Into A
ST STA A-M • t t 0 • 4 5 4+
STB B - M • I t 0 • 4 5 4+
STD D - M:M + 1 • t I 0 • 5 6 5+
STS S - M:M + 1 • I I 0 • 6 7 6+
STU U - M:M + 1 • I I 0 • 5 6 5+
STX X - M:M + 1 • I I 0 • 5 6 5+
STY Y-M:M+l • I I 0 • 6 7 6+
SUB SUBA A- M - A 8 I I 1 t 4 5 2 4+
SUBS 8- M - 8 8 I t t I 4 5 2 4+
SUBD D-M:M+ 1 - D • I I I I 6 7 4 6+
SWI SWI6 Software Interrupt 1 • • • • • 19
SW126 Software Interrupt 2 • • • • • 20
SW136 Software Interrupt 3 • • • • • 20
SYNC Synchronize to • • • • • ~2
Interrupt
TFR Rl. R2 R1 - R2' • • • • • 7
TST TSTA Test A • t ! 0 • 2
TST8 Test B • ! ! 0 • 2
TST Test M • I ! 0 • 6 7 14

6809 STACKING ORDER

Simple Conditional Branches

Condition Camp tern ent

BEQ BNE

BMI BPL

BCS BCC

BVS BVC

PULL ORDER CC

A

B

DP X Hi X Lo Y Hi Y Lo

U/S Hi U/S Lo PC Hi PC Lo I

PUSH ORDER

6809 VECTORS FFFE Restart

FFFC NMI

FFFA SWI

FFF8 IRQ

FFF6 FIRQ

FFF4 SW12

FFF2 SW13

FFFO Reserved

Signed Conditional Branches

Condition Complement

BGT BLE

BGE BLT

BEQ BNE

BLE BG r

BLT BGE

INCREASING MEMORY

I

Unsigned Condiuonal Branches

Condition Complement

BHI BlS

BHS BlO

BEQ BNE

BlS BHI

BlO BHS

INDEXED ADDRESSING MODES

NON INDIRECT INDIRECT
Assembler + Assembler +
TYPE FORMS Form cycles Form cycles
CONSTANT OFFSET FROM R NO OFFSET ,R 0 [, RJ 3
5 BIT OFFSET n,R 1 defaults to 8-bit
8 BIT OFFSET n,R 1 [n,RJ 4
16 BIT OFFSET n,R 4 [n,R] 7
ACCUMULATOR OFFSET FROM R A-REGISTER OFFSET A,R 1 [A,R] 4
B-REGISTER OFFSET B,R 1 [B,RJ 4
D-REGISTER OFFSET D,R 4 [D,R] 7
AUTO INCREMENT /DECREHENT R INCREMENT BY 1 ,R+ 2 not allowed
INCREMENT BY 2 ,R++ 3 [,R++J I 6
DECREHENT BY 1 ,-R 2 not allowed
DECREMENT BY 2 ,--R 3 [,--RJ 6
CONSTANT OFFSET FROM PC 8 BIT OFFSET n,PCR 1 [n,PCRJ 4
16 BIT OFFSET n,PCR 5 [n,PCR] 8
EXTENDED INDIRECT 16 BIT ADDRESS - - En] 5 R = X,Y,U, or S

15

16

MOTOROLA 68000 PROG~ING MODEL

31 1615 8 7 0
DO
01
02 Eight
03
04 Data
Registers
05
06
07
31 1615 0
I AO
i- I -
- A1
-
A2 Seven
- - Address
A3
- - Registers
- A4
-
A5
i- -
A6
[ - - - - - - - - - - - - -- -l Two Stack Pdnters
_ User Stack Pointer - A7
LSuQervisor ..;;ta9<_PoLnter _ J
31 0
Program Counter
15 87 0
I I I status Register
I STATUS REGISTER

System Byte

User Byte

Condition Codes

Trace mode supervisor}

State ---I

Interrupt } ----'

Mask

Extend Negative---------------'

Zero

Overflow -----------------'

17

MOTOROLA 68000 INSTRUCTION SET

Data organisation in memory

An address specifies a particular byte in the memory space of the 68000. Yords and long words may only be accessed at even addresses, this address being that of the high order byte of the word. Thus where n is an even address the byte order of words and long words is as follows:

word:
n high byte
n + 1 low byte
long word:
n highest byte
n + 1
n + 2
n + 3 lowest byte Instruction set

In the following table the complete set of instruction mnemonics known to the assembler is listed. Yhere given, one of the extension letters shown in braces {} should be used; the variants shown in brackets [] are optional.

Mnemonic

Description

ABCD ADD[OX]. {BYL} AND. {BYL} ASL. {BYL} ASR. {BYL}

Add Decimal with Extend Add

Logical And

Arithmetic Shift Left Arithmetic Shift Right

Bcc BCHG BCLR BRA BSET BSR BTST

Branch Conditionally Bit Test and Change Bit Test and Clear Branch Always

Bit Test and Set Branch to Subroutine Bit Test

CHK

Check Register Against Bounds

18

CLR. {BWL} CMP[M]. {BWL}

DBcc DIVS DIVU

EOR. {BWL} EXG

EXT. {WL}

JMP JSR

LEA LINK

LSL. {BWL} LSR. {BWL}

MOVE[Q). {BWL} MOVEM. {WL} MOVEP. {WL} MULS

MULU

NBCD

NEG. {BWL} NOP

NOT. {BWL}

OR. {BWL}

PEA

RESET ROL. {BWL} ROR. {BWL} ROXL.{BWL} ROXR. {BWL} RTE

RTR

RTS

SBCD

Scc

STOP SUB[QX).{BWL} SWAP

TAS

TRAP TRAPV TST. {BWL}

UNLK

Clear Operand Compare

Test Cond.,Decrement and Branch Signed Divide

Unsigned Divide

Exclusive Or Exchange Registers Sign Extend

Jump

Jump to Subroutine

Load Effective Address Link Stack

Logical Shift Left Logical Shift Right

Move

Move Multiple Registers Move Peripheral Data Signed MUltiply Unsigned MUltiply

Negate Decimal with Extend Negate

No Operation One's Complement

Logical Or

Push Effective Address

Reset External Devices Rotate Left without Extend Rotate Right without Extend Rotate Left with Extend Rotate Right with Extend Return from Exception Return and Restore

Return from Subroutine

Subtract Decimal with Extend Set Conditional

Stop

Subtract

Swap Data Register Halves

Test and Set Operand Trap

Trap on Overflow Test

Unlink

19

In the above table BYL represent byte, word, long respectively; Q indicates a quick variant where the immediate data forms part of the instruction opcode, for ADDQ and SUBQ data must lie in range 1 to 8, for MOVEQ range is -128 to 127; X indicates that the X bit of the CCR is used (for multiple precision arithmetic). The branch instructions Bee, BRA and BSR may optionally be followed by.§ for branches within -128 to 127 (excluding 0, -1) bytes.

Condition Codes

The following two letter codes may be substituted in place of cc for the conditional instructions in the above table.

CC carry clear C
CS carry set C
EQ equal to zero Z
F always false (not branches) 0
GE greater than or equal to zero N. v+t:LV
GT greater than zero N.V.Z+N.V.Z
HI higher C.Z
LE less than or equal to zero z+N.ThN. V
LT less than zero N.V+N.V
MI minus N
NE not equal to zero Z
PL plus N
RA always true (branches only) 1
T always true (not branches) 1-
VC overflow clear V
VS overflow set V In the above the following letters are used for the condition code bits:

Z set if result zero, cleared otherwise

V set if overflow generated, cleared otherwise C set if a carry generated, cleared otherwise X extension bit, used for multiple precision

Addressing Modes

Dn

An

(An)

(An)+

-(An)

VAL(An) VAL(An,Rn: {YL}) ADDRESS: {YL} #VAL

Data register direct Address register direct Address register indirect

Address register indirect with post increment Address register indirect with predecrement Address register indirect with displacement Address register indirect with index Absolute address

Immediate data

Numerical values are preceded by $ = hex, % = binary, \ ASCII, ~ = octal. Ones followed by a full stop are decimal.

20

In the above:-

An is an address register, aO-a7 (SP (stack pointer) is a synonym for A7).

Dn is a data register, dO-d7.

Rn is a data or address register.

Other registers are:-

USP = user stack pointer,

CCR = condition code register (lower 8 bits of SR); SR PC = program counter.

status register;

Assembler Directives (Pseudo-ops)

.ascii 'string' initialise store with string
.asciz ' string' ini tialise store with null terminated string
.blkb count zero fill count bytes of store
.blkw count zero fill count words of store
.blkl count zero fill count long words of store
.bss switch to BSS segment
.byte vall, •.. , vaIN initialise store with byte values
.comm name, count reserve count bytes with label name in BSS
segment
.data switch to data segment
.end Program end. .globl symboll, ... ,symboIN

declare global symbols

.insrt file take input from file
. long vall, ... , vaIN ini tialise store with long word values
.text switch to text segment
.word vall, ..• , vaIN initialise store with word values
LABEL=expression assign value to LABEL 21

MOTOROLA PERIPHERAL INTERFACE ADAPTOR (PIA) MC 6821

80ltl Llnl. From Peripher.'

80lta Linl. from Peripher.'

Control

COntrOl'

Lin ••

vss (Ground I VCC

(+5 Volt Power)

Lin,.

PS7 CSI CS2

PAO PA7 CAl CA2
P,ripher.1
Ott.
Registl' A

Oat .. Oirection
R.-oIilt., A
I I I I I I I

Control
Rlgi'tl' A PSO

Peripher.' Oat. ReGilt"8

"0" • Input

"1" • Outout

Control Regis,e, B

cso est ffi

From or S Olt. From Registe,
MPU Write Linl. MPU Se'.ct
From to MPU From MPU
MPU Addre" Addre"
Lin,. Linll
PIA Functions TABLE 1 - INTERNAL ADDRESSING

TABLE 2 - CONTROL WORD FORMAT

7 6 5 I 4 I 3 2 1 I 0
IRCAl IRCA2 CA2 Control DOAA CAl Control
Access
7 6 5 I 4 I 3 2 1 I 0
IRCBl IRCB2 CS2 Control DOAS CSl Control
Access Control
Register Sit
RSl RSO CRA·2 CRB·2 Location Selected
0 0 1 X Peripheral Register A
0 0 0 X Data Direction Register A
0 1 X X Control Register A
1 0 X 1 Peripheral Register S
1 0 X 0 Data Direction Register B
1 1 X X Control Register B CAA

CAS

X " Don't Care

TABLE 3 - CONTROL OF INTERRUPT INPUTSCA1 AND CB1

MPU Interrupt
CRA·l CRA·O Interrupt Input Interrupt Flag Request
(CRB-l) (CRB·O) CAl (CB1) CRA-7 (CRB-7) IROA (IROB)
a a L Active Set high on L of CA 1 Disabled - IRa reo
(CS1) mains high
a 1 L Active Set high on L of CA 1 Goes low when the
(CB1) interrupt flag bit CRA·?
(CRB·?) goes high
1 0 i Active Set high on t of CAl Disabled - IRa re-
(CB1) mains high
1 1 i Active Set high on i of CA 1 Goes low when the
(CB1) interrupt flag bit CRA·?
(CRB·7) goes high Notes: 1. 2. 3.

i indicates positive transition (low to high) L indicates negative transition (high to low)

The Interrupt flag bit CRA·? is cleared by an MPU Read of the A Data Register, and CRB·? is cleared by an MPU Read of the B Data Register.

If CRA·O (CRB-O) is low when an interrupt occurs (Interrupt disabled) and is later brought high, IRQA (IROB) occurs on the positive transition of CRA·O (CRB.O).

4.

22

TABLE 4 - CONTROL OF CA2 AND CB2 AS INTERRUPT INPUTS CRA5 ICR B51 is low

MPU Interrupt
CRA-S CRA-4 CRA-3 Interrupt Input Interrupt Flag Request
(CRB-S) (CRB-4) (CRB-3) CA2 (CB2) CRA-6 (CRB-6) IRaA (IRaB)
0 0 0 ~ Active Set high on ~ of CA2 Disabled - IRQ ra-
(CB2) mains high
0 0 1 ~ Active Set high on ~ of CA2 Goes low when the
(CB2) interrupt flag bit CRA-6
(CRB-6) goes high
0 1 0 i Active Set high on i of CA2 Disabled - IRQ re-
(CB2) mains high
0 1 1 i Active Set high on i of CA2 Goes low when the
(CB2) interrupt flag bit CRA-6
(CRB-6) goes high Notes: 1. i indicates positive transition (low to high)

2. ! indicates negative transition (high to low)

3. The Interrupt flag bit CRA-6 is cleared by an MPU Read of the A Data Register and CRS-6 is cleared by an MPU Read of the S Data Register.

4. If CRA-3 (CRB-3) is low when an interrupt occurs (Interrupt disabled) and is later brought high. IRCA (IRQB) occurs on the positive transition of CRA-3 (CRB-3).

TABLE 5 - CONTROL OF CB2 AS AN OUTPUT CRB-5 is high

CB2
CRB-5 CRB-4 CRB-3 Cleared Set
1 0 0 Low on the positive transition of High when the interrupt flag bit
the' first E pulse following an CRB-7 is set by an active transi-
MPU Write "S" Data Register tion of the CB 1 signal.
operation.
1 0 1 Low on the positive transition of High on the positive transition of
the first E pulse following an MPU the next "E" pulse.
Write "S" Data Register opera-
tion.
1 1 0 Low when CRB-3 goes low as a Always low as long as CRS-3 is
result of an MPU Write in Control low. Will go high on an MPU Write
Register "B". in Control Register "S" that
changes CRS-3 to "one".
1 1 1 Always high as long as CRB-3 is High when CRB-3 goes high as a
high . .will be cleared when an result of an MPU write into control
MPU Write Control Register "S" register "S".
results in clearing CRB-3 to
"zero". TABLE 6 - CONTROL OF CA2 AS AN OUTPUT CRA-5 is high

CA2
CRA-S CRA-4 CRA-3 Cleared Set
1 0 0 Low on negative transition of E High on an active transition of
after an MPU Read "A" Data the CA 1 signal.
operation.
1 0 1 Low immediately atter an MPU High on the negative edge of
Read "A" Data operation. the next "E" pulse.
1 1 0 Low when CRA-3 goes low as a Always low as long as CRA-3
result of an MPU Write in is low.
Control Register "A".
1 1 1 Always high as long as CRA-3 High when CRA-3 goes high as
is high. a result of a Write in Control
Register ·'A". 23

ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER (ACIA) MC6850

EXPANDED BLOCK DIAGRAM

rt.JI1S1nl' ClOCk 4
tl1able 14
.----L
At~lJfI·Wrjhf lJ :1 ChIp
Chll) Setec t a 8 S"h'Cl
cn.o Stelwct 1 10 --.J and
Ch~iJSt!lect 2 9 R"ao,Wril.
Rt.!t)lsuu Swt'llict 11 ContrOl 6 Transmtt Data

Transmit Shilt RegISter

Tran,mit D'lla Register

24 Claar lo,S .. m2

D022i

D121~

0220 :: I

OJ 19 I

Status ReglSte,

7 Inttfrrupt R.Quint

Oal" Bus

23 Oata C."rrlQr D~t8ct

04 18 ~ Bullers 0517 --J

i

0616 : :,

D7 15

I

Von = Pin 12 VSS ~ Pin

TABLE 1 - DEFINITION OF ACIA REGISTER CONTENTS

Buffe, Add, ...
Data RS e R7W RS e RIW RS .1fiW RS. R/W
Bus T,ansmit Recei".
Line Oala Dala Conllol Sialus
Numb., Registe, ReQiSl. R'gililt Regislt'
(Write Onlv) (R .. d Onlv) (Wril. Only) (Rud Onlvl
0 0.'11 Bic o· Oata Bit 0 Count.' Divide A.c.,,,., O~u .. R.gII.f1'
S.'.CI 1 (CROI Fulllf'ORFI
1 0.,. Bit 1 DOli Bill Coun,., Oi",de T'in,rnl' O~I. R.-glll,.'
S.lect 2 ICR 1) emply ITOREI
2 0.,. Bit 2 Dati Bit :z WO,d SellCt 1 O.t. C.rller Oeu,,:;c
ICR2) ,'DCDI
;) Data BII a Olio Bit ;) Word StllCI 2 Cit,)' to S,nu
ICR;)) Icf~1
4 0111 Bil 4 Dill BII 4 WorlJ S',." ;) F ',)11'1"9 ~ ,ror
(CR4) IF E I
fI Oa .. BII S DOli Bit 5 T,an •• nic Canuol 1 Ace_tl".' O v ""un
(CRS) IOVHNI
6 O.la BII S Dill Bit S Trlnlmll Conuol 2 P."ly Error It'El
ICRS)
7 O,ua Bil 7'" Oall Ilil 7" R,ca", InltrruPI Inter,u,n RIIII.H,."
Enlul, (CR7) IIRQI L .. dln~ to" .' LSB • BOlO

O .. li ult w.1I tl4l' lero in 7·bic plus pariry mode" OM' .. hit is ",Jon't Cit'" in 7·bit plus J,Ji,ity rnod.s.

24

COu~R DIVIDE SELECT BITS (CRO AND CR1)

-
CRI CRO Function
a a ;. 1
a 1 ;. 16
1 a + 64
1 1 M."er Reset WORD SELECT BITS (CR2, CR3, AND CR4)

CR4 CR3 CR2 Function
a a a 7 BiU,. t:.\o'en;a.IICY t 2 SLOP Ud~
a a 1 7 SitS • Odd P.ltlt", • 2 SlOP B,a
a 1 a 7 6iu ... Evllln Parity. 15101> B,'
a 1 1 7 Bin. Odd PorilY • 1 SlOP ~Il
1 a a 8 Blls • 2 SlOP B, ..
1 a 1 8 Sin .. I SlOP Bit
1 1 a 8 Bin .. Even P.ritv • 1 5101> Bol
1 1 1 8 Bin tOdd Parity • 1 SlOP Bol TRANSMITTER CONTROL BITS (CRS AND CR6)

CRS CRS Function
a a ATS· low, TranllHllllng Interrupt D'sat".,(1.
a 1 RTS" low, Trilnullining Inttltrupt cn.c,I",J
1 0 R"TS .. high, Trans.mltting Intert\,Il,ll OI, .. C,I.:&.S
1 1 Fff'S ~ low, Tran5nuU a Brlli.~ ",...100 Ul.
Tranl""l Oa" OulPUl. Tran"nltllng
InuuruP1OI'.l"llid. J Receive Interrupt Enable Bit (CR7) - The follo'.'JlIlIJ interrupts will be enabled by a high level in bit position 7 of the Control Register (CR7): Receive Data RcC]istl.:r Full, Overrun, or a low to hig" tr ansistion on lilt! DJti;Carr'~-r Detect (()C1J) signal line.

NOTES

1. RDRF is cleared by reading the data register.

2. TDRE indicates that a character can be written to the data register.

3. If DCD is high then RDRF will indicate empty unconditionally.

4.

If CTS is high then TDRE is inhibited. effect on the CTS status bit.

Master reset has no

25

26

SYNERTEK 6502 PROCESSOR PROGRAMML~G MODEL

I Accumulator - A

7 0 I X - Index register I

7 0 I Y - Index register I

8 7 0 111 S -Stack pointer I

15 8 7

I PC - Program icounter

o

Processor sto tus register

o

Carry '"----- Zero

'"------ Interrupt mask 1----- Decimal mode 1...------ Break command

L-- Overflow

\....--------- Negative

27

Four (or more) paged ROMS (only one active at a time)

RAM 16 K BANK 1

RAM 16K BANK 0

r r---R....l.A-M-U-S-LE-O-F-O...LR----L8000 32768

HI MEM., __ HIGH_RESOLUTION GRAPHICS!,

__ ,. Moveab Ie boundary

- 4000 16384

t

L~~:~gYNAMI~yARIABLE_sroRAqs~oveable boundary

USER'S ~ 2000 8192

PAGE BASIC PROGRAM AREA

RESERVEO FOR OPERATING Boundary set by

SYSTEM USE system configuration

~---~~~--LOOOO 0

r

BBC MICROCOMPUTER MEMORY MAP

HEX DECIMAL IrO;r:;P:r=EnRA-;-::;Tffil N:-;-;G~S::=:Y-:::S=T E=O:M----=R-O-M.....- F F F F 65535

MEMORY MAPPE01NPUi< FFOO 65280

1 ~O~UTP~UTw... FCOO 64512

OPERATING SYSTEM· ROM

ROM12 ROM13 ROM14 ROM15 COOO .49152

28

BBC MICROCOMPUTER BLOCK DIAGRAM

ECONET

ANALOGUE INPUT

CASSETTE RS423 RGB

VIDEO

UHF

SP

k~· ... · .. ~ 99_~ j ~
• ........ • •
•• ••
9 t lMODULATOR]

ECONET ADC ACIA ~ SER PROC
INTERFACE )..I PD7002 6850 2C199 PAL r-
t t t ENCODER
"- VIDEO

PROC HTELETEXJi
en-- SOUND 5C094 SAA5050
76489 ~ }JP
EAKER VIA-A 6502 .-

6522
16K DRAM
+
Bank 1
1

I KEYBOARD CRT 16K DRAM
CONTROLLER Bank 0
684.5

rtROM~
, SEL
I
DISC VIA-B M
INTERFACE 6522 ~ 0 a 1 2 3
S
t

1 1 t 1 1 ~ 1
DISC PRINTER U l USER 1 MHz BUS TUBE
PORT
'- ~ \Jl.J ~ 29

BBC MICROCOMPUTER REFERENCE SUMMARY (abridged)

(From the Computing Service document by K. Edgcombe, 1983)

1. Typing in and running BASIC programs

AUTO n,m RENUMBER m, n LIST n,m LISTOn

CTRL U line-number DELETE n,m CTRL N, CTRL 0

RlJN

line numbering: start m, step n AU.

start m, step n REN.

n to m (or n or n, or ,m) L.

sets list options (0 to 7) LISTO

delete line being typed

alone deletes one line

delete lines n to m inclusive DEL.

set & unset page mode (SHIFT steps on) separates commands on same line

runs current program RUN

2. Saving and loading BASIC programs

Program name (on (on

SAVE "name" LOAD "name" CHAIN "name" CLEAR

NEW

OLD

3. Special keys

tape) = up to 10 characters, no spaces disc) = :n.x.name, name up to 7 chars current program to tape (or disc) into memory; ""= next on tape

load and run; 1111 as above

vars. from memory (not A% to Z%) before new program

restore old program after BREAK

SA. LO. CH. CL. NEW O.

ESCAPE (key) normally stops a BASIC program

BREAK (key) soft reset: clears variables and program

CTRL BREAK (keys) hard reset including soft keys & clock SHIFT BREAK (keys) carry out auto-boot option (disc)

COpy (key) from text cursor to block cursor

*KEY n text programs user-defined (soft) keys:

(red keys 1-9, 10=BREAK, 11-15=COPY and arrows, see *FX4,2) :11 for return, : x for CTRL x,

:! add 128 to next ASCII code

*FX18 reset (cancel) user-defined keys

VDU 23,n,ml, •• m8 programs ASCII n to new char. V.

step left, right, down,up

or 11) left, right, down, up one step or K) ditto

to m across, n down (n range 0-24, m range 0-19 or 0-39 or 0-79) (TAB(m) to position m across)

to top left of text window

to left of current line =horizontal position =vertical position switch cursor off switch cursor on

4. Text cursor

Arrow keys VDU 8 (9,10 CTRL H (I,J VDU 31,m,n

PRINT TAB(m,n) VDU 30

VDU 13

POS VPOS

VDU 23,1,0; 0 ; 0 ; 0 ; VDU 23,1,1;0;0;0;

30

v.

P.TAB V.

V.

POS VP. V. V.

5. Screen and window control

CLS clear screen (text window) CLS

*TV n move display (l=up 1 line, 255=down)

*TV 0,1 turn off display interlace *TV

VDU 21 disable screen output V.

VDU 6 re-enable screen output V.

VDU 28,xmin,ymin,xmax,ymax define text window V.

VDU 26 reset text and graphics windows V.

VDU 5 text at graphics cursor V.

VDU 4 text at text cursor V.

6. BASIC variables and constants

Variable name:

Integer variable name String variable name:

Resident integers:

Range: reals integers strings Accuracy (reals)

Special variable names:

FALSE 0

TRUE -1

PI 3.14159265

TIME centiseconds

[LET] variable=exprn DIM name1(n),name2(m) DIM name3(n1,n2) •• LOCAL name1,name2 ••

letter + letters, digits or

name% name $

A% to ~~9and @% +38

+ 2x10 to 2x10

-2147483648 to +2147483647 up to 255 characters

9 significant figures

from arbitrary start assignment

declare arrays

etc.

local vars in procedure

7. Structure in ~ BASIC program

REPEAT : commands : UNTIL condition

IF condition THEN commands (terminated by end of line) IF condition THEN commands ELSE commands

FOR v=n1 TO n2 STEP n3 : commands : NEXT [v]

GOTO n unconditional jump

GOSUB n jump keeping return address

END end of execution

STOP (fatal in Basic 2)end and output message

RETURN to last stored return address

ON v GOTO n1,n2.. if v=l goto n1 etc.

ON v GOSUB n1,n2.. similarly

DEF PROCname(v1,v2, .•• ) DEF

commands defines procedure

ENDPROC

PROCname(arg1,arg2, .. ) calls procedure DEF FNname(v1,v2, ••• )

commands defines function

=expression

v=FNname(arg1,arg2 •• ) calls function Conditions:- TRUE, FALSE, any numeric (O=FALSE), comparisons: = <> < > <= or >= compounds with AND, OR, NOT and ()

FA. TRUE PI T1. LET DIM

LOC.

REP. U.

IF-TH.EL. FoTO S.N. G.

GOS.

END

STO.

R.

ON G. ON GOS.

PRO. E.

PRO. DEF FN

FN TRUE,FA.

A. OR NOT

8. Operators and precedence

Group 1 : unary + and -, NOT, functions, brackets, ? , $
. , . ,
Group 2 : ,., (to power)
Group 3 : * / , DIV, MOD
,
Group 4 : +, -
Group 5 : = , <>, <, >, <=, >=
Group 6 : AND
Group 7 : OR, EOR 9. Built-in functions

Random numbers:

RND(X), RND(-X) (reset generator), RND (maximum range) Arithmetic:

n MOD m, n DIV Trigonometric:

SIN, COS, TAN,

Strings:

EV AL( st ring) VAL(string) STR$( num ) ASC(string) CHR$(n)

STRINGS(n,string) LEN(string) INSTR(strl,str2) LEFT$(string,n) RIGHT$(string,n) MID$(str,nl,n2)

m, SQR, ABS, SGN, LN, LOG, EXP

ASN, ACS, ATN, DEG, RAD

evaluate expression in string turn number string into number turn number into number string ASCII value of 1st char in string character whose ASCII value is n mUltiple copies to length n length

posn of str2 in strl

left n characters of string rt. n characters of string n2 chars from nl on

10. Input

INPUT ["text",]vars [prompt and] read from keyboard INPUT LINE stringvar include commas & leading spaces INPUT TAB(x,y) "text",vars move to (x,y) first

INPUT SPC(n) move on n spaces

GET =ASCII number of key pressed

GET$ =string containing key pressed

INKEY(n) as GET but wait only n centisecs. gives -1 if no key pressed

test if a key is currently pressed as GET$ but wait only n centisecs. flushes keyboard input buffer

from DATA list

INKEY(-n) INKEY$(n) *FX 15,1

READ varl,var2 ••• DATA vall,va12 ••. RESTORE n ADVAL(n)

ADVAL(O)

ADVAL( -n)

EV. VAL STR. ASC CHR. STRI. LEN INS. LE. RI. M.

I.

I. LIN. I.TAB I.SPC GET GE. INKEY

INK.

REA.

set up DATA list D.

data pointer to line n RES.

reads fromm analogue input channel n AD. 'fire' buttons, last conversion, etc. tests various internal buffers

11. Output to screen ~ printer

PRINT varlist

vars in list separated by P.

commas for lO-character fields on same line (strings at left of field, numbers at rt.), semicolons to print adjacent on same line, , to insert new line.

-var prints var in hexadecimal

32

PRINT TAB(x,y) or TAB(x) start at (x,y) or x

PRINT SPC(n) print n spaces

COUNT =no. of chars. since last newline

Print formats:

@%=&B4B3B2B1 (default value 10) where B1=print field width

B2=digits (total, mantissa, or after decimal pt) B3=0 for G format, 1 for E format, 2 for F format B4=1 if @% is to affect STR$, 0 otherwise

Printer:

VDU 2 CTRL B VDU 3 CTRL C *FX5 ,1 *FX5,2 *FX6,0

12. File handling

file name (tape) file name (disc) n=OPENIN(string) n=OPENUP(string) n=OPENOUT(string) INPUT# n,varlist PRINT# n,varlist m=BGETII(n)

BPUTtt n,m

CLOSEtt n

m=EOFtt( n)

m=PTRtt n

m=EXTtt (n)

enable printer enable printer disable printer disable printer

use parallel printer line use serial printer line

allow linefeeds to be sent to printer

up to 10 characters, no spaces :n.x.name (name up to 7 chars) open for input

open to update (Basic 2 only) open for output

read variables (internal format) output (internal format)

read one byte

write one byte

close file

-1 if end, 0 otherwise pointer(disc only) length (disc only)

13. Assembler and memory control

to mlc code routine at-address n =result of mlc code function at n top of available memory

bottom of available memory

top of user's program

bottom of user's program

contents of byte M

contents of M+N (M must be variable) 4 bytes at M

4 bytes at M+N (M must be variable) string at byte M onwards

(newline (ASCII 13) terminates)

[ and ] bracket Assembler code

Call to OSeLI (CALL &FFF7) passes string to OS cmd line interpreter (string addressed by X% and Y%)

CALL n [parms] USR(n)

HlMEM

LOMEM

TOP

PAGE

?M H?N

!M M!N $M

33_

P.TAB P.SPC COU.

OP.

OPENO. loll p.II B.II BP.# CLO.# EOFtt PT.# EXTII

CA.

USR

H.

LOM.

TOP

PA.

14. Sound
VDU 7 short beep (bell) V.
*FX211,n alter bell channel
*FX213 ,n alter bell frequency
*FX214,n alter bell duration SOUND &HSFC,A,P,D sound defined by so.

H=l to allow previous note to continue, 0 otherwise S=n to synchronise with n other channels (n=O to 2) F=1 to override and flush channel, 0 otherwise C=channel number, 0 to 3

A=amplitude (-15 to 0) or envelope number (1-4) P=pitch (0-255, middle C=53) for channels 1-3 P=pitch range for channel 0 (noise):

0-3 periodic: high, medium, low or as channell

4-7 white: high, medium, low or as channell D=duration (unit 1/20 sec) 0 to 254 or -1 (indefinite)

ENVELOPE N,T,PI1,PI2,PI3,PN1,PN2,PN3,AA,AD,AS,AR,ALA,ALD

N=envelope number ENV.

T=step length (centiseconds, 0 to 127):

add 128 to switch off auto-repeat

PI1 to PI3 pitch change/step in 3 sections (-128 to 127) PN1 to PN3 no. of steps in sections 1 to 3 (0 to 255) AA,AD,AS,AR: amplitude change/step in Attack, Decay,

Sustain and Release phases

(-127 to 127 (AA & AD) or to 0 (AS & AR» ALA and ALD: target amplitude at end of Attack and Decay phases (0-126)

*FX21,n *FX210,1

flushes sound channels, n=4-7 for channels 0-3 suppresses all sound

15. Modes

Mode Graphics Colours Text screen map

0 640x256 2 8Ox32 20K
1 320x256 4 40x32 20K
2 160x256 16 20x32 20K
3 2 80x25 16K
4 32Ox256 2 40x32 10K
5 160x256 4 20x32 10K
6 2 4Ox25 8K
7 Teletext display 40x25 lK Modes available on Model A: 4, 5, 6 and 7

MODE n changes to mode n

VDU 22,n ditto

Mode at switch-on is usually 7.

MO. V.

34

16. Colour (Modes 0 to 6)

COLOUR n set text colour C.

GCOL m,n· set graphics action and colour GC.

Action in GCOL:

0: plot the colour specified

1, 2, 3: OR, AND. or EOR colour with that already there 4: invert colour already there

POINT(x,y) = logical colour at PO. graphical (x ,y)

VDU 19,m,n,0,0,0 sets logical colours: V. m=logical, n=actual

VDU 20 resets all colours to defaults V.

2-colour modes O=black l=white
4-colour modes O=black l=red
2=yeUow 3=white
16-colour mode (~)

O=black l=red 2=green 3=yellow
4=blue 5=magenta 6=cyan 7=white
8=flashing black-white 9=flashing red-cyan
10=flashing green-magenta II=flashing yellow-blue
12=flashing blue-yellow 13=flashing magenta-green
14=flashing cyan-red 15=flashing white-black To change background, add 128 to colour

17. Graphics

Origin initially at bottom left:

~nge of x: 0 to 1279. Range of y: 0 to 1023.

DRAW x,y draw straight line to x,y DR.

~~VE x,y move without drawing MOV.

PLOT k,x,y draw to x,y as defined by k PL.

Values of k:

o move relative to last point 1 draw relative to last point

2 draw relative in logical inverse colour 3 draw relative in background colour

4 move to absolute posion (=MOVE)

5 draw to absolute position (=DRAW)

6 draw absolute in logical inverse colour 7 draw absolute in background colour

Add 8 to above to omit last point in 'inverting actions' Add 16 to above for a dotted line

Add 24 to above for effects of 8 and 16 1mti"O<'+"9:.-o ""a"t:fuve "t'O'iJl'1ft'S'iiig1:e--pui-nt-uni"y

Add 80 to above to fill triangle (x,y + last 2 pts).

VDU 24,xmin;ymin;xmax;ymax; sets graphics window V.

VDU 29,x;y; moves graphics origin V.

35