You are on page 1of 5

CHO MNG NGY NH GIO VIT NAM 20/11/2010

THIT K CHUYN MCH CHO BIN TN MA TRN TRC TIP 3 PHA 4 DY IMPLEMENTING COMMUTATION FOR THREE-PHASE FOUR-LEG DIRECT MATRIX CONVERTER-TFDMC
PGS.TS. BI QUC KHNH Khoa in, Trng i hc Bch Khoa H ni ThS. NG HNG HI, KS. ON VN TUN Khoa in TTB, Trng HHH Tm tt Bin tn ma trn ang c quan tm nghi n cu nhiu hn do c nhiu u im. Cc kha bn dn hai chiu s dng trong bin tn ma trn yu cu qu trnh chuyn mch tng i phc tp. Bi bo cp n cc phng php chuyn mch v thit k chuyn mch bn bc theo chiu dng in cho bin tn ma trn trc tip 3 pha 4 dy. Qu trnh chuyn mch ca TFDMC c m phng trn cng c phn mm Matlab\State Flow kim chng. Ngn ng VHDL c s dng lp trnh vi c thc hin logic chuyn mch bn bc theo chiu dng in ca TFDMC trn CPLD (Complex Programmable Logic Device). Cc kt qu nhn c chng t phng php c p dng l thch hp. Abstract The matrix converter is being more interested in the study due to many advantages. However, bidirectional switches used in matrix converter requires complicated commutation. This paper presents some commutation methods and four-step commutation with the sign of load current for three-phase four-leg direct matrix converter. The TFDMC commutation is modeled on software tools Matlab\State Flow to verify its feasibility. VHDL language is used to implement the TFDMC four-step switching sequence logic on CPLD (Complex Programmable Logic Device). The obtained results verified the operation of proposed method. 1. t vn Bi n tn ma trn (Matrix Converter MC) l b bin i trc tip AC-AC, c nhi u u im nh trao i cng sut theo hai chiu, dng in u vo c dng hnh sin, h s cng sut u vo gn bng mt [1]. Bi n tn ma trn trc tip 3 pha - 4 dy (TFDMC) c ch ra trn hnh 1, u vo c ba nhnh, u ra c bn nhnh, ba nhnh cho ba pha mt nhnh cho dy trung tnh, cu trc ny p ng c cc yu cu cho cc ph ti cn s dng dy trung tnh. Chuyn mch l qu trnh chuyn dng in t mt van bn dn ang dn b kha li sang mt van khc va m ra. Khc vi bin tn truyn thng, cc van bn dn hai chiu trong bin tn ma trn yu cu qu trnh chuyn mch tng i phc tp. Qu trnh chuyn mch trong bi n tn ma trn tun th theo hai quy tc, l khng c ngn mch pha li v khng c h mch pha ti. Quy tc th nht m bo khng xy ra ngn mch pha in p li gy ra xung dng in ln ph hy van. Quy tc th hai m bo khng gy ra hi n tng h mch pha ti gy ra qu in p, nh thng cc van bn dn. Nhiu phng php chuyn mch c nghin cu v p dng cho bin tn ma trn, chuyn mch bn bc [2], chuyn mch hai bc [3], chuyn mch mt bc, chuyn mch thng minh [2]. Do qu trnh chuyn mch din ra rt nhanh nn logic chuyn mch thng c thc hi n trn cc thit b phn cng nh l CPLD, FPGA. Logic ca qu trnh chuyn mch rt phc tp nn m bo tnh chnh xc ca cc trng thi logic, trc khi th

Tp ch Khoa hc Cng ngh Hng hi

S 24 11/2010

93

Hnh 1. Bin tn ma trn trc tip 3 pha- 4 dy.

CHO MNG NGY NH GIO VIT NAM 20/11/2010

nghim trn phn cng cn phi tin hnh m phng kim chng. 2. Chuyn mch trong bin tn ma trn 2.1. Kha bn dn hai chiu Kha bn dn hai chiu (BDS) s dng cho bin tn ma trn c xy dng trn c s cc van bn dn iu khin hon ton vi cc s nh c th hin trn hnh 2a.

a)

b)
Hnh 2. Kha bn dn hai chiu.

c)

S s dng cu diot, gm mt IGBT v bn diot, dng kha hai chiu ny khng yu cu iu khin qu trnh chuyn mch. Tuy nhin nhc im ca BDS ny l dng in chy qua ba phn t nn gy tn tht kh ln. S s dng hai IGBT mc song song ngc theo kiu chung emittor hoc chung collector v cc diot. Cc diot s dng trong kha hai chiu phi l cc diot c thi gian ng ct nhanh. Hai ki u s sau c ch to th nghim thnh modul, hnh 2b, 2c. 2.2. Cc phng php chuyn mch trong bin tn ma trn Nguyn l ca chuyn mch c l m r qua vic xt trng hp chuyn mch t pha A sang pha B, biu di n trn hnh 3. Gi thit pha A ang dn dng, pha B kho v dng ti c chiu theo hnh 3. Hai kha SA1 v SA2 u m m bo dng in c th chy theo hai chi u, tuy nhi n ti thi im xt ch thc s c kha SA1 v DA2 ang dn dng. Khi c l nh chuyn sang pha B, Hnh 3. Chuyn mch gia hai pha. logic ca qu trnh chuyn mch c th din ra theo bn bc, hai bc hoc mt bc theo chiu dng in. 2.2.1. Chuyn mch bn bc Logic ca qu trnh chuyn mch din ra theo bn bc nh sau: Ngt tn hiu iu khin ti van khng dn SA2, i u khin m van SB1, ngt tn hiu iu khin van SA1, i u khin m van SB2. Trong trng hp dng in c chiu ngc li th trnh t chuyn mch s c thc hin ngc li. hnh trng thi logic cho cc van bn dn tham gia chuyn mch c ch ra trn hnh 4a. th tn hiu iu khin cc van bn dn theo thi gian c th hin trn hnh 4b. Thi gian hon tt mt qu trnh chuyn mch ph thuc vo thi gian kha (td) ca IGBT c s dng.

a)

b)

Hnh 4. a) hnh trng thi logic cc van, b) th tn hiu iu khin chuyn mch.

2.2.2. Chuyn mch hai bc Hn ch ca phng php chuyn mch bn bc l phi qua bn bc mi chuyn mch xong, phi c thng tin chnh xc v in p chuyn mch hay chiu dng in ng thi khng c Tp ch Khoa hc Cng ngh Hng hi S 24 11/2010 94

CHO MNG NGY NH GIO VIT NAM 20/11/2010

s thay i chiu dng in trong sut qu trnh chuyn mch. C th nhn thy rng khi bit chnh xc trc chiu dng in th khng cn pht tn hiu cho van bn dn khng dn dng trong kha hai chiu, do bn bc chuyn mch ch cn l i hai bc. Trong phng php chuyn mch theo hai bc, khi chiu dng in c xc nh r (I > 0 hoc I <0) th ch iu khin cho mt van dn ang thc s dn dng, khi chi u dng in cha c xc nh r, ang trong qu trnh i chiu, lc ny n ang nm trong ngng quanh gi tr khng, trnh trng hp h mch dng ti phi iu khin m c hai IGBT trong kha hai chiu ang dn dng. Trn hnh 5 ch ra qu trnh chuyn mch hai bc gia hai pha A v B, nt m l ng i ca dng in.

a) trng thi u

b) bc 1

c) bc 2

Hnh 5. Chuyn mch t pha A sang pha B khi IL > 0.

2.2.3. Chuyn mch mt bc Theo s trn hnh 3, khi cn chuyn mch gia hai pha u vo A v B, nu bit c chnh xc du ca in p UAB v chiu dng in IL th qu trnh chuyn mch ch cn mt bc. Tn hiu iu khin s chuyn t mt IGBT ang dn dng sang mt IGBT pha khc c cng chi u dn dng. Thi gian cn thit cho chuyn mch mt bc l rt ngn, tuy nhin phng php ny l i i hi phi xc nh chnh xc du ca in p, chiu ca dng in v chu nh hng mnh t cc nhiu lon ca in p li. 3. Thit k chuyn mch TFDMC Bi n tn ma trn trc tip 3 pha 4 dy ch ra trn hnh 1, s dng hai IGBT mc emitor chung lm kha bn dn hai chiu. Phng php chuyn mch bn bc c p dng cho TFDMC. Qu trnh chuyn mch gia cc pha u vo trong bi n tn ma trn trc tip 3 pha 4 dy l hon ton c lp vi nhau, do qu trnh chuyn mch gia cc pha u vo cho mt pha u ra s bao gm ba hnh trng thi logic nh hnh 4a kt hp li vi nhau v c biu din trn hnh 6a. Vi cu trc ny, h thng chuyn mch s bao gm bn hnh trng thi logic nh hnh 6a tng ng vi bn nhnh u ra a, b, c, n ca bin tn. Logic chuyn mch ca bin tn ma trn trc tip 3 pha - 4 dy c ch ra trong bng 1, trong trng thi logic th nht ng vi vic chuyn t AB, BC, CA, trng thi logic th hai ng vi vic chuyn t BA, CB, AC.

a)

b)

Hnh 6. a) hnh trng thi logic ca chuyn mch ba pha, b) cu trc iu khin ca TFDMC.

Tp ch Khoa hc Cng ngh Hng hi

S 24 11/2010

95

CHO MNG NGY NH GIO VIT NAM 20/11/2010

Trn hnh 6b ch ra v tr ca khi chuyn mch (CM) trong cu trc iu khin ca bin tn ma trn trc tip 3 pha 4 dy. Do qu trnh chuyn mch din ra rt nhanh v logic chuyn mch phc tp, nn chp logic l p trnh c c tch hp cao CPLD c s dng thc hin logic chuyn mch. CPLD m nhn hai chc nng, m ha, la chn cc t hp van trong bng trt t thc hin cc vect chun v thc hin logic chuyn mch bn bc. Tn hiu vo ca CPLD bao gm cc h s iu bin di c tnh trong khi DSP, cung cp thng tin cho vic l a chn cc t hp van tng ng vi cc vector chun c n nh, tn hiu xc nh chiu dng in c gi v t phn o lng, cung cp thng tin cho qu trnh chuyn mch. CPLD gi ra cho khi Gate driver 24 tn hi u cho 12 kha bn dn hai chiu. Ngn ng VHDL c s dng lp trnh thc hin logic chuyn mch bn bc trn CPLD. Lu thut ton cho vic lp trnh iu khin chuyn mch t pha A sang pha B c ch ra trn hnh 8a. T trng thi ban u, kim tra du ca dng in ti, nu IL > 0 th thc hin chuyn mch theo trnh t LOGIC1, nu IL < 0 th thc hi n chuyn mch theo trnh t LOGIC2, thc hin tng t cho trng hp cn l i.
Bng 1. Logic chuyn mch ca bin tn ma trn trc tip 3 pha 4 dy.
SA1.S A2 - SB1.SB2 - SC1.SC2
A

SA1 IL > 0 10 11 01 01 00 00 00 01

SA2 00 00 00 01 10 11 01 01

SB1 01 11 10 11 00 00 00 10 10 11 01 01 00 00 00 01

SB2 00 00 00 11 01 11 10 10 00 00 00 01 10 11 01 01

SC1

SC2

Bc 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

11 - 00 - 00 00 - 11 - 00

IL < 0

00 - 11 - 00 00 - 00 - 11

IL > 0

IL < 0 10 11 01 01 00 00 00 01 00 00 00 01 10 11 01 01

00 - 00 - 11 11 - 00 - 00

IL > 0

IL < 0

01 11 10 11 00 00 00 10 01 11 10 11 00 00 00 10

00 00 00 11 01 11 10 10 00 00 00 11 01 11 10 10

4. M phng chuyn mch TFDMC M phng TFDMC c thc hin trn phn mm Matlab, trong phn logic chuyn mch bn bc theo chiu dng in c thc hin trn cng c State Flow, kt qu m phng c ch ra trn hnh 7 vi ti R-L c thng s R = 10 Omh, L = 0,2H. Ngn ng phn cng VHDL c la chn lp trnh v m phng vic thc hin logic chuyn mch bn bc theo chiu dng in ca TFDMC trn CPLD, kt qu m phng c ch ra trn hnh 8b.

a)

b)

Tp ch Khoa hc Cng ngh Hng hi

S 24 11/2010

96

CHO MNG NGY NH GIO VIT NAM 20/11/2010

c)

d)

Hnh 7. a) Chuyn mch bn bc ca tn hiu iu khi n, b) Tn hiu iu khin cho cc van IGBT ca pha a u ra, c) in p dy u ra, d) in p ri trn kha bn dn hai chiu.

a)

b)

Hnh 8. a) Lu thut ton khi chuyn mch t pha A sang pha B, b) kt qu m phng trn ngn ng VHDL.

5. Kt lun Bi bo khi qut cc phng php chuyn mch cho bin tn ma trn v thit k chuyn mch cho bin tn ma trn trc tip 3 pha 4 dy. Vic p dng phng php chuyn mch bn bc cho bin tn ma trn trc tip 3 pha 4 dy nhn c kt qu tch cc. Cc kt qu nhn c t vic m phng qu trnh chuyn mch trn State Flow cho thy logic chuyn trng thi ca cc van bn dn ng trnh t v r rng, khng c s qu in p trn cc van bn dn v in p u ra. Vic thc hin logic chuyn mch trn CPLD m bo c tch cht ng ct nhanh ca cc van bn dn trong qu trnh chuyn mch. Kt qu m phng trn ngn ng VHDL l c s trin khai phn chuyn mch ca bin tn ma trn trc tip 3 pha 4 dy trong thc t. TI LIU THAM KHO [1] Bi Quc Khnh, ng Hng Hi, on Vn Tun, iu bin vect khng gian cho bin tn ma trn gin tip 3 pha 4 dy, Tp ch Khoa hc v Cng ngh Hng hi, s 22, trang 27-33, 2010. [2] Trn Trng Minh, Lun n tin s k thut, H ni, 2007. [3] Ziegler, M.; Hofmann, W., Implementation of a two steps commutated matrix converter, Power Electronics Specialists Conference, 1999. PESC 99. 30th Annual IEEE , Volume: 1 , 27 June-1 July 1999. Page(s): 175 -180 vol.1. Ngi phn bin: TS. Trn Sinh Bin

Tp ch Khoa hc Cng ngh Hng hi

S 24 11/2010

97