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Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________ AIM:To write the program to implement operation of 2x4 Decoder and observe wave forms SOFTWARE REQUIRED:Xilinx software THEORY:

DECODERS

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

D0 <= Abar and Bbar. . D2 <= A and Bbar. Ghatkesar (M). entity DECODER_2x4_DF is Port ( A : in STD_LOGIC. OUTPUT WAVEFORM FOR DECODER_2x4_DF: DECODERS ANURAG GROUP OF INSTITUTIONS.). B : in STD_LOGIC. D0 : out STD_LOGIC. A.TITLE: Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________ VHDL CODE FOR DECODER_2x4_DF: library IEEE.Bbar : STD_LOGIC. Bbar <= not B. D2 : out STD_LOGIC.STD_LOGIC_1164. Venktapur (V). D3 <= A and B. CSE DEPT. D3 : out STD_LOGIC). end DF. D1 : out STD_LOGIC. begin Abar <= not A.ALL. INDIA. D1 <= Abar and B.P. use IEEE. architecture DF of DECODER_2x4_DF is Signal Abar. Ranga Reddy (Dist. end DECODER_2x4_DF.

Ranga Reddy (Dist. Venktapur (V). A.TITLE: Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________ RTL SCHEMATIC FOR FA_DF GATE: TOPVIEW DECODERS INTERNAL HARDWARE CIRCUIT DIAGRAM ANURAG GROUP OF INSTITUTIONS. CSE DEPT. INDIA.P. Ghatkesar (M).). .

Cout <= '0'. elsif (A = '1' and B = '0' and Cin = '1') then SUM <= '0'. elsif (A = '0' and B = '1' and Cin = '1') then SUM <= '0'. Ranga Reddy (Dist. end FA_Behavioral. Cout : out STD_LOGIC). A. Cout <= '1'. INDIA. Cout <= '1'. Cout <= '1'.B. Cout <= '1'. . end if. Cout <= '0'.STD_LOGIC_1164. elsif (A = '1' and B = '1' and Cin = '0') then SUM <= '0'. Ghatkesar (M). Cout <= '0'. elsif (A = '1' and B = '0' and Cin = '0') then SUM <= '1'. CSE DEPT. end process. Cin : in STD_LOGIC. Venktapur (V). architecture Behavioral of FA_Behavioral is begin process (A. end Behavioral. B : in STD_LOGIC. else SUM <= '1'. use IEEE.). Cout <= '0'.Cin) begin if (A = '0' and B = '0' and Cin = '0') then SUM <= '0'. entity FA_Behavioral is Port ( A : in STD_LOGIC.ALL.TITLE: Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________ DECODERS VHDL CODE FOR FA-BEHAVIORAL GATE: library IEEE. OUTPUT WAVEFORM FOR FA-BEHAVIORAL GATE: ANURAG GROUP OF INSTITUTIONS. elsif (A = '0' and B = '1' and Cin = '0') then SUM <= '1'.P. SUM : out STD_LOGIC. elsif (A = '0' and B = '0' and Cin = '1') then SUM <= '1'.

). .P. A. CSE DEPT. Ghatkesar (M).TITLE: Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________ DECODERS RTL SCHEMATIC FOR FA-BEHAVIORAL GATE: TOPVIEW ANURAG GROUP OF INSTITUTIONS. INDIA. Ranga Reddy (Dist. Venktapur (V).

SUM1. end FA_STRUC. Y : out STD_LOGIC). .CARRY1). OUTPUT WAVEFORM FOR FA-STRUCTURAL: ANURAG GROUP OF INSTITUTIONS. S : out STD_LOGIC. end component. Q : in STD_LOGIC. A. Ghatkesar (M). X : out STD_LOGIC. O1: OR_GATE port map (CARRY1. Cin : in STD_LOGIC.Cout).CARRY2:STD_LOGIC.CARRY1. H2: HA1 port map (SUM1.CARRY2).).P.ALL. use IEEE. Y_OR : out STD_LOGIC).B. begin H1: HA1 port map (A. component OR_GATE is Port ( P : in STD_LOGIC.S. B : in STD_LOGIC. M : in STD_LOGIC.SUM2.CARRY2.TITLE: Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________ INTERNAL HARDWARE CIRCUIT DIAGRAM DECODERS VHDL CODE FOR FA-STRUCTURAL: library IEEE. end component. end STRUCTURAL. Ranga Reddy (Dist. signal SUM1. entity FA_STRUC is Port ( A : in STD_LOGIC. Cout : out STD_LOGIC). architecture STRUCTURAL of FA_STRUC is component HA1 is Port ( L : in STD_LOGIC.Cin. CSE DEPT. INDIA. Venktapur (V).STD_LOGIC_1164.

.). Ranga Reddy (Dist.P. Venktapur (V). INDIA.TITLE: Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________ DECODERS RTL SCHEMATIC FOR FA-STRUCTURAL: TOPVIEW INTERNAL HARDWARE CIRCUIT DIAGRAM ANURAG GROUP OF INSTITUTIONS. Ghatkesar (M). A. CSE DEPT.

236ns ANURAG GROUP OF INSTITUTIONS. A. Ranga Reddy (Dist. Venktapur (V).). INDIA. CSE DEPT.TITLE: Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________ DECODERS RESULTS: Device utilization summary: --------------------------Selected Device : 3s500efg320-4 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 1 2 5 5 out of out of out of 4656 9312 232 0% 0% 2% Timing Summary: --------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 6.P. Ghatkesar (M). .