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T_TO_J-K FLIP FLOP CONVERSION VHDL CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
--------------------------------------------------------entity T_to_JK is
Port ( J,K,clock,reset : in STD_LOGIC;
Q,Q1 : inout STD_LOGIC);
end T_to_JK;



Library ieee declaration.
In “ieee” library std_logic_1164 package is
declared for std_logic data types (predefined data
types).

Entity describes circuit external ports.
J, K, clock, reset: - input port to T flipflop.
Q, Q1: - output port to T flip-flop.

--------------------------------------------------------architecture structural_con of T_to_JK is
--------------------------------------------------------signal s1,s2,s3: std_logic;
-----------------------------------component t_ff
 Signal s1, s2,s3 are declared to hold a
particular value. These are acting as inout
port (t,clk,rst:in std_logic;
ports.
y,z:out std_logic);

Components (t_ff , and1 and or_1)
end component;
declaration.
--------------------------------- Declarative part of J-K flip-flop’s
component and_1 is
architecture.
port (a,b:in std_logic;
 Components represent the structure of
converted flip-flop circuit.
c:out std_logic);
 And1 component performs AND
end component;
operation in digital circuit.
--------------------------------- Or_1 component performs operation in
component or_1 is
digital circuit.
port (d,e:in std_logic;
f:out std_logic);
end component;
--------------------------------------------begin
------------------------------------------------------------------------a1:and_1 port map (J,Q1,s1);
 Statements part of the
architecture.
a2:and_1 port map (K,Q,s2);

Components are port mapped to
a3:or_1 port map (s1,s2,s3);
perform J-K flip-flop operation.
ff: t_ff port map (s3,clock,reset,Q,Q1);
-------------------------------------------------------------------------end structural_con;
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