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S-R_TO_J-K FLIP FLOP CONVERSION VHDL CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
--------------------------------------------------------entity SR_to_JK is
Port ( J,K,clock,reset : in STD_LOGIC;
Q,Q1 : inout STD_LOGIC);
end SR_to_JK;




Library ieee declaration.
In “ieee” library std_logic_1164 package is
declared for std_logic data types (predefined data
types).

Entity describes circuit external ports.
J, K, clock, reset: - input port to J-K flipflop.
Q, Q1: - output port to J-K flip-flop.
q:- present state, qbar: - next state.

--------------------------------------------------------architecture structural_con of SR_to_JK is
--------------------------------------------------------signal s1,s2:std_logic;
----------------------------------- Signal s1, s2 are declared to hold a
component s_rff
particular value. These are acting as inout
port (s,r,clk,rst:in std_logic;
ports.
x,y:inout std_logic);
 Components (s_rff and and1) declaration.
 Declarative part of D flip-flop’s
end component;
architecture.
----------------------------------- Components represent the structure of
component and1 is
converted flip-flop circuit.
port (a,b:in std_logic;
 And1 component represents AND
c:out std_logic);
operation in digital circuit.
end component;
-----------------------------------begin
------------------------------------------------------------------------ Statements part of the
a1:and1 port map (J,Q1,s1);
architecture.
a2:and1 port map (Q,K,s2);
 Components are port mapped to
ff:s_rff port map (s1,s2,clock,reset,Q,Q1);
perform J-K flip flop operation.
-------------------------------------------------------------------------end structural_con;

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