ONILNE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R) T FLIP-FLOP VHDL CODE USING BEHAVIOURAL MODELING

 Library ieee declaration. In “ieee” library std_logic_1164 package is declared for std_logic data types (predefined data types).

library IEEE;  use IEEE.STD_LOGIC_1164.ALL; -------------------------------------------------------

entity t_ff is  Port ( T, clock, reset : in STD_LOGIC;   Q,Q1 : out STD_LOGIC);  end t_ff; ------------------------------------------------------architecture behavioral_tff of t_ff is -------------------------------------------------------Architecture begins. begin -------------------------------------------------------process (T, clock, reset) variable x: std_logic:=’0’; begin if (clock' event and clock='1' ) then if ( reset='1' ) then x<='0'; elsif ( T='0' ) then x<=x; elsif ( T='1') then x<=not x; end if; end if; Q<=x; Q1<=not x; end process; ----------------------------------------------------------end Behavioral_tff;

Entity describes circuit external ports. T , clock, reset: - input port to T flip flop. Q, Q1: - output port to T flip flop. Q:- present state, Q1: - next state.

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In a process all the statements will be executed sequentially. In process, a variable (x) is declared to hold the output value. Its life is bounded till process end. If clock rising edge is +ve and reset is ‘0’ then flip flop will work otherwise its output will be previous state. Truth table of T flip flops…. T 0 1 Q Previous state toggle Q1 Previous sate toggle

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