# 5.

2) Full Subtractor:

Definition: Unit that performs 1-bit subtraction with borrow-in is defined as a fullsubtractor (FS)

Truth Table: bin X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Y 0 1 0 1 0 1 0 1 bout D (x-bin-y) 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 Comment 0-0-0 = 0, No borrow 0-0-1 = -1, borrow 2, so: 2-1 = 1 1-0-0 = 1, No borrow 1-0-1 = 0, No borrow 0-1-0 = -1 (bin=1), borrow 2, so: 2-1 = 1 0-1-1 = -2 , borrow 2, so: 2-2=0 1-1-0 = 0, No borrow 1-1-1 = -1, borrow 2, so: 2-1 =1

K-Map and function derivation:

Implementation and symbol of full subtractor (FS):

6-bit Ripple-borrow subtractor using full subtractor:

X5 Y5 bout FS

X4 Y4

X3 Y3

X2 Y2

X1 Y1

X0 Y0 bin

FS

FS

FS

FS

FS

5.4 (b) Design CLA using the library in Table 3.14 and Table 3.15
Ci

P i g i

C i+1

P i+1

C i+2

gi+1

C i+3

P i+2 gi+2

P (i,i+3)

g(i,i+3)

P i+3 gi+3 C i+4

5.15 (a) Redesign the 2-bit comparator that compares X = x1x0 with Y=y1y0, under the condition that x0 and y0 will never be 1 at the same time

Original truth table for a 2-bit comparator: x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 y1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x0 y0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 G 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 L 0 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0

Highlighted are the cases where x0 and y0 are equal to 1. Since these cases will never arise (stated in the question), the values of G and L can be considered don’t cares for these cases. Note the changes in the truth table from the original, changes are highlighted in gray. x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 y1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x0 y0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 G 0 0 1 x 0 0 0 x 1 1 1 x 0 0 1 x L 0 1 0 x 1 1 1 x 0 0 0 x 0 1 0 x

x1y1

x0y0 00 01 11 00 x 01 x 11 x 10 1 1 x

10 1 1 1

G = x1y1’ + x1x0 + y1’x0 00 01 11 10 00 1 x 01 1 1 x 1 x1y1 11 1 x 10 x L = x1’y1 + y1y0 + x1’y0

Implementation of G and L functions in terms of AND, OR, NOT gates:

X1 X0 G

Y1 Y0 L

From Table 3.14 and Table 3.15, inverter has 2 transistors, 2-input AND has 6 transistors, and 3-input OR has 8 transistors. Above implementation of functions G and L has 2 inverters, 3 2-input AND gates and 2 3-input OR gates. So the implementation has 2*2 + 3*6 + 2*8 = 38 transistors. In the original implementation given in 5.21(c) there are 4 inverters, 2 2-input AND gates, 4 3-input AND gates and 2 3-input OR gates. This requires 4*2 + 2*6 + 4*8 + 2*8 = 68 transistors (using data in Table 3.14 and Table 3.15). The serial implementation of 8-bit comparator shown in Figure 5.22(a) has 8 2-bit comparators. So the original implementation would require 68 * 8 = 544 transistors. However, using the condition that x0 and y0 are never equal to 1, the transistor count can be reduced to only 38 * 8 = 304 transistors.