A Presentation On Refining Hardware/Software interfaces

By : Arun Kishor Johar & Suresh Kumar M-Tech VLSI Design

Guided By : Dr. Lava Bhargava (Associate Professor ) MNIT Jaipur

Refining Hardware/Software interfaces

Any behavioral description can be implemented as either as Software or Hardware. If Software then behavioral description will be compiled into instruction set of chosen processor. If Hardware then it will be synthesized into structure of components from a given library. Processor with memory is considered as Software Component. While others are termed as hardware components like ASIC.

A Hardware software system architecture

1. The hardware and Software components are connected by a bus. 2. A bus master is any component that can control the bus and initiate data transfer such as processors ,Disk controllers and DMA controllers. 3. A bus slave is any component that can respond to bus master. 4. When two or more bus masters are connected to a single bus we need a bus arbiter.

A partitioned specification

Target Architecture
v1 to v6 represents variables . B1 to B4 represents behaviors . p1 to p3 are ports . Software variable v1 Software ports p1 Hardware variables v3 v5 v6 Hardware ports p3 Shared variables v2 v4 Shared port p2

Variable Distribution

Fig(a) Both Hardware and shared variable reside in the memory Fig(b)Hardware variable reside in ASIC while shared variable resides in memory Fig(c)both hardware and shared variable reside in ASIC If we assign Software variables to ASIC then it will increase the cost of ASIC due to extra Silicon. Assigning Hardware variables to ASIC will increase BUS Traffic and Slow down ASIC So here we will find a Tradeoff between performance and cost for any shared variable

Figure aspects.. Behavior A is executed on processor Behavior B1 and B2 are synthesized into ASIC If we assume average channel rates of X , Y1 and Y2 are avgrate(X), avgrate (Y1) and avgrate (Y2) then bus transfer rate for fig(a) will be avgrate(X)+avgrate (Y1) +avgrate (Y2) For fig( (b) avgrate(X)+avgrate (Y1) For fig (c) avgrate(X)

Algorithm : Variable distribution Determine Sb /* set of buses*/ Determine Sv /* set of variables */ mincost = mincost_bus = unknown mincost_var_dist = unknown for each B Sb loop for each D of Sv loop datarate(D,B) C mapped to B avgrate(C) if (datarate(D,B) rate(B)) then mincost = currcost mincost_bus=B mincost_var_dist = D end if end if end loop end loop if (mincost = ) then return( failure) else return(mincost_bus, mincost_var_dist) end if

Interface Generation

Figure(a) Two components (b) Component and a bus Sometimes designer encounters a situation where communication protocol of selected bus and selected component are incompatible and no off-the-shelf component available to be used for interface. Here we generate a technique for interfacing between two incompatible components which consists of following steps:1. Represent the protocols of components to be interfaced as ordered relations. 2. Partition relations into relation groups. 3. Generate an interface description by inverting each operation in relation group i.e. replacing each operation in the relation group with its dual operation.

Algorithm : Generate Interface Process /* generate relations for each protocol*/ Ra = CreateRelations(Pa) Rb = CreateRelations(Pb) /*partition relations into a set G of relation groups G = GroupRelations(Ra,Rb) /* add dual statement for each operation in G to interface procsess for each relation group Gi G loop for each relation Rj Gi loop for each atomic operation Ok Rj loop AddDualStatement(IP,Ok) end loop end loop end loop CreateAndOptimizePorts(IP,Pa,Pb)

Data Access Refinement

When we assign a behavior and variable it accesses to different partitions, we need to refine the variable access in the description since the definition of the variable has been moved away from the behavior.

Software Partition
Memory

ASICs Dual Port Buffer

Hardware Partition
Memory

V1

V2

V3

V4

V5

V6

B1

B2

B3

B4

P1

P2

P3

After The Variable Distribution: Assume that

The Shared variable V2 and hardware variable V5 have been assign to memory. Shared variable V4 has been assign to the ASICs dual port buffer.

A Specification Mapping to target architecture

Data accesses within the same partition are not a problem, since they will be taken care of either by software compilation, as is the case V1 in the figure or by a hardware synthesis tool, as is the case with V3 and V6.

A Specification Mapping to target architecture

Therefore, the task of data access refinement is to refine data access across partitions as in case V2, V4 & V5.

Relations for the component's Protocol

Component A: ADDRP <= AddrVar(31 downto 0); DREQP <= 1; Wait until (DRDYP =1); DataVar(31 downto 0) <= DATAP; A1 [(true) : ADDRP <= AddrVar(31 downto 0) DREQP <= 1 + A2 [( DRDYP = 1) : DataVar(31 downto 0) <= DATAP]

Relations for the bus's Protocol

Bus B: Put address on ADDR; AS* <= 0; Wait until (DTACK =0); Data on DATA is ready; AS* <= 1; B1 [(true): Put address on ADDR; AS* <= 0;+ B2 *(DTACK =0): Data on DATA is ready; AS* <= 1;+

Relations Groups
Protocol Protocol in (a) in (b) ----------------------------------------------A1 (32) B1 (32) ----------------------------------------------A2 (32) B2 (32) -----------------------------------------------G1=(A1 B1) G2=(B2 A2)

Generated Interface

Software Behaviors Access Memory Locations

This type of data access is carried out through the processors Load/Store instructions.

Hardware Behaviors Access Memory Locations

Since this type of data access is carried out by ASIC through a direct-memory access (DMA) mechanism we called them DMA operations.

Software Behaviors Access Ports or the ASICs Buffer

This type of data access is carried out through the processors in/out or move instructions

Hardware Behaviors Access the ASICs Buffer

This type of data access is carried out by ASICs access to its buffer locations, we call them buffer operations. These operations use separate bus in the ASIC.

Tasks of Data Access Refinement

Assign address to variables or ports that have been mapped to the global address space. Replace the software access to those variables assigned to the memory by the load and store operations. Similarly, replace hardware access to those variables with DMA operations. Use in and out operations to replace software access to those variables that are mapped to ASICs. Use buffer operations to replace their access from hardware behaviors. Use in and out operations to replace any software access to the ports that are mapped to global address space

Control Access Refinement

Unlike data access channel which exists between behavior and variable, control channel exists between two behaviors to indicate the starting or completion of behavior
Error

Assigned to hardware implementation

One solution to this problem would be to introduce Hand-Shaking Protocol. Using two shared variables: Start and Done.

Could be mapped to the target architecture

Control refinement will be completed after the data access refinement for shared variable Start and Done is performed

 This control refinement scheme is a simple one since the rest of software parts will not be affected by B2s being moved to hardware. We should be aware however, that this scheme would require the processor to pull the location that store the value of the variable Done, and this may waste processors clock cycles.
Since commercial processors usually provide an interrupt mechanism

More efficient method of control access refinement is possible.

Tasks of Control access refinement

Chose a control scheme, such as polling or interrupt. Then insert the corresponding communication protocols in the software and the hardware behaviors. Insert any necessary software behaviors, such as interrupt service routines. Refine the accesses to shared variables that have been introduced by insertion of the protocols.

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