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Prepared by: Students of S.E.-COMPUTER (A) Academic Year 2009-2010
MAHATMA EDUCATION SOCIETY’S PILLAI’S INSTITUTE OF INFORMATION TECHNOLOGY ENGINEERING, MEDIA STUDIES & RESEARCH Dr.K.M.Vasudevan Pillai’s Campus, Sector-16, New Panvel-410206.
TECHNICAL REPORT ON CENTRAL PROCESSING UNIT : Prepared by : Akhil Reghunathan Nilesh Jamdade Manisha Arutla Babu C.Laxmanan CEA301 CEA319 CEA304 CEA306
CLASS: - S.E. (COMPUTER) DEPARTMENT OF HUMANITIES
Under the guidance of Prof.Dr. Malavika Sharma Prof.Dr. Malavika Sharma (Head of Department)
Letter of Transmittal
From Students of S.E.-COMPTUTER (A), PIIT, New Panvel -410206 22nd October, 2009
To Prof .Dr. (Mrs.) Malavika Sharma PIIT, New Panvel -410206. Subject: A Technical Report on Central Processing Unit Dear Madam,
We take this opportunity in seeking permission to write a technical report on Central Processing Unit as asked by you on 1st October, 2009.The report is now completed, and it is attached to this cover memorandum. We have tried to meet your requests and hope that the report will be useful for your reference. Thank you Yours faithfully, Akhil Reghunathan Nilesh P.Jamade Manisha Arutla Babu.C.Laxmanan
This report is done as a part of our curriculum of second year computer engineering third semester in subject ‘Presentation and Communication Techniques (PCT)’. The main aim of this report writing is to utilize our presentation and communication skills. The name of our presentation topic is ‘CPU’. In this we have covered CPU Architecture, Basic Instruction Cycle, Basic addressing modes, and Instruction formats. This report gives complete knowledge of all the topics covered.
We would like to convey our deepest gratitude to the faculty and staff of Pillai’s Institute of Information Technology for their unrelenting support and encouragement throughout the project. We are greatly indebted to our honorable Principal Dr.G.T. Thampi for his support and his generosity in providing us with facilities relevant to our project. It has been privilege to have been blessed with constructive guidance by our project guide Prof.Dr. Malavika Sharma. Whose security helped us to make our project flawless.
The central processing unit (CPU) is the component of a computer that actually processes the data. CPU designs vary a great deal, but for our purposes we may treat all CPUs as having simply an arithmetic-logic unit, a control unit, and several registers. In recent designs, a memory management unit is also often found. Each CPU has a built-in clock that controls the pace of events and synchronizes the operations of its various parts. The control unit of a CPU coordinates all the actions performed by the CPU and the peripheral devices it controls. The control unit performs four basic functions: fetch (getting the next program instruction from memory), decode (determining what the instruction just fetched means), execute (performing the requested action), and write-back (writing the results, if necessary, to memory or to a local register). A CPU is capable of executing a set of basic operations, such as writing a character to memory, reading a character from memory, or comparing two numbers to see which is larger. The code word ordering a CPU to perform one of these basic operations is called an instruction, and the set of instructions that the CPU is able to perform is called its instruction set.
Table of Content
Letter of transmittal Preface Acknowledgments Executive Summary Chapter I Introduction i ii iii iv 1
Basic Instruction Cycle
Basic Instruction Format
Chapter I INTRODUCTION
In order to work, a computer needs some sort of "brain" or "calculator". At the core of every computer is a device roughly the size of a large postage stamp. This device is known as the central processing unit, or CPU for short. This is the "brain" of the computer; it reads and executes program instructions, performs calculations, and makes decisions. The CPU is reponsible for storing and retrieving information on disks and other media. It also handles information on from one part of the computer to another like a central switching station that directs the flow of traffic throughout the computer system. • It is a processor, because it processes(moves and calculates) data.
• It is central,because it is the centre of data processing
Central Processing Unit(CPU):“The Heart of the computer” that takes care of all the computations and processes. CPU in any digital computer is responsible for execution of instructions .It comprises of a number of registers and the digital functions that implement arithmetic logic, shift and transfer micro-operations The processor unit, when combined with a control unit that supervises the sequence of micro-operations is called a central processing unit (CPU). Controls the operation of the computer and performs its data processing functions; often simply referred to as processor • Main Memory: Stores data • I/O: Moves data between the computer and its external environment • System Interconnection: Some mechanism that provides for communication among CPU, Main Memory and I/O Its major structural components are:Control Unit: Controls the operation of the CPU and hence the computer
Arithmetic & Logic Unit: Performs the computer’s data processing functions
Registers:- Provides storage internal to the CPU
CPU interconnection: Some mechanism that provides for communication among the control unit, ALU and Registers. • Internal CPU bus is needed to transfer data between the various registers and the ALU. • ALU operates on data in internal CPU registers. • Basic elements of an ALU are Arithmetic and Boolean logic unit, complements and shifter shift right and shift left). • The number of registers in a processor unit may vary. Recent computers employ a larger number of processor registers. • An operation in a processor unit is implemented with a sequence of microoperations .The processor unit need only have circuits that implement simple, basic micro-operations such as add and shift. Other operations, such as multiplication and division are generated with the help of control unit. The digital function that implements the micro-operations on the information stored in processor registers is commonly called an arithmetic logic unit or ALU .The ALU receives information from the registers and perform a given operation as specified by the control .The result of the operation is then transferred to a destination register.
Major components of CPU are:1) Arithmetic logic unit 2) Control unit 3) Memory Unit
1. Arithmetic Logical Unit (ALU): After you enter data through the input device it is stored in the primary storage unit. The actual processing of the data and instruction are performed by Arithmetic Logical Unit. The major operations performed by the ALU are addition, subtraction, multiplication, division, logic and comparison. Data is transferred to ALU from storage unit when required. After processing the output is returned back to storage unit for further processing or getting stored.
2. Control Unit (CU): The next component of computer is the Control Unit, which acts like the supervisor seeing that things are done in proper fashion. The control unit determines the sequence in which computer programs and instructions are executed. Things like processing of programs stored in the main memory, interpretation of the instructions and issuing of signals for other units of the computer to execute them. It also acts as a switch board operator when several users access the computer simultaneously. Thereby it coordinates the activities of computer’s peripheral equipment as they perform the input and output. Therefore it is the manager of all operations mentioned in the previous section.
3. Memory Unit: Main memory is needed in a computer to store in instructions and the data at the 3
time of program execution. It was pointed out by Von Neumann that the same memory can be used for storing data and instruction. The memory unit stores all information in a group of memory cells as binary digits. Each memory location has unique address and can be addressed independently. The contents of desired memory location are provided to the CPU by referring to the address of memory location. The amount of information, which can be transferred between CPU & memory, depends on the sizes of Bus connecting the two.
CPU Architecture contains the following: Address Registers: Address registers store the addresses of specific memory locations. Often many integer and logic operations can be performed on address registers directly (to allow for computation of addresses). Sometimes the contents of address register(s) are combined with other special purpose registers to compute the actual physical address. This allows for the hardware implementation of dynamic memory pages, virtual memory, and protected memory. The number of bits of an address register (possibly combined with information from other registers) limits the maximum amount of addressable memory. A 16bit address register can address 64K of physical memory. A 24-bit address register can address address 16 MB of physical memory. A 32-bit address register can address 4 GB of physical memory. A 64-bit address register can address 1.8446744 x 1019 of physical memory. Addresses are always unsigned binary numbers. See number of bits.
MIX: one jump registers; named J-register; two bytes and sign is always positive Motorola 680x0, 68300: 8 long word (32 bit) address registers; named A0, A1, A2, A3, A4, A5, A6, and A7 (also called the stack pointer) Store addresses in PC: Program Counter to hold address of next instruction to be fetched MBR: Memory Buffer Register for value to be read/written from/to memory IR: Instruction Register to contain opcode of the last Instruction
Accumulator: Accumulators are registers that can be used for arithmetic, logical, shift, rotate, or other similar operations. The first computers typically only had one accumulator. Many times there were related special purpose registers that contained the source data for an accumulator. Accumulators were replaced with data registers and general purpose registers. Accumulators reappeared in the first microprocessors Register(s) Accumulates bits swapped in and out of the ALU.
Shifter: Stores, carries and rotates results
Program Counter: Almost every digital computer ever made uses a program counter. The program counter points to the memory location that stores the next executable instruction. Branching is implemented by making changes to the program counter. Some processor designs allow software to directly change the program counter, but usually software only indirectly changes the program counter (for example, a JUMP instruction will insert the operand into the program counter). An assembler has a location counter, which is an internal pointer to the address (first byte) of the next location in storage (for instructions, data areas, constants, etc.) while the source code is being converted into object code. Register Contains the address of the next instruction to be fetched and executed. The program counter is then incremented and the next processing cycle begins.
Stack Pointer : Stack pointers are used to implement a processor stack in memory. In many processors, address registers can be used as generic data stack pointers and queue pointers. A specific stack pointer or address register may be hardwired for certain instructions. The most common use is to store return addresses, processor state information, and temporary variables for subroutines
Register Keeps track of the STACK.
Control Path: Control path is responsible for instruction fetch and execution sequencing. It is responsible for operand fetch. It is responsible for saving results.
STACK: Register(s) A stack register is a computer central processor register whose purpose is to keep track of a call stack. On an accumulator-based architecture machine, this may be a dedicated register such as SP on an Intel x86 machine. The Stack is not part of the CPU it is part of memory. The pull operation results in a transfer of the word at the top of the stack into the accumulator. The push operation puts a word on the stack. The final accumulator contents are deposited on top of the stack. The Stack Pointer keeps track of what’s next on the stack. First word at the bottom.
Chapter III BASIC INSTRUCTION CYCLE
The Instruction Fetch Execute Cycle is one of the most important mental models of computation as aptly put by Prof. Rockford Ross. This embodies the basic principle of how all modern processors work. This functional model has remained more or less the same over the decades no matter how and when the development of processors have taken place ever since the days of Von Newmann architecture to today’s Super computers. This document is to be read in conjunction with the tutorial presented on the Instruction Fetch Execute Cycle of the Intel processor. The principles are fairly simple and can be easily generalized to any processor or Operating System. It further proceeds to explain what happens when a computer is first switched on till the time it is ready to accept instructions from the user. It is very important to appreciate the fact that an Operating System (OS) is just like any other program albeit a little more complex as compared to user written programs. The OS provides the functionality to load and execute other programs and thus possesses certain privileges which user programs do not possess. A user program can and does request for OS intervention through a mechanism called system calls e.g. trap, page fault etc. • • • • Once started, a computer continuously performs the following: Fetch next instruction from memory Decode the instruction Execute the instruction
Special purpose registers used are 1. PC: Program Counter to hold address of next instruction to be fetched 2. MBR: Memory Buffer Register for value to be read/written from/to memory 3. IR: Instruction Register to contain opcode of the last Instruction
INSTRUCTION CYCLE: An instruction as the name instructs the computer what to do. In simple terms, every line of a program that we as users write instructs the computer to perform a series of operations. We may argue that our programs comprise of the instructions belonging to one of those of the High Level Languages like C, C++, and Java etc. A computer understand these high level instructions by converting them into a machine understandable form known as machine language comprising of 1’s and 0’s. Thus the following instruction in C eg.: int cnt; cnt = cnt +2; may get translated into the corresponding machine language as: 000101010101111101010101010000000111111….. We as users would not be able to understand this machine language. To make better sense we resort to Assembly Language where each machine language instruction is assigned a code known as a mnemonic. So instead of remembering some string of 0's and 1's, the programmer would only need to remember short codes like ADD, MOV etc. e.g. mov al, 0x21 The above mnemonic means to move the value of the hexadecimal number 21 into a Register called al. These mnemonics are in turn converted into machine instructions. Therefore, the Central Processing Unit (CPU) can now begin to execute the instructions by fetching them from the memory. The CPU does this continuously till it is shut down. The processing required for a single operation is called an instruction cycle. The entire process of fetching, decoding and executing an instruction constitutes the CPU’s instruction cycle. It uses simplified two steps referred as fetch cycle and execute cycle as shown in figure below. Program execution halts only if the machine is turned OFF, some sort of unrecoverable error occurs or a program instruction that halts the computer is encountered.
DATA FLOW: • • • Depends on CPU design In general: Assume CPU employ PC,IR,MAR,MBR Fetch — PC contains address of next instruction — Address moved to MAR — Address placed on address bus — Control unit requests memory read — Result placed on data bus, copied to MBR, then to IR — Meanwhile PC incremented by 1 The exact sequence of events during an instruction cycle depends on the design of the processor. We can however, indicate in general terms what must happen. Let us assume that a processor that employs a memory address register (MAR), a memory buffer register (MBR), a program counter (PC), and an instruction register (IR). During fetch cycle, an instruction is read from memory. Figure shows the flow of data during this cycle. The PC contains the address of the next instruction to be fetched. This address is moved to MAR and placed on the address bus. The control unit requests a memory read, and the result is placed on the data bus and copied into the MBR and then moved to the IR. Meanwhile, the PC is incremented by 1, preparatory for the next fetch. Once the fetch cycle is over, the control unit examines the contents of the IR to determine if it contains an operand specifier using indirect addressing. If so, an indirect cycle is performed. As shown in figure, this is a simple cycle. The rightmost N bits of MBR, which contains the address reference, are transferred to the MAR. Then the control unit requests a memory read, to get the desired address of the operand into the MBR.
Execution Cycle: • Processor-memory — data transfer between CPU and main memory • Processor I/O — Data transfer between CPU and I/O module • Data processing — Some arithmetic or logical operation on data • Control — Alteration of sequence of operations — e.g. jump • Combination of above
The fetch and indirect cycles are simple and predictable. The execute cycle takes many forms; the form depends on which of the various machine instruction is in the IR. This cycle may involve transferring data among registers, read or write from memory or I/O, and/or the invocation of the ALU.
INSTRUCTION CYCLE STATE DIAGRAM: The execution cycle for a particular instruction may involve more thane one reference to memory. For any given instruction cycle, some states may be null and others may be visited more than once. In the figure shown below, on first line three circles (operations) represent the CPU access to memory or I/O. And on second line five circles (operations) represent the internal CPU operation. The states can be described as: • • • • Instruction Address Calculation (iac): Determine the address of the next instruction to be executed. Instruction Fetch (if): Read instruction from its memory location into CPU. Instruction Operation Decoding (iod): Analyze instruction to determine type of operation to be performed and operands to be used. Operand Address Calculation (oac): If the operation involves reference to an operand in memory or variable via I/O then determine the address of the operand. Operand Fetch (of): Fetch the operand from memory or read it in from I/O. Data Operation (do): Perform the operation indicated in the instruction. Operand Store (os): Write the result into memory or out to I/O.
Chapter IV INSTRUCTION FORMAT
An instruction is a command to the CPU to perform one of its primitive processing functions. An instruction is divided into parts. The first part is the opcode. The opcode represents the instruction type. The second part is operands. Operands are data items or the location of data items needed to perform the instruction. The instructions can be placed into the following categories: data movement, data transformation, sequence control. Normally defines the location that contains the operand Instruction formats vary between microprocessors and minicomputers and mainframe computers. As the machine instructions are generally longer in larger computers with their larger memory words, the instruction format or how the instruction is translated differs. Each instruction is composed of fields. The lengths of instructions and the lengths and positions of the fields differ depending on the instruction and the computer. An operation (function) code is part of all instructions. How the remainder of the instruction is translated and the names assigned to the parts vary. Let’s take a look at two examples of computer instruction formats, one for a microcomputer and one for a mainframe. We begin with the op (function) code, which is common to both; only the length differs. A typical machine instruction begins with the specification of an operation to be performed, the operation (op) code. Refer back to figure 8-1. The op code tells the computer/processor what basic operation to perform. The op code, a part of every instruction, is usually located at the beginning of each instruction format. Following the op code is information, if needed, to define the location of the data or the operand on which the operation is to be performed. This location in memory, called the operand address, at the start of the operation (the source), or that will contain the modified operand upon completion of the operation (the destination). The remainder of the instruction and how it is structured differs from one computer or computer type to another. The designators in each field and the positions of the fields within the instruction determine how the instruction will affect the operand, registers, memory, and general flow of data in and out of the computer. Instruction formats vary between microprocessors and minicomputers and mainframe computers. As the machine instructions are generally longer in larger 12
computers with their larger memory words, the instruction format or how the instruction is translated differs. Each instruction is composed of fields. The lengths of instructions and the lengths and positions of the fields differ depending on the instruction and the computer. An operation (function) code is part of all instructions. How the remainder of the instruction is translated and the names assigned to the parts vary. Let’s take a look at two examples of computer
An instruction format defines the layout of the bits of an instruction, in terms of its constituents parts. An instruction format must include an opcode and, implicitly or explicitly, zero or more operands. Each explit operand is referenced using one of the addressing modes that are available for that machine. The format must, implicitly or explicitly, indicate the addressing mode of each operand. For most instruction sets, more than one instruction format is used. Four common instruction formats are shown in the figure on the next slide .instruction formats, one for a microcomputer and one for a mainframe. We begin with the op(function) code, which is common to both; only the length differsThis section discusses variable and fixed length instructions, RISC, and CISC. You should emphasize the dependence of the instruction format on the coding method for various operand types as described in Chapter 4. Also make it clear that the term instruction format should be interpreted in the plural, not the singular. That is, a CPU uses various formats representing various combinations of operands.
The discussion of RISC and CISC is necessarily simple. CISC is defined as a CPU design philosophy that uses variable length instructions, implements a large number of complex instructions, and employs relatively few registers. Emphasize to the students that “pure” RISC and CISC are two ends of a continuum and that few processors truly represent either extreme. The term RISC, taken literally, would imply no more than a couple dozen instructions – an extreme not seen in any CPU widely used in general purpose computer systems. The chapter purposely avoids a discussion of micro coding. It also avoids discussing the decomposition of CPU instructions into smaller components for execution, instruction component reordering, and branch prediction. These topics are extremely complex and well beyond the depth of knowledge required by IS students. Also, the technologies of instruction decomposition, component reordering, and branch prediction are widely implemented in both RISC and
CISC architectures so they are not the differentiating characteristics they once were. See the text web site for references that cover these topics. We discuss the fields and the designators as we discuss the two instruction formats. Microcomputer Instruction Formats A basic 16-bit microinstruction is divided into a number of separate fields. Refer to figure 8-3 as a reference. You’ll notice the lengths of the fields vary. The op code is located in the most significant bits (215 through 213). B (bit 212) tells the computer to use all 16 bits as a word or divide the 16 bits into 8-bit bytes • Layout of bits in an instruction
• Includes (implicit or explicit) operand(s) • Usually more than one instruction format in an instruction set • In selecting the instruction format(s) the following factors should be considered. 1. The number of instructions to be represented.
2. The addressability and addressing modes. 3. The ease of decoding. 4. Type of instruction field (fixed or variable) 5. The cost of hardware required to decode and execute instructions. • The main instruction is function of an:
1. Specify an operation to be performed on data. 2. Specify the operand / data to be used. The operands specify input data, memory location etc.
Opcode • The opcode field is used to specify the operation to be performed.
Operand • The operand field is used to specify the add. of the operands in main memory or in processor.
There are 16 registers; each of 32 bit long. • • • Reg-0 (0000) being the Accumulator. Reg-1(0001) being the Zero register, which contains the value 0. All other registers are general purpose register.
Basic Instruction Format Opcode Register 1 Index Register Memory Address
Chapter V Addressing Modes
The processor can access operands in various ways. The addressing mode refer to the effective address EA.(i.e. final address used to access a operand) formation mechanisms. Addressing modes are either explicitly specified ir implied bt the instruction. The different major addressing modes available are as follows: 1. Immediate Addressing 2. Register Addressing 3. Direct Addressing 4. Register Indirect Addressing 5. Register Relative Displacement Addressing 6. Implicit Addressing All the above listed modes are not provided on all processors. Different processors may refer to an addressing mode using different names. Now we consider each addressing mode separately. (1) Immediate Addressing The operand data is directly specified in the operand field. The instruction is a multiword instruction, where the operand immediately follows the opcode. Both the opcode & the operand are fetched from memory using program counter. The instruction format of immediate addressing is as shown in fig.
The immediate addressing modes can be used for (1) Loading internal registers with initial value, (2) Perform arithmetic or logical operation on immediate data. (2) Register Addressing In this addressing mode the instruction opcode specifies the CPU registers 16
where the operand is stored. There are different ways of implementing this. When 2 registers are specified one will be used as source while the other will be used as destination. Using internal registers instead of memory for operand makes this mode instructions execute faster than other mode instructions. The instruction format of register addressing is as shown in fig
. (3) Direct Addressing The effective memory address where the operand is present is directly specified with in the instruction. The instruction will contain opcode followed by direct memory address. Both the opcode and direct address are fetched from memory by using program counter. The direct address available is then used to access the operand. The instruction format of direct addressing is as shown in fig.
(4) Register Indirect Addressing In this register indirect mode the instruction opcode specifies an internal register or register pair which contains the effective address to be used for addressing operand in memory. This mode is used to save program space & improve speed of program execution in situations where data elements are to be accessed from memory. The instruction format of register indirect addressing is as shown in fig.
Some processors provides some variations in this mode. (a) Address register indirect with post increment. In this the effective address is in the specified address register. The operand is accessed using this address. After the operand is accessed the effective address in address register is incremented by the operand size. (b) Address register indirect with predecrement. In this effective address is in specified address register. Before this effective address is used, the address register is decremented by the operand size. After decrementing register contents these are used to access memory operand.
(5) Register Relative Addressing
In relative addressing mode, the operand comes from a location relative to the 18 executed instructions position. The operands effective address is generated by the sum of the contents of the program counter & the signed value specified by the instruction in itsaddress field. The instruction format of relative addressing
mode is as shown in fig.
(6) Implicit Addressing Implicit addressing also called as implied addressing or inherent addressing. It is available in some processors. In this case the instruction opcode doesn’t specify register or memory. It automatically implies the operand position. As an example it is implied that operand is available in specific register, the opcode doesn’t give register code but assumes it is present. Accumulator
Chapter VI Conclusion
The Central Processing Unit (CPU) or processor is the portion of a computer system that carries out the instructions of a computer program, and is the primary element carrying out the computer's functions. Thus CPU makes a hold with the computer processing. It controls the cycle for the flow of the instruction which is much favorable for the memory to carry on with the instruction cycle. It also handles information on from one part of the computer to another like a central switching station that directs the flow of traffic throughout the computer system. This functional model has remained more or less the same over the decades no matter how and when the development of processors has taken place ever since the days of Von Newman architecture to today’s Supercomputers.
Beasley, Maurine H. "Roosevelt, Eleanor," World Book Online, http://www.worldbookonline.com, October 10, 2009, Chicago: World Book, Inc. http://www-03.ibm.com/servers/deepcomputing/bluegene.html http://www.es.jamstec.go.jp/esc/eng/ES/hardware.html William Stallings. Computer Organization and Architecture 4/E and 5/E. Prentice Hall. http://williamstallings.com/COA5e.html and/http://williamstallings.com/COA/COA7e.html John L. Hennessy, David A. Patterson. Arquitectura de compotators, un enfoque cuantitativo. Ed. McGraw-Hill. 1995. David A. Patterson, John L. Hennessy. Estructura y diseño de computadores. Interficie circuitería/programación. Ed. Reverté, S.A. 2000. Heuring, V.; Jordan, H., "Computer systems design and architecture", Menlo Park, CA [etc.]: Addison Wesley Longman, cop. 1997. Patterson, D; Hennessey, J., "Computer Architecture. A quantitative approach", San Francisco: Morgan Kaufmann, cop. 2003.
Instruction Fetch Execute Cycle during System Boot up: When the computer is powered on, the PC as usual points to some specific address. This pointer holds the address of the instruction to be executed. Thus, the Program Counter is initialized to some specific address like 0xfffffff0 in the case of Intel CPUs. This address would be different for different Operating Systems. This is the address of Read Only Memory (ROM). ROM contains a special program called Boot Loader. Thus immediately, after we turn on the computer, the instructions comprising the Boot loader start executing because the PC was initialized with its address. The boot loader loads the OS from disk to the memory and then executes a JUMP instruction to that section of memory. The boot loader only loads a part of the OS and the instructions subsequent to the jump instruction read the remaining part of the OS into memory. The above process can be summarized as follows: · The ROM contains the Basic Input Output System (BIOS) which makes a call to the boot loader program. · The boot loader program loads the OS from disk to memory. It reads from the first sector of the disk which is termed as the Master Boot Record (MBR). · The boot loader copies the code from the MBR to memory, starting at some specified location depending on the processor. · The boot loader then performs a jump to that address, and subsequently the code for the OS starts executing.
Basic Logic Gate of a 4 bit ALU.
Power PC Instruction Formats(1)
Power PC Instruction Formats(2)
absolute address An address in a computer language that identifies a storage location or device without the use of any intermediate reference. accumulator The name of the CPU registers in a single-address instruction format. The accumulator, or AC, is implicitly one of the two operands for the instruction. address bus That portion of a system bus used for the transfer of an address. Typically, the address identifies a main memory location or an I/O device. address space The range of addresses that can be referenced.
arithmetic and logic unit (ALU) A part of a computer that performs arithmetic operations, logic operations, and related operations. bit In the pure binary numeration system, either of the digits 0 and 1.
buffer Storage used to compensate for a difference in rate of flow of data, or time of occurrence of events, when transferring data from one device to another. bus A shared communications path consisting of one or a collection of lines. In some computer systems, CPU, memory and I/O components are connected by a common bus. byte Eight bits. Also referred to as octet.
cache A relatively small fast memory interposed between a larger, slower memory and the logic that accesses the larger memory. The cache holds recently accessed data, and is designed to speed up subsequent access to the same data. central processing unit (CPU) That portion of a computer that fetches and executes instructions. It consists of an arithmetic and Logic Unit (ALU), a control unit, and registers. Often simply referred to as a processor. computer instruction An instruction that can be recognized by the processing unit of the computer for which it is designed. Synonymous with machine instruction. computer instruction set A complete set of the operators of the instructions of a computer together with a description of the types of meanings that can be attributed to their operands. Synonymous with machine instruction set.
control unit That part of the CPU that controls CPU operations, including ALU operations, the movement of the data within the CPU, and exchange of data and control signals across external interfaces. 26
That portion of a system bus used for transfer of data.
execute cycle That portion of the instruction cycle during which the CPU performs the operation specified by the instruction opcode. fetch cycle That portion of the instruction cycle during which the CPU fetches from the memory the instruction to be executed. immediate address The contents of an address part that contains the value of an operand rather than an address. indexed address An address that modified by the content of an index register prior to or during the execution of a computer instruction. index register A register whose contents can be used to modify an operand address during the execution of computer instruction; it can be also used as a counter. An index register may be used to control the execution of a loop, to control the use of an array, as a switch, for table lookup, or as a pointer index address An address of storage location that contains an address. input –Output (I/O) Permiting to either input or output or both. Refers to the movement of data between a computer & a directly attached peripheral instruction cycle instruction. The processing performed by a CPU to execute a single
instruction Format the layout of a computer as a sequence of bits. The format divides the instruction into fields, corresponding to the constituents elements of the instruction. I/O Controller CPU. A relatively simple i/o o/p module that requires detailed control from the
I/O processor An i/o module with its own processor, capable of executing its own specialized i/o instruction, in some cases general purpose machine instructions. MAR memory address register contains address of the storage location being accessed. MBR memory buffer register contains data read from the memory or data to be written to memory. opcode Abbreviated form for operation code.
operand An entity on which an operation is performed. stack An ordered list in which terms are appended to & deleted from the same end of the list i.e. the top. 27
Accumulator (AC), 3, 4 Address , 12 Registers, 7, 14 Addressing , 14 Architecture ,2, 3 Architecture CPU, 2, 3 Arithmetic and Logic Unit (ALU) , 3 Central Processing Unit (CPU) , 2, 3
Instruction Formats, 10, 11 Operands ,12 Address Register, 13, 14 Control And Status Registers, 18 Control Unit (CU), 3,4 Instruction Cycles, 6 Instruction Execute, 8 Instruction Fetch, 7
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