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from this file you can know how to write verilog coding for logic gates using dataflow modeling

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//NOT gate

module notgate(a,y);

input a;

output y;

assign y= ~a;

endmodule

//OR gate

module orgate(a,b,y);

inpput a,b;

output y;

assign y=(a|b);

endmodule

//AND gate

module andgate(a,b,y);

input a,b;

output y;

assign y=(a&b);

endmodule

//NOR gate

module norgate(a,b,y);

inpput a,b;

output y;

assign y=~(a|b);

endmodule

//NAND gate

module nandgate(a,b,y);

input a,b;

output y;

assign y=~(a&b);

endmodule

//XOR gate

module xorgate(a,b,y);

input a,b;

output y;

assign y=(a^b);

endmodule

//XNOR gate

module xnorgate(a,b,y);

input a,b;

output y;

assign y=(~(a^b));

endmodule

- Clock DividerUploaded byMurali
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