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8051

MICROCONT-
ROLLER
INTERRUPTS

Submitted by:

Preet Komal
Singh

010714
Ece-E1
8051 Interrupts
As the name implies, an interrupt is some event which
interrupts normal program execution.
As stated earlier, program flow is always sequential, being
altered only by those instructions which expressly cause
program flow to deviate in some way. However, interrupts
give us a mechanism to "put on hold" the normal program
flow, execute a subroutine, and then resume normal
program flow as if we had never left it. This subroutine,
called an interrupt handler, is only executed when a
certain event (interrupt) occurs. The event may be one of
the timers "overflowing," receiving a character via the
serial port, transmitting a character via the serial port, or
one of two "external events." The 8051 may be configured
so that when any of these events occur the main program
is temporarily suspended and control passed to a special
section of code which presumably would execute some
function related to the event that occurred. Once
complete, control would be returned to the original
program. The main program never even knows it was
interrupted.

The ability to interrupt normal program execution when
certain events occur makes it much easier and much
more efficient to handle certain conditions. If it were not
for interrupts we would have to manually check in our
main program whether the timers had over flown,
whether we had received another character via the serial
port, or if some external event had occurred. Besides
making the main program ugly and hard to read, such a
situation would make our program inefficient since wed be
burning precious "instruction cycles" checking for events
that usually don’t happen.

The 8051 provides five interrupt sources. These are listed
below.
1. Timer 0 (TFO) and timer 1 (TF1) interrupt.
2. External hardware interrupts, INTO and INT1.

3. Serial communication interrupt TI and RI

The Fig. shows the interrupt structure of 8051.
Interrupt Vector Table
In 8051, all interrupts are vectored interrupts and
have vector locations as listed in Table 15.1 when
interrupt is activated 8051 reads the address of
interrupt service routine from the vector location.

Interrupt Vector location

External hardware interrupt 0 (INTO) 0003H

Timer 0 internet (TFO Overflow) 00OBH

External hardware Interrupt 1 (INT1) 0013H

Timer 1 interrupt (TF1 Overflow) 001BH

Serial communication interrupt (Rl and Tl) 0023H
(Reception/Transmission of Serial
Character)
INTERRUPT VECTOR TABLE FOR 8051

Enabling and Disabling an Interrupt
When 8051 is reset, all interrupts are disabling. These are
enabled by software. All of the bits that generate
interrupts can be set or cleared by software, with the
same result as though it had been set or cleared by
hardware. That is, interrupts can be generated or pending
interrupts can be cancelled in software.
Each of these interrupt sources can be individually
enabled or disabled by setting or clearing a bit in Special
Function Register IE (Fig. 15.2) . IE contains also a global
disable bit, EA, which disables all, interrupts at once.
Note in Fig. 15.2 that bit position IE.6 is unimplemented.
In the 8051s, bit position IE.5 is also unimplemented. User
software should not write is to these bit positions, since
they may be used in future MCS-51 products.
(MSB)

(LSB)

EA - ET2 ES ET1 EX1 ET0 EX0

Symbol Position Name and Significance

EA IE.7 Enable AH control bit.

Cleared by software to disable all interrupts, independent of the state of IE.4-IE.0.

- IE.6 (Reserved)

ET2 IE.5 (Reserved)

ES IE.4 Enable Serial port control bit

Set/cleared by software to enable/disable interrupts from Tl or Rl flags.

ET1 IE.3 Enable Timer 1 control bit.

Set/cleared by software to enable/disable interrupts from timer/counter 1

EX1 IE.2 Enable External interrupt 1 control bit.

Set/cleared by software to enable/ disable interrupts from INT1.

ETO IE.1 Enable Timer 0 control bit

Set/cleared by software to enable/disable interrupts from timer/counter 0.

EXO IE 0 Enable external interrupt 0 control bit.

Set/cleared by software to enable/disable interrupts from INTO.
INTERRUPT ENABLE REGISTER

Timer Interrupts and Programming
The Timer 0 and Timer 1 Interrupts are generated by TFO
and TF1, which are set by a rollover in their respective
Timer/Counter registers (except see Timer 0 in Mode 3).
When a timer interrupt is generated, the flag that
generated it is cleared by the on-chip hardware when the
service routine is vectored.
As the timer flag (TF) is set (=1) when the timer rolls over.
In polling method, the TF is monitored with the instruction
'JNB TF, target address'. We have to wait until the TF is
raised. The problem with this polling method is that 8051
cannot do anything else until TF is set to high. This
problem can be solved using interrupt method. If the
timer interrupt in the IE register is enabled, TF is set
whenever the timer is rolled over and the 8051 is
interrupted. Thus the 8051 can perform anything else
until it is interrupted. After interruption (timer rolling over)
only the 8051 remains busy in executing interrupt service
routine.

Programming External Hardware Interrupts
Pins, P 3.2 (pin number 12) and P 3.3 (pin number 13) in
port 3 are used as external hardware interrupts INTO and
INT1, respectively. The external Interrupts INTO and INT1
can each be either level-activated or transition-activated,
depending on bits ITO and IT1 in Register TCON. The flags
that actually generate these interrupts are bits IEO and
IE1 in TCON. When an external interrupt is generated, the
flag that generated it is cleared by the hardware when the
service routine is vectored to only if the interrupt was
transition-activated. If the interrupt was level-activated,
then the external requesting source is what controls the
request flag, rather than the on-chip hardware.
If ITx = 0, external interrupt x is triggered by a
detected low at the INTx pin. If ITx = 1, external interrupt
x is edge-triggered. In this mode if successive samples of
the INTx pin show a high in one cycle and a low in the
next cycle, interrupt request flag IEx in TCON is set. Flag
bit IEx then requests the interrupt.
Since the external interrupt pins are sampled once
each machine cycle, an input high or low should hold for
at least 12 oscillator periods to ensure sampling. If the
external interrupt is transition-activated, the external
source has to hold the request pin high for at least one
machine cycle, and then hold it low for at least one
machine cycle to ensure that the transition is seen so that
interrupt request flag IEx will be set. IEx will be
automatically cleared by the CPU when the service routine
is called.
If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactivate
the request before the interrupt service routine is
completed, or else another interrupt will be generated.

Example: Write an 8051 ALP to glow LED for a fraction of
second when external interrupt INTO is activated.
Solution
ORG 0000H LJMP MAIN
O
R C
B G L
R
0 P
0 1
0 .
3 0
H
S ;
E R
T E
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.
0
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0
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0
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3
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0
E
H
R
2
,
M
# O
0
V
F
F I
H E
,
; #
D
1
J
N 0
Z 0
0
B 0
A
0
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K 0
1
B
S n
E T d
u
r i
n f

O n
N o
t
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D e
r
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a r
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t u
r
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t e
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n

S

;
;
Serial
Commu
nication
Interru
pts and
Progra
mming
The
Serial port
Interrupt
is
generated
by the
logical OR
of RI and
TI. Neither
of these
flags is
cleared by
hardware
when the
service
routine is
vectored
to. In fact,
the
service
routine
will
normally
have to
determine
whether it
was RI or
TI that
generated
the
interrupt,
and the
bit will
have to be
cleared in
software.
In this
case, the
8051 can
perform
other
tasks in
addition
to serial
communic
ation, i.e.
sending
and
receiving
data from
serial
communic
ation port.
We
know that
transmit
interrupt
(TI) flag is
set (=1)
when the
last bit of
the
framed
data (stop
bit) is
transmitte
d. This
indicates
that the
SBUF
register
is ready
to
transmit
the next
byte. The
receive
interrupt
(RI) flag
is set
(=1)
when the
complete
frame of
data
(with
stop bit)
is
received.
RI
indicates
that the
received
byte
needs to
be picked
up before
it is lost
by new
incoming
serial
data.
All the
above
concepts
are
applied
equally
using
polling or
an
interrupt.
Only
differenc
e is in
serving
the serial
communi
cation
needs. In
polling
method,
the flag
(TI or RI)
is
monitore
d. The
8051
cannot
do
anything
else until
this flag
is set to
high. This
problem
is solved
using
interrupt
method.
When
8051 has
received
a byte or
is ready
to send
the next
byte, the
RI or TI
flag
respectiv
ely is set.
Any other
work can
be
performe
d while
the serial
communi
cation
needs
are
served.
There is a
single
interrupt
set aside
for serial
communi
cation. If
IE
register
(IE.4) is
enabled,
when RI
or TI is
set (= 1),
the 8051
is
interrupt
ed. When
interrupt
ed, the
ISR
written at
0023h is
executed
by 8051.
In ISR,
the TI
and RI
flags
must be
examined
to check
which
one
caused
the
interrupt
and
according
to flag
the
response
is given.

Interru
pt
priority
Each
interrupt
source
can also
be
individuall
y
programm
ed to one
of two
priority
levels by
setting or
clearing a
bit in
Special
Function
Register
IP. A low-
priority
interrupt
can itself
be
interrupte
d by a
high-
priority
interrupt,
but not by
another
low
priority
interrupt.
A high-
priority
interrupt
can’t be
interrupte
d by
another
interrupt
source.

If two
requests
of
different
priority
levels are
received
simultane
ously, the
request of
higher
priority
level is
served. If
requests
of the
same
priority
level are
received
simultane
ously, an
internal
polling
sequence
determine
s which
request is
serviced.
Thus
within
each
priority
level there
is a
second
priority
structure
determine
d by the
polling
sequence,
as follows:
Note that
the
"priority
within
level"
structure
is only
used to
resolve
simultane
ous
requests
of the
same
priority
level.

The IP
register
contains a
number of
unimplem
ented bits.
1P.7 and
IP.6 are
vacant in
the 8052s,
and in the
8051s
these and
IP.5 are
vacant.
User
software
should not
write Is to
these bit
positions,
since they
User
software
should not
write Is to
these bit
positions,
since they
may be
used in
future
MCS-51
products.

Nested
Interru
pts
Consid
er a case,
the 8051
is
executing
an ISR for
servicing
an
interrupt
and
another
interrupt
is
occurred.
In such a
case, if
the new
coming
interrupt
is high
priority
interrupt
then only
it can
interrupt
the
previously
occurred
low-
priority
interrupt.
These are
called
nested
interrupts
". Thus, in
8051 a
low-
priority
interrupt
can be
interrupte
d by high-
priority
interrupt
but not by
another
low-
priority
interrupt.
In 8051,
all the
interrupts
are
latched
and kept
internally.
But the
low-
priority
interrupt
is serviced
only after
finishing
the
servicing
of the
high-
priority
interrupts.

Softwar
e
Triggeri
ng of
Interru
pt
Softwa
re
triggering
of the
interrupts
is possible
in 8051.
This
means the
interrupt
can be
caused by
setting an
interrupt
flag with
an
instruction
. For
example,
if the IE
bit for
timer 1 is
set, an
instruction
'SETB TFV
will
interrupt
the 8051
and 8051
will start
executing
ISR. Thus,
it is not
needed to
wait for
timer 1 to
roll over
to have an
interrupt.
Since we
are using
instruction
to create
an
interrupt,
it is called
software
triggering
.This is
useful for
testing an
ISR by
way of
simulation
.