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Compal Confidential
2

2

NAWF2 M/B Schematics Document
Intel Penryn Processor with Cantiga + DDRIII + ICH9M+M92-S2 XT

2009-09-17
REV:1.0

3

3

4

4

2009/07/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/07/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A4853
Rev
A

401817
Sheet

Monday, September 28, 2009
E

1

of

53

A

B

C

Compal Confidential

1

LCD Conn.

page 4

uPGA-478 Package
(Socket P) page

VRAM 512MB / 256MB
64M16 x 4 / 32M16 x 4
page 21

DDR2 500MHz
ATI M92-S2 XT

LVDS

page 23

1

H_D#(0..63)

Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2

Intel Cantiga

CRT Conn.

Dual Channel

BANK 0, 1, 2, 3

page 14,15

1.5V DDRIII 800/1066

uFCBGA-1329

page 24

page 16

4,5,6

PCI-Express 16x

page 17,18,19,20,21,22

Clock Generator
ICS9LPRS387

page 4

FSB
667/800/1066MHz

H_A#(3..35)

E

Thermal Sensor
EMC 1402

Intel Penryn Processor

Fan Control

Model Name : NAWF2
File Name : LA-4853P
P/N : DA60000FI00
P/N : DA60000FI10

D

page 7,8,9,10,11,12,13

DMI
PCI-Express

2

USB conn x2

C-Link

Intel ICH9-M

USB port 0, 6

CMOS
Camera

page 34

page 23

3.3V 48MHz

MINI Card x1
WLAN

LAN ATHEROS
AR8132

page 36

2

USB

3.3V 24.576MHz/48Mhz
S-ATA

Card Reader
Realtek RTS5159

HD Audio

BGA-676
page 25,26,27,28

port 0

port 1

HDA Codec

page 31

page 33

ALC272

HDD
Conn.

RJ45

page 29

Audio AMP

page 38

ODD
Conn.
page 29

page 39

Phone Jack x2

page 32

page 39

LPC BUS
3

3

ENE KB926 D3

LS-4851P

RTC CKT.
page 26

POWER/B Conn.

page 35

page 36

Int.KBD

Touch Pad

Power On/Off CKT.

page 36

page 36

page 37

DC/DC Interface CKT.

BIOS

page 40

page 36

Power Circuit DC/DC
4

page 41,42,43,44
45,46,47,48,49

4

2009/07/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/07/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A4853
Document Number

Rev
A

401817
Sheet

Monday, September 28, 2009
E

2

of

53

A

B

C

D

SIGNAL

STATE

Voltage Rails

1

2

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

Power Plane

Description

S1

S3

S5

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

VIN

Adapter power supply (19V)

N/A

N/A

N/A

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

Full ON

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+0.75VS

0.75V switched power rail for DDR terminator

ON

OFF

OFF

+1.05VS

1.05V switched power rail

ON

OFF

OFF

+1.1VS

1.1V switched power rail

ON

OFF

OFF

+1.5V

1.5V power rail for DDR

ON

ON

OFF

+1.5VS

1.5V switched power rail

ON

OFF

OFF

+1.8V

1.8V power rail for GMCH LVDS

ON

ON

OFF

Vcc
Ra/Rc/Re

+1.8VS

1.8V switched power rail

ON

OFF

OFF

Board ID

2.5V switched power rail

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V

3.3V power rail for SB

ON

ON

OFF

0
1
2
3
4
5
6
7

+3V_LAN

3.3V power rail for LAN

ON

ON

ON

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

+VGA_CORE

Core voltage for GPU

ON

OFF

OFF

IDSEL#

EC SM Bus1 address

REQ#/GNT#

Device

Address

Device

Address

Smart Battery

0001 011X b

EMC 1402-1

1001 100X b

EEPROM(24C16/02) 1010 000X b

GMT G781-1

1001 101X b

Board ID
0
1
2
3
4
5
6
7

UHCI1
EHCI1

UHCI2

UHCI4

Device

Address

Clock Generator
(ICS9LPRS387, SLG8SP556V)

1101 001Xb

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V

BTO Option Table
PCB Revision

BTO Item
GM45
8132

0.1(PVT2)
1.0(Pre-MP)

EHCI2

UHCI5
UHCI6

BOM Structure
GM@
8132@

PCIE table
PCIE port1

USB table

UHCI3

ICH9M SM Bus address

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V

BOARD ID Table

Interrupts

EC SM Bus2 address

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%

2

External PCI Devices
Device

1

Board ID / SKU ID Table for AD channel

+2.5VS

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

3

E

Port0
Port1
Port2
Port3
Port4
Port5
Port6
Port7
Port8
Port9
Port10
Port11

MB USB Conn.

PCIE port2

Wireless Card

PCIE port3

PCIE LAN

3

PCIE port4

CMOS Camera
Card Reader

PCIE port5
PCIE port6

MB USB Conn.

SATA table
Wireless Card

SATA port0

HDD

SATA port1

ODD

SATA port2
SATA port3
SATA port4

4

4

SATA port5

2009/07/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/07/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A4853
Document Number

Rev
A

401817
Sheet

Monday, September 28, 2009
E

3

of

53

5

4

3

2

1

H_A#[3..35]
H_REQ#[0..4]

FAN1 Conn

H_RS#[0..2]

<7> H_RS#[0..2]

+5VS

JCPU1A

<7> H_ADSTB#1
<26> H_A20M#
<26> H_FERR#
<26> H_IGNNE#

A6
A5
C4

A20M#
FERR#
IGNNE#

<26> H_STPCLK#
<26> H_INTR
<26> H_NMI
<26> H_SMI#

D5
C6
B4
A3

STPCLK#
LINT0
LINT1
SMI#

M4
N5
T2
V3
B2
D2
D22
D3
F6

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

ADDR GROUP_1

H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>

F1

H_BR0# <7>

LOCK#

H4

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

C1
F3
F4
G3
G2

HIT#
HITM#

G6
E4

EN_DFAN1

<35> EN_DFAN1

H_INIT# <26>

1
R51

1
2
3
4

+VCC_FAN1
VSET
2
330_0402_5%
1
C106
0.01U_0402_16V7K

H_LOCK# <7>
H_RESET#
H_RS#0
H_RS#1
H_RS#2

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

VEN
VIN
VO
VSET

GND
GND
GND
GND

D6
1SS355_SOD323-2

8
7
6
5

+3VS

20080430
Add soft-start for +5VS drop issue

C121
1000P_0402_50V7K
1
2

R55
10K_0402_5%

H_HIT# <7>
H_HITM# <7>

XDP_BPM#5
XDP_TCK
XDP_TDI

PROCHOT#
THERMDA
THERMDC

D21
A24
B25

H_PROCHOT#
H_THERMDA
H_THERMDC

THERMTRIP#

2

BAS16_SOT23-3
C122
10U_0805_10V4Z
1
2

2

H_RESET# <7>

D7

1

G993P1UF_SOP8

H_TRDY# <7>

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D

U5

H_IERR#

D20
B3

+5VS

10U_0805_10V4Z
2

1

H5
F21
E1

C114
1

40mil

JP12

+VCC_FAN1

1
2
3

<35> FAN_SPEED1

1

XDP_TMS
XDP_TRST#
XDP_DBRESET#

C115
1000P_0402_50V7K

ACES_85205-03001
CONN@

2

C

XDP_DBRESET# <27>

THERMAL

ICH

B

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>

1

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

C

BR0#
IERR#
INIT#

H1
E2
G5

2

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

DEFER#
DRDY#
DBSY#

CONTROL

K3
H2
K2
J3
L1

ADS#
BNR#
BPRI#

XDP/ITP SIGNALS

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

<7> H_ADSTB#0

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

+1.05VS

C7

H_THERMTRIP# <8,26>

XDP_TDI

R43

1

2

54.9_0402_1%

XDP_TMS

R42

1

2

54.9_0402_1%

XDP_BPM#5

R16

1
@

2

54.9_0402_1%

H_PROCHOT#

R70

2

1

56_0402_5%

H_IERR#

R54

2

1

56_0402_5%

XDP_TRST#

R41

2

1

54.9_0402_1%

XDP_TCK

R17

1

2

54.9_0402_1%

left NC if no ITP
H CLK
BCLK[0]
BCLK[1]

A22
A21

CLK_CPU_BCLK <16>
CLK_CPU_BCLK# <16>

RESERVED

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

ADDR GROUP_0

D

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

2

<7> H_A#[3..35]
<7> H_REQ#[0..4]

Layout Note:
H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil

39Ohm

B

Penryn
CONN@
+3VS

C159
0.1U_0402_16V4Z
1
2

BSEL1

BSEL0

BCLK

0

0

0

266

1

0

U9
H_THERMDA

1
C158

R12
56_0402_5%
@

200

2200P_0402_50V7K
2

1

VDD

SMCLK

8

2

DP

SMDATA

7

3

DN

ALERT#

6

4

THERM#

GND

5

2

0

+1.05VS

1

BSEL2

1

1

166

H_THERMDC

EC_SMB_DA2 <22,35>

1

2
R109
10K_0402_5%

+3VS

B

2

0

EC_SMB_CK2 <22,35>

E

H_PROCHOT#

3

1

C

A

EMC1402-1-ACZL-TR_MSOP8

OCP# <27>

Q2
MMBT3904_SOT23-3
@

A

Address 1001 100X b

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/01/21

Issued Date

Deciphered Date

2010/01/21

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SCHEMATIC,MB A4853
Document Number

Rev
A

401817
Monday, September 28, 2009

Sheet
1

4

of

53

5

4

3

H_D#[0..63]

2

H_D#[0..63]

<7> H_DSTBN#0
<7> H_DSTBP#0
<7> H_DINV#0

C

2

+1.05VS

1

R386
1K_0402_1%

R387
2K_0402_1%

R406
R405

2
2

C438 1

GTL_REF0
TEST1
1 @ 1K_0402_5%
TEST2
1 @ 1K_0402_5%
TEST3
PAD @
T2
2 @ 0.1U_0402_16V4Z TEST4
TEST5
@
T26 PAD
@
TEST6
T27 PAD

1

Width=4 mil ,
Spacing: 15mil
(55Ohm)

2

Trace Close CPU < 0.5'

<7> H_DSTBN#1
<7> H_DSTBP#1
<7> H_DINV#1

<16> CPU_BSEL0
<16> CPU_BSEL1
<16> CPU_BSEL2

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

MISC

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

DATA GRP 2

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

DATA GRP 1

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

DATA GRP 3

D

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

DATA GRP 0

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

JCPU1C

<7>
+CPU_CORE

JCPU1B

COMP[0]
COMP[1]
COMP[2]
COMP[3]

R26
U26
AA1
Y1

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

E5
B5
D24
D6
D7
AE6

H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>

H_DSTBN#3 <7>
H_DSTBP#3 <7>
H_DINV#3 <7>
COMP0
COMP1
COMP2
COMP3

R393
R394
R15
R14

1
1
1
1

H_PWRGOOD
H_CPUSLP#

2
2
2
2

27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%

H_DPRSTP# <8,26,47>
H_DPSLP# <26>
H_DPWR# <7>
H_PWRGOOD <26>
H_CPUSLP# <7>
PSI# <47>

Penryn
CONN@

TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)

B

1

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
Penryn
CONN@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

VCCA[01]
VCCA[02]

B26
C26

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VCCSENSE

VSSSENSE

AE7

VSSSENSE

+CPU_CORE
D

C

+1.05VS

20mils
+1.5VS
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
1
R376

1

C157
<47>
<47>
0.01U_0402_16V7K
<47>
2
2
<47>
<47>
10U_0805_10V4Z
<47>
<47>

2
100_0402_1%

B

+CPU_CORE

VCCSENSE <47>
VSSSENSE <47>

1
R375

.

1
C156

2
100_0402_1%

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/01

Issued Date

Deciphered Date

2010/07/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SCHEMATIC,MB A4853
Document Number

Rev
A

401817
Monday, September 28, 2009

Sheet
1

5

of

53

3V6M 2 2 2 2 2 2 2 2 10U_0805_6.3V6M (Place these capacitors on North side.3V6M 10U_0805_6. INC.3V6M @ 10U_0805_6. Inc.3V6M @ 10U_0805_6.3V6M 10U_0805_6. INC.3V6M @ 10U_0805_6. Date: 5 4 3 2 SCHEMATIC.5VM_R9 0.05VS 1 .3V6M @ 10U_0805_6.Primary Layer) +CPU_CORE 1 1 C455 1 C450 1 C442 1 C441 C469 1 C443 1 C468 1 C467 10U_0805_6.3V6M 10U_0805_6.8nH/6 32X22uF 3m ohm/32 0.3V6M @ 10U_0805_6. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.3V6M 10U_0805_6.1U_0402_16V4Z 0. C13 + 1 C119 1 C120 1 C118 1 C78 1 C77 1 C79 330U_D2E_2.1U_0402_16V4Z 0. mohm ESL.3V6M @ 10U_0805_6.3V6M 10U_0805_6.3V6M @ 10U_0805_6.3V6M (Place these capacitors on South side.3V6M 10U_0805_6.3V6M 10U_0805_6. 2009 Sheet 1 6 of 53 .5VM_R9 2 1 + C107 330U_D2E_2.1U_0402_16V4Z 2 2 2 2 2 2 2 0.Primary Layer) +CPU-CORE Decoupling SPCAP.3V6M 10U_0805_6.3V6M 2 2 2 2 2 2 2 2 10U_0805_6.3V6M 10U_0805_6.nH 4X330uF 6m ohm/4 1.Secondary Layer) +CPU_CORE 1 1 C112 1 C105 1 C104 1 C97 1 C440 C444 1 C110 1 C109 10U_0805_6.3V6M 2 2 2 2 2 2 2 2 10U_0805_6.3V6M 10U_0805_6. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.6nH/32 +1.3V6M @ 10U_0805_6.Secondary Layer) +CPU_CORE 1 1 C108 1 C103 1 C102 1 C92 1 C91 C457 1 C456 1 C96 10U_0805_6. INC.1U_0402_16V4Z A A Compal Electronics.3V6M 10U_0805_6. Compal Secret Data Security Classification 2009/07/01 Issued Date Deciphered Date 2010/07/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.MB A4853 Document Number Rev A 401817 Monday.3V6M 10U_0805_6. September 28.1U_0402_16V4Z 0.3V6M C (Place these capacitors on North side.1U_0402_16V4Z 0.5 4 3 2 +CPU_CORE +CPU_CORE 2 x 330uF(6mOhm/2) JCPU1D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 D C B VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] Penryn CONN@ 1 P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] 2 x 330uF(6mOhm/2) 1 + C98 1 C113 330U_D2E_2.5VM_R9 2 1 + + C90 330U_D2E_2.3V6M (Place these capacitors on South side.uF ESR.5VM_R9 2 330U_D2E_2.3V6M 10U_0805_6.6nH/32 32X10uF 3m ohm/32 0.5VM_R9 2 D South Side Secondary North Side Secondary +CPU_CORE 1 1 C465 1 C466 1 C451 1 C95 1 C111 C94 1 C93 1 C458 10U_0805_6.3V6M 2 2 2 2 2 2 2 2 10U_0805_6.Polymer MLCC 0805 X5R B C.

.4 3 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 1 +1.5") R134 2 H_RESET# H_CPUSLP# C12 E11 H_AVREF A11 B11 C216 @ 0.1U_0402_16V4Z H_CPURST# H_CPUSLP# H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 J8 L3 Y13 Y1 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 L10 M7 AA5 AE6 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 L9 M8 AA6 AE5 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 B15 K13 F13 B13 B14 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#_0 H_RS#_1 H_RS#_2 B6 F12 C8 H_RS#0 H_RS#1 H_RS#2 H_AVREF H_DVREF 1 <4> D H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4> H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 C <5> <5> <5> <5> <5> <5> <5> <5> B H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5> H_REQ#[0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. INC...B9 A A Compal Electronics.63] D R139 <4> H_RESET# <5> H_CPUSLP# 1 1K_0402_1% 1 width:spacing=10mil:20mil (<0.9_0402_1% B H_SWING H_RCOMP F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 C5 E3 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP 2 +1.05VS R126 2 221_0402_1% H_SWING 2 width=10mil 1 R125 C 2 C206 0. Compal Secret Data Security Classification 2009/07/01 Issued Date Deciphered Date 2010/07/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.4] H_RS#[0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.35] U23A <5> H_D#[0.MB A4853 Document Number Rev A 401817 Monday.05VS H_A#[3. Inc.1U_0402_16V4Z 1 100_0402_1% H_RCOMP 1 width=10mil R395 2 24.. INC. 2009 Sheet 1 7 of 53 . INC. Date: 5 4 3 2 SCHEMATIC. September 28.2] <4> <4> CANTIGA ES_FCBGA1329 GM@ 2 2K_0402_1% 1 2 HOST 5 within 100mil to Ball A9. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.

27.05VS AH37 AH36 AN36 AJ35 AH34 0.47> VGATE <27> ICH_PWROK MCH_CFG_16 MCH_CFG_19 MCH_CFG_20 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 CFG 2 PM_EXTTS#0 10K_0402_5% 2 PM_EXTTS#1 10K_0402_5% 2 MCH_CLKREQ# 10K_0402_5% 1 R177 1 R202 1 R189 +3VS T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28 PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 BC28 AY28 AY36 BB36 DDRA_CKE0 DDRA_CKE1 DDRB_CKE0 DDRB_CKE1 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 BA17 AY16 AV16 AR13 DDRA_SCS0# DDRA_SCS1# DDRB_SCS0# DDRB_SCS1# SA_ODT_0 SA_ODT_1 SB_ODT_O SB_ODT_1 BD17 AY17 BF15 AY13 DDRA_ODT0 DDRA_ODT1 DDRB_ODT0 DDRB_ODT1 SM_RCOMP SM_RCOMP# BG22 BH21 SMRCOMP SMRCOMP# SM_RCOMP_VOH SM_RCOMP_VOL BF28 BH28 SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST# AV42 AR36 BF17 BC36 SM_PWROK SM_REXT R366 1 SM_DRAMRST# R368 1 R367 1 B38 A38 E41 F41 CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC# PEG_CLK PEG_CLK# F43 E43 CLK_MCH_3GPLL CLK_MCH_3GPLL# DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 AE41 AE37 AE47 AH39 DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 AE40 AE38 AE48 AH40 DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 AE35 AE43 AE46 AH42 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 AD35 AE44 AF46 AH43 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3 2 C 2 B E E Q33 MMBT3904_SOT23-3 Q34 MMBT3904_SOT23-3 3 2 330_0402_5% 2 B 3 1 R397 1 C 2 R398 54.1U_0402_16V4Z 2 1 ME CANTIGA ES_FCBGA1329 GM@ MISC 1 +1. Inc.2U_0603_6.21K_0402_1% 2 R159 2 R163 1 @ 4.21K_0402_1% 1 @ 2.21K_0402_1% 1 @ 2.3V6K 2 3.5V SM_DRAMRST# <14. 1 +1.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. INC.1U_0402_16V4Z 2 CLK_MCH_3GPLL <16> CLK_MCH_3GPLL# <16> DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 C418 1K_0402_1% 1 2 R221 @ 0_0402_5% R222 1K_0402_1% 1 +1. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.21K_0402_1% 1 @ 2. 2009 1 8 of 53 .5V DDR3 RSVD RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 DDR CLK/ CONTROL/ D M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 2 1 5 2 R175 2 R142 2 R162 2 R158 2 R161 2 R154 2 R153 2 R155 1 @ 2. PCIE disable DDPC_CTRLDATA 0 = Digital DisplayPort Disable * (Default) 1 = Digital DisplayPort Device Present R183 1K_0402_1% CL_RST#0 <27> 1 CL_CLK0 <27> CL_DATA0 <27> MCH_CFG_5 MCH_CFG_6 C264 1 R182 511_0402_1% MCH_CFG_7 MCH_CFG_9 MCH_CLKREQ# C422 R564 1 R565 1 2 CL_VREF 2 CLK_DREF_96M CLK_DREF_96M# CFG20 (PCIE/SDVO select) ICH_PWROK D 0.21K_0402_1% 1 @ 2.47> PM_DPRSLPVR R133 1 R143 1 R140 1 R29 B7 N33 P32 AT40 AT11 T20 R32 PM <27> PM_SYNC# <5.31.25.02K_0402_1% A MCH_CFG_19 MCH_CFG_20 2009/07/01 Issued Date Compal Electronics.21K_0402_1% 1 @ 2. INC.47> H_DPRSTP# <14> PM_EXTTS#0 <15> PM_EXTTS#1 PM_SYNC#_R PM_DPRSTP#_R PM_EXTTS#0 PM_EXTTS#1 GMCH_PWROK 2 100_0402_5% MCH_RSTIN# THERMTRIP#_R 2 0_0402_5% DPRSLPVR_R 0_0402_5% 2 2 0_0402_5% 2 0_0402_5% DDRA_CLK0# DDRA_CLK1# DDRB_CLK0# DDRB_CLK1# R363 CFG16 B R141 1 R135 1 AR24 AR21 AU24 AV20 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 GRAPHICS VID <16> MCH_CLKSEL0 <16> MCH_CLKSEL1 <16> MCH_CLKSEL2 MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 DMI C SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 <14> <14> <15> <15> 2 RSVD22 RSVD23 RSVD24 RSVD25 DDRA_CLK0 DDRA_CLK1 DDRB_CLK0 DDRB_CLK1 2 BG23 BF23 BH18 BF18 AP24 AT21 AV24 AU20 1 RSVD20 CLK AY21 SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 2 RSVD15 RSVD16 RSVD17 COMPENSATION B31 B2 M1 All RSVD balls on GMCH should be left No Connect.05VS A R404 1K_0402_5% MCH_CFG_10 MCH_CFG_12 MCH_TSATN# MCH_CFG_13 MCH_CFG_16 HDA 1 +3VS NC +3VS SM_RCOMP_VOH 1 C419 R369 <14> <14> <15> <15> SM_VREF DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# 1K_0402_1% <14> <14> <15> <15> 2 <17.01U_0402_16V7K R220 1K_0402_1% 20mil SM_PWROK <37> 2 499_0402_1% 1 R362 +1.9_0402_1% MCH_TSATN# MCH_TSATN_EC# <35> 1 1 R403 1K_0402_5% 2 1 2 1 1 2.26> H_THERMTRIP# <27.21K_0402_1% 1 @ 4.6_0402_1% 1 SDVO_CTRLDATA CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF C423 SM_RCOMP_VOL 80 Ohm For Cantiga CFG19 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 2 2 SM_DRAMRST# would be needed for DDR3 only MCH_CLKREQ# <16> MCH_ICH_SYNC# <27> 0. Rev A 401817 Date: 5 4 3 2 Sheet Monday.5V 2 80. Compal Secret Data Security Classification +3VS 2010/07/01 Deciphered Date Title SCHEMATIC.4 3 U23B MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_9 MCH_CFG_10 MCH_CFG_12 MCH_CFG_13 VGATE GMCH_PWROK 2 @ 0_0402_5% 2 0_0402_5% 1 R224 ICH_PWROK 1 R223 <16.6_0402_1% 2 80. September 28.02K_0402_1% 1 @ 4. * (Default) 1 = PCIE/SDVO are operating simu. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. B L_DDC_DATA 0 = No SDVO Card Present * (Default) 1 = SDVO Card Present 0 = LFP Disable * (Default) 1 = LFP Card Present.01U_0402_16V7K For HM51 2 2 0_0402_5% 0_0402_5% CLK_DREF_SSC CLK_DREF_SSC# R566 1 R567 1 2 2 0_0402_5% 0_0402_5% +DIMM_VREF as close as possible to the related balls Strap Pin Table C 011 = FSB667 010 = FSB800 000 = FSB1067 CFG[2:0] 0 = DMI x 2 1 = DMI x 4 CFG5 * (Default) 0 = iTPM Host Interface is enabled CFG6 CFG9 1 = iTPM Host Interface is Disabled 0 = Lane Reversal Enable 1 = Normal Operation * (Default) CFG10 0 = PCIe Loopback Enable 1 = Disable * (Default) 00 01 10 11 CFG[13:12] = Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation * *(Default) (Default) 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled * (Default) 0 = Normal Operation *(Default) 1 = DMI Lane Reversal Enable 0 = Only PCIE or SDVO is operational.02K_0402_1% 1 @ 2.3V6K 2 DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# N28 M28 G36 E36 K36 H36 TSATN# B12 HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC B28 B30 B29 C29 A28 0.35> PLT_RST# <4.15> CLK_DREF_96M <16> CLK_DREF_96M# <16> CLK_DREF_SSC <16> CLK_DREF_SSC# <16> C278 <27> <27> <27> <27> DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 <27> <27> <27> <27> DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 <27> <27> <27> <27> DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3 <27> <27> <27> <27> 1 2. INC.01K_0402_1% <14> <14> <15> <15> B33 B32 G33 F33 E33 GFX_VR_EN C34 <14> <14> <15> <15> +1.2U_0603_6.26.

INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. 2009 Sheet 1 9 of 53 ... INC..7] U23D B GM@ U23E SA_BS_0 SA_BS_1 SA_BS_2 BD21 BG18 AT25 DDR_A_BS0 <14> DDR_A_BS1 <14> DDR_A_BS2 <14> SA_RAS# SA_CAS# SA_WE# BB20 BD20 AY20 DDR_A_RAS# <14> DDR_A_CAS# <14> DDR_A_WE# <14> SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 A MEMORY SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SYSTEM C AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 DDR DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 <14> <14> <14> <14> <14> <14> <14> <14> CANTIGA ES_FCBGA1329 AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 BC16 BB17 BB33 DDR_B_BS0 <15> DDR_B_BS1 <15> DDR_B_BS2 <15> SB_RAS# SB_CAS# SB_WE# AU17 BG16 BF14 DDR_B_RAS# <15> DDR_B_CAS# <15> DDR_B_WE# <15> SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 B <14> DDR_A_DQS#[0. September 28.7] DDR_B_DM[0..7] DDR_A_MA[0.MB A4853 Document Number Rev A 401817 Monday.7] DDR_B_DQ[0. Inc...63] 3 GM@ C DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 <15> <15> <15> <15> <15> <15> <15> <15> B CANTIGA ES_FCBGA1329 A A Compal Electronics.7] <15> DDR_B_DQS#[0.14] <15> DDR_B_MA[0.7] DDR_B_MA[0... Compal Secret Data Security Classification 2009/07/01 Issued Date Deciphered Date 2010/07/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS..63] <15> DDR_B_DM[0..14] 1 SYSTEM D <15> DDR_B_D[0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.63] MEMORY <14> DDR_A_MA[0..14] D DDR_B_DQS#[0...63] DDR_A_DM[0. Date: 5 4 3 2 SCHEMATIC.7] 2 DDR <14> DDR_A_D[0..5 4 DDR_A_D[0.14] DDR_A_DQS#[0. INC... AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.7] <14> DDR_A_DM[0.

1U_0402_16V7K PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 0.1U_0402_16V7K C833 0.05VS PCIE_MTX_C_GRX_N[0.1U_0402_16V7K C811 0. INC.1U_0402_16V7K PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15 B 2 L29 VGA 2 LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK 2 2 1 1 R157 R156 R160 0_0402_5% 0_0402_5% 0_0402_5% 2 C41 C40 B37 A37 TV 2 GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDS C C44 B43 E37 E38 GRAPHICS D L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN PCI-EXPRESS L32 G32 M32 M33 K33 J33 M29 LBKLT_EN GM@ CANTIGA ES_FCBGA1329 1 R174 0_0402_5% Change to 0Ohm for DIS A A R186 1 R176 1 R179 1 @ @ 2 0_0402_5% TV_DCONSEL_0 2 0_0402_5% TV_DCONSEL_1 2 100K_0402_5% LBKLT_EN Compal Electronics.1U_0402_16V7K PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 0..1U_0402_16V7K PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 0.1U_0402_16V7K C827 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 0... Compal Secret Data Security Classification 2009/07/01 Issued Date Deciphered Date 2010/07/01 Title SCHEMATIC.1U_0402_16V7K C831 0. Rev A 401817 Date: 5 4 3 2 Monday.1U_0402_16V7K C835 0..1U_0402_16V7K 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 0.1U_0402_16V7K 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C825 0..15] C812 1 C832 1 49. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.1U_0402_16V7K PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 0.15] <17> PCIE_GTX_C_MRX_N[0.1U_0402_16V7K C839 0.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.1U_0402_16V7K PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 0.1U_0402_16V7K C817 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 0. INC..1U_0402_16V7K C829 0.1U_0402_16V7K C815 0. September 28.15] <17> C 2 2 C814 1 2 C816 1 2 C818 1 2 C820 1 2 C822 1 2 C824 1 2 C826 1 2 C828 1 2 C830 1 2 2 C834 1 2 C836 1 2 C838 1 2 C840 1 +1.9_0402_1% 2 C809 0.1U_0402_16V7K C837 0.15] PCIE_GTX_C_MRX_P[0.5 4 3 2 1 U23C 1 TV_DCONSEL_0 TV_DCONSEL_1 Change to 0Ohm for DIS 2 H47 E46 G40 A40 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 H48 D45 F40 B40 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 A41 H38 G37 J37 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 B42 G38 F37 K37 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3 F25 H25 K25 TVA_DAC TVB_DAC TVC_DAC H24 TV_RTN R173 1 0_0402_5% R172 1 0_0402_5% R171 1 0_0402_5% B CRT_IREF C31 E32 TV_DCONSEL_0 TV_DCONSEL_1 E28 CRT_BLUE G28 CRT_GREEN J28 CRT_RED G29 CRT_IRTN H32 J32 J29 E29 CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC PEG_COMP 1 R184 PEG_COMPI PEG_COMPO T37 T36 PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15 10mils C810 1 2 D PCIE_MTX_C_GRX_N[0.1U_0402_16V7K C823 0. Inc.15] PCIE_MTX_C_GRX_P[0. INC.1U_0402_16V7K PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 0.15] <17> PCIE_MTX_C_GRX_P[0..15] PCIE_GTX_C_MRX_N[0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 0.1U_0402_16V7K C813 0..1U_0402_16V7K PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15 0.15] <17> PCIE_GTX_C_MRX_P[0. 2009 Sheet 1 10 of 53 .1U_0402_16V7K PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 0. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.1U_0402_16V7K C819 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_16V7K C821 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 0.

THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.1U_0402_16V7K 0.3V6K 0. INC.1U_0402_16V4Z Place on the edge DDR3 Reference PILLAR_ROCK CRB Rev1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. BD16.5V VCC_SM: 2600mA (330UF*1.5 4 U23F 3 2 1 +VGFX_CORE +1.4mA (GMCH).1U_0402_16V7K 0.84mA (330UF*2.05VS VCC T17 T18 Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14 Place close to the GMCH NCTF VCC_SM_AT13 VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16 VCC VCC_SM_AW16 BA36 BB24 BD16 BB21 AW16 AW13 AT13 VCC VCC_SM_BA36 VCC_SM_BB24 VCC_SM_BD16 VCC_AXG_NTCF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC CORE C SM Pins BA36. 22UF*1.05VS 1 @ 1 + C485 C255 C265 C266 1 U23G C256 220U_D2_4VM_R15 0.1UF*1) 1 C269 1 + 1 C252 1 C251 C263 330U_D2E_2.0 GFX PAD PAD VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42 VCC: 1930. Rev A 401817 Date: 5 4 3 2 Sheet Monday. 10UF*1.1U_0402_16V4Z 2 2 2 10U_0805_10V4Z 0. 0.22U_0402_6.3V6K Cavity Capacitors VCC_AXG: 6326. BB24.22U_0402_6.3V6K 1U_0402_6.22U_0402_6. Compal Secret Data Security Classification 2010/07/01 Deciphered Date Title SCHEMATIC. 0.34mA (MCH) (270UF*1. Inc. AT13 could be left NC for DDR2 board. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. 1U*1. BB21.3V4Z 2 2 2 2 2 2 2 0.1U_0402_16V7K VCC SM LF DDR3 VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7 AV44 BA37 AM40 AV21 AY5 AM10 BB13 VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7 1 C213 AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23 B CANTIGA ES_FCBGA1329 C215 1 C205 1 C230 1 C272 1 C270 1 C279 1 GM@ A 0. 22UF*2.3V4Z CANTIGA ES_FCBGA1329 GM@ 2009/07/01 Issued Date Compal Electronics.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.47U_0603_16V4Z 1U_0402_6.5VM_R9 2 AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 T32 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 C +1.3V4Z 10U_0805_10V4Z 0.1U_0402_16V7K 0. VCC Reference PILLAR_ROCK CRB Rev1.1U_0402_16V7K 0. INC.47U*1.1U_0402_16V4Z @ R568 0_0402_5% Cavity Capacitors 1 C482 +@ 330U_D2E_2. AW13.1UF*2) +VGFX_CORE C243 C244 C234 1 C235 1 C236 1 C242 1 @ @ 0.22U_0402_6.1U_0402_16V7K 0. INC.5V +VGFX_CORE B @ @ VCC_AXG_SENSE VSS_AXG_SENSE AJ14 AH14 VCC_AXG_SENSE VSS_AXG_SENSE GFX NCTF A D +1.22UF*2. 0.5VM_R9 10U_0805_10V4Z 2 2 2 2 10U_0805_10V4Z 0.3V6K 0.1U_0402_16V7K 2 2 2 2 2 0.1U_0402_16V4Z 2 2 @ @ 2 @2 1U_0402_6. AW16.05VS VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 Place close to the GMCH For HM51 +1. 2009 1 11 of 53 .0 POWER D VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 POWER 2600mA AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29 VCC_SM_BA36 VCC_SM_BB24 VCC_SM_BD16 VCC_SM_AW16 VCC_SM_AT13 1 1 1 1 1 C214 C229 C228 C240 C271 @ @ @ @ @ 0.47U_0603_16V4Z 10U_0805_10V4Z 0. 1210.1UF*1) +1. 0. September 28. 22UF*1. 0.

1UF*1) C434 CRT FOR EMI 20080226 L18 1 2 MBK1608121YZF_0603 1 C433 VCCA_HPLL: 24mA +1.8V_TX_LVDS 1 2 @ R226 1 C292 C293 0_0603_5% @ @ 1000P_0402_50V7K 2 2 10U_0805_10V4Z 0_0402_5% VCC_HV: 105. 0. 1UF*1) 1 2 R152 0_0805_5% PLL 480mA AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16 +1.05VS_DPLLB L6 1 2 MBK1608121YZF_0603 VCCA_MPLL: 139.1U_0402_16V4Z @ C483 2 2 0.7U_0805_10V4Z 2 2 2 2 4.363mA +1.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.01UF*1) +3VS VCCA_SM: (22UF*2.3V6M 0.05VS K47 VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 +3VS 1 2 0.5VS_QDAC (0.1U_0402_16V4Z Please check Power source if want support IAMT + C478 @ 220U_D2_4VM_R15 2 1 2 R170 0_0603_5% +1.05VS_PEG: 1782mA +1.69mA @ 2 0.3V6M 2 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 1 2 R108 0.1U_0402_16V4Z VTTLF_CAP1 A8 VTTLF_CAP2 L1 AB2 VTTLF_CAP3 C190 1 C445 1 C470 1 0. 22UF*1.47U_0603_16V4Z 2 2 2 0.05VS_DPLLA 2 2 0_0402_5% 10U_0805_10V4Z 0.3mA 1 2 1 2 R361 C250 1_0402_1% 10U_0805_6.696mA (0.6833333mA (0.3V4Z 2 1 C233 Please check Power source if want support IAMT VCCA_DAC_BG: 2.8V_TX_LVDS: 118.05VS R569 +1.022U_0402_16V7K A AA47 LVDS 1 2 L7 MBK1608221YZF_0603 48.1U_0402_16V4Z 2 2 0.05VS_DPLLB VSSA_DAC_BG F47 VCCA_DPLLA L48 VCCA_DPLLB +1.3V4Z VCCA_TV_DAC_1 VCCA_TV_DAC_2 58. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. 0.2mA (22UF*1.85mA (10UF*1. 0. 1000PF*1) 1 2 R225 0_0805_5% C287 0.1UF*1.3V4Z R575 0_0402_5% 2 1 1 2 +3VS 10_0603_5% CH751H-40PT_SOD323-2 Compal Electronics. 0.5_0603_1% B27 A26 U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1 2 1 C189 852mA 73mA 2 220U_D2_4VM_R15 0_0402_5% VCCA_DPLLA +3VS_CRTDAC 2 0.311111mA (1UF*1) Security Classification 2 +1.05VS_HPLL AD1 VCCA_HPLL +1.1U_0402_16V4Z 2 R571 0_0402_5% 2 Close to Ball A26.05VS_DPLLA U23H 2 1 L12 1 2 MBK1608121YZF_0603 2. 0.1UF*1) 1 1 C241 C254 C253 @ 2.3mA VCC_HV_1 VCC_HV_2 VCC_HV_3 456mA VCCD_TVDAC C152 1 +1.5V L17 MBK1608121YZF_0603 R572 C35 B35 A35 DDR3 C424 +1. Inc.1U_0402_16V4Z 2 2 2 22U_0805_6.47U_0603_16V4Z 0.1UF*1.1uH 20% C267 For HM51 +1. 0.3V6M 2 2 2 0.3V6M NO_STUFF VCCA_TV_DAC: 40mA (0. INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.3V6M 2 2 1U_0402_6.8V_TX_LVDS SM CK R262 @ 0_0402_5% 1 2 A CK For HM51 A SM C151 22U_0805_6.5V_SM_CK 87.31mA VCCD_PEG_PLL: 50mA (0.3V6K (0.05VS AH48 AF48 AH47 AG47 +1.01U_0402_16V7K For HM51 1 1 2 R144 100_0603_1% R165 0_0402_5% @ 2 VCCD_LVDS_1 VCCD_LVDS_2 2 BF21 BH20 BG20 BF20 0.05VS_HPLL +1.1U_0402_16V4Z +1. 0. B27 +1. 0.05VS_HPLL VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4 VCC_HDA 2 +1.7U_0805_10V4Z 2 2 0.5VS 24mA 1 C481 2 VCCA_CRT_DAC: 73mA (0.05VS_DMI VCC_DMI: 456mA (0.79mA +3VS_TVDAC +3VS_TVDAC 1 C154 +1.7U_0805_10V4Z 2.3V6M 1_0402_1% +1.1U_0402_16V4Z FOR EMI 20080226 VCCA_DAC_BG B25 1 1 C290 R570 @ @ C305 +1.2UF*1.8mA (22UF*1.05VS VCCA_PEG_BG 50mA No CIS Symbol L10 1 2 MBK1608221YZF_0603 2 1 1 2 C304 R201 10U_0805_6.47U_0603_16V4Z D +1.01UF*1 for each DAC) VCCD_HPLL C246 1 C245 1 M38 L37 +1.1UF*1) 2 C +1.8mA 50mA 157.05VS For HM51 0.1UF*1) 1uH 30% 118.8V_LVDS 1 1 C274 @ C273 @ 10U_0805_6.414mA AD48 AXF 1 C289 13.35mA (10UF*1.1UF*1.1UF*1) 1 2 VTTLF1 VTTLF2 VTTLF3 +1.1U_0402_16V4Z 10U_0805_6.1U_0402_16V4Z 1 TV DMI 1 2 +1.5VS 50mA VCCD_PEG_PLL 60.05VS_MPLL 1 L22 1 2 MBK1608121YZF_0603 +1. 4. 4.05VS_PEGPLL VCCA_PEG_PLL: 1 C288 AA48 0.05VS VCCD_LVDS: 60. Compal Secret Data 2009/07/01 Issued Date A R263 D15 +1.1UF*1) VTT: 852mA (270UF*1.7UF*2.05VS_MPLL AE1 VCCA_MPLL VCCA_LVDS: 13.7U_0805_10V4Z 2 2 2 22U_0805_6.05VS Deciphered Date 2010/07/01 Title SCHEMATIC.2U_0603_6.5VS_HDA 1 L19 1 2 MBK1608221YZF_0603 180Ohm@100MHz @ 1 C155 +1.47U_0603_16V4Z CANTIGA ES_FCBGA1329 GM@ +1.01UF*1) +VCCA_PEG_BG 1 C291 @ 1000P_0402_50V7K 2 A PEG A LVDS +3VS +1. 2.01U_0402_16V7K 220U_D2_4VM_R15 2 R261 0_0402_5% 1 2 +1.05VS_PEG (220UF*1.3V6K 0. 0. 2.414mA (0.1UF*1) 1 C464 @ + VTT 120Ohm@100MHz 1 @ C479 @ Please check Power source if want support IAMT +1.05VS_A_SM_CK R573 0_0402_5% VCCA_SM_CK: 24mA (22UF*1.05VS 4.696mA +1.1UF*1) +1. Rev A 401817 Date: 5 4 3 2 Sheet Monday.2mA (1000PF*1) J48 VCCA_LVDS J47 VSSA_LVDS 64.8V Please check Power source if want support IAMT 0.2U_0603_6.47UF*1) +1. September 28.1U_0402_16V4Z 2 2 0.363mA 1 1782mA VTTLF VCCD_QDAC D TV/CRT L28 AF1 B22 B21 A21 105.01U_0402_16V7K C153 C HDA VCCD_HDA: 50mA (0.1UF*1) 0.8V 1 R192 0_0603_5% @ VCCD_QDAC: 48.8mA (220UF*1.01U_0402_16V7K B 1 4. 1UF*1) B24 A24 R402 0_0402_5% For HM51 VCCD_TVDAC: 58. 0.1UF*1.2UF*1.05VS_AXF POWER VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 24mA AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23 1 Close to Ball A25 For HM51 +3VS C231 +3VS_DACBG L20 MBK1608221YZF_0603 1 1 1 C473 C461 C474 @ @ @ @ 0.2mA (0. 4.8mA 2 1 A25 +3VS_DACBG VCCA_PEG_BG: 0.7UF*1) V48 U48 V47 U47 U46 +1.2mA +1.5VS_TVDAC 1 2 R399 0_0603_5% 1 1 C471 C459 @ 10U_0805_6.05VS_A_SM 1 VCCA_PEG_PLL 50mA 1 + 220U_D2_4VM_R15 4.1UF*1.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 1 1 1 R264 0_0805_5% 2 +1.05VS 1 2 1 C232 1 +1.5VS_TVDAC 1 Please check Power source if want support IAMT VCC_AXF: 321.1U_0402_16V4Z VCCA_DPLLB: 64.05VS_PEGPLL Please check Power source if want support IAMT VCC_TX_LVDS VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4 M25 2 VCC_SM_CK: 119.5 4 3 2 1 +1.3V6M 2 2 1U_0402_6.01UF*1) VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8 1 R574 0_0402_5% 2 1 1 C472 C460 @ @ 0. 0. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. INC.2mA HV 1 Please check Power source if want support IAMT +3VS 139. 2009 1 12 of 53 .3V6M 1U_0402_6.1U_0402_16V4Z Please check Power source if want support IAMT D 1 1 (4.1UF*1) Also power for internal Thermal Sensor 0.01UF*1) 180Ohm@100MHz C247 1 C257 1 0.2mA PEG +3VS_CRTDAC 1 2 L21 MBK1608221YZF_0603 1 1 C475 C462 @ 1 @ @ + 0.05VS B + C312 C311 10U_0805_10V4Z 2 2 220U_D2_4VM_R15 +1.5VS_QDAC VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 A32 VCCD_HPLL: 157.1UF*1) +1.5VS +1. INC.7UF*1.7UF*1.

INC. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. Rev A 401817 Date: 5 4 3 2 Sheet Monday. INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.5 4 3 B VSS AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6 BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 BA16 VSS_235 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS VSS NCTF C 1 U23J VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS SCB D VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 VSS_351 VSS_352 VSS_353 VSS_354 U24 U28 U25 U29 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17 VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 BH48 BH1 A48 C1 A3 NC U23I AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36 2 CANTIGA ES_FCBGA1329 GM@ NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 D C B E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48 CANTIGA ES_FCBGA1329 A A GM@ 2009/07/01 Issued Date Compal Electronics. Inc. Compal Secret Data Security Classification 2010/07/01 Deciphered Date Title SCHEMATIC.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. September 28. INC. 2009 1 13 of 53 .

3V6M <9> DDR_A_BS2 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 SM_DRAMRST# <8.1U_0402_16V4Z A C907 2.7] DDR_A_D4 DDR_A_D5 2. September 28.3V6M DDR_A_D26 DDR_A_D27 +DIMM_VREF <8.1U_0402_16V4Z DDR_A_MA12 DDR_A_MA9 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 DDR_A_D14 DDR_A_D15 10U_0603_6..5V DDR_A_D28 DDR_A_D29 C895 DDRA_CLK0 DDRA_CLK0# <8> DDRA_CLK0 <8> DDRA_CLK0# 2 1 Layout Note: Place these 4 Caps near Command and Control signals of DIMMA DDR_A_D22 DDR_A_D23 0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.16> +0.1U_0402_16V4Z DDR_A_MA3 DDR_A_MA1 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 D 1 DDR_A_DM2 10U_0603_6.1U_0402_16V4Z DDR_A_D56 DDR_A_D57 2 C896 DDR_A_D50 DDR_A_D51 2 1 0.1U_0402_16V4Z DDR_A_D34 DDR_A_D35 1K_0402_1% 2 DDR_A_MA14 2. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS..14] DDR_A_D6 DDR_A_D7 C893 DDR_A_D16 DDR_A_D17 DDR_A_DQS#0 DDR_A_DQS0 C904 DDR_A_D10 DDR_A_D11 <9> DDR_A_DQS[0..5 4 +1.16> D_CK_SCLK <15. INC.2U_0603_6. Date: 5 2 G1 C887 0.7] C888 DDR_A_DQS#1 DDR_A_DQS1 +1.204 DDR_A_MA2 DDR_A_MA0 DDRA_CLK1 DDRA_CLK1# DDR_A_BS1 DDR_A_RAS# DDRA_SCS0# DDRA_ODT0 DDRA_ODT1 DDR_VREF_CA_DIMMA DDR_A_D36 DDR_A_D37 DDRA_CLK1 <8> DDRA_CLK1# <8> +0.3V4Z C905 DDR_A_DQS#4 DDR_A_DQS4 B 2 C900 DDR_A_D32 DDR_A_D33 DDRA_CKE1 2 1 1U_0603_10V4Z <8> DDRA_SCS1# 2 1 1U_0603_10V4Z DDR_A_MA13 DDRA_SCS1# 1 1U_0603_10V4Z DDR_A_WE# DDR_A_CAS# DDR_A_D30 DDR_A_D31 1U_0603_10V4Z <9> DDR_A_BS0 <9> DDR_A_WE# <9> DDR_A_CAS# DDR_A_DQS#3 DDR_A_DQS3 10U_0805_6..1U_0402_16V4Z DDR_A_DQS#6 DDR_A_DQS6 DDR_A_MA6 DDR_A_MA4 C903 DDR_A_D48 DDR_A_D49 2 1 C C902 DDR_A_D42 DDR_A_D43 2 1 DDR_A_MA11 DDR_A_MA7 C901 DDR_A_DM5 2 1 C906 DDR_A_D40 DDR_A_D41 1 DDRA_CKE1 <8> 0.2U_0603_6.5VM_R7 2 2 Layout Note: Place near JDIMM2.5V 4 3 2 SCHEMATIC.15> +DIMM_VREF 10U_0603_6.3V6M DDR_A_BS2 DDR_A_DM1 SM_DRAMRST# 10U_0603_6.63] JDIMM2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 2 1 2 R602 10K_0402_5% 2 1 C908 1 0.5V 3 2 <9> DDR_A_DQS#[0.MB A4853 Document Number Rev A 401817 Sheet Monday.75VS DDR_A_BS1 <9> DDR_A_RAS# <9> DDRA_SCS0# <8> DDRA_ODT0 <8> +DIMM_VREF DDRA_ODT1 <8> 1 2 R600 0_0402_5% DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 2 1 1 2 2 1 2 1 2 1 1 2 1 2 B DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 PM_EXTTS#0 D_CK_SDATA D_CK_SCLK PM_EXTTS#0 <8> D_CK_SDATA <15.3V4Z +3VS G2 206 1 2 1 + C899 330U_D2E_2.203 & JDIMM2. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.1U_0402_16V4Z 205 1 1 C898 DDR_A_D58 DDR_A_D59 1 R601 2 10K_0402_5% 2 C897 DDR_A_DM7 1 0.2U_0805_16V4Z DDR_A_D8 DDR_A_D9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 C892 D VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 C891 DDR_A_D2 DDR_A_D3 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 C890 DDR_A_DM0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 C889 DDR_A_D0 DDR_A_D1 <8> DDRA_CKE0 1 +1. 2009 1 14 of 53 .3V6M DDR_A_MA8 DDR_A_MA5 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 +DIMM_VREF Layout Note: Place near JDIMM2 DDR_A_D20 DDR_A_D21 0.15> 10U_0603_6. Inc.5V <9> DDR_A_DM[0.3V6M DDRA_CKE0 C DDR_A_D12 DDR_A_D13 10U_0603_6. INC.3V6M DDR_A_MA10 DDR_A_BS0 R599 +1. INC.75VS A +0.2mm (BOT) 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. Compal Secret Data Security Classification DIMM0 REV H:5.7] +DIMM_VREF <9> DDR_A_D[0.3V6M DDR_A_DM3 1K_0402_1% C894 DDR_A_DQS#2 DDR_A_DQS2 R598 <9> DDR_A_MA[0.75VS CONN@ 2009/07/01 Issued Date Compal Electronics..

3V6M DDR_B_D16 DDR_B_D17 <9> DDR_B_DQS[0.3V6M DDR_B_DQS#2 DDR_B_DQS2 <9> DDR_B_MA[0.75VS C927 DDR_B_D34 DDR_B_D35 DDRB_CKE1 <8> 0..203 & JDIMM1..14> DDR_B_D14 DDR_B_D15 0.5V SM_DRAMRST# <8.1U_0402_16V4Z DDR_B_D26 DDR_B_D27 DDR_B_DM1 SM_DRAMRST# 10U_0603_6.5V <9> DDR_B_DQS#[0.3V6M DDR_B_D18 DDR_B_D19 Layout Note: Place near JDIMM1 DDR_B_D6 DDR_B_D7 10U_0805_6.16> D_CK_SCLK <14.3V6M 2 +1.14] 10U_0603_6. September 28...MB A4853 Document Number Rev A 401817 Sheet Monday.2mm (BOT) Compal Electronics.2U_0603_6.1U_0402_16V4Z <9> DDR_B_BS2 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 2 1 C917 DDR_B_BS2 DDR_B_DM2 1 0.3V6M DDR_B_D24 DDR_B_D25 1 DDR_B_D12 DDR_B_D13 10U_0603_6.1U_0402_16V4Z DDRB_CKE0 <8> DDRB_CKE0 DDR_B_D20 DDR_B_D21 10U_0603_6.16> 4 +0.7] DDR_B_DQS#0 DDR_B_DQS0 C916 DDR_B_D10 DDR_B_D11 DDR_B_D4 DDR_B_D5 C915 DDR_B_DQS#1 DDR_B_DQS1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 C926 DDR_B_D8 DDR_B_D9 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 C914 2 DDR_B_D2 DDR_B_D3 C910 C909 2 1 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 C913 1 0.A B C +1. INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.1U_0402_16V4Z 3 2 DDR_B_MA14 2.3V4Z DDR_B_DQS#4 DDR_B_DQS4 1 1 C920 DDR_B_D32 DDR_B_D33 2 C919 <8> DDRB_SCS1# 2 1 0. 2009 E 15 of 53 .7] B C D SCHEMATIC.204 1U_0603_10V4Z C924 DDRB_CLK0 DDRB_CLK0# <8> DDRB_CLK0 <8> DDRB_CLK0# DDR_B_D30 DDR_B_D31 1U_0603_10V4Z C923 DDR_B_MA3 DDR_B_MA1 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 2 1 DDR_B_DQS#3 DDR_B_DQS3 1U_0603_10V4Z C922 DDR_B_MA8 DDR_B_MA5 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 2 1 DDR_B_D28 DDR_B_D29 1U_0603_10V4Z DDR_B_MA12 DDR_B_MA9 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 DDR_B_D22 DDR_B_D23 2 1 0.3V6M DDR_B_DM3 Layout Note: Place these 4 Caps near Command and Control signals of DIMMA 10U_0603_6.14> +DIMM_VREF <9> DDR_B_DM[0.1U_0402_16V4Z 2.75VS +0.7] <9> DDR_B_D[0. Compal Secret Data Security Classification 2009/07/01 Issued Date 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. Inc.1U_0402_16V4Z C929 2.3V4Z +3VS 4 1 R605 C930 2 10K_0402_5% 205 G2 206 G1 2 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDRB_CLK1 DDRB_CLK1# 1 2 1 2 1 2 1 1 2 DDRB_CLK1 <8> DDRB_CLK1# <8> DDR_B_BS1 DDR_B_RAS# DDR_B_BS1 <9> DDR_B_RAS# <9> DDRB_SCS0# DDRB_ODT0 DDRB_SCS0# <8> DDRB_ODT0 <8> DDRB_ODT1 DDR_VREF_CA_DIMMB 2 +DIMM_VREF DDRB_ODT1 <8> R603 1 2 0_0402_5% DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D38 DDR_B_D39 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 1 2 1 2 3 C928 DDR_B_D40 DDR_B_D41 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 PM_EXTTS#1 D_CK_SDATA D_CK_SCLK PM_EXTTS#1 <8> D_CK_SDATA <14. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.75VS CONN@ DIMM1 REV H:9.2U_0805_16V4Z 1 DDR_B_DM0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 C912 DDR_B_D0 DDR_B_D1 C911 <8.63] +DIMM_VREF JDIMM1 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DM7 DDR_B_D58 DDR_B_D59 1 R604 2 10K_0402_5% 1 2 1 2 0.2U_0603_6. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. INC.5V D E +1. INC. Date: A + C921 @ 330U_D2E_2..5VM_R7 2 +0.3V6M <9> DDR_B_BS0 <9> DDR_B_WE# <9> DDR_B_CAS# DDRB_CKE1 C925 DDR_B_MA10 DDR_B_BS0 2 1 Layout Note: Place near JDIMM1.1U_0402_16V4Z DDR_B_MA13 DDRB_SCS1# 2 1 C918 DDR_B_WE# DDR_B_CAS# 2 1 10U_0805_6.

Pin28.05VS R384 @ 1K_0402_5% CLK_DREF_96M# <8> R576 @ R577 @ 2 CLK_XTALIN 1 22_0402_5% 1 22_0402_5% CLK_ICH_14M R304 2 CLK_DREF_96M <8> 39 CLK_PCI5 CLK_MCH_BCLK# <7> VGA: disable this pair by BIOS 13 Y2 14.15> VDD48 2 1 R308 @ H +CLK_VDD +CLK_VDD +3VS 3 G +CLK_VDDSRC Table : ICS9LPRS387 Control F L15 2 1 FBMA-L11-201209-221LMA30T_0805 1 1 1 1 1 1 1 1 C358 C371 C387 C370 C380 C381 C386 C347 10U_0805_10V4Z 10U_0805_10V4Z 0. Pin63.1U_0402_16V4Z U16 1 ICS9LPRS387. Pin63.27.31818MHz_20P_FSX8L14. PN:SA000020H10 SLG8SP556V.7K_0402_5% 1 2 3 SRCT7_LPR 61 CLK_PCIE_VGA SRCC7_LPR 60 CLK_PCIE_VGA# CK_PWRGD/PD# CPUT2_ITP_LPR/SRCT8_LPR 64 CPUC2_ITP_LPR/SRCC8_LPR 63 11 NC SRCT9_LPR 44 CLK_PCIE_MINI2 SRCC9_LPR 45 CLK_PCIE_MINI2# CLKSEL0 20 USB_48MHz/FSLA CLKSEL1 2 FSLB/TEST_MODE +3VS D_CK_SCLK 7 FSLC/TEST_SEL/REF0 8 REF1 69 GNDCPU 50 51 SRCT11_LPR 48 CLK_PCIE_LAN SRCC11_LPR 47 CLK_PCIE_LAN# 3 GNDREF CR#3 37 18 GNDPCI CR#4 41 22 GND48 CR#6 58 30 GND CR7# 65 26 GND CR#9 43 34 GNDSRC CR10# 49 59 GNDSRC CR#11 46 CR#A 21 42 73 Q23 2N7002_SOT23 SRCT10_LPR SRCC10_LPR GNDSRC GND_THERMAL_PAD For M92 CLK_PCIE_VGA# <17> X2 +3VS CLK_MCH_3GPLL# <8> CLK_PCIE_VGA <17> X1 D_CK_SDATA CLK_MCH_3GPLL <8> PCI_F5/ITP_EN 4 CLKSEL2 <27> Remove New Card CLK For HM51 5 +3VS +1.1U_0402_16V4Z 0. September 28.33> ICH_SMBDATA 3 CLK_PCIE_ICH 36 PCI1 S 1 35 14 +3VS 2 G R383 1K_0402_5% 1 2 1 CLKSEL1 SRCT3_LPR SRCC3_LPR 27M_NSSC <18> CLK_DREF_SSC <8> 27M_SSC <18> CLK_DREF_SSC# <8> CLK_DREF_SSC 1 0_0402_5% CLK_DREF_SSC# 1 0_0402_5% CLK_PCIE_SATA <26> CLK_XTALOUT 1 33_0402_5% R305 4. Compal Secret Data Security Classification MCH_CLKSEL2 <8> 2009/07/01 Deciphered Date CPU_BSEL2 <5> 2010/07/01 Title SCHEMATIC.3 D +3VS Clock Generator L16 2 1 FBMA-L11-201209-221LMA30T_0805 1 1 1 1 1 1 1 1 C384 C356 C357 C355 C352 C372 C385 C390 10U_0805_10V4Z 0.1U_0402_16V4Z 0.05VS 4 17 <27> CLK_PCIE_ICH# SRCT4_LPR 2 CLK_PCIE_SATA# <26> CLK_PCIE_ICH SRCC4_LPR Q22 2N7002_SOT23 CPU_BSEL1 <5> 2 G 2 CLK_PCIE_ICH# PCI2/TME S 2 <27.05VS 1 R303 1 R302 @ C354 1 2 R327 @ 56_0402_5% R313 1K_0402_5% 1 2 1 R314 0_0402_5% 2 27P_0402_50V8J C353 27P_0402_50V8J 1 2 <27> CLK_ICH_48M CPU_BSEL0 <5> <30> CLK_SD_48M SRCT2_LPR/SATAT_LPR 32 SRCC2_LPR/SATAC_LPR 33 CLK_PCIE_SATA# MCH_CLKSEL1 <8> D 1 R380 0_0402_5% 2 40 CLK_PCI3 15 PCI3 57 16 SRCT6_LPR CLK_MCH_3GPLL CLK_PCI4 PCI4/27_SELECT SRCC6_LPR 56 CLK_MCH_3GPLL# CK505_PWRGD1 R389 @ 1K_0402_5% R392 1K_0402_5% 1 2 1 R391 0_0402_5% 2 1 <27.1U_0402_16V4Z 2 2 2 2 2 2 2 2 0. INC.64 is SRC_CLK CLK_PCI5=1. Trusted Mode Enable(No overclocking allowed) 1 R310 2 10K_0402_5% 62 D mount to Enable ITP_CLK 2 @ 10K_0402_5% 38 CK505_PWRGD 2 G Q28 2N7002_SOT23 @ S 3 1 R312 52 +CLK_VDDSRC 1 CLK_PCI4 2 10K_0402_5% 1 R593 CLK_PCI5 CLK_ENABLE# <47> VDDREF CLK_PCI5=0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 10U_0805_10V4Z 0. 2009 G Sheet 16 of H 53 . THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. 29 is 27MHz Pin24.318181M20FDB CLK_ICH_48M R325 2 CLK_SD_48M R311 2 CLK_MCH_BCLK <7> CLK_PCIE_SATA MCH_CLKSEL0 <8> <27> CLK_ICH_14M 1 R390 @ 0_0402_5% CLK_MCH_BCLK# CLK_CPU_BCLK# <4> VDDSRC_IO H_STP_PCI# 10P_0402_50V8J CLK_PCI_LPC For EMI 10/9 1 R379 @ 0_0402_5% CLK_MCH_BCLK 67 31 CPU_STOP# CK_PWRGD 1 C346 1 68 CLK_PCI4 2 10K_0402_5% <35> CLK_PCI_LPC C345 1 CPUT1_LPR_F VDDSRC_IO 53 2 1 R292 CLK_CPU_BCLK <4> CPUC1_LPR_F VDDSRC_IO H_STP_CPU# CLK_PCI4=0.1U_0402_16V4Z +1.47> VGATE +1. INC.A FSLC B FSLB FSLA CLKSEL2 CLKSEL1 CLKSEL0 C CPU MHz SRC MHz PCI MHz 0 0 0 266 100 33.1U_0402_16V4Z 0. Pin28.7K_0402_5% 1 2 2 CLK_PCI2 +1. Rev A 401817 Date: A B C D E F Monday. INC.1U_0402_16V4Z 0. 29 is SRC_CLK CLK_PCI4=1. 25 is SRC_CLK D_CK_SCLK <14. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.15> Free-Run 6 CR#_10(WLAN) PCIEX10 PCIEX0 19 CR#_6(MCH) PCIEX6 PCIEX1 72 VDDCPU CPUT0_LPR_F 71 CR#_4(NEW CARD) PCIEX4 12 VDDPCI CPUC0_LPR_F 70 CLK_CPU_BCLK# CR#_9(MINI CARDII) PCIEX9 27 VDDPLL3 55 VDDSRC +3VS 2 SRC7(VGA_CLK): Discrete VGA[Enable] R301 10K_0402_5% @ 1 CLK_PCI2 2 10K_0402_5% 1 R306 CLK_PCI2=1.33> ICH_SMBCLK D 2 2 1 R388 10K_0402_5% CLKSEL2 1 2 R293 4.1U_0402_16V4Z 0.64 is ITP_CLK <27> H_STP_CPU# <27> H_STP_PCI# 2 @ 10K_0402_5% 2 @ CLK_PCI_LPC R307 2 2 @ CLK_PCI_ICH <25> CLK_PCI_ICH 10P_0402_50V8J CLK_PCI_ICH SRCT0_LPR/DOTT_96_LPR 24 CLK_DREF_96M SRCC0_LPR/DOTC_96_LPR 25 CLK_DREF_96M# VDDPLL3_IO 27MHz_NonSS/SRCT1_LPR/SE1 28 66 VDDCPU_IO 27MHz_SS/SRCC1_LPR/SE2 29 23 VDD96_IO 54 PCI_STOP# 2 1 R326 2.05VS 1 CLK_REQ# E CLK_PCIE_MINI2 <33> CLK_PCIE_MINI2# 3 <33> CLK_PCIE_LAN <31> CLK_PCIE_LAN# <31> MCH_CLKREQ# <8> (Pull High to +3VS at GMCH side) R5831 @ 2 0_0402_5% CLKREQB <18> 1 2 +3VS R336 10K_0402_5% MINI2_CLKREQ# <33> 1 R364 2 10K_0402_5% For M92 +3VS LAN_CLKREQ# <31> 4 (Pull High to +3VS at ICH side) SATA_CLKREQ# <27> ICS9LPRS387BKLFT_MLF72_10x10 Issued Date Compal Electronics.3 0 1 0 200 100 33.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. Inc.3 0 1 1 166 100 33.2K_0402_5% CLKSEL0 1 2 1 33_0402_5% 1 2 R328 @ 1K_0402_5% R309 2 1 33_0402_5% 0_0402_5% 2 0_0402_5% 2 <27> CK_PWRGD <8.1U_0402_16V4Z 0. PN:SA000020K00 9 D_CK_SDATA SCLK 10 D_CK_SCLK CLK_CPU_BCLK SDATA D_CK_SDATA <14.1U_0402_16V4Z 0. 25 is DOT96_CLK Pin24.1U_0402_16V4Z 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.

Date: 5 4 3 2 SCHEMATIC.15] <10> PCIE_GTX_C_MRX_P[0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.15] <10> PCIE_MTX_C_GRX_P[0.1VS PERSTB 216-0728018 A12 M92-S2 XT FCBGA 0FA ESD A A 2009/07/01 Issued Date Compal Electronics.1U_0402_16V7K 0.1U_0402_16V7K PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5 AA29 Y28 PCIE_RX5P PCIE_RX5N PCIE_TX5P PCIE_TX5N Y23 Y24 PEG_NRX_C_GTX_P5 PEG_NRX_C_GTX_N5 C605 1 C606 2 1 2 0.15] PCIE_MTX_C_GRX_P[0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_N0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1 AE29 AD28 PCIE_RX1P PCIE_RX1N PCIE_TX1P PCIE_TX1N AG29 AF28 PEG_NRX_C_GTX_P1 PEG_NRX_C_GTX_N1 C597 1 C598 2 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 AD30 AC31 PCIE_RX2P PCIE_RX2N PCIE_TX2P PCIE_TX2N AF27 AF26 PEG_NRX_C_GTX_P2 PEG_NRX_C_GTX_N2 C599 1 C600 2 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10 T30 R31 PCIE_RX10P PCIE_RX10N PCIE_TX10P PCIE_TX10N U24 U23 PEG_NRX_C_GTX_P10 C615 1 PEG_NRX_C_GTX_N10 C616 2 1 2 0. INC. INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.1U_0402_16V7K 0.1U_0402_16V7K 0.. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.1U_0402_16V7K 0.1U_0402_16V7K PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14 M30 L31 PCIE_RX14P PCIE_RX14N PCIE_TX14P PCIE_TX14N P24 P23 PEG_NRX_C_GTX_P14 C623 1 PEG_NRX_C_GTX_N14 C624 2 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P15 PCIE_GTX_C_MRX_N15 PCIE_CALRP Y22 R467 1 2 1. Inc.1U_0402_16V7K PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13 N29 M28 PCIE_RX13P PCIE_RX13N PCIE_TX13P PCIE_TX13N P27 P26 PEG_NRX_C_GTX_P13 C621 1 PEG_NRX_C_GTX_N13 C622 2 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N14 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15 L29 K30 PCIE_RX15P PCIE_RX15N PCIE_TX15P PCIE_TX15N M27 N26 PEG_NRX_C_GTX_P15 C625 1 PEG_NRX_C_GTX_N15 C626 2 1 2 0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 R29 P28 PCIE_RX11P PCIE_RX11N PCIE_TX11P PCIE_TX11N T26 T27 PEG_NRX_C_GTX_P11 C617 1 PEG_NRX_C_GTX_N11 C618 2 1 2 0.25..27K_0402_1% PCIE_CALRN AA22 R469 1 2 PCI EXPRESS INTERFACE C PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0 C B CLOCK <16> CLK_PCIE_VGA <16> CLK_PCIE_VGA# CLK_PCIE_VGA CLK_PCIE_VGA# AK30 AK32 PCIE_REFCLKP PCIE_REFCLKN L9 N9 N10 NC#1 NC#2 NC_PWRGOOD For Future ASIC Pin N10 need pull down @ 10K_0402_5% 2 1 R468 <8. September 28. 2009 Sheet 1 17 of 53 .1U_0402_16V7K 0.. INC.1U_0402_16V7K 0.35> PLT_RST# <25> PLTRST_VGA# 2 R578 1 0_0402_5% CALIBRATION AL27 2 1 @C627 @ C627 10P_0402_50V8J 2K_0402_1% +1.15] PCIE_GTX_C_MRX_N[0...1U_0402_16V7K 0.31.1U_0402_16V7K PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12 P30 N31 PCIE_RX12P PCIE_RX12N PCIE_TX12P PCIE_TX12N T24 T23 PEG_NRX_C_GTX_P12 C619 1 PEG_NRX_C_GTX_N12 C620 2 1 2 0.1U_0402_16V7K 0. Compal Secret Data Security Classification 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.1U_0402_16V7K 0.1U_0402_16V7K PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 W29 V28 PCIE_RX7P PCIE_RX7N PCIE_TX7P PCIE_TX7N Y27 Y26 PEG_NRX_C_GTX_P7 PEG_NRX_C_GTX_N7 C609 1 C610 2 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 AB30 AA31 PCIE_RX4P PCIE_RX4N PCIE_TX4P PCIE_TX4N AC25 AB25 PEG_NRX_C_GTX_P4 PEG_NRX_C_GTX_N4 C603 1 C604 2 1 2 0.15] <10> PCIE_GTX_C_MRX_N[0.1U_0402_16V7K PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8 V30 U31 PCIE_RX8P PCIE_RX8N PCIE_TX8P PCIE_TX8N W24 W23 PEG_NRX_C_GTX_P8 PEG_NRX_C_GTX_N8 C611 1 C612 2 1 2 0.15] D D U30A B AF30 AE31 PCIE_RX0P PCIE_RX0N PCIE_TX0P PCIE_TX0N AH30 AG31 PEG_NRX_C_GTX_P0 PEG_NRX_C_GTX_N0 C595 1 C596 2 1 2 0.15] PCIE_MTX_C_GRX_N[0.1U_0402_16V7K PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N3 AC29 AB28 PCIE_RX3P PCIE_RX3N PCIE_TX3P PCIE_TX3N AD27 AD26 PEG_NRX_C_GTX_P3 PEG_NRX_C_GTX_N3 C601 1 C602 2 1 2 0..1U_0402_16V7K 0.1U_0402_16V7K 0.MB A4853 Document Number Rev A 401817 Monday.5 4 3 2 1 PCIE_GTX_C_MRX_P[0.15] <10> PCIE_MTX_C_GRX_N[0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0..1U_0402_16V7K PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 Y30 W31 PCIE_RX6P PCIE_RX6N PCIE_TX6P PCIE_TX6N AB27 AB26 PEG_NRX_C_GTX_P6 PEG_NRX_C_GTX_N6 C607 1 C608 2 1 2 0..1U_0402_16V7K PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 U29 T28 PCIE_RX9P PCIE_RX9N PCIE_TX9P PCIE_TX9N V27 U26 PEG_NRX_C_GTX_P9 PEG_NRX_C_GTX_N9 C613 1 C614 2 1 2 0.

3V_DELAY CRT (3.3V4Z 1 C638 2 C636 2 0.3V R492 1K_0402_5% T37 PAD +TSVDD 1U_0402_6.8V@45mA VDD1DI) 10U_0603_6.1U_0402_10V6K GND OUT 3 1 IN GND 2 +VGA_CORE 0 (1.<23> TXOUT_L3P TXOUT_L3N AL19 AK18 I2C GENERAL PURPOSE I/O GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 <22> GPU_GPIO0 <22> GPU_GPIO1 <22> GPU_GPIO2 1 2 R585 100K_0402_5% 1 2 D31 RB751V_SOD323 <27.3V_DELAY DPLL_PVDD DPLL_PVSS +DPLL_VDDC AD14 DPLL_VDDC AM28 AK28 XTALIN XTALOUT 27MCLK XTALOUT R490 L51 TESTEN 1 1 BLM18PG121SN1D_0603 10U_0603_6.3V4Z 2 @ MCK1608471YZF 0603 1 C631 1 +DPC_VDD10 1 C632 C633 @ 10U_0603_6.8V 2 <16> 27M_NSSC +DPLL_PVDD 1 C650 2 1 C651 2 1 2 C652 THERMAL DDC1CLK DDC1DATA AE6 AE5 AUX1P AUX1N AD2 AD4 VGA_CRT_CLK <24> VGA_CRT_DATA <24> DDC2CLK DDC2DATA AC11 AC13 AUX2P AUX2N AD13 AD11 NC1 NC2 AB22 AC22 DDCAUX5P DDCAUX5N AE16 AD16 DDC6CLK DDC6DATA NC_DDCAUX7P NC_DDCAUX7N +3. INC.24> TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N AH18 AJ17 VGA_TXOUT2+ <23> VGA_TXOUT2.2V +DPLL_VDDC 0 1 1.8V@120mA +DPLL_PVDD) 1 @ 1U_0402_6.<23> TX4P_DPB1P TX4M_DPB1N AJ7 AH6 TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N AL23 AK22 VGA_TZOUT2+ VGA_TZOUT2- VGA_TZOUT2+ <23> VGA_TZOUT2.8V@20mA TSVDD) 2 1 VREF 1 Back bias (BB) control Back Bias Disabled : GPIO_21_BB_EN = 0V BBP connect directly to VDDC +3.3V6M 2 2 2 0.8VS L44 2 U30B For M92-S2: DO NOT Install any Component in this Box.5 4 3 (1. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.3V H2SYNC V2SYNC +AVDD (1. 2009 1 18 of 53 .3V@65mA A2VDD) L50 2 1 BLM18PG121SN1D_0603 10U_0603_6.1VS (1.MB A4853 Document Number Rev A 401817 Sheet Monday.24> VGA_CRT_VSYNC <22. Compal Secret Data Security Classification 2009/07/01 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.3V6M 2 2 +DPLL_PVDD 1U_0402_6.1U_0402_10V6K D +1.8V@1mA A2VDDQ) +VDD1DI A2VDDQ 2 C +VDD1DI 1U_0402_6. Inc.8VS 1 C653 1 C654 1 @ R495 @R495 1M_0402_5% C655 2 2 2 10U_0603_6.8VS 1 TXCAP_DPA3P TXCAM_DPA3N DPA DPB SCL SDA R559 10K_0402_5% 1 2 AF2 AF4 TX0P_DPA2P TX0M_DPA2N AG3 AG5 TX1P_DPA1P TX1M_DPA1N AH3 AH1 LVDS CONTROL 1 @ R484 10K_0402_5% 2 R486 499_0402_1% AB11 AB12 VARY_BL DIGON VGA_ENVDD <23> TX2P_DPA0P TX2M_DPA0N AK3 AK1 TXCLK_UP_DPF3P TXCLK_UN_DPF3N AH20 AJ19 VGA_TZCLK+ VGA_TZCLK- VGA_TZCLK+ <23> VGA_TZCLK. September 28.3V6M 2 2 2 @ 0.0V GPIO_5_AC_BATT# 2 10K_0402_5% R480 1 <35> VGA_ENBKL <22> SOUT_GPIO8 <22> GPU_GPIO9 SOUT_GPIO8 GPU_GPIO9 GPU_GPIO11 GPU_GPIO12 GPU_GPIO13 <22> GPU_GPIO11 <22> GPU_GPIO12 <22> GPU_GPIO13 C <48> VGA_PWRSEL0 <16> 27M_SSC <22> THM_ALERT# @ 1 R481 @ 1 R482 <48> VGA_PWRSEL1 <20> BB_EN BB_EN 1 R483 VGA_PWRSEL0 2 0_0402_5% R_27M_SSC 2 10K_0402_5% GPU_CTF VGA_PWRSEL1 2 0_0402_5% GPU_GPIO21 CLKREQB <16> CLKREQB 10/24 Reference AMD REF136-1 <20> TESTEN +3.35.8VS DAC2 10U_0603_6.3V AL13 AJ13 VDD2DI VSS2DI AD19 AC19 1U_0402_6.1V 1 C658 1 C659 1 1 0 0.3V4Z 1 C648 C647 2 2 +A2VDD 1 C649 2 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.40. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.<23> TX3P_DPB2P TX3M_DPB2N AK6 AM5 TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N AH22 AJ21 VGA_TZOUT1+ VGA_TZOUT1- VGA_TZOUT1+ <23> VGA_TZOUT1.1U_0402_10V6K 2 715_0402_1% 2 BB_EN DDC/AUX VREFG R488 PLL/CLOCK 249_0402_1% 2 2 2 R485 10K_0402_5% @ CLKREQB 75_0402_1% 1 2 R489 +3.1U_0402_10V6K (1.1U_0402_10V6K B PADT35 PAD T35 PAD T36 PADT36 +3. INC.41. Date: 5 4 3 2 SCHEMATIC.3V4Z 2 MCK1608471YZF 0603 1 L52 1 27MCLK (1.7K_0402_5% 1 1 MUTI GFX AA1 1 2 R470 @ 150_0402_1% Y4 AC7 Y2 U5 U1 VRAM_ID0 Y7 <22> VRAM_ID0 VRAM_ID1 V2 <22> VRAM_ID1 VRAM_ID2 Y8 <22> VRAM_ID2 VRAM_ID3 V4 <22> VRAM_ID3 AB7 W1 AB8 W3 AB9 W5 AC6 +DPC_VDD18 W6 AD7 AA3 AC8 +DPC_VDD10 AA5 AE8 AA6 1 2 R471 @ 0_0402_5%AE9 AB4 AD9 AB2 AC10 AC5 +1.3V4Z 2 +1.3V4Z 2 @ MCK1608471YZF 0603 1 C628 1 +DPC_VDD18 1 C629 C630 @ 10U_0603_6.<23> TXCBP_DPB3P TXCBM_DPB3N AK5 AM3 TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N AL21 AK20 VGA_TZOUT0+ VGA_TZOUT0- VGA_TZOUT0+ <23> VGA_TZOUT0.8V@70mA AVDD) L46 2 1 BLM18PG121SN1D_0603 1 C634 1 +A2VDDQ C642 2 0.8V@120mA +DPLL_PVDD) 0.3V_DELAY R474 1 R476 R1 R3 <23> VGA_LCD_CLK <23> VGA_LCD_DATA VGA_PWRSEL1 1 @ 10K_0402_5% VGA_PWRSEL0 1 @ 10K_0402_5% R584 2 R477 2 +3.3V6M 2 2 2 @ 0.1U_0402_10V6K +3. INC.<23> TX5P_DPB0P TX5M_DPB0N AK8 AL7 TXOUT_U3P TXOUT_U3N AK24 AJ23 VGA_CRT_R 1 R472 VGA_CRT_G 1 R473 VGA_CRT_B 1 R475 2 150_0402_1% 2 150_0402_1% 2 150_0402_1% D LVTMDP DAC1 R AM26 RB AK26 VGA_CRT_R <24> TXCLK_LP_DPE3P TXCLK_LN_DPE3N AL15 AK14 VGA_TXCLK+ <23> VGA_TXCLK.1V@300mA +DPLL_VDDC) 4 1 1 27MHz_16PF_6P27000126 A @C656 @ C656 22P_0402_50V8J 2 @C657 @ C657 2 22P_0402_50V8J Close to M92 Issued Date Compal Electronics.3V_DELAY AC1 AC3 AD20 AC20 1 AC16 1 0.8V@120mA +DPLL_PVDD) L45 1 @ 1U_0402_6.7K_0402_5% VGA_LCD_DATA 2 4.95V 1 1 0.9V C660 10U_0603_6. 2 216-0728018 A12 M92-S2 XT FCBGA 0FA 1 GPIO24_TRSTB @ R494 1K_0402_5% +1.3V 1 R487 1 1U_0402_6.44> ACIN U6 U10 T10 U8 U7 T9 T8 T7 P10 P4 P2 N6 N5 N3 Y9 N1 M4 R6 W10 M2 P8 P7 N8 N7 T11 R11 GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16_SSIN GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB GPIO_29_DRM_0 GPIO_30_DRM_1 L6 L5 L3 L1 K4 AF24 JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO TESTEN AB13 W8 W9 W7 AD10 GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 AC14 HPD1 RSET AD22 AVDD AVSSQ AG24 AE22 VDD1DI VSS1DI AE23 AD23 R2 R2B AM12 AK12 G2 G2B AL11 AJ11 B2 B2B AK10 AL9 C Y COMP AH12 AM10 AJ9 1 R478 2 499_0402_1% +AVDD 216-0728018 A12 M92-S2 XT FCBGA 0FA +VDD1DI +1.1U_0402_10V6K C646 @ R493 10K_0402_5% 0.1U_0402_10V6K (1.3V 1 1U_0402_6.1U_0402_10V6K XTALOUT @Y4 @ Y4 VGA_PWRSEL_0 A VGA_PWRSEL_1 +1.<23> AH16 AJ15 VGA_TXOUT0+ <23> VGA_TXOUT0.3V_DELAY B U30F DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23 LCD VGA_LCD_CLK 2 4.3V4Z 2 MCK1608471YZF 0603 0 1.3V_DELAY GPIO_5_AC_BATT AC(Performance mode) = 3.1VS L53 1 1U_0402_6.3V4Z 1 C641 2 2 C639 2 0.3V_DELAY GPIO24_TRSTB T31 PAD T32 PAD T33 PAD T34 PAD TESTEN +1.3V Battery saving mode = 0.3V4Z 1 C635 2 2 1 L47 2 1 BLM18PG121SN1D_0603 1 C637 PADT28 PAD T28 PAD T30 PADT30 PAD T29 PADT29 HSYNC_DAC2 <22> VSYNC_DAC2 <22> A2VDD AE20 +A2VDD AE17 +A2VDDQ A2VSSQ AE19 R2SET AG13 L48 2 1 BLM18PG121SN1D_0603 1 C640 10U_0603_6.1U_0402_10V6K (1.<23> G GB AL25 AJ25 VGA_CRT_G <24> TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N B BB AH24 AG25 VGA_CRT_B <24> TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N AL17 AK16 VGA_TXOUT1+ <23> VGA_TXOUT1.<23> HSYNC VSYNC AH26 AJ27 VGA_CRT_HSYNC <22.8VS T4 T2 DPLUS DMINUS R5 AD17 AC17 TS_FDO TSVDD TSVSS <22> GPU_THERMAL_D+ <22> GPU_THERMAL_D- 1 1 100_0402_5% R491 @ 10K_0402_5% 2 AF14 AE14 1.

INC.3V4Z 1 10U_0603_6.0] BA[2.1U_0402_10V6K C684 10U_0603_6.. INC.1U_0402_10V6K 2 DP PLL POWER DPE_PVDD DPE_PVSS DPA_PVDD DPA_PVSS +DPA_PVDD AG8 AG7 +DPE_PVDD 1U_0402_6..8VS MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8 MAA_9 MAA_10 MAA_11 MAA_12 MAA_13/BA2 MAA_14/BA0 MAA_15/BA1 K17 J20 H23 G23 G24 H24 J19 K19 J14 K14 J11 J13 H11 G11 J16 L15 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 BA2 BA0 BA1 DQMA_0 DQMA_1 DQMA_2 DQMA_3 DQMA_4 DQMA_5 DQMA_6 DQMA_7 E32 E30 A21 C21 E13 D12 E3 F4 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 MVREFDA MVREFSA RDQSA_0 RDQSA_1 RDQSA_2 RDQSA_3 RDQSA_4 RDQSA_5 RDQSA_6 RDQSA_7 H28 C27 A23 E19 E15 D10 D6 G5 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 WDQSA_0 WDQSA_1 WDQSA_2 WDQSA_3 WDQSA_4 WDQSA_5 WDQSA_6 WDQSA_7 H27 A27 C23 C19 C15 E9 C5 H4 QSA#0 QSA#1 QSA#2 QSA#3 QSA#4 QSA#5 QSA#6 QSA#7 ODTA0 ODTA1 L18 K16 ODTA0 ODTA1 CLKA0 CLKA0B H26 H25 CLKA0 CLKA0# CLKA1 CLKA1B G9 H9 CLKA1 CLKA1# RASA0B RASA1B G22 G17 RASA#0 RASA#1 CASA0B CASA1B G19 G16 CASA#0 CASA#1 CSA0B_0 CSA0B_1 H22 J22 CSA0# CSA1B_0 CSA1B_1 G13 K13 CSA1# CKEA0 CKEA1 K20 J17 CKEA0 CKEA1 WEA#0 WEA#1 2 2 J25 K7 NC_MEM_CALRN0 NC_MEM_CALRN1 WEA0B WEA1B G25 H10 243_0402_1%1 R501 @ 243_0402_1%1 R502 2 2 J8 K25 MEM_CALRP1 NC_MEM_CALRP0 AB16 G14 G20 L10 RSVD#1 RSVD#2 RSVD#3 DRAM_RST K8 L7 CLKTESTA CLKTESTB 1 @ 243_0402_1%1 R499 @ 243_0402_1%1 R500 1 DP E/F POWER +DPE_VDD18 DP A/B POWER L54 1U_0402_6.8VS R496 1 2 2 0_0402_5% 1 DQMA#[7.3V4Z 2 1 BLM18PG121SN1D_0603 1 10U_0603_6. September 28.1U_0402_10V6K +1.0] <21> MDA[63. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.0] <21> +1.8V@20mA +DPE_PVDD) R498 150_0402_1% 1 2 (1.8VS (1..8V@200mA +DPE_VDD18) R505 4.8V@120mA +DPLL_PVDD) L61 1 CSA1# <21> @ CKEA0 <21> CKEA1 <21> 2 MCK1608471YZF 0603 @ @ 1 C682 1 C683 2 2 0.3V 2 +DPA_VDD18 1U_0402_6..7K_0402_5% +1. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.0] <21> 1U_0402_6.3V4Z CASA#0 <21> CASA#1 <21> 2 1 BLM18PG121SN1D_0603 1 1 1 C679 C680 C681 +1.8VS 1 (1.3V 2 C673 AG18 AF19 1 C674 1 C675 2 0..1U_0402_16V4Z 2 Issued Date Compal Electronics.8VS R497 150_0402_1% 1 2 (1.3V 2 2 2 C666 0.3V4Z @ 2 2 0. 2009 Sheet 1 19 of 53 .3V4Z 1 C664 D L55 2 1 BLM18PG121SN1D_0603 1 C665 10U_0603_6.1U_0402_10V6K B PAD T38 PAD T39 PAD T40 216-0728018 A12 M92-S2 XT FCBGA 0FA 2 +1.3V AG19 AF20 NC_DPF_PVDD NC_DPF_PVSS DPB_PVDD DPB_PVSS AG10 AG11 +DPB_PVDD C676 2 1 C677 2 1 2 2 1 BLM18PG121SN1D_0603 C678 0..8VS +DPE_PVDD L58 10U_0603_6.1U_0402_16V4Z R510 100_0402_1% A C689 0.1U_0402_10V6K +DPF_VDD18 2 0.1V@200mA +DPA_VDD10) +DPA_VDD10 AG20 AG21 DPE_VDD10#1 DPE_VDD10#2 DPA_VDD10#1 DPA_VDD10#2 AF6 AF7 AG14 AH14 AM14 AM16 AM18 DPE_VSSR#1 DPE_VSSR#2 DPE_VSSR#3 DPE_VSSR#4 DPE_VSSR#5 DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5 AE1 AE3 AG1 AG6 AH5 AF16 AG17 DPF_VDD18#1 DPF_VDD18#2 NC_DPB_VDD18#1 NC_DPB_VDD18#2 AF22 AG22 DPF_VDD10#1 DPF_VDD10#2 DPB_VDD10#1 DPB_VDD10#2 AF8 AF9 AF23 AG23 AM20 AM22 AM24 DPF_VSSR#1 DPF_VSSR#2 DPF_VSSR#3 DPF_VSSR#4 DPF_VSSR#5 DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5 AF10 AG9 AH8 AM6 AM8 AF17 DPEF_CALR DPAB_CALR AE10 1 1U_0402_6.0] 3 R509 100_0402_1% +VDD_MEM18_REFD +VDD_MEM18_REFS 1 1 C688 0.1U_0402_10V6K CLKA0 <21> CLKA0# <21> CLKA1 <21> CLKA1# <21> 216-0728018 A12 M92-S2 XT FCBGA 0FA +1.0] <21> 2 BA[2.7K_0402_5% 2 R504 4.8VS CSA0# <21> (1.8V@20mA +DPB_PVDD) RASA#0 <21> RASA#1 <21> L60 1U_0402_6.3V4Z 1 1 ODTA0 <21> ODTA1 <21> C +1..0] <21> U30C U30G MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63 D C +1.0] MAA[12.5 4 MAA[12.1V@170mA +DPF_VDD10) 10U_0603_6. Inc.1U_0402_10V6K 2 2 2 AG15 AG16 1 C669 +DPA_VDD18 +1.1U_0402_10V6K QSA#[7.3V +DPE_VDD18 +1.3V C661 1 C662 1 C663 1U_0402_6.1VS AE13 AF13 +DPF_VDD10 L57 2 1 BLM18PG121SN1D_0603 QSA[7. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.3V6M 2 WEA#0 <21> WEA#1 <21> 1 10U_0603_6.3V4Z 1 C667 C668 2 DPE_VDD18#1 DPE_VDD18#2 NC_DPA_VDD18#1 NC_DPA_VDD18#2 AE11 AF11 +DPF_VDD10 0.8VS Close to K26 Close to J26 2 R508 100_0402_1% 2 R507 100_0402_1% 1 B 1 MDA[63.MB A4853 Document Number Rev A 401817 Monday. Date: 5 4 3 2 SCHEMATIC.1VS (1. Compal Secret Data Security Classification 2 2 2 1 1 A 2009/07/01 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.3V4Z 1 (1.3V C670 2 1 C671 2 1 2 C672 0.0] <21> 2 1 @ L56 BLM18PG121SN1D_0603 10U_0603_6.8VS K27 J29 H30 H32 G29 F28 F32 F30 C30 F27 A28 C28 E27 G26 D26 F25 A25 C25 E25 D24 E23 F23 D22 F21 E21 D20 F19 A19 D18 F17 A17 C17 E17 D16 F15 A15 D14 F13 A13 C13 E11 A11 C11 F11 A9 C9 F9 D8 E7 A7 C7 F7 A5 E5 C3 E1 G7 G6 G1 G3 J6 J1 J3 J5 +VDD_MEM18_REFD K26 +VDD_MEM18_REFS J26 DQA_0 DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63 MEMORY INTERFACE +1. INC...8V@20mA +DPA_PVDD) 2 BLM18PG121SN1D_0603 L59 1U_0402_6.

3V 2 2 2 2 1U_0402_6.8VS AA11 AA12 Y11 Y12 POWER +VDDR4 VDDR5#1 VDDR5#2 VDDR5#3 VDDR5#4 L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22 C869 +VDDR5 I/O VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4 2 1U_0402_6.3V4Z 1U_0402_6.3V 10U_0603_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.1U_0402_10V6K C754 2N7002_SOT23-3 C755 0.1V@2000mA +PCIE_VDDC) C715 2 2 0.3V4Z 1 1 1 1 1 1 C856 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.1U_0402_10V6K A 2 +1.3V4Z 1U_0402_6.3V 1 ISOLATED CORE I/O 2 L67 1U_0402_6.8VS M11 M12 1 C720 SPV10 C752 C751 +VGA_BBP NC_SPV18 H8 BACK BIAS 1U_0402_6.1U_0402_10V6K 0.3V4Z 1U_0402_6.3V4Z 0.1U_0402_10V6K 1U_0402_6.3V4Z C867 C737 1U_0402_6.5 4 3 2 1 +1.3V4Z 2 2 2 2 2 10U_0603_6.3V4Z 1U_0402_6.3V 10U_0603_6.3V4Z C745 +1.3V4Z 1 1 + C724 330U_D2E_2.3V4Z 0.3V4Z C753 D 1 <18> BB_EN AA27 AB24 AB32 AC24 AC26 AC27 AD25 AD32 AE27 AF32 AG27 AH32 K28 K32 L27 M32 N25 N27 P25 P32 R27 T25 T32 U25 U27 V32 W25 W26 W27 Y25 Y32 M6 N11 N12 N13 N16 N18 N21 P6 P9 R12 R15 R17 R20 T13 T16 T18 T21 T6 U15 U17 U20 U3 U9 V13 V16 V18 V6 Y10 Y15 Y17 Y20 Y6 2 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V 1 1 C712 2 +VDDC_CT (1.3V VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17 C857 2 C710 1 C695 1 C694 1 C709 1 C848 1 2 2 2 10U_0603_6.3V4Z 1 1 1 1 +VGA_CORE C875 MEM CLK 10U_0603_6.3V4Z (1.3V4Z 1U_0402_6.3V4Z 1 1 C726 C725 1 LEVEL TRANSLATION 2 2 2 1U_0402_6.1VS C716 <18> TESTEN 2 1U_0402_6.3V4Z C714 AA20 AA21 AB20 AB21 C713 1 C855 1 C854 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 +VGA_CORE +VGA_CORE VSSRHA PLL 2 1 BLM18PG121SN1D_0603 1 10U_0603_6.1U_0402_10V6K AA17 AA18 AB17 AB18 @ 1 2 R5110_0402_5% U11 1 2 R512 0_0402_5% U12 V11 V12 VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4 2 2 2 2 2 2 0.1U_0402_10V6K 1U_0402_6.1U_0402_10V6K 10U_0603_6.3V4Z 1 VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8 C698 2 0.3V4Z 1U_0402_6. INC.8VS 4 2 1 BLM18PG121SN1D_0603 2 1 L72 1U_0402_6.1U_0402_10V6K 1U_0402_6.3V 1 C877 1 C747 1 SPVSS (+VGA_CORE@2000mA +VDDCI) 1U_0402_6.3V C735 1 C730 1 C729 1 C872 1 C873 2 1 C874 10U_0603_6.3V4Z 2 2 1U_0402_6.3V4Z C728 C727 1U_0402_6.3V4Z 0.3V4Z 1U_0402_6.3V4Z C717 +VDDRHA C738 L64 2 1 BLM18PG121SN1D_0603 VDDR4#1 VDDR4#2 VDDR4#3 VDDR4#4 VDDC#1 VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8 VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23 1U_0402_6.3V 10U_0603_6.3V 10U_0603_6.3V 2 1 L70 BLM18PG121SN1D_0603 2 1U_0402_6.3V4Z 1U_0402_6.1U_0402_10V6K 3 D S Q44 2 G +VDDR4 1 1 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 +VGA_BBP NC_MPV18 H7 J7 2 0.3V4Z 1U_0402_6.3V4Z 1 1 C871 +1.3V4Z 1 2 10U_0603_6.3V4Z 2 0.3V C749 C748 B 1 M13 M15 M16 M17 M18 M20 M21 N20 1 C719 1U_0402_6. INC.3V 10U_0603_6.3V4Z 0.8VS PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8 C696 2 10U_0603_6.3V 2 +VDDR5 1 C760 2N7002DW-T/R7_SOT363-6 Q42B C759 1 5 C758 R523 10K_0402_5% A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6 216-0728018 A12 M92-S2 XT FCBGA 0FA 2 G Q43 SI2301BDS_SOT23 Q42A 2N7002DW-T/R7_SOT363-6 1 2 BB_EN GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8 GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55 PCIE_VSS#1 PCIE_VSS#2 PCIE_VSS#3 PCIE_VSS#4 PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31 2 10U_0603_6.3V4Z 1U_0402_6.8V@500mA +PCIE_GDDR) 1 C845 1 C847 1 C706 1 C705 C690 C708 C693 C701 C879 C878 C700 C699 1 1 1 1U_0402_6.3V4Z 1U_0402_6.3V4Z 10U_0603_6.3V 1 1 2 L68 MCK2012221YZF 0805 C876 2 2 1U_0402_6.3V4Z 1U_0402_6. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.8VS C756 2 R522 S 3 1 1 6 GND#56 GND#57 GND#58 GND#59 GND#60 GND#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87 D Q41 2 0.1U_0402_10V6K C860 2 C743 2 10U_0603_6.3V4Z 1 AA15 N15 N17 R13 R16 R18 R21 T12 T15 T17 T20 U13 U16 U18 U21 V15 V17 V20 V21 Y13 Y16 Y18 Y21 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V 2 C853 1 C852 1 C851 1 PCIE H13 H16 H19 J10 J23 J24 J9 K10 K23 K24 K9 L11 L12 L13 L20 L21 L22 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z2 D +PCIE_GDDR 1 U30D 2 1 C692 1 C704 1 C691 1 C703 1 C702 1 S 1U_0402_6.3V4Z +3.3V4Z 1 1 1 1 1 1U_0402_6.3V_DELAY 216-0728018 A12 M92-S2 XT FCBGA 0FA VSS_MECH#1 VSS_MECH#2 VSS_MECH#3 A32 AM1 AM32 GND C B 3 D 1 +3VS SI2301BDS_SOT23 2 G R520 100K_0402_5% +5VS 1 L71 2 1 BLM18PG121SN1D_0603 1 100K_0402_5% 2 10U_0603_6. INC. Compal Secret Data Security Classification 2009/07/01 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V C 1 C850 C849 1 C844 1 C843 1 C846 1U_0402_6.3V4Z +3.3V L69 1 2 MCK1608471YZF 0603 AM30 C697 +PCIE_PVDD 1 C742 C741 1U_0402_6.8VS (1. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. Date: 5 4 3 2 SCHEMATIC.3V4Z 10U_0603_6. 2009 Sheet 1 20 of 53 .3V4Z 1 1 2 2 10U_0603_6.MB A4853 Document Number Rev A 401817 Monday.3V @ A 2 C736 1 C734 1 C733 1 C732 1 C731 1 C864 2 2 1U_0402_6.3V4Z 1U_0402_6.3V 1 10U_0603_6.3V 2 1 BLM18PG121SN1D_0603 1 1 C859 L63 PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8 PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12 AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26 C858 +1.1U_0402_10V6K PCIE_PVDD L8 1 C744 2 1 +SPV10 C750 2 10U_0603_6.1U_0402_10V6K Issued Date Compal Electronics.3V4Z 1U_0402_6.3V4Z 1 1 1U_0402_6.8V@2200mA) 1U_0402_6. Inc.3V4Z U30E +1.3V4Z 2 1 C841 1 C842 1 MEM I/O C707 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z CORE +1.8VS L62 1 2 MCK2012221YZF 0805 1 (1. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.1U_0402_10V6K 0.8VS L17 2 (+VGA_CORE@9000mA +VDDC) C868 1U_0402_6.5VM_R9 C863 1 C862 1 C861 1 C723 1 C722 1 1U_0402_6.3V 2 1 2 0.3V4Z 1U_0402_6.3V_DELAY 10U_0603_6.1U_0402_10V6K 1U_0402_6.3V4Z 1 1 2 R521 150K_0402_5% C757 3 +3VS +1.3V4Z C721 1 2 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 C865 1 C866 1 C746 2 1 2 2 1U_0402_6.3V4Z 1U_0402_6.8V@110mA +VDDC_CT) C711 10U_0603_6.3V4Z 1U_0402_6. September 28.3V4Z 1U_0402_6.3V 1 +VDDCI 2 BBP#1 BBP#2 2 1U_0402_6.3V4Z C870 VDDRHA L16 2 C718 2 +1.

0] <19> QSA#[7.3V4Z QSA7 QSA#7 QSA6 QSA#6 +VRAM_REF4 BA2 HYB18T256161BF-25 VRAM@ +1.99K_0402_1% 1 1 1 1 <19> QSA[7.. INC.99K_0402_1% 2 R524 4.99K_0402_1% R525 4.1U_0402_16V4Z 1 +1. 2009 Sheet 1 21 of 53 A .3V4Z 1 CLKA0# <19> CLKA0# R533 56_0402_5% 2 +1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.3V4Z 0. INC.3V6M 1 1 C780 2 C781 1 C782 2 2 10U_0603_6.0] 1 1 1 1 R528 4.3V4Z QSA3 QSA#3 QSA0 QSA#0 K9 F7 E8 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 VDD1 VDD2 VDD3 VDD4 VDD5 A1 E1 J9 M9 R1 VDDL VSSDL J1 J7 U33 Group0 Group3 +1.1U_0402_16V4Z 1 C803 2 1 C804 2 0.8VS 1 ODTA1 C766 2 1U_0402_6.0] +1.99K_0402_1% C771 0..8VS ODTA1 K9 ODT QSA4 QSA#4 F7 E8 LDQS LDQS QSA5 QSA#5 B7 A8 UDQS UDQS +VRAM_REF3 J2 VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 VDD1 VDD2 VDD3 VDD4 VDD5 A1 E1 J9 M9 R1 VDDL VSSDL J1 J7 Group5 Group4 +1.1U_0402_16V4Z 2 WEA#0 <19> WEA#0 CSA1# <19> CSA1# CASA#0 <19> CASA#0 WEA#1 <19> WEA#1 RASA#0 <19> RASA#0 CASA#1 <19> CASA#1 CKEA0 <19> CKEA0 RASA#1 <19> RASA#1 ODTA0 <19> ODTA0 CKEA1 <19> CKEA1 C772 0..0] 2 2 2 +VRAM_REF1 QSA#[7.8VS CLKA0 <19> CLKA0 CLKA1# <19> CLKA1# 10U_0603_6.3V4Z C HYB18T256161BF-25 VRAM@ BA[2.1U_0402_16V4Z 1 VREF VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VSS1 VSS2 VSS3 VSS4 VSS5 A3 E3 J3 N1 P9 NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8 L2 L3 BA0 BA1 MAA12 MAA11 MAA10 MAA9 MAA8 MAA7 MAA6 MAA5 MAA4 MAA3 MAA2 MAA1 MAA0 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CLKA1# K8 CLKA1 J8 K2 CKE CSA1# L8 CS WEA#1 K3 WE RASA#1 K7 RAS CASA#1 L7 CAS DQMA#4 F3 DQMA#5 B3 LDM UDM +1.1U_0402_16V4Z 1 C783 2 0.1U_0402_16V4Z 0.3V6M 1 C799 1 C800 2 0.1U_0402_16V4Z 1 R531 4.1U_0402_16V4Z 2009/07/01 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. September 28.8VS ODT LDQS LDQS BA0 BA1 ODTA0 C762 2 1U_0402_6.8VS +1.0] <19> BA[2.1U_0402_16V4Z 1 2 2 C775 1 2 C774 0.1U_0402_16V4Z 2 Issued Date Compal Electronics. INC.3V4Z 0.0] +VRAM_REF2 B 1 DQMA#[7.1U_0402_16V4Z 1 C792 2 1 C793 2 1 C794 2 1 1 C796 2 2 2 1 C797 470P_0402_50V7K C798 470P_0402_50V7K 2 10U_0603_6.0] <19> MAA[12.01U_0402_16V7K 1 C795 2 R534 56_0402_5% C806 10U_0603_6.5 4 3 U31 D L2 L3 BA0 BA1 MAA12 MAA11 MAA10 MAA9 MAA8 MAA7 MAA6 MAA5 MAA4 MAA3 MAA2 MAA1 MAA0 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CKEA0 CSA0# WEA#0 CK CK K2 CKE L8 CS K3 WE RASA#0 K7 RAS CASA#0 L7 CAS DQMA#1 F3 DQMA#2 B3 LDM UDM ODTA0 QSA1 QSA#1 C QSA2 QSA#2 K9 F7 E8 B7 A8 +VRAM_REF1 J2 A2 E2 L1 R3 R7 R8 BA2 1 U32 BA0 BA1 CLKA0# K8 CLKA0 J8 2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 VDD1 VDD2 VDD3 VDD4 VDD5 A1 E1 J9 M9 R1 VDDL VSSDL J1 J7 MDA20 MDA21 MDA17 MDA23 MDA22 MDA19 MDA16 MDA18 MDA8 MDA10 MDA9 MDA15 MDA11 MDA12 MDA13 MDA14 Group2 Group1 UDQS UDQS VREF VSS1 VSS2 VSS3 VSS4 VSS5 A3 E3 J3 N1 P9 NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8 MAA12 MAA11 MAA10 MAA9 MAA8 MAA7 MAA6 MAA5 MAA4 MAA3 MAA2 MAA1 MAA0 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0.01U_0402_16V7K 1 C805 0.1U_0402_16V4Z R532 56_0402_5% 1U_0402_6.8VS 0.0] R527 4..3V4Z HYB18T256161BF-25 VRAM@ +1.1U_0402_16V4Z 2 R530 4.01U_0402_16V7K 1 C786 2 1 C787 2 1 C788 2 2 0.8VS 2 C778 2 0.1U_0402_16V4Z 1 1 C773 1 1 10U_0603_6.1U_0402_16V4Z 1 CK CK K2 CKE CSA0# L8 CS WEA#0 K3 WE RASA#0 2 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 BA0 BA1 CKEA0 K7 RAS CASA#0 L7 CAS DQMA#3 DQMA#0 F3 B3 LDM UDM +1..8VS QSA[7.3V6M 1 1U_0402_6.99K_0402_1% +VRAM_REF3 +VRAM_REF4 2 2 2 C770 0. Compal Secret Data Security Classification 2 0.0] CSA0# <19> CSA0# +1.1U_0402_16V4Z 2 B ODTA1 <19> ODTA1 2 C769 0.99K_0402_1% 1 MDA[63.8VS BA0 BA1 L2 L3 BA0 BA1 MAA12 MAA11 MAA10 MAA9 MAA8 MAA7 MAA6 MAA5 MAA4 MAA3 MAA2 MAA1 MAA0 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CLKA1# CLKA1 K8 J8 CK CK K2 CKE CKEA1 CSA1# L8 CS WEA#1 K3 WE RASA#1 K7 RAS CASA#1 L7 CAS F3 B3 LDM UDM K9 ODT F7 E8 LDQS LDQS B7 A8 UDQS UDQS J2 VREF A2 E2 L1 R3 R7 R8 NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8 DQMA#7 DQMA#6 0.8VS 0..3V6M 1U_0402_6.3V6M 1 2 +1.3V6M 1U_0402_6.8VS C789 10U_0603_6.1U_0402_16V4Z 1 C801 2 1 C802 2 0.1U_0402_16V4Z 0..01U_0402_16V7K 1 C779 2 10U_0603_6.0] <19> DQMA#[7. Date: 5 R535 56_0402_5% 0.3V4Z CLKA1 <19> CLKA1 1 2 C777 1 1 2 C776 0.3V6M 0..8VS 1 C761 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 L2 L3 CLKA0# K8 CLKA0 J8 +1.8VS 4 3 2 SCHEMATIC. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.99K_0402_1% 1 MAA[12.1U_0402_16V4Z 0..8VS DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 VDD1 VDD2 VDD3 VDD4 VDD5 A1 E1 J9 M9 R1 VDDL VSSDL J1 J7 MDA48 MDA53 MDA49 MDA55 MDA52 MDA50 MDA54 MDA51 MDA60 MDA61 MDA56 MDA62 MDA58 MDA57 MDA59 MDA63 Group6 D Group7 +1.8VS CK CK 1 C764 U34 BA0 BA1 CKEA1 C763 LDQS LDQS +VRAM_REF2 J2 HYB18T256161BF-25 VRAM@ VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 MDA5 MDA4 MDA6 MDA3 MDA0 MDA7 MDA2 MDA1 MDA30 MDA26 MDA29 MDA25 MDA24 MDA28 MDA27 MDA31 2 UDQS UDQS A2 E2 L1 R3 R7 R8 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 ODT B7 A8 BA2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VSS1 VSS2 VSS3 VSS4 VSS5 A3 E3 J3 N1 P9 C765 2 1U_0402_6. Inc.0] <19> MDA[63.3V6M A 1 +1.1U_0402_16V4Z 10U_0603_6...99K_0402_1% 2 R529 4..1U_0402_16V4Z 1 C784 1 C785 2 2 0.1U_0402_16V4Z 2 C790 2 0.MB A4853 Document Number Rev A 401817 Monday.8VS 1 C767 C768 2 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VSS1 VSS2 VSS3 VSS4 VSS5 A3 E3 J3 N1 P9 2 1U_0402_6.1U_0402_16V4Z 1 C791 2 0. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.0] R526 4.1U_0402_16V4Z 1 2 A2 E2 L1 R3 R7 R8 BA2 MDA45 MDA42 MDA47 MDA41 MDA40 MDA46 MDA44 MDA43 MDA34 MDA35 MDA37 MDA36 MDA33 MDA39 MDA32 MDA38 +1.

8VS 10K_0402_5% 2 R589 @ 1 10K_0402_5% 2 R553 @ 1 +1.8V SA00002DL10 512MB(x4) Hynix 64Mx16 1.3V_DELAY GPIO_22_ROMCSB ROMIDCFG(2:0) GPIO[13:11] 1 VIP_DEVICE_STRAP_ENA SMS_EN_HARD 1 2 R548 10K_0402_5% BIF_RX_PLL_CALIB_BP V2SYNC H2SYNC CCBYPASS 2 2 SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT GENERICC 1 AUD[1] HSYNC 0 AUD[0] VSYNC AUD[1] AUD[0] 0 0 No audio function 0 1 Audio for DisplayPort and HDMI if dongle is detected 1 0 Audio for DisplayPort only 1 1 Audio for both DisplayPort and HDMI 4 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED.7K_0402_5% STRAPS PIN GPU Change to SA007810210 M92 S2-XT Address 1001 101X b 2 R551 @ 1 +1.8VS 10K_0402_5% 2 R590 @ 1 10K_0402_5% VRAM_ID0 <18> 2 R591 @ 1 10K_0402_5% VRAM_ID[3:0] Project VRAM size Vendor Part Number# Compal Part Number# 256MB(x4) Hynix 32Mx16 1.2.1. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.8V SA00002UH20 1000 0001 512MB(x4) ATI 64Mx16 1.5 4 3 2 1 CONFIGURATION STRAPS STRAPS ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED.35> Q45A 2N7002DW-T/R7_SOT363-6 3 EC_SMB_DA2_PX 0 5 6 0 IGNORE VIP DEVICE STRAPS +3.24> VGA_CRT_HSYNC <18> VSYNC_DAC2 <18> HSYNC_DAC2 2 2 2 2 1 1 1 1 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% @ R540 R541 @ R542 @ R543 2 2 2 2 1 1 1 1 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% @ R544 @ R545 @ R546 @ R547 2 2 2 2 1 1 1 1 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% D VSYNC_DAC1 and HSYNC_DAC1 pull up to HDMI & DISPLAYPORT AUDIO funciton BIF_VGA DIS 0 0 BIF_RX_PLL_CALIB_BP GPIO21 GPIO5_AC_BATT TEST BIOS_ROM_EN +3.2. September 28.0) 2 R554 @ 1 +1. Compal Secret Data Security Classification 2009/07/01 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.8V (E-die) SA000031O10 0100 DVPDATA (3. INC. THEY MUST NOT CONFLICT DURING RESET GENERICC H2SYNC PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED.3V_DELAY DESCRIPTION OF DEFAULT SETTINGS RECOMMENDED SETTINGS TX_PWRS_ENB GPIO0 PIN PCIE FULL TX OUTPUT SWING 1 TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 1 BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 1 BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0 GPIO9 VGA ENABLED STRAPS <18> <18> <18> <18> <18> <18> <18> <18> D GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 SOUT_GPIO8 GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 SOUT_GPIO8 R536 R537 R538 @ R539 GPU_GPIO9 GPU_GPIO11 GPU_GPIO12 GPU_GPIO13 GPU_GPIO9 GPU_GPIO11 GPU_GPIO12 GPU_GPIO13 9/1 For PVT <18.3V_DELAY EC_SMB_CK2_PX 0 0 1 ENABLE EXTERNAL BIOS ROM R549 10K_0402_5% C 1 4 3 2 SCHEMATIC. INC.0 VRAM_ID1 <18> VRAM_ID2 <18> A GPIO21_BB_EN Closed to GPU U35 <18> GPU_THERMAL_D+ C AMD RESERVED CONFIGURATION STRAPS EC_SMB_DA2 <4.8VS 10K_0402_5% 2 R592 @ 1 10K_0402_5% VRAM_ID3 <18> A Issued Date Compal Electronics. THEY MUST NOT CONFLICT DURING RESET +3.24> VGA_CRT_VSYNC <18.1.1U_0402_16V4Z GPIO_28_TDO 2 B C808 1 1 2200P_0402_50V7K 2 <18> GPU_THERMAL_D- 1 VCC SMBCLK 8 EC_SMB_CK2_PX 2 DXP SMBDATA 7 EC_SMB_DA2_PX 3 DXN ALERT 6 4 THERM GND 5 THM_ALERT# <18> +3.35> Q45B 2N7002DW-T/R7_SOT363-6 VGA Thermal Sensor XX EC_SMB_CK2 <4.3V_DELAY C807 0.MB A4853 Document Number Rev A 401817 Monday. Inc. INC.8VS 10K_0402_5% 2 R552 @ 1 +1. THEY MUST NOT CONFLICT DURING RESET +3.8V SA00003LT10 0010 512MB(x4) Samsung 64Mx16 1.3V_DELAY VRAM_ID0=VRAM_ID0_0 VRAM_ID1=VRAM_ID1_1 VRAM_ID2=VRAM_ID2_2 VRAM_ID3=VRAM_ID3_3 B 1 R550 G781-1_SOP8 2 4. 2009 Sheet 1 22 of 53 . THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. Date: 5 VRAM_ID 3.

JLVDS1 +INVPWR_B+ +3VS <18> VGA_LCD_CLK <18> VGA_LCD_DATA <18> VGA_TZOUT0<18> VGA_TZOUT0+ <18> VGA_TZOUT1+ <18> VGA_TZOUT1<18> VGA_TZOUT2+ <18> VGA_TZOUT2<18> VGA_TZCLK<18> VGA_TZCLK+ <27> USB20_N3 <27> USB20_P3 VGA_LCD_CLK VGA_LCD_DATA VGA_TZOUT0VGA_TZOUT0+ VGA_TZOUT1+ VGA_TZOUT1VGA_TZOUT2+ VGA_TZOUT2VGA_TZCLKVGA_TZCLK+ 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 GND 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 GND 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 DAC_BRIG 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 DAC_BRIG <35> INVTPWM R410 1 DISPOFF# 2 0_0402_5% INVT_PWM <35> +LCDVDD W=60mils VGA_TXOUT0VGA_TXOUT0+ +LCDVDD VGA_TXOUT0.<18> VGA_TXCLK+ <18> +3VS ACES_88242-4001 CONN@ A A 2009/07/01 Issued Date Compal Electronics. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. 2009 1 23 of 53 .1U_0402_16V4Z VGA_TXCLK.<18> VGA_TXCLKVGA_TXCLK+ 2 1 C492 10U_0805_10V4Z 2 C488 0. Conn.5 4 3 2 1 LCD POWER CIRCUIT D D +LCDVDD +3VS +3V 1 W=60mils 1 R415 300_0603_5% 1 3 2 R414 100K_0402_5% 2 3 Q36A 1 2 2 Q37 AO3413_SOT23-3 2 1 1 1K_0402_5% 1 C491 6 4 2 R413 G 5 W=60mils 1 1 1 +LCDVDD 0. INC.1U_0402_16V4Z 2 2 R407 @ 100K_0402_5% C C 1 +3VS BKOFF# <35> BKOFF# R411 @ 4.7U_0805_10V4Z 2 C493 0. INC.047U_0402_16V7K 2 2N7002DW-T/R7_SOT363-6 0_0402_5% D 2N7002DW-T/R7_SOT363-6 R408 4. Rev A 401817 Date: 5 4 3 2 Sheet Monday. INC.7U_0805_10V4Z S Q36B <18> VGA_ENVDD C495 2 1 C494 4.7K_0402_5% 2 R613 0_0402_5% 1 2 D20 1 @ DISPOFF# 2 CH751H-40PT_SOD323-2 +INVPWR_B+ PVT2 for 8/24 L24 2 1 FBMA-L11-201209-221LMA30T_0805 W=40mils B+ DAC_BRIG L23 2 1 FBMA-L11-201209-221LMA30T_0805 C489 1 1 INVTPWM C490 DISPOFF# 1 C484 1 C486 1 C487 2 2 2 220P_0402_50V7K 220P_0402_50V7K 220P_0402_50V7K 680P_0402_50V7K 68P_0402_50V8J 2 2 B B LCD/PANEL BD. Compal Secret Data Security Classification 2010/07/01 Deciphered Date Title SCHEMATIC.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. Inc. September 28.<18> VGA_TXOUT0+ <18> VGA_TXOUT1VGA_TXOUT1+ VGA_TXOUT1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.<18> VGA_TXOUT1+ <18> VGA_TXOUT2+ VGA_TXOUT2- 1 VGA_TXOUT2+ <18> VGA_TXOUT2.

2K_0402_5% 1 1 +3.22> VGA_CRT_HSYNC R47 1 2 R40 5 2 0.2K_0402_5% 2 R50 2. INC.3P_0402_50V8J 3. Date: A B C D SCHEMATIC. September 28. INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_16V4Z 2 3 2 3 2 3 2 RB491D_SC59-3 +3VS L42 VGA_CRT_G <18> VGA_CRT_G L31 R464 L30 1 1 <18> VGA_CRT_B 1 VGA_CRT_B R443 R442 C547 1 C534 1 C532 CRT_R_1 2 FCM2012C-800_0805 L41 1 CRT_G_1 2 FCM2012C-800_0805 L40 1 CRT_B_1 2 FCM2012C-800_0805 1 1 C546 1 1 C535 L39 C533 2 FCM2012C-800_0805 CRT_R_2 1 2 FCM2012C-800_0805 CRT_G_2 1 2 FCM2012C-800_0805 CRT_B_2 1 1 C560 1 C559 1 @ 2 2 2 150_0402_1% 150_0402_1% 150_0402_1% 2 2 2 3.3P_0402_50V8J 3.3P_0402_50V8J 2 2 2 8P_0402_50V8J 8P_0402_50V8J 8P_0402_50V8J C558 1 @ @ 2 8P_0402_50V8J JCRT1 2 2 8P_0402_50V8J 8P_0402_50V8J C557 Change 3.MB A4853 Document Number Rev A 401817 Sheet Monday.1U_0402_16V4Z P 1 R30 1 2 0_0402_5% CRT_VSYNC 2 A U3 Y 4 CRT_VSYNC_1 G <18.3V_DELAY VGA_CRT_CLK <18> Q4 2N7002_SOT23 4 4 2009/07/01 Issued Date Compal Electronics.1U_0402_16V4Z OE# C88 1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 2 VGA_CRT_R <18> VGA_CRT_R 1 2 74AHCT1G125GW_SOT353-5 1 1 W=40mils 2 C62 +CRT_VCC 68P_0402_50V8J 5 2 0. INC.1A_6VDC_FUSE 1 C12 0.22> VGA_CRT_VSYNC OE# C75 1 +CRT_VCC 3 For HM51 74AHCT1G125GW_SOT353-5 +CRT_VCC For HM51 +3. Inc.A B C D D27 D26 E W=40mils D25 +5VS +R_CRT_VCC +CRT_VCC D4 1 1 CRT Connector 1 DAN217_SC59 DAN217_SC59 DAN217_SC59 F1 2 1 1 2 1. Compal Secret Data Security Classification 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.3p For M92 Change 8p For M92 +CRT_VCC P 2 1 0_0402_5% 2 CRT_HSYNC 2 A 1 L4 2 0_0603_5% 1 L3 2 0_0603_5% CRT_HSYNC_2 3 1 1 10K_0402_5% Y R463 100K_0402_5% 1 DDCCLK C101 2 68P_0402_50V8J 1 CRT_HSYNC_1 4 CRT_DET# <27> DDCDATA U4 16 17 SUYIN_070549FR015S208CR CONN@ 2 100P_0402_50V8J CRT_VSYNC_2 1 1 C76 C89 @ @ 10P_0402_50V8J 10P_0402_50V8J 2 2 For HM51 G <18. 2009 E 24 of 53 .3V_DELAY Place closed to chipset 2 3 3 VGA_CRT_DATA <18> 1 3 D S 2 G Q6 2N7002_SOT23 DDCCLK 1 1 2 2 G 1 D For HM51 R582 10K_0402_5% S DDCDATA 2 3 R581 10K_0402_5% R29 2. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.

INC. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. Date: 5 4 3 2 SCHEMATIC. 2009 Sheet 1 25 of 53 . AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.2K_1206_8P4R_5% +3VS RP29 1 2 3 4 PCI_PIRQG# PCI_PIRQE# PCI_REQ#0 PCI_PIRQH# 8 7 6 5 8.MB A4853 Document Number Rev A 401817 Monday.2K_1206_8P4R_5% RP31 C 1 2 3 4 PCI_PIRQF# PCI_SERR# PCI_PIRQA# PCI_PIRQC# 8 7 6 5 8.5 4 3 2 1 DMI for ESI-compatible operation +3VS PCI_GNT#1 RP4 PCI_DEVSEL# PCI_FRAME# PCI_REQ#1 PCI_REQ#2 8 7 6 5 D U11B D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3 RP20 1 2 3 4 PCI_PLOCK# PCI_IRDY# PCI_PERR# PCI_PIRQB# 8 7 6 5 8. Inc. INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.2K_1206_8P4R_5% RP11 1 2 3 4 PCI_STOP# PCI_PIRQD# PCI_REQ#3 PCI_TRDY# 8 7 6 5 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# 8. September 28.2K_1206_8P4R_5% PLT_RST# CLK_PCI_ICH R132 10_0402_5% @ PLT_RST# <8.35> CLK_PCI_ICH <16> C 1 1 2 3 4 D Low= DMI for ESI-compatible operation High= Default* (Internal pull-up) C194 10P_0402_50V8J @ Interrupt I/F PIRQA# PIRQB# PIRQC# PIRQD# ICH9-M ES_FCBGA676 2 PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# H4 K6 F2 G2 PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 1 A16 Swap Override Strap Low= A16 swap override Enable High= Default* PCI_GNT#3 R123 2 1K_0402_5% PCI_GNT#3 @ 1 B B R614 1 0_0402_5% 2 1 PCI 1 1 LPC* R124 1 2 1K_0402_5% PCI_GNT#0 @ R131 1 2 1K_0402_5% @ 2 0 PVT2 8/24 +3VS @ U41 2 B 1 Y A NC7SZ08P5X_NL_SC70-5 SPI_CS#1 <27> 2 R579 @ 4 1 100_0402_5% PLTRST_VGA# <17> For M92 1 1 R83 100K_0402_5% @ 5 SPI PLT_RST_BUF# <33> P 1 4 3 NC7SZ08P5X_NL_SC70-5 0 P Y A 1 Boot BIOS Loaction G SPI_CS#1 @ U8 2 B 3 PCI_GNT#0 PLT_RST# G Boot BIOS Strap 5 +3VS @ R580 100K_0402_5% A 2 A Pre-MP 9/17 Compal Electronics.17.2K_1206_8P4R_5% J5 E1 J6 C4 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI F1 G4 B6 A7 F13 F12 E6 F6 PCI_REQ#0 PCI_GNT#0 PCI_REQ#1 PCI_GNT#1 PCI_REQ#2 PCI_GNT#2 PCI_REQ#3 PCI_GNT#3 C/BE0# C/BE1# C/BE2# C/BE3# D8 B4 D6 A5 PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# D3 E3 R1 C6 E4 C2 J4 A4 F5 D7 PCI_IRDY# PCI_PAR PLTRST# PCICLK PME# C14 D4 R2 REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME# @ PAD T12 @ PAD T9 @ @ @ @ PAD PAD PAD PAD T11 T15 T13 T14 @ PAD T16 Remove PCIRST# For HM51 Place closely pin B10 CLK_PCI_ICH 2 8. INC.31. Compal Secret Data Security Classification 2009/07/01 Issued Date Deciphered Date 2010/07/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.

INC.8.9_0402_1% BAS40-04_SOT23-3 1 1 C307 1 C306 +3VS EC_KBRST# <35> 2 SATA_ITX_DRX_N0 +1.05VS ICH_RTCX1 X1 IHDA R113 R130 10M_0402_5% 2 1 1 C164 15P_0402_50V8J 2 1 C Q12 2 B E 2SC2411K_SOT23 @ 3 close Con.1U_0402_16V4Z B SATA_ITX_C_DRX_N0 <29> SATA_ITX_C_DRX_P0 <29> SATA_ITX_C_DRX_N1_15 <29> MAINPWON <42.8> 1 56_0402_5% +1.5VS_PCIE_ICH R129 GLAN_COMP 2 24. INC.43> 15 ODD SATA_ITX_C_DRX_P1_15 <29> +1. sdie H_THERMTRIP# A A +VCC_HDA_ICH ICH_TP3 <27> Compal Electronics. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.01U_0402_16V7K SATA_ITX_C_DRX_P1_15 2 0.9_0402_1% HDA_BITCLK_ICH 1 SATA_LED# HDA_SYNC_ICH C HDA_RST_ICH# +3V 1 <38> HDA_SDIN0 @ R117 HDA_SDOUT_ICH 10K_0402_5% HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 AG5 HDA_SDOUT AG8 SATALED# <29> SATA_DTX_C_IRX_N0 <29> SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 SATA_ITX_DRX_N0 SATA_ITX_DRX_P0 AJ16 AH16 AF17 AG17 SATA0RXN SATA0RXP SATA0TXN SATA0TXP <29> SATA_DTX_C_IRX_N1 <29> SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 SATA_ITX_DRX_N1 SATA_ITX_DRX_P1 AH13 AJ13 AG14 AF14 SATA1RXN SATA1RXP SATA1TXN SATA1TXP 2 1 2 AF4 AG4 AH3 AE5 HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 10K_0402_5% FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 K5 K4 L6 K2 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 FWH4/LFRAME# K3 LPC_FRAME# LDRQ0# LDRQ1#/GPIO23 J3 J1 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 D <35> <35> <35> <35> LPC_FRAME# <35> R169 2 A20GATE A20M# N7 AJ27 EC_GA20 H_A20M# DPRSTP# DPSLP# AJ25 AE23 DPRSTP# R207 1 DPSLP# R210 1 FERR# AJ26 FERR# CPUPWRGD AD22 H_PWRGOOD IGNNE# AF25 H_IGNNE# INIT# INTR RCIN# AE22 AG25 L3 H_INIT# H_INTR EC_KBRST# NMI SMI# AF23 AF24 H_NMI H_SMI# STPCLK# AH27 H_STPCLK# THRMTRIP# AG26 THRMTRIP_ICH# TP12 AG27 SATA4RXN SATA4RXP SATA4TXN SATA4TXP AH11 AJ11 AG12 AF12 SATA5RXN SATA5RXP SATA5TXN SATA5TXP AH9 AJ9 AE10 AF10 SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS AH18 AJ18 AJ7 AH7 HDA_RST# AG7 AE8 <36> SATA_LED# 15 HDD R118 AE7 SATA_LED# PROJECT_ID2 1 10K_0402_5% EC_GA20 <35> H_A20M# <4> 0_0402_5% H_DPRSTP# 0_0402_5% H_DPSLP# 2 2 1 R206 +3VS H_DPRSTP# <5. Inc. 2009 Sheet 1 26 of 53 .768KHZ_12.01U_0402_16V7K SATA_ITX_C_DRX_P0 2 0.05VS R203 @ 330_0402_5% 1 2 1 4 IN LPC OUT NC CPU NC 2 RTC SM_INTRUDER# 3 SATA 2 32.01U_0402_16V7K 1 C397 1 C398 SATA_ITX_C_DRX_N1_15 2 0.01U_0402_16V7K H_THERMTRIP# <4. September 28. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. INC. Compal Secret Data Security Classification R92 1K_0402_5% @ R248 1K_0402_5% @ 2009/07/01 Issued Date Deciphered Date 2010/07/01 Title SCHEMATIC.47> H_DPSLP# <5> H_FERR# 2 56_0402_5% H_FERR# <4> H_PWRGOOD <5> <38> HDA_BITCLK_AUDIO <38> HDA_SYNC_AUDIO <38> HDA_RST_AUDIO# <38> HDA_SDOUT_AUDIO 1 R242 1 R251 1 R241 1 R247 HDA_BITCLK_ICH 2 33_0402_5% HDA_SYNC_ICH 2 33_0402_5% HDA_RST_ICH# 2 33_0402_5% HDA_SDOUT_ICH 2 33_0402_5% 2 R230 1 56_0402_5% 2 R146 1 10K_0402_5% H_INIT# <4> H_INTR <4> H_NMI <4> H_SMI# <4> C H_STPCLK# <4> R205 1 2 54.5 4 3 2 1 Pre-MP 9/17 +RTCVCC 1 +RTCVCC 1 R89 20K_0402_5% +RTCVCC 1 2 R90 20K_0402_5% 2 R112 332K_0402_1% ICH_INTVRMEN 1 2 J1 @ 10K_0603_5% C129 1U_0603_10V6K 1 2 C23 C24 RTCX1 RTCX2 ICH_RTCRST# ICH_SRTCRST# SM_INTRUDER# A25 F20 C22 RTCRST# SRTCRST# INTRUDER# ICH_INTVRMEN B22 A22 INTVRMEN LAN100_SLP E25 GLAN_CLK C13 LAN_RSTSYNC F14 G13 D14 LAN_RXD0 LAN_RXD1 LAN_RXD2 D13 D12 E13 LAN_TXD_0 LAN_TXD_1 LAN_TXD_2 B10 GPIO56 B28 B27 GLAN_COMPI GLAN_COMPO AF6 AH4 HDA_BIT_CLK HDA_SYNC 1 2 J2 @ 10K_0603_5% C136 1U_0603_10V6K 1 2 1 +3VS R214 PROJECT_ID2 10K_0402_5% 2 +1.5P_MC-306 H_DPRSTP# R231 H_DPSLP# R233 LAN / GLAN 1M_0402_5% +1.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.05VS +RTCBATT Remove 17 HDD For HM51 R382 1K_0402_5% D19 CLK_PCIE_SATA# CLK_PCIE_SATA SATARBIAS CLK_PCIE_SATA# <16> CLK_PCIE_SATA <16> R215 1 +RTCVCC 2 24. HDA_SDOUT_ICH 5 Rev A 401817 Date: 4 3 2 Monday.05VS H_IGNNE# <4> ICH9-M ES_FCBGA676 B 56_0402_5% U11A ICH_RTCX2 2 56_0402_5% 2 +RTCVCC 1 @ 1 1 D @ 2 2 C163 15P_0402_50V8J 2 1 1 3 1 2 +CHGRTC C435 0.9_0402_1% H_THERMTRIP# 2 R204 SATA_ITX_DRX_P0 SATA_ITX_DRX_N1 SATA_ITX_DRX_P1 SATA_ITX_C_DRX_N0 2 0.

6_0402_1% DMI Termination Voltage SPI_CLK SPI_CS0# SPI_CS1#GPIO58/CLGPIO6 OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8#/GPIO44 OC9#/GPIO45 OC10#/GPIO46 OC11#/GPIO47 AG2 AG1 SPI USB 2 10K_0402_5% EC_PWROK <35.7K_0402_5% +3V D14A DMI_MTX_IRX_N1 DMI_MTX_IRX_P1 DMI_ITX_MRX_N1 DMI_ITX_MRX_P1 <8> <8> <8> <8> DMI_MTX_IRX_N2 DMI_MTX_IRX_P2 DMI_ITX_MRX_N2 DMI_ITX_MRX_P2 <8> <8> <8> <8> DMI_MTX_IRX_N3 DMI_MTX_IRX_P3 DMI_ITX_MRX_N3 DMI_ITX_MRX_P3 <8> <8> <8> <8> 6 2 BAV99DW-7_SOT363 D14B 4 3 5 R228 2.2K_0402_5% H_STP_PCI# 2 10K_0402_5% H_STP_CPU# 2 10K_0402_5% SB_SPKR 2 1K_0402_5% OCP# 2 10K_0402_5% MISC GPIO Controller Link 1 R151 1 R147 1 R209 1 R81 1 R95 1 R168 1 R238 2010/07/01 Deciphered Date Title SCHEMATIC. INC.40. 2009 1 27 of 53 .47> VR_ON PROJECT_ID0 2 10K_0402_5% 2 10K_0402_5% PROJECT_ID1 2 10K_0402_5% PM_DPRSLPVR 2 100K_0402_5% ICH_GPIO49 2 1K_0402_5% ICH_TP11 C10 PWROK 2 B @ L4 E20 M5 AJ23 S4_STATE#/GPIO26 1 1 R237 1 R236 1 R232 1 R148 1 R208 @ PM_CLKRUN# ICH_GPIO57 3 1 R256 1 R93 1 R91 1 R79 1 R127 1 R229 1 R82 1 R94 1 R78 1 R120 1 R588 1 1 R119 10K_0402_5% @ 2 R98 ICH_SMBCLK 2 2.1U_0402_16V7K PCIE_ITX_PRX_N3 0.1U_0402_16V7K PCIE_ITX_PRX_P3 10K_1206_8P4R_5% SPI_MOSI LAN_RST# L29 L28 M27 M26 <34> USB_OC#0 NAWF2 RP32 PBTN_OUT# PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P2 PCIE_ITX_PRX_N2 PCIE_ITX_PRX_P2 10K_1206_8P4R_5% 1 2 3 4 R3 D20 0.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. SUB USB20_N3 USB20_P3 USB20_N4 USB20_P4 Remove New Card For HM51 USB20_N6 USB20_P6 <23> <23> <30> <30> USB20_N6 <34> USB20_P6 <34> 1 C191 SUB USB20_N3 USB20_P3 USB20_N4 USB20_P4 R111 453_0402_1% 0. INC.1U_0402_16V7K <25> SPI_CS#1 Project_ID0 B13 PWRBTN# 2 1 C308 10P_0402_50V8J @ ICH_PWROK <8> 1 R150 PM_BATLOW# LAN_RST# 1 1 R211 10K_0402_5% USB_OC#5 USB_OC#9 USB_OC#8 USB_OC#11 1 SATA GPIO Remove Express Card For HM51 High: CRT Plugged <24> CRT_DET# PM_SLP_S3# <35> PM_SLP_S4# <35.24K_0402_1% Remove Bluetooth For HM51 USB20_N10 USB20_P10 USB20_N10 <33> USB20_P10 <33> CL_VREF1_ICH MINI CARD 1 C193 No Reboot Strap R114 453_0402_1% A 0. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.2K_0402_5% BAV99DW-7_SOT363 B +3VS CLK_PCIE_ICH# <16> CLK_PCIE_ICH <16> R196 24.1U_0402_16V4Z 2 Compal Electronics.2K_0402_5% EC_THERM# 2 8.16. September 28.2K_0402_5% EC_LID_OUT# 2 10K_0402_5% ICH_GPIO10 2 10K_0402_5% S4_STATE# 2 10K_0402_5% PROJECT_ID1 2 10K_0402_5% STP_PCI# STP_CPU# ICH_GPIO13 ICH_GPIO17 ICH_GPIO18 ICH_GPIO20 ICH_GPIO22 ICH_GPIO27 ICH_GPIO28 SATA_CLKREQ# ICH_GPIO38 ICH_GPIO39 ICH_GPIO48 ICH_GPIO49 ICH_GPIO57 @ @ T10 PAD PAD T5 <16> SATA_CLKREQ# 1 ICH_GPIO13 2 10K_0402_5% 1 A14 E19 OCP# CRT_DET ICH_GPIO7 EC_SMI# <4> OCP# +3V R97 SMBALERT#/GPIO11 H_STP_PCI# H_STP_CPU# @ PAD T3 +3V C A17 ICH_VGATE Remove CP_PE# For HM51 1 R597 EC_LID_OUT# ICH_PCIE_WAKE# SERIRQ EC_THERM# <33> ICH_PCIE_WAKE# <35> SERIRQ <35> EC_THERM# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# 1 <35> PM_CLKRUN# PMSYNC#/GPIO0 E <16> H_STP_PCI# <16> H_STP_CPU# SUS_CLK C @ ICH_GPIO22 2 10K_0402_5% ICH_GPIO7 2 10K_0402_5% ICH_GPIO17 2 10K_0402_5% ICH_GPIO18 2 10K_0402_5% ICH_GPIO20 2 10K_0402_5% SATA_CLKREQ# 2 10K_0402_5% ICH_GPIO38 2 10K_0402_5% ICH_GPIO39 2 10K_0402_5% ICH_GPIO48 2 10K_0402_5% M6 P1 C16 E16 G17 2 B PM_SYNC# <8> PM_SYNC# SUSCLK SLP_S3# SLP_S4# SLP_S5# R136 10_0402_5% @ 1 @ SUS_STAT#/LPCPD# SYS_RESET# R252 10_0402_5% @ CLK_ICH_14M <16> CLK_ICH_48M <16> 2 @ R4 G19 CLK_ICH_14M CLK_ICH_48M 5 @ SUS_STAT# XDP_DBRESET# H1 AF3 CLK14 CLK48 clocks CLK_ICH_14M P @ PAD T20 <4> XDP_DBRESET# 2 10K_0402_5% G @ RI# CLK_ICH_48M 3 @ F19 SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37 Direct Media Interface @ EC_SWI# SMB PROJECT_ID1 PROJECT_ID0 R234 1 2 <35> EC_SWI# <35> EC_LID_OUT# 1 R595 1 R596 1 R258 1 R145 1 R213 1 R166 1 R257 1 R235 1 R212 SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1 <16. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. INC.33> ICH_SMBCLK <16.1U_0402_16V7K 0. Rev A 401817 Date: 5 4 3 2 Sheet Monday.9_0402_1% 1 2 USB20_N0 USB20_P0 R110 3.2K_0402_5% ICH_SMBDATA 2 2.2K_0402_5% EC_SWI# 2 10K_0402_5% ICH_SMLINK0 2 10K_0402_5% ICH_SMLINK1 2 10K_0402_5% LINKALERT# 2 10K_0402_5% XDP_DBRESET# 2 10K_0402_5% 2 ICH_PCIE_WAKE# 1K_0402_5% PM_BATLOW# 2 8.44> D9 CH751H-40PT_SOD323-2 V27 V26 U29 U28 DMI_MTX_IRX_N0 DMI_MTX_IRX_P0 DMI_ITX_MRX_N0 DMI_ITX_MRX_P0 DMI1RXN DMI1RXP DMI1TXN DMI1TXP Y27 Y26 W29 W28 DMI_MTX_IRX_N1 DMI_MTX_IRX_P1 DMI_ITX_MRX_N1 DMI_ITX_MRX_P1 DMI2RXN DMI2RXP DMI2TXN DMI2TXP AB27 AB26 AA29 AA28 DMI_MTX_IRX_N2 DMI_MTX_IRX_P2 DMI_ITX_MRX_N2 DMI_ITX_MRX_P2 DMI3RXN DMI3RXP DMI3TXN DMI3TXP AD27 AD26 AC29 AC28 DMI_MTX_IRX_N3 DMI_MTX_IRX_P3 DMI_ITX_MRX_N3 DMI_ITX_MRX_P3 DMI_CLKN DMI_CLKP USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBRBIAS USBRBIAS# T26 T25 CLK_PCIE_ICH# CLK_PCIE_ICH AF29 AF28 DMI_IRCOMP AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2 <8> <8> <8> <8> 1 R227 2009/07/01 2 4.47> B16 J29 J28 K27 K26 D USB_OC#10 USB_OC#3 USB_OC#7 USB_OC#2 Internal TPM Strap 2 0_0402_5% SLP_M# PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3 0.37> C 2 1 +3V 100K_0402_5% SB_RSMRST# 2 1 ACIN <18. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.33> ICH_SMBDATA AH23 AF19 AE21 AD20 PCI .5VS_PCIE_ICH USB20_N0 <34> USB20_P0 <34> CL_VREF0_ICH MB USB Conn.Express @ G16 A13 E17 C17 B18 Power MGT @ Place closely pin AC1 U11C ICH_SMBCLK ICH_SMBDATA LINKALERT# ICH_SMLINK0 ICH_SMLINK1 SYS / GPIO D @ SERIRQ 2 10K_0402_5% PM_CLKRUN# 2 8. Compal Secret Data Security Classification EC_RSMRST# <35> 1 DMI_MTX_IRX_N0 DMI_MTX_IRX_P0 DMI_ITX_MRX_N0 DMI_ITX_MRX_P0 Low= Default* SB_SPKR High= "No Reboot" ICH9-M ES_FCBGA676 Issued Date 1 Q10 MMBT3906_SOT23-3 1 3 R99 DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI_ZCOMP DMI_IRCOMP D23 D24 F23 2 10K_0402_5% CL_RST#0 <8> ICH_GPIO24 @ ICH_GPIO10 ICH_ACIN ICH_GPIO9 @ R254 10K_0402_5% N29 N28 P27 P26 1 +3VS T7 CL_VREF0_ICH CL_VREF1_ICH A16 C18 C11 C20 MEM_LED/GPIO24 GPIO10/SUS_PWR_ACK GPIO14/AC_PRESENT WOL_EN/GPIO9 2 R76 F24 B19 CL_RST0# CL_RST1# R88 EC_PWROK CL_CLK0 CL_CLK1 C25 A19 D CK_PWRGD <16> ICH_PWROK F21 D18 ICH_PWROK No used Integrated LAN.24K_0402_1% Within 500 mils +1.37.47> VGATE VGATE 1 A For MINI_CARD1 For HM51 4 A20 TP11 AG19 AH21 AG21 A21 C12 C21 AE18 K1 AF8 AJ22 A9 D19 L1 AE19 AG22 AF21 AH24 A8 GPIO1 GPIO6 GPIO7 GPIO8 GPIO12 GPIO13 GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5 M7 AJ24 B21 AH20 AJ20 AJ21 SPKR MCH_SYNC# TP3 TP8 TP9 TP10 PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P2 PCIE_ITX_C_PRX_N2 PCIE_ITX_C_PRX_P2 PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3 PCIE_ITX_C_PRX_N3 PCIE_ITX_C_PRX_P3 C238 2 C239 2 2 Q11G 2N7002_SOT23 8 7 6 5 RSMRST# D22 0 C237 2 C220 2 R80 2 10K_0402_5% PM_SLP_M# CL_CLK0 <8> CL_DATA0 CL_DATA1 F22 C19 CL_DATA0 <8> @ PAD 1 U7 ICH_PWROK 4 B 2 EC_PWROK A 1 VGATE Y NC7SZ08P5X_NL_SC70-5 PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 G29 G28 H27 H26 PERN4 PERP4 PETN4 PETP4 E29 E28 F27 F26 PERN5 PERP5 PETN5 PETP5 C29 C28 D27 D26 PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP S PAD T8 PAD T4 Project_ID1 Project_ID2 1 0 <34> USB_OC#6 USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11 GPIO49 Low= Desktop used High= Mobile* (Internal pull-up) D25 E23 SPI_MOSI SPI_MISO N4 N5 N6 P6 M1 N2 M4 M3 N3 N1 P5 P3 USBRBIAS 2 1 R197 Within 500 mils 22.1U_0402_16V4Z 2 CMOS Camera Card-Reader +3V MB HS USB CONN R115 3. Inc. connecting LAN_RST# to GND SB_RSMRST# R6 1 1 A Low= Disable* High= iTPM enable by MCH strap PBTN_OUT# <35> 1 CK_PWRGD R5 CL_VREF0 CL_VREF1 2 C225 10P_0402_50V8J @ PM_DPRSLPVR <8.35.37> PM_SLP_S5# <35> U11D G <33> <33> <33> <33> 1 8 7 6 5 BATLOW# CLPWROK RP33 1 2 3 4 DPRSLPVR CK_PWRGD ICH_VGATE NC7SZ08P5X_NL_SC70-5 3 2 USB_OC#1 10K_0402_5% 2 USB_OC#4 10K_0402_5% ICH_PWROK M2 DPRSLPVR/GPIO16 1 T19 ICH9-M ES_FCBGA676 CRT_DET 1 R149 1 R167 VRMPWRGD +3VS PD just for ES1 sample +3V ICH_TP8 ICH_TP9 ICH_TP10 WAKE# SERIRQ THRM# D21 U36 Y <31> <31> <31> <31> For PCIE LAN @ @ @ PAD PAD PAD CLKRUN# PAD P VR_ON 2 SB_SPKR S4_STATE# G20 @ 2 2 <38> SB_SPKR <8> MCH_ICH_SYNC# R121 <26> ICH_TP3 100K_0402_5% T22 +3VS T23 T21 <35.5 4 3 2 1 +3VS Place closely pin B2 <35> EC_SMI# <35> EC_SCI# @ @ 5 B <8.41.

5VS (4. INC.1U_0402_16V4Z 2 2 2 2 2 2 0.7U_0805_10V4Z 2010/07/01 Deciphered Date Title SCHEMATIC.1U_0402_16V4Z close to AG29 close to AD19 close to G6 +3VS C281 1 C300 1 C294 1 close to AJ6 VCCHDA AJ4 VCCSUSHDA AJ3 C223 1 C224 @ @ PAD PAD T24 T6 VCCSUS1_5[1] AD8 TP_VCCSUS1_5_ICH_1 @ PAD T25 VCCSUS1_5[2] F18 VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04] A18 D16 D17 E22 VCCSUS3_3[05] AF1 2 R216 R217 0.1U_0402_16V4Z 0.7U_0805_10V4Z 0.1U_0402_16V4Z 0.5VS_PCIE_ICH L9 2 1 FBMA-L11-201209-221LMA30T_0805 1 +1.022U_0402_16V7K 0.3V4Z 2 2 0. 0.1U_0402_16V4Z C166 GLAN POWER A C297 VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] USB CORE 0.1U_0402_16V4Z 2 2 0.2UF*1) C280 + C268 1 C275 1 C259 220U_D2_4VM_R15 10U_0805_10V4Z 2 2 2 10U_0805_10V4Z 2.3V4Z 2 2 +5V 1U_0402_6.3V4Z 1 D R193 100_0402_5% 1 1 10_0402_5% @ D13 CH751H-40PT_SOD323-2 1 R194 2 1 +ICH_V5REF_SUS C276 1U_0402_6.1U_0402_16V4Z 2 0.5VS A6 CORE C162 VCCP_CORE 1 1 C175 1 C192 D10 CH751H-40PT_SOD323-2 PCI A23 +RTCVCC R122 100_0402_5% 3 U11F VCCPSUS 2 4 VCCPUSB +3VS 2 5 +5VS 1 1 C222 C221 @ @ 1U_0402_6. 2.7UF*1) 0_0603_5% C207 A27 VCCGLANPLL D28 D29 E26 E27 VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] A26 +VCCGLAN_ICH R128 VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 1 1 C170 R29 VCC_DMI[1] VCC_DMI[2] W23 Y23 V_CPU_IO[1] V_CPU_IO[2] AB23 AC23 VCC3_3[01] VCC3_3[02] VCC3_3[07] AG29 AJ6 AC10 VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06] AD19 AF20 AG24 AC20 VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] VCC3_3[14] B9 F9 G3 G6 J2 J7 K7 1 0.022UF*2) close to T1 +VCCCL1_05_INT_ICH +VCCCL1_5_INT_ICH +3VS +1.3V4Z AC9 VCC1_5_A[17] AC18 AC19 VCC1_5_A[18] VCC1_5_A[19] AC21 VCC1_5_A[20] G10 G9 VCC1_5_A[21] VCC1_5_A[22] AC12 AC13 AC14 VCC1_5_A[23] VCC1_5_A[24] VCC1_5_A[25] close to AJ5 2 0.1UF*1) ICH9-M ES_FCBGA676 +3VS 2009/07/01 Issued Date Compal Electronics. 2009 Sheet 1 28 of 53 .1UF*2) 4.022U_0402_16V7K close to A18 (0.3V6K +1. INC.1U_0402_16V4Z +3V C261 1 C262 1 0.5V +3V AA26 AA27 AA3 AA6 AB1 AA23 AB28 AB29 AB4 AB5 AC17 AC26 AC27 AC3 AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29 AD4 AD5 AD6 AD7 AD9 AE12 AE13 AE14 AE16 AE17 AE2 AE20 AE24 AE3 AE4 AE6 AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27 AF5 AF7 AF9 AG13 AG16 AG18 AG20 AG23 AG3 AG6 AG9 AH12 AH14 AH17 AH19 AH2 AH22 AH25 AH28 AH5 AH8 AJ12 AJ14 AJ17 AJ8 B11 B14 B17 B2 B20 B23 B5 B8 C26 C27 E11 E14 E18 E2 E21 E24 E5 E8 F16 F28 F29 G12 G14 G18 G21 G24 G26 G27 G8 H2 H23 H28 H29 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] (0. 1UF*1) 1 1 C295 C296 10U_0805_10V4Z 2 1U_0402_6.5VS (10UF*1.01U_0402_16V7K +1.1U_0402_16V4Z 2 2 1U_0402_6.7U_0805_10V4Z 2 +1.7UF*1) 1 4.5VS_DMIPLL_ICH L8 1 2 MBK1608301YZF_0603 VCCGLAN3_3 +1.1 +ICH_V5REF 0. 0.1U_0402_16V4Z 2 2 0.3V4Z 2 AJ19 G 2 <40> SBPWR_EN# 1 0.3V4Z +ICH_V5REF_SUS +ICH_V5REF +3V 2 +5V 2 +5VALW 2 2 1U_0402_6. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.7UF*1.5VS C301 V5REF_SUS AC11 AD11 AE11 AF11 AG10 AG11 AH10 AJ10 B close to AC7 V5REF ARX 1 AC16 AD15 AD16 AE15 AF15 AG15 AH15 AJ15 +1.1U_0402_16V4Z 0.1U_0402_16V4Z 2 +3VS 2 VCCSATAPLL ATX 1 VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCC1_5_B[47] VCC1_5_B[48] VCC1_5_B[49] VCC1_5_A[09] VCC1_5_A[10] VCC1_5_A[11] VCC1_5_A[12] VCC1_5_A[13] VCC1_5_A[14] VCC1_5_A[15] VCC1_5_A[16] +1.1U_0402_16V4Z 2 1 C298 C299 D C277 1 Q8 AO3413_SOT23-3 1U_0402_6. 2.2UF*1)10U_0805_10V4Z 2 2.2U_0603_6.5VS S 3 +5VALW AE1 AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29 F25 G25 H24 H25 J24 J25 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T24 T27 T28 T29 U24 U25 V24 V25 U23 W24 W25 K23 Y24 Y25 VCCRTC VCCA3GP +1. 0.3V6K +1. Inc.05VS C167 VCCDMIPLL U11E +1.3V4Z (220UF*1.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. Compal Secret Data Security Classification 4. 0. INC.1U_0402_16V4Z +1.2U_0603_6.5VS +3VS +VCCSUS_HDA_ICH @ 2 T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7 A24 B24 0_0603_5% C302 +VCCSUS1_5_ICH_INT_2 1 VCCCL3_3[1] VCCCL3_3[2] close to K7 @ AC8 TP_VCCSUS1_05_ICH_1 F17 TP_VCCSUS1_05_ICH_2 G22 G23 1 +VCC_HDA_ICH 1 VCCCL1_05 VCCCL1_5 C173 close to B9 VCCSUS1_05[1] VCCSUS1_05[2] VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] 1 0.5VS +VCC_GLANPLL_ICH R87 0_0603_5% 1 C161 C160 (10UF*1.05VS C137 C169 1 1 C168 (4.1UF*1) 2 0.1U_0402_16V4Z 0_0603_5% C165 1 C303 R219 0_0603_5% R218 0_0603_5% 0.1U_0402_16V4Z 2 2 0.5VS_SATAPLL_ICH C L11 1 2 MBK1608301YZF_0603 +1.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1 +VCCLAN1_05_INT_ICH C174 0.1UF*1.1U_0402_16V4Z AJ5 VCCUSBPLL AA7 AB6 AB7 AC6 AC7 VCC1_5_A[26] VCC1_5_A[27] VCC1_5_A[28] VCC1_5_A[29] VCC1_5_A[30] A10 A11 VCCLAN1_05[1] VCCLAN1_05[2] A12 B12 VCCLAN3_3[1] VCCLAN3_3[2] 1 +1.1U_0402_16V4Z +VCCLAN_ICH R116 0_0603_5% C172 1 2 0.01UF*1) 1 C260 C258 10U_0805_10V4Z 2 0.1U_0402_16V4Z C208 1 +1.5VS (10UF*1. Rev A 401817 Date: 5 4 3 2 Monday.1U_0402_16V4Z VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25 VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12] A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29 D C B ICH9-M ES_FCBGA676 A (1UF*1. 22UF*2. September 28.05VS C171 (4.

Rev A 401817 Date: 5 4 3 2 Monday.3 VCC3.1U_0402_16V4Z 1 C498 2 1 C499 2 1000P_0402_50V7K C502 2 10U_0805_10V4Z 1 1 C501 2 C500 2 1000P_0402_50V7K 10U_0805_10V4Z SATA HDD Conn. 2009 Sheet 1 29 of 53 .01U_0402_16V7K <26> SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_P1 1 C395 SATA_DTX_IRX_P1_15 2 0. D D JSATA2 <26> SATA_ITX_C_DRX_P0 <26> SATA_ITX_C_DRX_N0 1 2 3 4 5 6 7 SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0 SATA_DTX_IRX_N0 SATA_DTX_IRX_P0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +3VS <26> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 1 C504 SATA_DTX_IRX_N0 2 0.3 VCC3.5 4 +5VS 2 1 +3VS 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. Inc. Compal Secret Data Security Classification 2009/07/01 Issued Date Deciphered Date 2010/07/01 Title SCHEMATIC.3VM_R45M 2 @ 1 C393 2 1 C394 2 1000P_0402_50V7K C392 <26> SATA_ITX_C_DRX_P1_15 <26> SATA_ITX_C_DRX_N1_15 SATA_ITX_C_DRX_P1_15 SATA_ITX_C_DRX_N1_15 SATA_DTX_IRX_N1_15 SATA_DTX_IRX_P1_15 2 1 2 3 4 5 6 7 GND A+ AGND BB+ GND 8 9 10 11 12 13 DP +5V +5V MD GND GND 10U_0805_10V4Z R347 1 @ 2 1K_0402_1% +5VS B GND GND 15 14 B SANTA_206401-1_13P CONN@ <26> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 1 C396 SATA_DTX_IRX_N1_15 2 0.01U_0402_16V7K A A Compal Electronics.1U_0402_16V4Z 1 + 1 C570 150U_B2_6. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.01U_0402_16V7K <26> SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 1 C503 SATA_DTX_IRX_P0 2 0.01U_0402_16V7K +5VS C GND HTX+ HTXGND HRXHRX+ GND VCC3. INC. +5VS JSATA1 0. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. September 28. INC.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.1U_0402_16V4Z 1 3 1 C497 2 0. INC.3 GND GND GND VCC5 VCC5 VCC5 GND RESERVED GND VCC12 VCC12 GND VCC12 GND 24 23 C OCTEK_SAT-22SU1G_NR CONN@ SATA ODD Conn.

INC.5 4 3 2 2 R316 1 1 0_0402_5% U14 2 C359 40~60 mil 1 R555 1 R556 +3VS +3VALW +3VS @ 2 0_0805_5% 2 0_0603_5% C350 1 0.3V6K 2 1 3 7 9 11 33 AV_PLL NC NC CARD_3V3 D3V3 D3V3 8 44 45 47 48 3V3_IN RST# MODE_SEL XTLO XTLI 4 5 14 DM DP GPIO0 C377 1U_0402_6.1U_0402_16V4Z +XDPWR_SDPWR_MSPWR 1 R318 2 0_0603_5% +CARDPWR B 2 B JREAD1 2 C348 0. Rev A 401817 Date: 5 4 3 2 Monday.7U_0603_6.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_16V4Z 1 @ 2 D Vender suggesttion RST# MODE_SEL XTLO XTLI 2 R333 100K_0402_5% 1 2 RST# 2 0_0402_5% 1 R334 USB20_N4 USB20_P4 <27> USB20_N4 <27> USB20_P4 <36> 5IN1_LED# 1 @ 4. 2009 1 Sheet 30 of 53 . INC.19K_0402_1% 12 32 RREF 6 46 AGND AGND 10 22 30 XD_CLE_SP19 XD_CE#_SP18 XD_ALE_SP17 SD_DAT2/XD_RE#_SP16 SD_DAT3/XD_WE#_SP15 XD_RDY_SP14 SD_DAT4/XD_WP#/MS_D7_SP13 SD_DAT5/XD_D0/MS_D6_SP12 SD_CLK/XD_D1/MS_CLK_SP11 SD_DAT6/XD_D7/MS_D3_SP10 MS_INS#_SP9 SD_DAT7/XD_D2/MS_D2_SP8 SD_DAT0/XD_D6/MS_D0_SP7 SD_DAT1/XD_D3/MS_D1_SP6 XD_D5_SP5 XD_D4/SD_DAT1_SP4 SD_CD#_SP3 SD_WP_SP2 XD_CD#_SP1 EEDI 43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18 XTAL_CTR MS_D5 13 24 EEDO EECS EESK SD_CMD 15 16 17 36 DGND DGND +REG18 1 C341 2 1U_0402_6. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.3V4Z D XDCLE XDCE# XDALE SDDAT2_XDRE# SDDAT3_XDWE# XD_RDY SDDAT4_XDWP#_MSD7 SDDAT5_XDD0_MSD6 SDCLK_XDD1_MSCLK_L SDDAT6_XDD7_MSD3 MS_INS# SDDAT7_XDD2_MSD2 SDDAT0_XDD6_MSD0 SDDAT1_XDD3_MSD1 XDD5_MSBS XDD4_SDDAT1 SDCD SDWP XDCD XTAL_CTR 2 R277 2 R317 1 0_0603_5% SDCLK_XDD1_MSCLK 1 0_0402_5% +3VS SD_CMD 2 2 2 @ C376 47P_0402_50V8J VREG MS_D4 NC 2 0_0402_5% RTS5159E-GR_LQFP48_7X7 1 @ 1 2 C374 6P_0402_50V8D 2 2 2 @ Y3 12MHZ_16PF_7A12000026 1 @ C R331 0_0603_5% 1 R329 33_0402_5% @ XTLI 1 1 R330 <16> CLK_SD_48M C C373 22P_0402_50V8J @ 1 2 C375 6P_0402_50V8D +CARDPWR XTLO 1 EMI C476 @ 2 1 1 C342 C480 0.1U_0402_16V4Z +CARDPWR XDCD XD_RDY SDDAT2_XDRE# XDCE# XDCLE XDALE SDDAT3_XDWE# SDDAT4_XDWP#_MSD7 34 1 2 3 4 5 6 7 8 XD-VCC XD-CD-SW XD-R/B XD-RE XD-CE XD-CLE XD-ALE XD-WE XD-WP SDDAT5_XDD0_MSD6 SDCLK_XDD1_MSCLK SDDAT7_XDD2_MSD2 SDDAT1_XDD3_MSD1 XDD4_SDDAT1 XDD5_MSBS SDDAT0_XDD6_MSD0 SDDAT6_XDD7_MSD3 9 24 25 27 28 29 31 33 XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7 MS-VCC MS-SCLK MS-INS MS-BS MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 10 12 16 23 19 21 18 14 SDCLK_XDD1_MSCLK MS_INS# XDD5_MSBS SDDAT0_XDD6_MSD0 SDDAT1_XDD3_MSD1 SDDAT7_XDD2_MSD2 SDDAT6_XDD7_MSD3 SD-VCC SD-CLK SD-CMD SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-WP-SW SD-CD-SW 20 22 15 30 32 11 13 35 36 SDCLK_XDD1_MSCLK SD_CMD SDDAT0_XDD6_MSD0 XDD4_SDDAT1 SDDAT2_XDRE# SDDAT3_XDWE# SDWP SDCD SDCLK_XDD1_MSCLK 1 1 R294 100K_0402_5% +CARDPWR R563 10_0402_5% @ 2 1 1 @ 4in1-GND 4in1-GND 4in1-GND 4in1-GND 17 26 37 38 2 C477 22P_0402_50V8J TAITW_R015-300-LM_36P_NR-T CONN@ A A For HM51 Issued Date Compal Electronics. September 28.3V4Z 1 MODE_SEL 1 R332 0_0402_5% 2 R315 1 2 6. INC. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. Inc. Compal Secret Data Security Classification 2009/07/01 Deciphered Date 2010/07/01 Title SCHEMATIC.1U_0402_16V4Z +XDPWR_SDPWR_MSPWR 1 C349 0.1U_0402_16V4Z 2 2 10U_0805_10V4Z 0.

L1 stuffed and R39 removed. September 28.1U_0402_16V4Z Y1 LAN_X1 R39 1 s o r e h t A 2 8114@ C69 2 C57 2 C56 +1. INC.2_AVDDL AVDDH0 AVDDH1 AVDDH2 15 19 25 +2.25.1U_0402_16V4Z 2 1 +3V_LAN +1.1U_0402_16V7K 0.1U_0402_16V7K Place Close to Chip 2 R36 LAN_X1 LAN_X2 RBIAS 1 2.1U_0402_16V4Z +3V_LAN R38 10K_0402_1% 8114@ Q39 8132@ 1 2 +2.7K_0402_1% C87 R21 4. If not overclocking.1U_0402_16V7K 8132@ <8.1U_0402_16V4Z If overclocking. remove C80 Place Close to Pin 28、32、45、46 C17 C16 0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.5V_VDDH 2 8114@ 0_0603_5% C100 0.1U_0402_16V4Z Issued Date 2009/07/01 1 C61 0.5V_VDDH NC_0 NC_1 NC_2 NC_3 NC_4 NC_5 20 21 23 24 26 35 2 8114@ FBMA-L11-201209-221LMA30T_0805 2 1 2 DVDDL0 DVDDL1 DVDDL2 DVDDL3 AVDDVCO1 1 AVDDVCO2 3 C59 0.5V_VDDH 1 2 C15 1U_0603_10V4Z 1 1 2 2 C66 0. +3V_LAN 2 2 8132@ 4.7K_0402_1% 1 C72 1 C86 1 C85 0.1U_0402_16V4Z +1.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.2_AVDDL 1 1 C516 C520 10U_0805_10V4Z 0. Compal Secret Data Security Classification C18 0.1uF(SE070104Z80).1U_0402_16V4Z 2 8132@ 4 2 MMJT9435T1G_SOT223 8114@ +1.1U_0402_16V4Z 4 4.1U_0402_16V4Z 0.7U_0805_10V4Z 8132@ 2 0_0603_5% +2.2_AVDDL L2 FBMA-L11-201209-221LMA30T_0805 1 2 8114@ U2 60mil C84 2 8114@ C83 C70 +1.A B C D +3V_LAN E Layout Notice : Place as close chip as possible.1U_0402_16V4Z 8114@ 1 1 Place Close to Pin8、16、22、36、39 CTR12 1 C63 C54 0.1U_0402_16V4Z 2010/07/01 Deciphered Date Title SCHEMATIC.1U_0402_16V4Z 0.5V_VDDH R432 0_0402_5% 2 2 3 C521 0.2_AVDDL 1 C71 0.1U_0402_16V4Z 2 8132@ A0 A1 A2 GND VCC WP SCL SDA 2 0_1206_5% R18 4.<32> C65 0.9_0402_1% LAN_X2 AR8132L 10/100 LAN C82 33P_0402_50V8K L1 Place Close to Chip C55 1 0. 2009 Date: Rev A 401817 A B C D Sheet E 31 of 53 . R39.7K_0402_5% <16> CLK_PCIE_LAN 3 <16> CLK_PCIE_LAN# 1 1000P_0402_50V7K CLK_PCIE_LAN_C 1 0.1U_0402_16V4Z 2 2 2 0.8_VDD/LX 2 8114@ 0_0603_5% 1 R48 TWSI_SCL TWSI_SDA AT24C02BN-SH-T_SO8 8114@ +1.1U_0402_16V4Z +2.1U_0402_16V4Z 8114@ 8114@ 2 2 1 C60 8132@ 1U_0603_10V4Z 1 1 1 1 1 1 2 2 2 2 2 2 C68 8114@ 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.37K_0402_1% TWSI_CLK TWSI_DATA 29 30 LED_ACTn LED_10_100n 47 48 LED_DUPLEXn 27 TRXP0 TRXN0 TRXP1 TRXN1 13 14 17 18 AVDDL_REG AVDDL/AVDDL_REG 11 42 TWSI_SCL TWSI_SDA LAN_ACTIVITY# LAN_LINK# LAN_ACTIVITY# <32> LAN_LINK# <32> LAN_CLKREQ# <16> R35 LAN_MIDI0+ LAN_MIDI0LAN_MIDI1+ LAN_MIDI1AVDDVCO1 AVDDVCO2 1 2 R28 0_0603_5% 2 2 R34 2 R33 2 R27 49. AR8132: L1=0ohm(SD002000080).5V_VDDH/VDD17 1 R46 1 2 3 4 +2.7U_0805_10V4Z 8 7 6 5 2 4 1 R44 +3VALW 1 1 C11 1 L5 0.5V_VDDH/VDD17 1U_0603_10V4Z CTR12 0.<32> LAN_MIDI1+ LAN_MIDI1- LAN_MIDI1+ <32> LAN_MIDI1.1U_0402_16V7K 1 VDD18O 2 VDD33 6 VDDHO 5 CTR12 3 4 PERSTn WAKEn 7 VBG1P18V 41 REFCLKP 40 REFCLKN <27> PCIE_ITX_C_PRX_P3 43 RX_P <27> PCIE_ITX_C_PRX_N3 44 RX_N <27> PCIE_PTX_C_IRX_P3 C20 <27> PCIE_PTX_C_IRX_N3 C19 2 1 2 1 PCIE_PTX_IRX_P3 38 TX_P PCIE_PTX_IRX_N3 37 TX_N 9 10 XTLO XTLI 31 33 SMCLK SMDATA 12 34 RBIAS TESTMODE 49 GND 0.1U_0402_16V7K CLK_PCIE_LAN#_C 1 0.7UH_1008HC-472EJFS-A_5%_1008 U1 +AVDD_CEN +AVDD_CEN 1 +AVDD_CEN_C1 R45 8132@ 1 2 R49 0_0603_5% C99 4.C67=0.9_0402_1%C64 1 1 2 1 49. L1 stuffed and R28 removed.1U_0402_16V4Z Compal Electronics.35> PLT_RST# <35> EC_PME# +3V_LAN R37 1 2 4.2_DVDDL 2 C81 33P_0402_50V8K Place Close to Pin15、19、25 Pre-MP 9/17 LAN_MIDI0+ LAN_MIDI0- LAN_MIDI0+ <32> LAN_MIDI0. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.17. Monday.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 25MHZ_20P 2 1 2 2 1 0_0603_5% 2 1 C67 C80 1000P_0402_50V7K 1U_0603_10V4Z 2 @ 0. R28. INC.2_DVDDL 1 2 C73 8132@ 1U_0603_10V4Z AR8132L-AL1E_QFN48_6X6 1 1 2 2 8114@ C58 0.1U_0402_16V4Z 1 1 2 2 C74 0.8_VDD/LX 1 8114@ 1U_0603_10V4Z +3V_LAN 2 1 2 1 +2.9_0402_1% 1 1 1 2 49.1U_0402_16V4Z +1.1U_0402_16V4Z 28 32 45 46 +1. Inc. INC.9_0402_1% 49.2_DVDDL AVDDL0 AVDDL1 AVDDL2 AVDDL3 AVDDL4 8 16 22 36 39 +1.

September 28.1K_0402_5% C4 220P_0402_50V7K 1 RJ45_MIDI1+ RJ45_MIDI1- 1 1 1 2 C2 1 2 R4 75_0402_1% <31> LAN_LINK# Amber LED- 6 PR2- 5 PR3- 4 PR3+ RJ45_MIDI1+ 3 PR2+ RJ45_MIDI0- 2 PR1- RJ45_MIDI0+ 1 PR1+ LAN_LINK# 10 +3V_LAN R10 2 1 510_0402_5% SHLD2 16 SHLD1 15 SHLD2 14 SHLD1 13 PR4PR4+ RJ45_MIDI1- 2 R3 75_0402_1% LAN_TCT Amber LED+ 11 7 Pulse H0013 C 12 8 1 <31> LAN_MIDI0+ <31> LAN_MIDI0- 10/100 : TL8515C_LF GBE : GSL5009-1 T1 Guide Pin C Green LED- 9 Green LED+ FOX_JM36113-L2R8-7F CONN@ C3 1 2 0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. Compal Secret Data Security Classification 2009/07/01 Issued Date Deciphered Date 2010/07/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.1U_0402_16V4Z RJ45_GND 1 LANGND 1 2 1 C8 1000P_1206_2KV7K Place close to TCT pin C556 2 2 40mil C555 4. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. Date: 5 4 3 2 SCHEMATIC. INC.1U_0402_16V4Z B B LAN_ACTIVITY#_1 2 D29 @ PJDLC05_SOT23 1 2 C7 68P_0402_50V8J @ 1 LAN_LINK# 3 LAN_LINK# LAN_ACTIVITY#_1 1 2 C10 68P_0402_50V8J @ For EMI A A Compal Electronics. INC. 2009 Sheet 1 32 of 53 . INC.5 4 D 3 2 1 D 2 +AVDD_CEN 1 R7 0_0603_5% <31> LAN_MIDI1+ <31> LAN_MIDI1- 1 2 3 4 5 6 7 8 LAN_MIDI1+ LAN_MIDI1- RD+ RDCT NC NC CT TD+ TD- JRJ45 RX+ RXCT NC NC CT TX+ TX- <31> LAN_ACTIVITY# RJ45_MIDI0+ RJ45_MIDI0- 16 15 14 13 12 11 10 9 LAN_ACTIVITY# R11 2 LAN_MIDI0+ LAN_MIDI0- 2 LAN_ACTIVITY#_1 1 510_0402_5% 2 R8 5. Inc.MB A4853 Document Number Rev A 401817 Monday.1U_0402_16V4Z RJ45_GND 2 C9 220P_0402_50V7K 40mil 0.7U_0805_10V4Z 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.

7U_0805_10V4Z 2 1 C431 0.1U_0402_16V4Z 2 1 C428 4. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.27> USB20_N10 <27> USB20_P10 <27> (LED_WWAN#) (LED_WLAN#) MINI1_LED# <36> (9~16mA) 2 FOX_AS0B226-S99N-7F CONN@ 1 @ 1 1 1 1 @ @ 3 1 @ H28 H_3P8 1 @ FD4 FIDUCIAL_C40M80 1 @ H22 H_3P3 1 FD1 @ H6 H_2P8 H21 H_4P6X4P0N @ @ H27 H_2P8 @ H29 H_3P8 @ @ H30 H_5P1X4P1N @ FD3 @ FIDUCIAL_C40M80 @ FD2 @ FIDUCIAL_C40M80 1 @ @ 1 1 @ 1 H20 H_3P4 H17 H_3P4 H16 H_4P2 H8 H_4P0N H15 H_4P2 1 @ @ 1 1 H5 H_2P8 H18 H_3P4 @ H23 H_3P4 1 H10 H_4P2 @ 1 3 @ @ H24 H_3P4 1 H11 H_4P2 H4 H_3P4 H25 H_3P4 1 1 1 @ @ 1 H9 H_3P4 H26 H_3P4 1 H7 H_3P4 @ 1 1 1 @ H19 H_3P4 1 H14 H_3P4 1 H1 H_3P4 1 53 54 55 56 G1 G2 G3 G3 2 <35> E51TXD_P80DATA <35> E51RXD_P80CLK (WAKE#) 1 3 5 7 9 11 13 15 @ FIDUCIAL_C40M80 4 4 2009/07/01 Issued Date Compal Electronics. INC. Date: A B C D SCHEMATIC.MB A4853 Document Number Rev A 401817 Sheet Monday.A B C D E Mini Card Power Rating For Wireless LAN +3VS_WLAN +3VS_WLAN R378 1 R370 1 @ 2 0_1206_5% +3VS 2 0_1206_5% +3V 1 2 1 Power Primary Power (mA) 1 C432 4.5VS 500 375 5 (Not wake enable) +1. September 28.1U_0402_16V4Z Auxiliary Power (mA) Peak Normal +3VS 1000 750 +3V 330 250 250 (wake enable) +1.5VS WL_OFF# PLT_RST_BUF# +3V_WLAN R373 1 R374 1 MINI_SMBCLK MINI_SMBDATA R372 1 R357 1 2 0_0603_5% 2 0_0603_5% @ @ @ WL_OFF# <35> PLT_RST_BUF# <25> +3VS +3V 2 0_0402_5% ICH_SMBCLK 2 0_0402_5% ICH_SMBDATA ICH_SMBCLK <16. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. INC.7U_0805_10V4Z 2 1 C426 0. Inc.1U_0402_16V4Z 2 C427 0.27> ICH_SMBDATA <16. 2009 E 33 of 53 . INC.5VS Normal 1 JMINI2 R381 1 <27> ICH_PCIE_WAKE# @ 2 0_0402_5% Remove bluetooth For HM51 <16> MINI2_CLKREQ# <16> CLK_PCIE_MINI2# <16> CLK_PCIE_MINI2 <27> PCIE_PTX_C_IRX_N2 <27> PCIE_PTX_C_IRX_P2 <27> PCIE_ITX_C_PRX_N2 <27> PCIE_ITX_C_PRX_P2 +3VS_WLAN For MINICARD Port80 Debug E51TXD_P80DATA E51RXD_P80CLK R377 1 2 0_0402_5% E51TXD_P80DATA_R 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 +3VS_WLAN +1.1U_0402_16V4Z 2 1 C425 0. Compal Secret Data Security Classification 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.

September 28.A B C D E 1 1 2 2 USB CONN. 2009 E 34 of 53 . Compal Secret Data Security Classification 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. INC. +USB_VCCA +USB_VCCA W=80mils W=80mils +USB_VCCA +USB_VCCA 1 + 1 C538 1 + C549 150U_B2_6. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.3VM_R45M 2 2 @ 470P_0402_50V7K 3 JUSB2 <27> USB20_N6 <27> USB20_P6 USB20_N6 USB20_P6 1 2 3 4 VCC DD+ GND 5 6 7 8 GND1 GND2 GND3 GND4 3 JUSB1 USB20_N0 USB20_P0 <27> USB20_N0 <27> USB20_P0 SUYIN_020173MR004G565ZR CONN@ 1 2 3 4 VCC DD+ GND 5 6 7 8 GND1 GND2 GND3 GND4 SUYIN_020173MR004G565ZR CONN@ +3V +5VALW +USB_VCCA 1 80mil U28 USB20_P0 6 CH3 CH2 3 USB20_P6 C540 1 GND IN IN EN# OUT OUT OUT FLG TPS2061DRG4_SO8 +USB_VCCA 5 Vp Vn 8 7 6 5 R461 100K_0402_5% USB_OC#6 <27> 2 D23 1 2 3 4 1 2 R460 10K_0402_5% USB_OC#0 <27> 1 4. Inc.1U_0402_16V4Z 4 <40> SYSON# CM1293-04SO_SOT23-6 2009/07/01 Issued Date Compal Electronics. Date: A B C D SCHEMATIC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.3VM_R45M 2 2 470P_0402_50V7K C537 1 C548 150U_B2_6.MB A4853 Document Number Rev A 401817 Sheet Monday. INC.7U_0805_10V4Z 2 2 2 4 USB20_N6 4 CH4 CH1 1 USB20_N0 C539 0.

7U_0805_10V4Z Deciphered Date 100P_0402_50V8J 1 100P_0402_50V8J 1 100P_0402_50V8J 1 A Compal Electronics.37> VGA_ENBKL <18> EAPD <38> EC_THERM# <27> SUSP# <37.2K_0402_5% 2 EC_SMB_DA2 2.7K_0402_5% 1 BATT_TEMP <42> BATT_OVP <44> ADP_I <44> 20mil Security Classification 2 +3VALW SPI Device Interface SPI Flash ROM R31 ACOFF <44> ECAGND 2 1 C332 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.40.45.37> BKOFF# <23> WL_OFF# <33> 1 100K_0402_5% Analog Board ID definition.17] <36> 0.17] C421 D Place on RAM door E51RXD_P80CLK E51TXD_P80DATA NC C331 1000P_0402_50V7K 1 2 3 4 1 2 3 4 2 2 2 0.25.47> ACIN <18. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 21 23 26 27 PWM Output DA Output 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 FAN_SPEED1 INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 AD D E51RXD_P80CLK E51TXD_P80DATA 4 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 C 1 R290 1 R291 EC_SCI# PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D 1 2 3 4 1 <27> EC_SCI# <27> PM_CLKRUN# 12 13 37 20 38 Place on MiniCard +3VALW 1 2 3 4 IN 2 1 R270 47K_0402_5% 2 1 C320 0.1U_0402_16V4Z 9/17 Pre-MP C367 15P_0402_50V8J 2 X2 32. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. Inc. INC.22> +3VALW B 1 R279 1 R280 1 R295 1 R296 1 R320 2 EC_SMB_CK1 2.1U_0402_16V4Z AGND R289 2 LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 1 2 3 4 5 7 8 10 69 C340 @ 22P_0402_50V8J 2 1 <26> EC_GA20 <26> EC_KBRST# <27> SERIRQ <26> LPC_FRAME# <26> LPC_AD3 <26> LPC_AD2 1 @ 33_0402_5% <26> LPC_AD1 <26> LPC_AD0 2 67 9 22 33 96 111 125 U13 VCC VCC VCC VCC VCC VCC R557 PLT_RST# 2 100K_0402_5% 1 KSO[0.17.2K_0402_5% 2 EC_SMB_DA1 2.2K_0402_5% 2 KSO1 47K_0402_5% 2 KSO2 47K_0402_5% 2 LID_SW# 100K_0402_5% EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 <27> PM_SLP_S3# <27> PM_SLP_S5# <27> EC_SMI# <8> MCH_TSATN_EC# <4> FAN_SPEED1 Remove BT_ON# For HM51 <37> ON/OFF <36> PWR_SUSP_LED <36> NUM_LED# +3VS EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 PM_SLP_S3# PM_SLP_S5# EC_SMI# 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 E51TXD_P80DATA E51RXD_P80CLK ON/OFF PWR_SUSP_LED NUM_LED# 2 EC_SMB_CK2 2.1U_0402_16V4Z EC_PME# 2 10K_0402_5% @ 1 R319 C344 JP13 KSI[0.7K_0402_5% 2 TP_DATA 4...1U_0402_16V4Z 1 C369 1 C365 ECAGND 1 3 5 2 SCHEMATIC.45.46.1U_0402_16V4Z +3VALW PLT_RST# E51RXD_P80CLK <33> E51TXD_P80DATA <33> JP9 OUT <8. AD_BID0 1 R273 Rb B EC_CRY1 C368 SUSP# PBTN_OUT# EC_PME# 1 2 PM_SLP_S4# <27.7] 1 1 C319 +3VALW 1 2 +EC_VCCA 2 FBM-L11-160808-800LMT_0603 2 0. September 28.46> VR_ON <27..768KHZ_12.. 2009 Sheet 1 35 of 53 . 2010/07/01 Title Date: 4 1 100K_0402_5% 1 100K_0402_5% C THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.37. Please see page 3.1U_0402_16V4Z 1 2 1 +3VALW 0.44> EC_RSMRST# <27> EC_LID_OUT# <27> EC_ON <37> EC_SWI# <27> EC_PWROK <27. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.2K_0402_5% EC_CRY1 EC_CRY2 122 123 AVCC INVT_PWM BEEP# Remove FANPWM For HM51 BATT_TEMP BATT_OVP DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F 68 70 71 72 DAC_BRIG EN_DFAN1 IREF PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F 83 84 85 86 87 88 EC_MUTE# SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 97 98 99 109 3S/4S# 65W/90W# SBPWR_EN LID_SW# SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# 119 120 126 128 EC_SPIDI/FWR# EC_SPIDO/FRD# EC_SPICLK EC_SPICS#/FSEL# CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 73 74 89 90 91 92 93 95 121 127 EC_RCIRRX EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 100 101 102 103 104 105 106 107 108 PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 110 112 114 115 116 117 118 V18R 124 PS2 Interface AD_BID0 GPIO SM Bus PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A GPI XCLK1 XCLK0 11 24 35 94 113 A KB926QFD3_LQFP128_14X14 3S/4S# R324 @ ID_15_17 DAC_BRIG <23> EN_DFAN1 <4> IREF <44> CALIBRATE# <44> R321 R322 TP_CLK TP_DATA 3 @ FSTCHG BATT_GRN_LED# CAPS_LED# BATT_AMB_LED# PWR_LED SYSON VR_ON ACIN EC_LID_OUT# EC_ON EC_PWROK BKOFF# WL_OFF# ID_15_17 65W/90W# 2 R323 3S/4S# <44> 65W/90W# <44> SBPWR_EN <40> LID_SW# <36> EC_SI_SPI_SO <36> EC_SO_SPI_SI <36> EC_SPICLK <36> EC_SPICS#/FSEL# <36> +3VALW R272 100K_0402_5% Ra FSTCHG <44> BATT_GRN_LED# <36> CAPS_LED# <36> BATT_AMB_LED# <36> PWR_LED <36> SYSON <40.5P_MC-306 C366 C333 BATT_TEMP 2 C420 BATT_OVP 2 C364 ACIN 2 4.49> PBTN_OUT# <27> EC_PME# <31> EC_CRY2 1 1 15P_0402_50V8J 2 VGA_ENBKL EAPD C325 18K_0402_5% 2 0.MB A4853 Document Number Rev A 401817 Monday.27.1U_0402_16V4Z C343 1000P_0402_50V7K 1 1 KSI[0. INC.31> PLT_RST# ACES_85205-0400 @ NC <16> CLK_PCI_LPC GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC KSO[0.01U_0402_16V7K 63 64 65 66 75 76 +3VALW ACES_85205-0400 @ INVT_PWM <23> BEEP# <38> BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 GND GND GND GND GND 1 R281 1 R282 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int.4 3 2 1 For EC Tools +3VALW L13 2 +3VALW 1 R276 10K_0402_5% EC_RCIRRX +5VS 2 TP_CLK 4.7K_0402_5% <42> <42> <4.41.7] <36> 2 2 2 0. 5 2 +3VALW TLOCK_LED# <36> TP_CLK <36> TP_DATA <36> Compal Secret Data 2009/07/01 2 EC_MUTE# <39> L14 ECAGND 2 1 FBM-L11-160808-800LMT_0603 Issued Date 1 100K_0402_5% 2 4. INC.40.22> <4.

Inc. INC. Date: SCHEMATIC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_16V4Z EC_SPICS#/FSEL# SPI_WP# SPI_HOLD# +SPI_VCC 1 3 7 4 CS# WP# HOLD# GND U21 <35> EC_SPICS#/FSEL# EC_SPICS#/FSEL# 2 4.To TP/B Conn. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. September 28.7] <35> KSO[0.17] TP_DATA 3 2 RIGHT_BTN# 1 KSI[0.2K_0402_5% YG 3 R345 1 Q3B 2N7002DW-T/R7_SOT363-6 5 <35> PWR_SUSP_LED 10K_0402_5% LED2 +3VALW 2 <35> PWR_LED 1 C36 PWR_SUSP_LED# Q3A 2N7002DW-T/R7_SOT363-6 2 KSO10 PWR_LED# 6 2 @ 100P_0402_50V8J Compal Footprint TLOCK_BTN# KSI3 1 2 @ 100P_0402_50V8J 1 KSO8 KSI2 1 1 C35 KSI3 WL_BTN# 2 C28 KSO11 C37 KSI1 KSI5 KSI0 KSO9 For HM51 ACES_85201-20051 ACES_85201-26051 CONN@ KSO16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TP_LOCK_LED# KSO0 KSI2 PWR_SUSP_LED# PWR_LED# ON/OFFBTN# KSI1 MINI1_LED# MEDIA_LED# NUM_LED# CAPS_LED# <37> ON/OFFBTN# <35> KSI1 <33> MINI1_LED# 5 6 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 5 6 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 28 27 3 G2 G1 4 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 5 6 +3VS JKB2 LEFT_BTN# 3 2 (Right) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 To POWER/B JP14 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 D11 @ PJDLC05_SOT23 0.7] INT_KBD Conn.MB A4853 Document Number Rev A 401817 Monday.. ACES_85201-0605 CONN@ C218 100P_0402_50V8J 2 ENE suggestion SPI Frequency over 66MHz SST: 50MHz MXIC: 70MHz ST: 40MHz 1 6 5 4 3 2 1 TP_CLK TP_DATA LEFT_BTN# RIGHT_BTN# 3 1 R358 +3VALW 1 BATT_GRN_LED# BATT_GRN_LED# <35> HT-297DQ-GQ_AMB-YG Issued Date Compal Electronics. Footprint SO8 EC_SPICLK <35> EC_SO_SPI_SI <35> EC_SI_SPI_SO <35> C217 100P_0402_50V8J MX25L8005M2C-15G_SOP8 EC_SPICLK_R 1 2 2 2 FOR EMI LEFT_BTN# R354 22_0402_5% @ TP_CLK +5VS +3VALW SW4 SMT1-05-A_4P 1 RIGHT_BTN#3 SW3 SMT1-05-A_4P 1 ACES_85201-26051 CONN@ 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 G2 G1 4 2 4 2 LEFT_BTN# 3 SW2 @ SMT1-05-A_4P 1 RIGHT_BTN#3 SW1 @ SMT1-05-A_4P 1 4 2 4 2 +5VS 28 27 <35> LID_SW# <35> TLOCK_LED# <35> KSO0 <35> KSI2 <35> NUM_LED# <35> CAPS_LED# KSO0 For HM51 C30 1 2 @ 100P_0402_50V8J KSO17 C29 1 2 @ 100P_0402_50V8J KSO15 C31 1 2 @ 100P_0402_50V8J KSO14 C32 1 2 @ 100P_0402_50V8J KSO13 C33 1 2 @ 100P_0402_50V8J KSO7 C39 1 2 @ 100P_0402_50V8J KSO12 C34 1 2 @ 100P_0402_50V8J KSO6 C40 1 2 @ 100P_0402_50V8J KSO5 C41 1 2 @ 100P_0402_50V8J KSO4 C42 1 2 @ 100P_0402_50V8J KSI4 1 2 @ 100P_0402_50V8J KSO3 C43 1 2 @ 100P_0402_50V8J KSI1 C27 1 2 @ 100P_0402_50V8J KSI4 C24 1 2 @ 100P_0402_50V8J KSO2 C46 KSI2 C26 2 @ 100P_0402_50V8J 1 2 @ 100P_0402_50V8J 1 KSO1 C47 1 2 @ 100P_0402_50V8J 1 2 @ 100P_0402_50V8J C25 1 2 @ 100P_0402_50V8J KSO0 C48 1 2 @ 100P_0402_50V8J C38 1 2 @ 100P_0402_50V8J KSI5 C23 1 2 @ 100P_0402_50V8J KSI6 C22 1 2 @ 100P_0402_50V8J KSI7 C21 1 2 @ 100P_0402_50V8J R22 +3VS R344 2 1K_0402_5% 2 1 PWR_SUSP_LED# For HM51 <26> SATA_LED# SATA_LED# PWR_LED# Q5A 2N7002DW-T/R7_SOT363-6 1 6 4 3 5 1 R32 +3VS +3VS PWR_LED# C51 1 2 @ 100P_0402_50V8J ON/OFFBTN# C52 1 2 @ 100P_0402_50V8J MINI1_LED# C44 1 2 @ 100P_0402_50V8J PWR_SUSP_LED#C50 1 2 @ 100P_0402_50V8J NUM_LED# C45 1 2 @ 100P_0402_50V8J MEDIA_LED# C49 1 2 @ 100P_0402_50V8J MEDIA_LED# Q5B 2N7002DW-T/R7_SOT363-6 HT-297DQ-GQ_AMB-YG LED1 1 2 R343 1. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.2K_0402_5% 4 +3VALW 1 2 R342 1K_0402_5% 2 3 BATT_AMB_LED# BATT_AMB_LED# <35> YG +3VALW A 2 3 FOR EMI 10K_0402_5% <30> 5IN1_LED# A 4 1 2 4 1.. U20 C417 1 2 0_0603_5% 2 0. INC.. 2009 Sheet 36 of 53 .7K_0402_5% SPI_HOLD# R359 1 R371 1 +3VALW 1 3 7 4 CE# WP# HOLD# VSS VDD SCK SI SO VCC SCLK SI SO +SPI_VCC EC_SPICLK_R EC_SO_SPI_SI EC_SI_SPI_SO 8 6 5 2 JTP1 +5VS <35> TP_CLK <35> TP_DATA MX25L512AMC-12G_SO8 @ 8 6 5 2 EC_SPICLK_R R356 1 R355 1 R360 1 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% Reserved for BIOS simulator. INC..17] <35> 1 (Left) C219 2 KSI[0. Compal Secret Data Security Classification 2009/07/01 Deciphered Date 2010/07/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.7K_0402_5% SPI_WP# 2 4.1U_0402_16V4Z 5 6 JKB1 D12 @ PJDLC05_SOT23 C416 10P_0402_50V8J @ 1 KSO[0.

MB A4853 Document Number Rev A 401817 Sheet Monday.35> For South Bridge 7 @ 7 2 G I G 1 2 CH751H-40PT_SOD323-2 @ C408 1U_0603_10V6K @ U19B SN74LVC14APWLE_TSSOP14 P P 2 1 <27.46. INC.40. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. INC.49> For +VCCP/+1.35. 2009 E 37 of 53 .1U_0402_16V4Z 2 G S C409 U19D SN74LVC14APWLE_TSSOP14 P P 2 D U19C SN74LVC14APWLE_TSSOP14 G <40> SUSP 5 1 SUSP 2 G Q31 2N7002_SOT23 @ 3 <35. September 28.35> PM_SLP_S4# Q57 1 14 2N7002W-T/R7_SOT323-3 3 R268 D33 2 G G Q19 3 2 2 D 2 G 1.1U_0603_25V7K C932 I O 2 S POWER OK Time delay 1RC Time 1 D P CH751H-40PT_SOD323-2 1 2 1 R608 0_0402_5% <27.A B C D E Power Button ON/OFF switch 1 1 +3VALW R341 R416 1 2 @ 10K_0603_5% 1 2 @ 10K_0603_5% 2 TOP Side R271 D17 2 ON/OFFBTN# <36> ON/OFFBTN# 1 100K_0402_5% Bottom Side ON/OFF <35> 1 51ON# 3 51ON# <41> DAN202UT106_SC70-3 DDR3 S4 1 S 2N7002_SOT23 10K_0402_5% 1 2 @ R609 0_0402_5% 1 <45> +1. Compal Secret Data Security Classification 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.22U_0603_16V7K @ SUSP# 1 2 R562 0_0402_5% Pre-MP 9/17 VGA_ON <48. Inc. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.47> VR_ON U19A SN74LVC14APWLE_TSSOP14 14 R349 180K_0402_5% @ D18 1 3 3 +3VS +3VALW 1 +3VALW 1 9 D30 @ For HM51 2 RB751V_SOD323 1 @ 8 2 0. INC.5V R607 10K_0402_5% 2 SM_PWROK <8> For South Bridge 7 EC_ON <35> EC_ON R606 47K_0402_5% 2 1 1 +3VALW +1.49> SUSP# @ 10K_0402_1% 7 R353 @ 10K_0402_1% 1 2 14 R352 C880 0.5VPGOOD +3VALW 1 2 1 0.45.1U_0402_16V4Z U19E SN74LVC14APWLE_TSSOP14 U19F SN74LVC14APWLE_TSSOP14 @ P O 10 VS_ON <45.5V 2 +3VALW 0.05VS 13 I O @ 12 1 R561 For +VGA_CORE 2 0_0402_5% @ C881 0. Date: A B C D SCHEMATIC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_16V4Z 4 1 2009/07/01 Issued Date Compal Electronics.1U_0402_16V4Z 2 C931 U42A SN74LVC14APWLE_TSSOP14 2 1 2 @ R610 10K_0402_5% Power ON Circuit +3VS +3VALW 1 +3VALW 2 O 3 14 I O SYS_PWROK 1 R348 4 @ 2 @ 0_0402_5% EC_PWROK <27.49> 2 7 2 O +3VALW C407 7 1 4 14 @ G I I G 6 P 14 @ 1 R560 @ 200K_0402_5% 11 1 2 O 7 @ @ +3VALW SUSP# I 14 0.

4K_0402_1% 2SC2411KT146_SOT23-3 2 B E 10mil 2 1 R417 2 560_0402_5% 1 C509 1 1 C510 1 C505 1 1U_0402_6.7U_0805_6.3VM HP_RIGHT <39> HP_LEFT <39> 10mil 1 HP_LEFT ALC272-GR_LQFP48_7X7 Codec Signals 39.75V +VDDA 1 2 C531 0.1K 4 GND 39.3V6K MONO_IN 12 1 <39> MIC1_R 2 2 C511 22P_0402_50V8J 2 1 0_0402_5% R429 MIC1_R 1 1 R422 20K_0402_1% C522 220P_0402_50V7K AMP_LEFT <39> 2 19 MIC2_VREFO MIC1_L <39> MIC1_L C519 2 DVDD_IO U26 3 C518 2 0.2K SENSE B GNDA GNDA 20K 10K PORT-H (PIN 32.1U_0402_16V4Z 2 2 10U_0805_10V4Z C528 25 2 40mil 1 1 2 INT_MIC_R 0.3V6K MIC1_C_R 22 4.1K 2009/07/01 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.1U_0402_16V4Z 1 2 L26 MBK1608121YZF_0603 INT_MIC_R 38 2 1 C513 0. Compal Secret Data Security Classification 5.3V6K MIC2_C_R 17 4.2K 20K 37 29 2 3 13 34 4 7 8 CBP 5 2 0_0402_5% SDATA_IN MONO_OUT <26> HDA_SDOUT_AUDIO 48 Sense Pin PCBEEP_IN 11 1 R427 <35> EAPD MIC1_R 2 1 2 0.1U_0402_16V4Z 1 <27> SB_SPKR L25 MBK1608121YZF_0603 1 2 3 560_0402_5% 2 D21 CH751H-40PT_SOD323-2 2 2 C506 R239 0_0805_5% 10U_0805_10V4Z 0.33) Issued Date Compal Electronics.3V4Z 1 <35> BEEP# C 1 Change D21 from RB751 to CH751 R431 1K_0402_1% 2 1 INT_MIC C515 2 1 2 +1.7U_0805_6. SCHEMATIC.2K_0402_5% @ 10mil +AVDD_HDA AGND 1 R466 2 0_0805_5% 1 R438 2 0_0805_5% 1 R437 2 0_0805_5% 1 R434 2 0_0805_5% 1 R426 2 0_0805_5% 1 R435 2 0_0805_5% PORT-B (PIN 21.1U_0402_16V4Z L28 1 2 FBMA-L11-201209-221LMA30T_0805 +5VS 2 2 2 0_0805_5% +5VAMP 2 1 1 10K_0402_5% 1 D32 CH751H-40PT_SOD323-2 1 1 R441 R419 10K_0402_5% +3VS 2 1 R420 2 1 2 Q38 R425 2.1U_0402_16V4Z MONO_IN 2 SHDN 5 BYP 4 HD Audio Codec 4.1U_0402_16V4Z 1 C517 AVDD2 C529 10U_0805_10V4Z 2 1 AVDD1 L27 1 2 FBM-L11-160808-800LMT_0603 C512 2 +1.3VM C524 1 3 2 10mil HP_RIGHT CODEC_VREF HP_RIGHT 1 MIC1_VREFO_L 2 HP_LEFT C525 2. Inc.11K_0402_1% <26> HDA_RST_AUDIO# RESET# <26> HDA_SYNC_AUDIO 10 SYNC Impedance SENSE A CPVEE 31 MIC1_VREFO 28 SENSE_A SENSE_B GPIO0/DMIC_DATA1/2 GPIO1/DMIC_DATA3/4 SENSE A SENSE B 47 EAPD D3 SM05T1G_SOT23-3 @ <26> 1 2 3 4 G1 G2 ACES_88266-02001 CONN@ 1 HDA_BITCLK_AUDIO SDATA_OUT SPDIFO1 DVSS1 DVSS2 HPOUT_R 32 CBN 30 VREF 27 JDREF 40 HPOUT_L 33 AVSS1 AVSS2 26 42 HDA_SDIN0_AUDIO DGND 1 R423 2 33_0402_5% HDA_SDIN0 <26> 2. 22) 10K 5.1U_0402_16V4Z R428 2 R433 2 6 C527 <39> MIC_PLUG# <39> HP_PLUG# BITCLK For EMI 1 2 MIC1_L C526 3 2 MIC2_VREFO 10U_0805_10V4Z C523 1 MIC1_C_L 21 4.7U_0805_6.2U_0402_6.5VS 15mil 1 9 1 DVDD 2 14 LINE2_L LOUT1_L 35 AMP_LEFT 15 LINE2_R LOUT_R 36 AMP_RIGHT MIC2_L LOUT2_L 39 MIC2_R LOUT2_R 41 15mil LINE1_L SPDIFO2 45 INT_MIC_R DMIC_CLK1/2 46 MIC2_C_L 16 4.01U_0402_25V7K G9191-475T1U_SOT23-5 @ C514 1 1U_0402_6. INC. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.3V4Z R424 10K_0402_5% 1 L29 1 2 FBMA-L11-201209-221LMA30T_0805 1 C544 2 R594 C545 1 IN 2 GND 3 0.3V4Z 40mil OUT 1 (output = 300 mA) 1 2 2 U27 60mil 0. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.1U_0402_16V4Z MIC2_VREFO 2 2 R421 10K_0402_5% +3VS 2 C508 1 1U_0402_6.7U_0805_6. 2009 G Sheet 38 H of 53 4 .3V6K 23 24 LINE1_R 18 LINE1_VREFO NC 43 20 LINE2_VREFO DMIC_CLK3/4 44 AMP_RIGHT <39> JMIC2 1 20K_0402_1% 1 5.A B C D E F G H 1 +VDDA C507 1 2 1U_0402_6.5VS_DVDD 1 +VDDA R430 2.2U_0402_6. INC.MB A4853 Document Number B C D E F Rev A 401817 Date: A GND Monday. INC.3V4Z +3VS_DVDD 0. September 28.

Compal Secret Data Security Classification 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.7K_0402_5% <38> MIC1_R MIC JACK D24 D28 CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2 Change D24. Speaker Conn. INC.D28 from RB751 to CH751 MIC2_R_1 3 6 2 1 MIC2_L_1 1 C551 220P_0402_50V7K 2 SINGA_2SJ-E351-S01 CONN@ 2 (HDA Jack) 4 4 2009/07/01 Issued Date Compal Electronics. September 28.1U_0402_16V4Z 1 1 C541 JSPK1 2 SPKL+ SPKL- 2 R23 R24 2 0_0603_5% 2 0_0603_5% 1 1 3 20mil 10 dB D5 PJDLC05_SOT23-3 @ +5VAMP C543 1 <38> AMP_LEFT 1 C530 2 1 3900P_0402_50V7K R458 2 0. INC. 2009 E 39 of 53 . Date: A B C D SCHEMATIC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. INC.7K_0402_5% 2 R452 4.47U_0603_10V7K AMP_C_LEFT 2 0_0603_5% 9 5 GAIN1 3 GAIN1 ROUT+ 18 SPKR+ ROUT- 14 SPKR- LOUT+ 4 SPKL+ LOUT- 8 SPKL- RIN- 20mil @ R457 100K_0402_5% SPK_R+ SPK_R- 2 0_0603_5% 2 0_0603_5% 1 1 3 GAIN0 R85 R86 D8 PJDLC05_SOT23-3 @ 1 2 SPKR+ SPKR- 2 2 GAIN0 1 AMP_C_RIGHT 17 2 0_0603_5% RIN+ 3 4 G1 G2 Left 1 ACES_88266-02001 CONN@ R456 100K_0402_5% 1 2 1 2 3 4 G1 G2 Right ACES_88266-02001 CONN@ 1 C561 2 1 3900P_0402_50V7K R465 7 1 2 2 <38> AMP_RIGHT 1 2 0.47U_0603_10V7K LINE Out/Headphone Out 21 20 13 11 1 2 NC BYPASS TPA6017A2_TSSOP20 JHP1 8 7 2 C553 HP_RIGHT <38> HP_LEFT HP_LEFT 1 R462 1 R454 HPOUT_R_1 1 2 56.47U_0603_10V7K 1 2 JSPK2 2 C542 1 @ R439 100K_0402_5% 1 R440 100K_0402_5% VDD PVDD1 PVDD2 U29 1 16 15 6 1 1 SPK_L+ SPK_L2 C562 10U_0805_10V4Z 2 A LIN+ LIN- HPF 600Hz EC_MUTE# 19 SHUTDOWN GND5 GND1 GND2 GND3 GND4 <35> EC_MUTE# 12 10 Keep 10 mil width 2 1 2 C554 0.B C D E +5VAMP Int. 0. Inc.2_0402_1% L43 HPOUT_L_1 1 2 56.MB A4853 Document Number Rev A 401817 Sheet Monday.2_0402_1% L38 C552 HP_PLUG# <38> HP_PLUG# 330P_0402_50V7K 330P_0402_50V7K 1 1 20mil <38> HP_RIGHT 2 5 4 HPOUT_R_2 2 FBM-11-160808-700T_0603 2 FBM-11-160808-700T_0603 3 6 2 1 HPOUT_L_2 MIC1_VREFO_L MIC1_VREFO_L 2 2 SINGA_2SJ-E351-S03 CONN@ 3 3 1 1 1 1 1 R455 1 R436 <38> MIC1_L 2 1K_0603_1% 2 1K_0603_1% 1 L37 1 L36 MIC_PLUG# 5 4 2 2 FBM-11-160808-700T_0603 2 FBM-11-160808-700T_0603 1 C550 220P_0402_50V7K JMIC1 8 7 <38> MIC_PLUG# R453 4. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.

2M_0402_5% +1.5V 1 C885 2 @ 3 2 S +1.8VS_GATE 2 1 R275 @ 200K_0402_5% R337 470_0603_5% 1 2 10U_0805_10V4Z 1 +VSB 1 3 10U_0805_10V4Z 1 @ @ C883 10U_0805_10V4Z 2 2 1U_0402_6.3V4Z 3 2 R288 100K_0402_5% 2 D D D D 2 C884 @ 1 1 C882 @ 1 1 U40 8 7 6 5 D 2 G Q27 S 2N7002_SOT23 <35> SBPWR_EN 3 6.05VS C566 1000P_0402_50V7K 2 1 2 +3VS 1 C567 @ 0.41.46> SYSON 1 D 9/1 For PVT2 3 2 1 R558 200K_0402_5% 1 SUSP 1 D D 2 1 R299 33K_0402_5% +VSB SYSON# <34> SYSON# Q26A 1 100P_0402_50V8J 10U_0805_10V4Z 2 2 2 2 1000P_0402_50V7K 10U_0805_10V4Z C318 10U_0805_10V4Z 1000P_0402_50V7K 2 2 2 2 1U_0603_10V4Z 100P_0402_50V8J 5VS_GATE 1 C361 1 1 2 C379 AP4800_SO8 1 6 1 C363 1 1 1 C117 C362 1 1 1 8 7 6 5 1 1 1 2 3 4 S S S G 1 C439 D D D D 2 U15 8 7 6 5 2N7002_SOT23 +3VS SUSP D 2 2 G Q46 S 2N7002_SOT23 R267 470_0603_5% 2N7002DW-T/R7_SOT363-6 1 R286 10K_0402_5% 2 2 D +VSB 1. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. September 28.5V DDR3 +1. Inc. INC.8V 2 G Q29 S 2N7002_SOT23 @ <18.49> SUSP# 1 2 2 G Q52 S 2N7002_SOT23 2 SUSP G Q51 2N7002_SOT23 +5VALW 0.35.1U_0603_25V7K 1 3 3 Reserve for EMI request D 1.8V to +1.1U_0402_16V4Z 2 C565 @ 0.45. 2009 E 40 of 53 .37.988A R586 2.5VS SBPWR_EN# <28> SBPWR_EN# 2 D 1 1 +1.8VS 2009/07/01 Issued Date Compal Electronics.1U_0402_16V4Z 1 2 B+ B++ 1 C564 @ 0.A B C E +3VALW TO +3V_SB(ICH8M AUX Power) +5VALW +3VALW +5VS +5VALW +3V 2 +5VALW TO +5VS D U10 C116 R298 @ 470_0603_5% C226 1 D D D D S S S G R287 100K_0402_5% 1 2 3 4 C176 1 C177 1 R198 470_0603_5% AP4800_SO8 10U_0805_10V4Z 2 2 1U_0603_10V4Z 2 10U_0805_10V4Z 1 SBPWR_EN# Q47 2 3 S 0.1U_0603_25V7K +5VALW S 2 3 3 2 G 3V_GATE 2 1 R199 200K_0402_5% +VSB 1 S C351 2 SUSP G Q48 @ 2N7002_SOT23 SYSON <35.1U_0603_25V7K 1 1 9/1 For PVT2 2 SUSP G Q32 2N7002_SOT23 5 <35.8VS +1.8V +1.8VS 1 2 3 4 S S S G C886 @ AP4800_SO8 @ SUSP 2 Q54 G 2N7002_SOT23 S 1 D 2 SUSP G Q53 2N7002_SOT23 +1. Compal Secret Data Security Classification JUMP_43X118 2010/07/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.1VS DDR3 Pre-MP 9/17 2 1 1 1 R587 470_0603_5% D 2 SUSP G Q58 2N7002_SOT23 @ S D 2 SYSON# G Q16 @ 2N7002_SOT23 S 3 S R259 470_0603_5% 1 1 D 2 SUSP G Q24 2N7002_SOT23 3 S @ 1 D 2 SYSON# G Q59 2N7002_SOT23 2 2 2 3 S 4 R611 470_0603_5% @ 1 1 1 D For HM51 R283 470_0603_5% 1 R612 470_0603_5% 3 D 2 G Q55 S 2N7002_SOT23 @ 3 ACIN 3 1 2 2 @ 2 SUSP G Q56 2N7002_SOT23 4 For HM51 J3 2 +1.1U_0402_25V4K 1 +1.8V 2 1 1 +1.MB A4853 Document Number Rev A 401817 Sheet Monday.5V C563 @ 0.2M_0402_5% @ 1 1 S S S G 1 C436 10U_0805_10V4Z 2 2 1U_0603_10V4Z AP4800_SO8 10U_0805_10V4Z 2 2 10U_0805_10V4Z 2 1 D D D D 3 C437 8 7 6 5 1 2 S S S G 1 C429 1 Q26B U12 D D D D 1 2 3 4 1 1 C430 1 +1.1U_0603_25V7K 2 G Q50 S 2N7002_SOT23 2 2 SBPWR_EN# G Q49 2N7002_SOT23 R284 100K_0402_5% 2N7002DW-T/R7_SOT363-6 C195 2 1 D 2 0. INC. Date: A B C D SCHEMATIC. INC.5VS 2 U22 8 7 6 5 SUSP <37> SUSP @ 1 2 R244 0_0805_5% +1.5V to +1.5V 3 +3VALW TO +3VS +3VALW 1 R285 100K_0402_5% +1.75VS +1. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.27. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.45.46.5VS_GATE 2 1 R266 510K_0402_5% 1 C391 0.1U_0402_16V4Z 0.1U_0603_25V7K R300 100K_0402_5% 3 3 SUSP D S C314 2 3 1 C310 10U_0805_10V4Z 2 2 1U_0603_10V4Z AP4800_SO8 S 3VS_GATE C313 1 1 10U_0805_10V4Z 2 2 10U_0805_10V4Z D 2 1 R365 270K_0402_5% +VSB C309 1 C315 4 R385 470_0603_5% 1 2 3 4 R297 2.44> ACIN +1.05VS +0.1U_0402_16V4Z 2 C568 @ 0.

H-->L 16.5VP 2 JUMP_43X118 Issued Date 2009/07/17 Deciphered Date 1 4 +1. Inc.05VSP JUMP_43X118 1 OUT 1 3 2 2 JUMP_43X118 +5VALW JUMP_43X118 PR15 200_0603_5% PU2 G920AT24U_SOT89-3 3.05VSP 2 PC9 10U_0805_10V4Z 2 PJ7 2 +1.5VP +1.75VS JUMP_43X79 1 IN GND 2 PJ6 1 1 +1.976V L-->H 17.3V 4 +VGA_CORE 3 PJ5 RTCVREF +CHGRTC 1 1 JUMP_43X118 PJ3 +VSBP PR17 560_0603_5% 1 2 +VGA_CORE PJ17 2 +VGA_COREP JUMP_43X39 PR16 560_0603_5% 1 2 1 1 JUMP_43X118 2 2 PC7 0.22U_1206_25V7K 2 PR14 22K_0402_1% 1 2 2 +VGA_COREP PJ2 N1 PR13 100K_0402_1% PJ18 +3VALW 680P_0402_50V7K PC130 1000P_0402_50V7K 2 2 PR12 200_0603_5% 1 2 PR11 68_1206_5% 1 CHGRTCP PR10 68_1206_5% +1.27.05VS 2 2 1 +1. INC.728V 18.75VSP 2 1 1 +0.8V 2 2 2 PJ4 1 1 +VSB 2 +0.1VSDGPU VIN <38> 2 3 1 <37> 51ON# 100P_0402_50V8J 1 2 PC131 1 2 PC100 1 2 VS 1 1 2 2 2 +1.38> BATT+ 1 1 PJ1 2 +3VALWP 3 2 JUMP_43X118 2 1 1 PJ8 +1. INC.384V ML1220T13RE PJ16 2 +1.5K_0402_1% PR6 0_0402_5% 1 2 4 1 1 PC2 100P_0402_50V8J 2 PC1 1000P_0402_50V7K PC3 100P_0402_50V8J 2 2 PJP1 2 3 1 2 1 G G 1 VIN <38> DC231000500 PR9 10K_0402_5% 1 2 2 1 1 D PC5 1000P_0402_50V7K 2 A RTCVREF 2 Vin Dectector - Min. 17.901V Max.44> ACIN 1 PC4 1000P_0402_50V7K PR3 84.8VP 2 +5VALWP PC8 0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.1U_0603_25V7K 2 1 1 2 8 PR5 22K_0402_5% 1 2 2 PD1 GLZ4.5V 1 Compal Electronics. Compal Secret Data Security Classification 2 JUMP_43X118 2009/07/17 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.MB A4853 Rev A 401817 Date: A B C Monday.1U_0603_25V7K 2 1 1 1 1 +1. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. 2009 D Sheet 41 of 53 .430V + PBJ1 2 1 +RTCBATT +RTCBATT Typ 17. SCHEMATIC.40. INC.35.5V 1 JUMP_43X118 2 N2 1 PJ9 PC10 1U_0805_25V4Z 2 +1.525V 17. September 28.B C <38> VIN 2 <38> VIN VS 1 PL1 SMB3025500YA_2P 1 DC_IN_S1 1 PR1 1M_0402_1% 1 2 1 SINGA_2DC-G756I200 @PR2 @ PR2 10K_0402_5% P 2 2 PR7 20K_0402_1% PC6 0.3B_LL34-2 2 3 - 0 PU1A LM358DT_SO8 PR8 10K_0402_5% + G 2 PR4 10K_0402_1% 1 2 1 1 <18. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.05VS +1.1VS 2 PQ1 TP0610K-T1-E3_SOT23-3 1 1 1 PD3 LL4148_LL34-2 2 1 1 1 JUMP_43X118 PD2 LL4148_LL34-2 <36.

42> PC16 0.4K_0402_1% 2 @ PC18 @PC18 0. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.38> 1 BATT_S1 1 2 3 4 5 6 7 8 9 2 1 2 3 4 5 6 7 GND GND 1 PJP2 1 PL2 SMB3025500YA_2P 1 2 1 2 2 BATT_TEMP <35> PH2 near main Battery CONN : BAT. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. September 28. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.01U_0402_25V7K 2 PC12 1000P_0402_50V7K MAINPWON <26.43> PR19 100K_0402_1% 1 2 1 1 EC_SMCA EC_SMDA 1 PC11 2 PH1 1 BATT+ <35.7K_0402_1% 1 2 EC_SMDA 6 + O @ PR33 @PR33 15. INC.3K_0402_1% 2 1 PR25 6.A B C D PH1 under CPU botten side : CPU thermal protection at 90 degree C Recovery at 70 degree C 2009_08_06 (0603->0402) PCBfootprint for Layout VL VL Change P/N for 0402-100K VL 2 VMB <38> PR18 100K_0402_1% TM_REF1 2 + P 3 - PU3A LM393DG_SO8 1 2 LL4148_LL34-2 3 4 2 1 PR26 100K_0402_1% 2 2 PR27 1K_0402_1% PR24 100K_0402_1% 2 1 VL 1 1 2 PC15 1000P_0402_50V7K 1 2 1 +3VALWP PR23 11.22U_1206_25V7K PQ3 TP0610K-T1-E3_SOT23-3 PR34 100K_0402_1% D S PQ4 SSM3K7002FU_SC70-3 2 1 2 G PC19 0.1U_0603_25V7K 3 @ 2 2 PR32 22K_0402_1% 1 2 VL 2 PR30 100K_0402_1% 1 1 B+ <36.1U_0402_16V7K 1 <43> SPOK 1 4 PR35 0_0402_5% 1 2 3 4 Issued Date Compal Electronics.40. Compal Secret Data Security Classification @ 2009/07/17 Deciphered Date 2009/07/17 Title SCHEMATIC.49K_0402_1% 2 1 1 PC14 0. Inc.39. INC.37. 2009 D Sheet 42 of 53 . thermal protection at 90 degree C Recovery at 70 degree C EC_SMB_CK1 <35> EC_SMB_DA1 <35> VMB <38> VL 2009_08_06 (0603->0402) PCBfootprint for Layout 2 Change P/N for 0402-100K PJP3 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 18 18 19 20 20 @ PH2 VL 100K_0402_1%_NCP15WF104F03RC PR31 @ 13.22U_0603_16V7K 2 2 1 PR22 100_0402_1% PD4 O SUYIN_200045MR007G180ZR_7P-T PR21 100_0402_1% PQ2 DTC115EUA_SC70-3 8 PR20 18K_0402_1% 1 2 G 2 100K_0402_1%_NCP15WF104F03RC PC13 0. Rev A 401817 Date: A B C Monday.22U_0603_16V7K - @PD5 @ PD5 LL4148_LL34-2 2 1 7 3 PU3B LM393DG_SO8 2 19 5 TM_REF1 1 3 17 1 4 6 8 4 5 P 3 5 G 3 @PR29 @ PR29 47K_0402_1% 1 2 4 2 1 2 2 1 1 EC_SMCA @ PR28 @PR28 47K_0402_1% VL 1 SUYIN_200109MS020G209ZR +VSBP 1 1 2 2 @ PC17 0.38. INC.

22U_0603_10V7K 8 +3. Imax=0.9089A (Freq=300KHz) PR42 61.42> MAINPWON NC 1 1 PR48 200K_0402_5% 1 2 4 VL + PC35 220U_6.7A_20% 2 1 PC34 680P_0402_50V7K 2 1 DRVH2 24 5 6 7 8 26 PC29 1U_0603_10V6K 1 2 19 2 7 LDO 3 V5FILT 6 VIN TP PC31 0.047U_0603_16V7K 3 28 14 @ PR51 0_0402_5% 2 2 PR55 0_0402_5% 2 A PGOOD2 2 1 PC37 0.42> 3 2 1 DH5 PR39 2.37.3VALWP Ipeak=5.1U_0603_25V7K LX3 PC23 4.7A_20% 1 2 1 1000P_0402_50V7K PR36 0_0805_5% 1 2 PC22 2200P_0402_50V7K 2 1 1 PC20 4.2_0603_5% BST5A 2 1 PC32 0.454A Delta I=0.97A .7*Ipeak=3.7U_1206_25V6K 2 1 PC21 4. Rev A 401817 Date: 5 4 C SPOK <42> ILM1 2VREF_ISL6237 2 2VREF_ISL6237 1 1 2 5 EN2 PC38 1U_0603_10V6K 1 2 27 2 PR52 0_0402_5% 2 EN1 1 1 @ PR56 47K_0402_5% 1 2 1 PC39 0.7U_1206_25V6K 2 1 PL14 FBMA-L11-322513-151LMA50T_1210 1 2 2 PC126 100P_0402_50V8J PJ10 JUMP_43X118 2 2 1 1 +3VALWP B ISL6237_B+ 12/25_DVT_EMI PL13 HCB4532KF-800T90_1812 1 2 D ISL6237_B+ ISL6237_B+ B++ B+ 3 2 Monday.6m ohm. INC.3V_M 2 FB5 PR46 1 PD7 1SS355_SOD323-2 1 VREF2 SKIPSEL PD6 GLZ5. Compal Secret Data Security Classification 2009/07/17 Issued Date Deciphered Date 2009/07/17 Title SCHEMATIC. INC.879A Choke DCRmax=33.7U_1206_25V6K 2 1 5 6 7 8 PC28 4.047U_0402_16V7K PQ9 TP0610K-T1-E3_SOT23-3 2 1 A Compal Electronics.921A (Freq=400KHz) @ PC40 0.7_1206_5% 2 1 DRVH1 VBST2 PL3 10UH_1164AY-100M=P3_4.7*Ipeak=4. 2009 Sheet 1 43 of 53 .7_1206_5% 1 PC30 330U_6.3V_M PL15 FBMA-L11-322513-151LMA50T_1210 1 2 8 7 6 5 1 PC127 2 PL4 10UH_1164AY-100M=P3_4.9K_0402_1% 1 2 17 PR44 10K_0402_1% 1 2 15 VBST1 PR41 4. INC.460A Delta I=0.627A ~ 11. Inc.5 4 3 2 1 <36.7U_1206_25V6K 2 1 VL 0_0402_5% 2 SN0806081RHBR_QFN32_5X5 PR54 0_0402_5% PR49 330K_0402_1% 2 1 2 B 1 PR50 330K_0402_1% +5VALWP Ipeak=6.22U_0603_25V7K PR53 806K_0603_1% <26.1B_LL34-2 1 2 @ 0.167A ~ 11A Iocp=Ilimit+Delta I/2 =9.38. Rds(on)=15m ohm(typical) Vlimit=(5E-06 * 330K)/10=165mV Ilimit=165mV/18m ~ 165mV/15m =9.40.507A Choke DCRmax=33.01A .3V6K 2 1 PC27 1U_0603_10V6K 1 2 2 1 2 33 V5DRV D +5VALWP 2 C DH3 PR38 2 1 BST3A 2. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. DCRtyp=28m ohm Rds(on)=18m ohm(max) .2_0603_5% PQ6 AO4466_SO8 4 1 1 1 4 PC33 680P_0402_50V7K VL 1 2 3 8 7 6 5 2 PQ7 AO4712_SO8 2 2 PC26 0.1U_0603_25V7K PU4 1 2 PR40 0_0402_5% + PQ5 AO4466_SO8 4 PR37 4. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. DCRtyp=28m ohm Rds(on)=18m ohm(max) .6m ohm.39.621A ~ 11. Rds(on)=15m ohm(typical) Vlimit=(5E-06 * 330K)/10=165mV Ilimit=165mV/18m ~ 165mV/15m =9.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. Imax=0. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.1U_0603_25V7K LL1 16 DRVL1 18 DL5 LL2 4 1 2 3 3 2 1 25 LX5 PQ8 AO4712_SO8 DL3 23 DRVL2 FB3 @ PR43 10K_0402_1% 1 VL 30 VOUT2 32 REFIN2 PGND 22 VOUT1 10 FB1 11 VSW 9 2VREF_ISL6237 1 PC36 2 1 20 PR47 100K_0402_1% 1 2 LDOREFIN @ PR45 2 29 EN_LDO PGOOD1 13 2 GND TRIP1 12 TRIP2 31 ILIM2 21 TONSE 2 1 VREF3 0_0402_5% 1 1000P_0402_50V7K 1 2 PC129 2 1 PC128 100P_0402_50V8J PC25 2200P_0402_50V7K 2 1 PC24 4.7U_0805_6.167A ~ 11A VS Iocp=Ilimit+Delta I/2 =9. September 28.

5V 2 1 2 2 2 2 2 4 3 100K_0402_1% 24751_VREF PQ20@ SI2301BDS-T1-E3_SOT23-3 PR83 499K_0402_1% ACSET 1 1 2 1 IREF=0.8*2*2.9K_0402_1% 1 PC51 LL4148_LL34-2 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.8C=0.7_1206_5% 2 PR69 340K_0402_1% 3 3 S PC55 0.1U_0603_25V7K 2 JUMP_43X118 CHGEN# 5 6 7 8 3 2 3 2 1 2 1 1 2 2 4 PR62 340K_0402_1% 1 2 PJ11 1 PC46 0.1% @ 1 EVT_02_03 PR86 100K_0402_1% <35> CALIBRATE# ACIN <18.3_1210_5% 1 2 3 PR57 0.40.015)=2. Icharge=0.36> PC57 10U_1206_25V6M 2 24751_VREF SI2301BDS-T1-E3_SOT23-3 90W adapter Vacset=3.9K+100K))=2.1/0.84A Icharge=(Vsrset/Vdac)*(0.9K_0402_1% CP Point Setting BATT+ 1 OVPSET 3 1 2 8 4 2 2 PC54 1U_0603_10V6K 1 OVPSET PQ15 2 3S/4S# <35> G SSM3K7002FU_SC70-3 Cells selector 3 24 ACOP 1 PR66 4.4*2=3.A B C D B+ 9 AGND DL_CHG LODRV 23 PGND 22 LEARN 21 CELLS 20 CELLS PC61 1U_0603_10V6K 11 VDAC 2 2 17 TP 29 2 1 PR72 17.41> 2 PR84 @ 0_0402_5% 1 2 ACGOOD# 1 PR82 @ 887K_0402_1% @ PR77 @PR77 100K_0402_1% 3 1 PR80 1 REGN 1 LI-4S :18.52A For 2400mA. INC.5012V BATT-OVP=0.8132V 4.38.1/PR56)=4.3*(100K/(64.01U_0402_25V7K 6 For 2200mA.39. INC. 2009 D Sheet 44 of 53 .27.1U_0603_25V7K REGN 2 3 Cell 1 2 PR67 47K_0402_1% GND 1 PR64 0.26V 3 0.9K))=1.3 2 2 G 3 <35> 65W/90W# PR93 100K_0402_1% S CP setting A 4.35.436V PR92 100K_0402_1% VREF 2 PQ15_GATE CP point=Iadapter*85% CP Point=(Vacset/Vvdac)*(0.01U_0402_25V7K 3 2 1 ACN ACP ACDET 24751_VREF CHG_B+ 1 5 6 7 8 28 1 CHGEN 0.1U_0402_16V7K PC65 ACOFF 1 SRP 24751_VREF PR73 100K_0402_1% 2 1 Input OVP : 22.2V 1.3*(50K/(50K+64.1112*VMB(18) LI-3S :13. September 28.8C=0.1U_0603_25V7K 2 1 PC50 2.01U_0402_25V7K 2 G PR78 340K_0402_1% 2 1 Fsw : 300KHz 19 VADJ D 2 G @PC60 @PC60 0.3_1210_5% <36.001V BATT-OVP=0.3V 2.1U_0603_25V7K Vacset=3.40.01U_0402_25V7K VIN 1 <35> PQ10 AO4407A_SO8 4 1 2 4 D PQ23 SSM3K7002FU_SC70-3 VBATT Calibrate# VDAC=3.3)*(0.1/PR64) IREF=((100k/(100K+17.3V)*(0. Inc.2_0603_5% 1 2 PC44 2200P_0402_25V7K BTST 1 27 PC43 4.0V----BATT-OVP=2.1U_0402_16V7K 1 2 2 PR61 3.001V 2 2 PQ14 AO4466_SO8 4 PR70 54.5) Per cell=4.1% 2 1 PR87 210K_0402_0.37. SCHEMATIC.4K))/3.5V----BATT-OVP=1.4K_0402_1% 2 1 2 2 24751_VREF 2 3 1 1 D S 2 G @ PQ19 SSM3K7002FU_SC70-3 VADJ 24751_VREF 2 1 PR89 100K_0402_1% 1 CHGEN# D S PQ22 SSM3K7002FU_SC70-3 2 G <35> FSTCHG 1 3 EVT_02_03 S PC68 @ 1000P_0402_50V7K 3 PQ21 @ SSM3K7002FU_SC70-3 2 2 1 1 D 2 G PR88 499K_0402_0.8755V 4.1U_0603_25V7K 1 1 D /BATDRV PQ15_GATE 3 2 12 13 1 PR74 200K_0402_1% 2 1 1 Input UVP : 17.436V/3.8*2.3 Issued Date Compal Electronics.7748*Icharge 1 @PR81 @ PR81 0_0402_5% 1 PR79 340K_0402_1% PR91 105K_0402_1% 1 IREF <35> RTCVREF ADP_I <35> PC69 0.42> 8 7 6 5 2 1 1 1 2 2 4 PR58 3.02)=Icharge @PC64 @PC64 0. Icharge=0.35V H=3.1U_0603_25V7K G PR90 64.1U_0805_25V7K 1 2 Place close to back to back MOS CELLS PC42 4. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.1U_0402_16V7K 1 2 1 1 1 PR71 24751_VREF 10 <35. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.1/0.02_2512_1% PL5 10UH_PCMB104T-100MS_6A_20% 1 2 2 LX_CHG PD8 2 PC53 10U_1206_25V6M 25 3 2 1 PH 1 ACDRV ACDET 2 4 5 4 1 ACDRV /BATDRV 5 6 7 8 DH_CHG 1 PQ12 AO4407A_SO8 PC52 10U_1206_25V6M 26 2 HIDRV 1 ACN ACP PR59 100K_0402_1% PQ13 AO4466_SO8 4 PC56 680P_0402_50V7K 2 3 1 PR63 2.3V ACGOOD# 24751_VREF CP POINT=(1.7U_1206_25V6K PVCC PC41 0. Compal Secret Data Security Classification 2009/07/17 Deciphered Date 2009/07/17 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.47U_0603_16V7K 1 2 7 2 @ PR68 @PR68 0_0402_5% 1 2 1 1 D ACSET REGN CELLS 2 6 1 4 Cell ACSET 2 2 VREF PR65 54.04A 2 ACOFF <35> 2 PQ16 100K_0402_1% 65W adapter R=(100K*100K)/(100K+100K)=50K 1 PC58 0.9K_0402_1% 24751_VREF 1 2 SE_CHG- BAT S <35> BATT_OVP PR85 10K_0402_1% 1 2 SE_CHG+ 18 IADAPT PQ17 SSM3K7002FU_SC70-3 PC67 0.2=3.901A VADJ ACSET PC59 0.0V L=0 4.1112*VMB(13.01U_0402_25V7K 1 PC66 100P_0402_50V8J 1 - PR76 100K_0402_1% BQ24751ARHDR_QFN28_5X5 2 2 G 8 P 5 15 PR75 10_0603_5% 1 2 BATDRV D + SRSET 1 SRSET 16 1 VS PU1B LM358DT_SO8 7 0 14 VMB <36> PQ18 SSM3K7002FU_SC70-3 2 Icharge Setting ICHG setting ACGOOD 2 S 1 S 2 1 PC62 0.015_2512_1% 4 1 2 3 PR60 100K_0402_1% 8 7 6 5 PQ11 AO4407A_SO8 PC45 0.7U_1206_25V6K 2 BTST 1 PC47 0.2U_0805_25V6K 1 PVCC PU5 1 PC49 PC48 0.MB A4853 Rev A 401817 Date: B C Monday.1U_0603_25V7K SRN 2 PC63 0. INC.

46> SYSON 4 PR95 300K_0402_5% 1 2 <36.75V 7 4 DRVH PGND VOUT 8 TON 3 PR105 PC78 2.198 =0. 1.3V_M 2 2200P_0402_50V7K PC124 PR116 10K_0402_1% 1 2 PR160 4.5VP DL_1.35us Fsw=261KHz(by caculation tool) 4 GND 1 <37. INC.2_0603_5% 0.7U_1206_25V6K 3 2 1 2 @ 1 @ PQ26 AO4466_SO8 2 1 B+ 1 HCB4532KF-800T90_1812 2 Green outline (For DDR3 changed) PR110 10K_0402_5% <Vo=1.5V Ton=19*e-12*143000(((2/3)*Vo+100mV)/19)+50ns =2.5 2 14 VBST 15 3 2 1 S S S PGOOD V5DRV PL7 1 1 6 TRIP 2 VFB LX_1.198A Vtrip=Rtrip*10uA=18K*10uA=0.5V> VFB=0.05VSP_1.38.0892A Iocpmax=(0. INC.5 2 + PC74 4.2073A 2 5 6 7 8 PR101 10K_0402_1% <35.75V Vo=VFB*(1+PR108/PR109)=0.3A Delta I=((19-1.39.7U_0805_10V6K PR108 12K_0402_1% 1 2 4 2 PC83 1U_0603_10V6K 3 2 +5VALW PQ27 FDS6670AS_NL_SO8 G PR109 30K_0402_1% 1 4 2 VFB=0.5VP-1 1 2 PR99 18K_0402_1% VOUT VBST 15 TP 1 EN_PSV TON 3 BST_1.5VP 2 PC76 1U_0603_10V6K 2 8 PR98 300_0402_5% 1 2 1 +5VALW @PC72 @PC72 0.009*1.05VSP 2 1UH_PCMB103E-1R0MS_20A_20% PR161 4.5m Ipeak=11.7U_0805_10V6K PC119 680P_0402_50V7K 2 <36.3A.5x3.37.8UH_SIL104R-1R8PF_9.75V Vo=VFB*(1+PR116/PR117)=0.64A Iocp=13.1U_0402_16V7K EN_PSV PU7 PR106 300_0402_5% 1 2 PC120 680P_0402_50V7K PC81 4.42> PQ25 FDS6670AS_NL_SO8 2200P_0402_50V7K PC125 1 5 6 7 8 SUSP# PC70 4. Compal Secret Data Security Classification 2009/07/17 Deciphered Date 2009/07/17 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.15/(0.05/19))/(L*Fsw)=2.3)+1.5VP 2 1 5 VFB=0.40..055A=16.15V Iocpmin=Vtrip/Rdsonmax*1.198A=22.198=13.5VP 2 4 PR97 PC71 2.5V 12 PR107 15K_0402_1% V5FILT 13 LL VFB=0.5V 11 1 5 DH_1.05VSP_1.98A Iocpmax=(0. INC.75*(1+10K/10K)=1.1U_0603_25V7K 1 2VBST_1.5/19))/(L*Fsw)=2. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.011*1.7_1206_5% 1 + 1 2 +5VALW PC80 330U_D2E_2.05VSP_1.MB A4853 Rev A 401817 Date: A B C Monday. SCHEMATIC.37..2073A Iocp=11.7_1206_5% +5VALW 1 PGND 12 TRIP 1 6 @ PC75 @PC75 47P_0402_50V8J 1 2 13 LL 2 VFB +1.49> VS_ON PR104 0_0402_5% 1 2 @ 2 D D D D 5 6 7 8 PC77 4.055=11.7U_1206_25V6K 1 Issued Date Compal Electronics.64A PU6 GND 1 2 VFB=0. September 28.1U_0402_16V7K 7 <Vo=1.075/(0.40.075/(0.5m Rdson(min)=9m Ipeak=9A.2Ipeak=13.49> SUSP# PC73 330U_6.56A . Imax=Ipeak*0..75*(1+12K/30K)=1.05)*(1.46.5V 1 2BST_1.05V> VFB=0.5A_30% DH_1.39.)=11.5VP 1 DRVL 1 TPS51117RGYR_QFN14_3.11A =>1/2DeltaI=1.5VP_B+ G 3 2 1 PR112 0_0402_5% 1 2 <35..05VSP_1.0892A~16. Inc.75*(1+12K/30K)=1.7=6.B C D 5 6 7 8 A PQ24 AO4466_SO8 4 @ PR162 1 3 2 1 0_0402_5% 2 D D D D 1 2 S S S PGOOD 14 LX_1.40.5)*(1.98~22.75V Vo=VFB*(1+PR108/PR109)=0.35us Fsw=262KHz 2 PL16 FBMA-L11-322513-151LMA50T_1210 1 2 1.015*1.15/(0.5VM 2 DL_1.5VPGOOD PL12 1 1.1U_0603_25V7K BST_1.3)+1.05V Fsw=261KHz Cout ESR=15m ohm Rdson(max. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.91A Delta I=((19-1.055A Vtrip=Rtrip*10uA=15K*10uA=0.75V Vo=VFB*(1+PR116/PR117)=0.018*1.05VSP_B+ 1 2 4 for HW pwr bdget updated PR103 300K_0402_5% 1 2 3 DRVL 9 1 10 1 +1.40.2_0603_5% 0.5V-1 1 2 2 1 @ PC82 @PC82 47P_0402_50V8J 1 2 2 TP 1 PC79 0.5V Fsw=262KHz Cout ESR=15m ohm Rdson(max)=9m Rdson(min)=11.75V DRVH 2 V5FILT PL6 1 B++ 1.5x3.1))+1.05V TPS51117RGYR_QFN14_3.1))+1.42> <37> +1.3969A =>1/2DeltaI=1. 2009 D Sheet 45 of 53 .3+1.05V Ton=19*e-12*143000(((2/3)*Vo+100mV)/19)+50ns =2.05V DL_1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.645e-7 us =>Vo/Vin=D=Ton/Ts =>Ts=3.37.18V Iocpmin=Vtrip/Rdsonmax*1.5VP 11 V5DRV 10 9 DL_1.75*(1+10K/10K)=1.38.2+1.645e-7 us =>Vo/Vin=D=Ton/Ts =>Ts=3.055 =0.Imax=7.

Compal Secret Data Security Classification Deciphered Date 2009/07/17 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.7U_0805_6. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_25V6 2 1 1 @PC150 @PC150 0.49> 1 2 PR198 0_0402_5% 1 2 PR200 402K_0402_1% 2 1 Cange TPS51117 to MP2121 SYSON <35. SCHEMATIC. INC.3V6M 2 5 SW 8 1 IN 9 1 SW 4 10 GND 2 PR201 0_0402_5% 3 EN/SYNC 2 2 GND PC156 22U_0805_6. 2009 Sheet 1 46 of 53 .3V6M 2 1 1 FB 2 2 2 PC154 10U_0805_10V4Z JUMP_43X79 1 PD11 B340A_SMA2 2 2 PC153 10U_0805_10V4Z 1 2 2 1 @ 1 PC152 0.1U_0402_16V7K 1 +0. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.8VP 2 316K_0402_1% PR199 C SUSP# <35.5A_20% 1 2 PC155 22U_0805_6.MB A4853 Rev A 401817 Date: 5 4 3 2 Monday. Inc. INC.5V PJ14 JUMP_43X79 B 2 1 B 6 NC 5 3 REFEN NC 7 4 VOUT NC 8 GND 9 +3VALW 1 VCNTL GND 2 2 PR118 1K_0402_1% 1 PC91 4.45> 1 RT9173DPSP_SO8 FOR DDR3 demand PC95 10U_0805_6.75VSP 2 PR120 1K_0402_1% PC93 0.3V6K VIN 2 1 2 2 PU9 1 PC92 1U_0603_6.37.3V6M A A 2009/07/17 Issued Date Compal Electronics.45. September 28.8VP 11 PR202 4.7_1206_5% @ MP2121DQ-LF-Z_QFN10_3X3 1 BS PL19 2.40.1U_0402_16V7K 1 PJ19 +5VALW Delete PJ12 & B++ PU13 1 +1.40.2UH_MSCDRI-74A-2R2M-E_6.45> PC157 680P_0603_50V7K FOR DDR3 demand Green outline (For DDR3 changed) 1 +1.1U_0402_16V7K 1 PC151 0.40. INC.3V6M S 2 3 PC94 0.1U_0402_16V7K 2 1 D 1 PQ30 2N7002W-T/R7_SOT323-3 2 G 1 PR119 0_0402_5% 1 2 SUSP 2 <35.5 4 3 2 1 D D @PR113 @ PR113 0_0402_5% 1 2 IN 7 POK TP 6 C +1. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.

2_0603_5% PC115 UGATE_CPU2 0. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.22U_0603_10V7K 3 PC96 10U_1206_25V6M 2 1 +CPU_B+ CPU_DPRSLPVR 1 2 PR126 499_0402_1% 1 0_0402_5% CPU_VR_ON 2 PR130 CPU_CLK_EN# 1 1 PR125 1CPU_VREF 0_0402_5% 0_0402_5% 1 0_0402_5% 2 2 CPU_ISLEW 2 1 PR127 124K_0402_1% CPU_OSRSEL 2 C CPU_V5FILT PC101 1U_0402_6.91K_0402_1% D A A 2009/07/17 Issued Date Compal Electronics.8K_0402_1% 2 PH32 1 2CPU_SN-1 1 PR136 28.36UH_PCMC104T-R36MN1R17_30A_20% 1 4 3 2 1 LGATE_CPU1 DRVL1 CSN1 4 3 2 1 BOOT_CPU1 1 PR135 2BOOT_CPU1-1 1 2 2.26> H_DPRSTP# PSI# Change P/N for 0402-100K CPU_VID6 <5> 2 PR147 100_0402_1% <5> PR143 20K_0402_1% 13 VSNS DPRSTP# CSP2 1 PC109 5 6 7 8 PU10 TPS51620RHAR_QFN40_6X6 9 @ CPU_CSN1 6 GNDSNS B+ 1 CPU_CSN2 26 CPU_CSP1-1 2 CPU_CSP1 27 V5IN 8 <36.8.40.35. Inc.3V6K @ VR_ON +5VS 1 PR124 0_0402_5% +3VS <8.8K_0402_1% 2 1 PQ36 SI4634DY-T1-E3_SO8 2 1 2 1 3 2 1 5 6 7 8 4 1 +CPU_CORE 3 2009_08_06 (0603->0402) PCBfootprint for Layout CPU_CSP2 3 2 1 3 2 1 4 PQ35 SI4634DY-T1-E3_SO8 1 2 +5VS PD10 1SS355_SOD323-2 VID0 VID1 PR158 4.8K_0402_1% 1 2 PH42 1 2CPU_SN-2 1 PR148 28.7K_0402_1% 100K_0402_1%_NCP15WF104F03RC 1 2 PC116 0. INC. SCHEMATIC.37> PM_DPRSLPVR <8. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.27> @ 2 CPU_TONSEL 2 PR128 CPU_TRIPSEL 2 PR129 1 PR123 @ 0_0402_5% <27. INC.38.27> VGATE <16> CLK_ENABLE# D 2 1 PR122 10K_0402_1% 2 1 PR121 1.16.22U_0603_10V7K 1 28 4 PQ32 SI4634DY-T1-E3_SO8 5 6 7 8 PGOOD DPRSLPVR VR_ON CLK_EN# TRIPSEL PWRMON 2 32 31 34 33 36 35 38 40 37 TONSEL OSRSEL ISLEW GND V5FILT 29 LL1 CSP1 1 VCCSENSE <5> +CPU_CORE 2 1 2 VSSSENSE PR146 100_0402_1% VBST 5 CPU_THERM 10 THERM PR142 0_0402_5% 1 1 2 PR141 0_0402_5% 2 1 B DRVH1 UGATE_CPU1 GND VR_TT# CPU_VSNS EVT_01_23 PD9 1SS355_SOD323-2 30 4 7 PL9 HCB4532KF-800T90_1812 1 2 4 VREF 12 2 CPU_CSP1-2 33P_0402_50V8J 2 CPU_CSN1-1 33P_0402_50V8J 2 CPU_CSN2-1 33P_0402_50V8J 2 CPU_CSP2-2 33P_0402_50V8J CPU_GNDSNS DROOP 11 1 CPU_CSP2 2 PR139 PC113 100P_0402_50V8J 1 470_0402_1% 1 PC106 1 PC108 1 PC110 1 PC114 2 CPU_CSN1 2 PR137 CPU_CSN2 2 PR138 PC105 100P_0402_50V8J 1 470_0402_1% 1 470_0402_1% 39 41 2 1 470_0402_1% 1 CPU_CSP1 2 PR134 PC97 10U_1206_25V6M 2 1 5 PQ31 SI7686DP-T1-E3_SO8 +5VS CPU_VREF 1 2 PR131 5.22U_0603_10V7K 1 PC122 2200P_0402_50V7K + 2 PC99 220U_25V_M PC98 2200P_0402_50V7K 2 1 5 6 7 8 PR132 17.76K_0402_1% 1 2CPU_DROOP 1 PC102 68P_0402_50V8J 1 2CPU_VREF 2 PC103 0.8K_0402_1% 2 1 1 PQ33 SI4634DY-T1-E3_SO8 1 2 PC117 680P_0402_50V7K 2 3 2 1 PC112 10U_1206_25V6M 1 2 4 PC111 10U_1206_25V6M 2 1 5 PQ34 SI7686DP-T1-E3_SO8 2 C PR133 69.3V6M 20 19 VID3 VID2 18 17 VID5 VID4 16 15 PSI# VID6 14 1CPU_DPRSTP# 0_0402_5% PSI# 1 0_0402_5% VID6 2 0_0402_5% VID5 2 0_0402_5% VID4 2 0_0402_5% VID3 2 0_0402_5% VID2 2 0_0402_5% VID1 2 0_0402_5% VID0 2 0_0402_5% 2 PR149 2 PR150 1 PR151 1 PR152 1 PR153 1 PR154 1 PR155 1 PR156 1 PR157 3 B PR145 69. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.7_1206_5% PC118 680P_0402_50V7K PR144 17.7_1206_5% +CPU_B+ +5VS 2 10U_0603_6.37. September 28. 2009 Sheet 1 47 of 53 .5 4 3 2 1 +3VS CSN2 PGND 25 DRVL2 24 LGATE_CPU2 LL2 23 PHASE_CPU2 VBST2 22 DRVH2 21 BOOT_CPU2 1 PR140 2BOOT_CPU2-1 1 2 2. INC.033U_0402_16V7K 2009_08_06 (0603->0402) PCBfootprint for Layout <5> <5> CPU_VID4 <5> CPU_VID3 <5> CPU_VID2 <5> CPU_VID1 <5> CPU_VID0 <5> CPU_VID5 <5.MB A4853 Rev A 401817 Date: 5 4 3 2 Monday.033U_0402_16V7K Change P/N for 0402-100K PL11 0.2_0603_5% PC104 PHASE_CPU1 0.7K_0402_1% 100K_0402_1%_NCP15WF104F03RC 1 2 PC107 0.42> PL10 0. Compal Secret Data Security Classification Deciphered Date 2009/07/17 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.36UH_PCMC104T-R36MN1R17_30A_20% 1 4 CPU_CSP2-1 2 PR159 4.39.

90V 2 1 1 2 VGA_PWRSEL1 <18> S +3VS @ PR192 10K_0402_1% PR183 @ 10K_0402_1% 1 PC149 0. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.2K_0402_1% 3 2 PR175 2 1 1 1 PC142 2 PR174 33K_0402_1% 2 2200P_0402_25V7K 2 22P_0402_50V8J PC140 1 1 VFB=0. Rev A 401817 Date: 5 4 3 2 Monday.134A 1.14V 0 D 10K_0402_5% 2 1 1 2 0 PR191 10K_0402_1% 2 1 2 G 2N7002W-T/R7_SOT323-3 1 3 S PQ42 3 1.49> VGA_ON 0.1U_0603_25V7K 5 1 2 LX_VCORE 1 D PC133 10U_1206_25V6M 1 2 B+ --> B++ PC132 10U_1206_25V6M FBMA-L11-322513-201LMA40T_1210 VIN 4 VCC 2 15 16 2 1 BOOT UG PHASE 3 PQ37 SI7686DP-T1-E3_SO8 PVCC 14 LG 13 PGND 12 ISEN 11 6269_VCORE PR1672 6269_VCORE 4 4.5 4 3 2 1 PL17 VGA_CORE B+_core fsw=331.5K_0402_1% FSET 9 2 6 PC139 0.01U_0402_25V7K 1 PR176 14K_0402_1% PR178 1 S 1 10K_0402_5% PR179 10K_0402_1% 1 2 2 @ PR180 PC143 10K_0402_1% 0.944A Iocp setting must higher than 13.5VM_R9M 2 2 1 8. INC.MB A4853 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.1U_0402_16V7K FB COMP EN 7 5 2 100K_0402_1% C 5 1 PR169 1 1 <37. INC. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.6K_0402_1% 2 PC141 0.06K_0402_1% B++ Rds=4. September 28.8 mOHM DCR=3m OHM DH_VCORE BST_VCORE 1 1 PR164 2 PR165 0_0603_5% 2 0_0603_5% +5VS DH_VCORE-1 1 2 PC134 0.3V6K D 330U_V_2. 2009 Sheet 1 48 of 53 . INC. Inc.62A (from HW pwr budget) Imax=8.96V PQ41 D PQ43 3 S PR194 10K_0402_1% 2 1 2 G 2N7002W-T/R7_SOT323-3 PR195 @ 10K_0402_5% VGA_PWRSEL0 <18> 1 1.2*Ipeak=13.022U_0402_25V7K 1 2 2 EVT (for Compensation setting) PQ40 2 G PR197 2K_0402_1% 1 40.7_1206_5% PC138 @680P_0603_50V7K 1 PC137 + 2 3 2 1 PR170 ISEN_VCORE 1 2 PQ38 @ D PQ39 7. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.022U_0402_25V7K 1 1 PR182 10K_0402_1% 21 2 G 2 0. Compal Secret Data Security Classification 2009/07/17 2009/07/17 Deciphered Date A @ Title SCHEMATIC.7_0603_5% 1 2 PC135 3 2 1 +3VS 1 PGOOD GND PU11 8 PR166 0_0603_5% 2.3V6K 10 3 2 1 2 EVT (for OCP setting) +VGA_COREP 1 5 D PR171 1 G S S S VO 4 G S S S 4 SI7636DP-T1-E3_SO8 1 2 SI7636DP-T1-E3_SO8 PR172 @4.2U_0603_6.944A Cesr=9 mOHM Low side Rds(on)=4.8mOHM 2 1 2N7002W-T/R7_SOT323-3 D 2 1 +3VS PR177 80.6V C B +3VS PR190 20K_0402_1% +3VS 2 2 B 1 0.2U_0603_6.675kHz Ipeak=11.20V 1 0 10K_0402_5% 2N7002W-T/R7_SOT323-3 2 D 0 @ PR181 PR193 Core Voltage Level 1 VGA_PWRSEL_1 1 VGA_PWRSEL_0 1 M92-S2 XT PR196 10K_0402_1% 1 A Issued Date Compal Electronics.56UH_ETQP4LR56WFC_21A_20% 1 2 ISL6268CAZ-T_SSOP16 PR168 10K_0402_5% 2 @ DCR=3m OHM DL_VCORE 1 2 PL18 PC136 2.

2009 Sheet 1 49 of 53 .3V6K VOUT VOUT 2 2 8 7 2 B VCNTL VIN VIN 1 2 PU12 6 5 9 @ PR189 22K_0402_5% 2 2 PC148 0.02K_0402_1% 2 <37.3V.1U_0402_10V7K 1 1 PR188 10K_0402_1% 1 2 <35.3V6M 1 APL5913-KAC-TRL_SO8 1 1 2 GND PR184 1. September 28.7U_0603_6. notice the res.MB A4853 Rev A 401817 Date: 5 4 3 2 Monday.45> VS_ON @ PR187 1K_0402_1% 1 2 FB 2 FB=0.46> SUSP# Ien=10uA.8*(1+(R1/R2)) +1.5 4 3 2 1 D D C C +3VALW PC144 1U_0402_6.40.3V6K 1 2 1 +1.5V 1 PJ15 @ JUMP_43X79 Vout=0.1VSDGPU 2 PC145 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.45. and pull high voltage from HW A A 2009/07/17 Issued Date Compal Electronics.8V 1 <37.022U_0402_25V7K B PC147 22U_0805_6.54K_0402_1% PR186 4. Vth=0.48> VGA_ON PR185 1K_0402_1% 1 2 3 4 1 EN POK PC146 4. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.37. Inc. SCHEMATIC. Compal Secret Data Security Classification Deciphered Date 2009/07/17 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. INC. INC. INC.

2 40 8 Load line over spec PR131: change to 5.2_0603_5% PR158: PR159: PC117: PC118: PR135: PR140: D C 20081124 DVT B Add 4.8VP PR97:change to 2. INC.9VSP: enable pin change from SUSP# to SUSP 0.7_1206_5% PC56:Add 680P_0402_50V7K +5VALW/+3VALW PC122: Reserve 2200P_0402_50V7K on B+ +1.2 20081124 DVT PR97:change to 2.7_1206_5% PC119:Add 680P_0402_50V7K +1.7_1206_5% PC120:Add 680P_0402_50V7K Add bead between B+ and 1.7_1206_5% Add 4.2_0603_5% PR160:Add 4.05VSP PR131: change to 5. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.2 0_0603_5% +CPU CORE +1.5VP: enable pin change from SUSP# to SYSON +0. INC.2 42 9 3D hang 10 3D hang Charger PR63:change to 2.2 39 0. SCHEMATIC.2 42 0.2_0603_5% PR160:Add 4.76K_0402_1% Charger 0.2_0603_5% PR158: PR159: PC117: PC118: PR135: PR140: 13 16 PR37: PR41: PC33: PC34: PR38: PR39: +CPU CORE 38 0.2 38 ADD PC49 20081124 DVT +1.R.I.76K_0402_1% 0.7_1206_5% Add 680P_0402_50V7K Add 680P_0402_50V7K change to 2.2_0603_5% change to 2.05VSP 11 3D hang EMI solution PR105:change to 2.2_0603_5% PR66:Add 4. September 28.05VSP PC125: Reserve 2200P_0402_50V7K on B+ PR37: PR41: PC33: PC34: PR38: PR39: Add 4.05VSP_B+ +5VALW/+3VALW 12 B EMI solution +CPU CORE EMI solution 17 EMI solution Add 4.7_1206_5% PC120:Add 680P_0402_50V7K Add bead between B+ and 1.2_0603_5% PR66:Add 4. List) Item D 2 1 Fixed Issue Reason for change Rev.7_1206_5% Add 4.5 4 Version change list (P.2 42 0. Compal Secret Data Security Classification 2009/07/01 Deciphered Date 2010/07/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.2 39 0.1 42 PR135 and PR140 change to 20080915 EVT 0.1 39 Add PJ15 to B+ 20080915 EVT 5 PR135 and PR140 change to 0.2_0603_5% PR161:Add 4.2_0603_5% change to 2.9VSP: enable pin change from SUSP# to SUSP 20081124 DVT 6 C 3 Page 1 of 3 of PWR Charger feedback trace too long 0_0603_5% ADD PC49 7 Power sequence error +1.2_0603_5% PL12 : Add HCB4532KF-800T90_1812 PC124: Reserve 2200P_0402_50V7K on B+ 0.7_1206_5% Add 680P_0402_50V7K Add 680P_0402_50V7K change to 2. PG# Modify List Date Phase 1 Add PC57 :10U_1206_25V_6M 0. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.2_0603_5% change to 2.2_0603_5% 20081124 DVT PC122: Reserve 2200P_0402_50V7K on B+ PR105 : change to 2.7_1206_5% Add 680P_0402_50V7K Add 680P_0402_50V7K change to 2.05VSP PR105:change to 2.1 42 Shift PC99 from +cpu_B+ to B+ 20080915 EVT 4 Add PJ15 to B+ 0. Inc.7_1206_5% Add 4.2_0603_5% PL12 : Add HCB4532KF-800T90_1812 PC124: Reserve 2200P_0402_50V7K on B+ 20081124 DVT 20081124 DVT PC125: Reserve 2200P_0402_50V7K on B+ A A Issued Date Compal Electronics.1 38 Add PC57 :10U_1206_25V_6M 20080902 EVT 2 Add snubber for EMI 0. 2009 Sheet 1 50 of 53 .2_0603_5% change to 2.7_1206_5% PC56:Add 680P_0402_50V7K +1.7_1206_5% Add 680P_0402_50V7K Add 680P_0402_50V7K change to 2.2 39 20081124 DVT PR63:change to 2.1 42 Add snubber for EMI 20080915 EVT 3 Shift PC99 from +cpu_B+ to B+ 0.2_0603_5% PR105 : change to 2.MB A4853 Rev A 401817 Date: 5 4 3 2 Monday.05VSP_B+ 20081124 DVT +1.5VP: enable pin change from SUSP# to SYSON +0.8VP 37 +CPU CORE Add 4. INC.2_0603_5% PR161:Add 4.7_1206_5% Add 4.7_1206_5% PC119:Add 680P_0402_50V7K 20081124 DVT +1.

PG# Date Modify List Phase D D Charger Charger 18 PQ20:Reserve(@)SI2301BDS-T1-E3_SOT23-3 PQ21:Reserve(@)SSM3K7002FU_SC70-3 PR82:Reserve(@)887K_0402_1% Battery PR84:Reserve(@)0_0402_5% & HW solution PC68:Reserve(@)1000P_0402_50V7K PR87:change to 210K_0402_1% PR88:change to 499K_0402_1% 38 0. 2009 2 A Sheet 51 of 1 53 . List) Page 2 of 3 for PWR Item Fixed Issue Reason for change Rev.05VSP PR104: Reserve(@)0_0402_5% PR110: change to 10K_0402_5% PR79 : Add 0.3 35 +1.1U_0402_16V7K C PQ20:Reserve(@)SI2301BDS-T1-E3_SOT23-3 PQ21:Reserve(@)SSM3K7002FU_SC70-3 PR82:Reserve(@)887K_0402_1% PR84:Reserve(@)0_0402_5% PC68:Reserve(@)1000P_0402_50V7K PR87:change to 210K_0402_1% PR88:change to 499K_0402_1% 20081124 DVT +1.I.5VP ADD PR113: 2.2_0603_5% ADD PR163: 4.05VSP 40 PR104: Reserve(@)0_0402_5% PR110: change to 10K_0402_5% PR79 : Add 0.7_1206_5% ADD PC121: 680P_0402_50V7K ADD PL16 :FBMA-L11-322513-151LMA50T_1210 PC100: 680P_0402_50V7K PC130: 1000P_0402_50V_7K PC131: 1000P_0402_50V_8J B 20081224 +1.5VP PR112: Reserve(@) 0_0402_5% PR112: Reserve(@) 0_0402_5% +3VALWP/+3VALW +3VALWP/+3VALW B 19 EMI soultion PC100: 680P_0402_50V7K PC130: 1000P_0402_50V_7K PC131: 1000P_0402_50V_8J 0. September 28.2_0603_5% ADD PR163: 4.5 4 3 2 1 Version change list (P.Fix output 5V for HW no HDMI Size SCHEMATIC.7_1206_5% ADD PC121: 680P_0402_50V7K ADD PL16 :FBMA-L11-322513-151LMA50T_1210 +3VALWP/+5VALWP A 20 0.3 POWER Solution PVT 37 20090111 PVT PR42: Reserve 61.R.9K_0402_1% +3VALWP/+5VALWP A COMPAL ELECTRONICS Title RT8206.5VP +1.2 39 +1.1U_0402_16V7K C +1.MB A4853 Document Number Rev 401817 Date: 5 4 3 Monday.5VP 40 ADD PR113: 2.

J:+-5% 0. September 28.3 38 0. List) Item Fixed Issue 3 2 1 Page 2 of 2 for PWR Reason for change Rev.R.I.MB A4853 Size A Document Number Date: 5 4 3 A Rev 401817 Monday.3 37 20090112 PVT Add PL 15 ( FBMA-L11-322513-151LMA50T_1210) Add PC126 ( 100P_0402_50V8J) Add PC128 ( 100P_0402_50V8J) Add PC129 ( 1000P_0402_50V7K) C 22 Adjust battery voltage PVT 0.5 4 Version change list (P.3 39 change PL7 to 42 Change PC106 to 33P_0402_50V8J Change PC108 to 33P_0402_50V8J Change PC110 to 33P_0402_50V8J Change PC114 to 33P_0402_50V8J Battery solution Reserve PR86 ( 100K_0402_1%) 20090112 1.PG# Date Modify List Phase D D Add PL 13 ( HCB4532KF-800T90_1812) Add PL 14 ( FBMA-L11-322513-151LMA50T_1210) 21 EMI solution Reduce the Noise 0.8u choke saturation B 23 Saturation current 24 GP BOM current too small Tolerance: K:+-10% .4 20090113 1UH_PCMB103E-1R0MS_20A_20% PVT B 20090123 PVT COMPAL ELECTRONICS A Title SCHEMATIC. 2009 2 C A Sheet of 52 1 53 .

C310. P. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. P. Q14 .37 Unstuff C407. P. R267.25 Unstuff U8. P.2k ohm as 18k ohm for Board ID C C B B A A Compal Electronics. Add J3 for +1. Q51. C884. C885. Compal Secret Data Security Classification 2009/07/01 Issued Date Deciphered Date 2010/07/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. SCHEMATIC. Inc. Q13.40 Unstuff R611. C886. Unstuff R244 . C881.35 Change R273 8. R545 for No HDMI Audio Function 2. D30 5. P.40 Change R558 120K ohm as 200K ohm . U40 for 1.31 Change C81.41 Unstuff R580.40 Unstuff C882. D33.40 Add R612. Add R614 for PCI_RST# D D 9/1 1. R275. P.37 Unstuff R609. Add R613 for BKOFF# 5. P. Q59 . 3. Q57 for DDR3 4.768kHz (TXC suggest value) 4. D20 . September 28. stuff C309. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.5 8/21 4 3 2 1 For Change DDR3 1. INC. Change R200K ohm as 270K ohm 9/17 1. 2009 Sheet 1 53 of 53 . Remove R260.22 Unstuff R544. P. C314. C883. C82 27pF as 33pF for Xtal 25MHz(TXC suggest value) 3. P. U12 for +1. R253. C315. Add R608.5V 2.26 Change C163. U41 6. INC. Q58 for +0. R266.23 Unstuff R411. R610 . P. R83 .8V . P. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.75VS . C164 18pF as 15pF for Xtal 32. Q54.MB A4853 Rev A 401817 Date: 5 4 3 2 Monday. Q52. INC. C313.8VS 2. R606. U42. R607. P. R560. C880. P.