Thit k FPGA d nh cho Hai la thiu

ki n nh n

Li ni u
Cun sch ny c vit trong lc cng ngh FPGA gn nh hon thin. K thut thit k FPGA hin
nay ang ch trng vo phn mm v ngn ng thit k. Thit k bng schematic gn nh khng cn v
khng thch hp vi phc tp ca cc thit k hin nay. Thit k bng HDL (VHDL v Verilog) ang
dn dn mt i, thay vo l thit k bng SystemC v SystemVerilog. SystemC v SystemVerilog
c s dng rt ph bin trong vic kim nh thit k. Vi vic cng ngh FPGA pht trin gn nh
chn mui nh vy, cc bn c khi tm hiu v FPGA qua internet thng b lc do qu nhiu thng tin
v khng bit bt u t u. Do , mc ch cui cng ca quyn sch ny l gip bn, mt ngi
cha bit g v FPGA cng nh HDL, thit k c mt chng trnh hon chnh bng ngn ng VHDL
hoc Verilog trong thi gian sm nht. u bn l sinh vin nm hoc trc gi ch lm vic vi l
trnh v by gi mun lm quen vi FPGA th y l cun sch nh cho bn.
Cun sch ny s bt u vi ti v k thut mch s, sau s hng dn cc bn v VHDL v
Verilog, ti n s tho lun cng ngh FPGA v cui cng l thit k trn FPGA. V i tng ca ca
sch ny l cc bn thiu kin nhn, nn mi ti s c tho lun phn trng yu nht, cc bn no
mun tm hiu su hn nn tm c cc ti liu chuyn bit.

Tip: khi sa cha mch s vic
cn lm th hai, yeah th 2
khng phi th 1, l kim tra
xem mch to clock c chy
ng khng. Vic lm u tin
l kim tra cc ngun in.
n Khi nim v mch s v cc linh kin c bn ca mch s
Clock - n np
Khi thit k mch s, khi nim quan trong nht l xung nhp, hay cn gi l clock, trong cc bn v
thng k hiu l clk hoc ck. Xung nhp l mt tn hiu tun hon c pht ra t mt mch ao ng
v dng xung l tng l xung vung. Tuy nhin trn thc t, cc xung nhp tn s cao (ln hn
40MHz), xung nhp khng cn dng xung vung na m c dng nh xung vung b t cc gc. Cc
hnh bn i chp t cc ao ng nghim (oscilloscope). Xung nhp quan trng trong mch s l v cc
linh kin trong mch s hot ng ng b theo xung nhp ny. Xung nhp ny ging nh nhp tim, ch
khi xung nhp chy th cc d liu trong mch mi c tnh ton v di chuyn gia cc thnh phn
trong mch.
Cc thng s ca clock bao gm: chu k (period), hot k
(duty cycle), thi gian ln (rise time), thi gian xung (fall
time), n nh (jitter).
Chu k (Period) ca xung nhp: thi gian trung bnh gia 2
sn ln hoc sn xung k tip nhau ca xung nhp.
rung (Jitter/uncertainty): trn thc t cc mch to
xung nhp khng th to c xung nhp vi cc chu k
chnh xc bng nhau. Thi gian gia sn ln/xung k
tip s thay i xung quanh 1 gi tr trung bnh. Hin tng ny gi l jitter. V d nh xung nhp
100MHz (chu k = 10 ns), s c lc thi gian gia sn l 9.8ns c lc l 10.2 ns. Vic ny nh hng
n nhiu cc mch chuyn i t tnh hiu tng t sang tn hiu s (Analog Digital Converter ADC),
v c nh hng cht t n hot ng ca mch s. bit thm chi tit, cc bn c th tham kho
bi p dng (application note, s vit tt l appnote) 3359 ca MAXXIM [].
Thi gian ln (rise time): Khong thi gian khi xung di chuyn ln t 10% gi tr cao nht n 90% gi tr
cao nht. Lu l ngng 10% v 90% ny l ngng ngi ta thng ng, khng c nh ngha c th,
bt buc. Thi gian ln ca mt xung l tng, xung vung, l bng 0, nhng v gii hn bng thng ca
linh kin, thi gian ln s c gi tri ng hu hn. bit thm chi tit bn c th tham kho trang
web ca AUBRAUX [].
Thi gian xung (fall time): khong thi gian xung di chuyn xung t 90% gi tr cao nht xung cn
10% gi tr cao nht.
Hot k (Duty Cycle) ca xung nhp: tnh bng t s gia thi gian xung mc cao v chu k ca xung.
DC = High-time/Period * 100%.


Hnh 1 nh ngha v cc tham s ca xung nhp clock

Hnh 2 Xung vung rt p

Hnh 3 Xung vung hi b bin dng

Hnh 4 Xung hon ton bi bin dng

High
Time
Period
Fall time / Rise Time
90%
10%
Thanh ghi - Flip-flop - Register
Flip-flop l mt thnh phn th v v quan trng trong mch s. thc hin 1 nhim v no , cc h
thng phi tri qua nhiu giai on x l. Chnh nh c flip-flop m cc mch s c th ghi nh cc d
liu, cc trng thi ca h thng, t c th hot ng tun t (sequentially) v x l s liu c. Mi
flip-flop hot ng ng b vi clock. Khi nim ng b s c gii thch r phn i.
Fli flo c bn nht gi l D-flipflop (v.t DFF), bao gm 3 cng : clk, D v Q. DFF hot ng nh sau: ti
mi sn ln (hoc xung), DFF s ghi nh gi tr ti cng D v cho ra cng Q. Trong tt c cc thi
im cn li, gi tr ca Q khng thay i. Trong hnh v DFF bn i, du tam gic nh k hiu rng tn
hiu clk hot ng sn; trong hnh a l sn ln, hnh b l sn xung (hnh trn nh c ngha h
nh). Khi biu din gi tr ti cc cng theo thi gian, ngi ta dng timing diagram, v s c t tri
sang phi.

DFFa, gi tr ti cng D c ly mu ti cc sn ln (positive edge) ca clock, v gi nguyn gi tr
mi thi im khc. Hay ni cch khc, gi tr ca Q ch thay i ti cc cnh ca clock. Chnh v vy m
ngi ta gi gi tr ca Q ng b vi clock. DFFb, vic tng t xy ra nhng gi tr c ly mu ti
sn xung (negative edge).
Vi thanh ghi DFF, ngi ta khng lm ch c khi no th ghi nh data v khi no th khng cn ghi
nh. Thanh ghi DFFE khc vi DFF ch c thm cng m (enable). Khi cng m bng 1, DFFE ghi nh
gi tr ti cng D ti sn ca clock v cho ra cng Q.

D Q
clk
D Q
clk
a
b
D Q
clk
ena
Tip: Mt tn hiu c khng nh
(asserted) ngha l tn hiu trng thi
bt, hot ng. Mt tn hiu c th l tn
hiu hot ng thp (active low signal),
hoc tn hiu hot ng cao (active high
signal). Tn hiu hot ng thp s hot
ng khi tn hiu mc 0, tn hiu hot
ng cao s hot ng khi tn hiu
mc 1.

D Q
clk
ena

D Q
clk
ena
h cc bn thy trong hnh trn, ch khi no cng ena c khng nh th DFFE mi nhn gi tr mi
nu khng, Q vn gi nguyn gi tr chu k trc. Theo Tip, cc bn th v dng sng cho cc flip flop
hnh i.

n b n n b ncn n ncn
Reset)
Cc fli flo thng c thm cng vo na l eset v Set. Cng set s a Fli-flo v trng thi 1
cng reset s a FF v trng thi 0 . eset bao gm loi ng
b v khng ng b. eset khng ng b ngha l khi c khng nh (assert) th u ra s c gi tr
0 ngay l tc, cn reset ng b ngha l khi khng nh, gi tr ra ch tr v 0 ti sn ln ti
theo ca clock. Chn eset s c ng hot ng cao (active high) hoc hot ng th (active lo). Khi
active lo, mch s c reset khi gi tr chn reset 0.

D Q
clk

D Q
clk
0
Sync Reset
Async Reset
Tip: Bn th tng tng s mt s thanh ghi
gm nhiu bit ghi nh trng thi ca mch s
ca bn. Bn mun khi reset, cc thanh ghi ny
tr v tt c bng 0, v khi g reset th mch
bt u hot ng. u iu kin ni trn khng
tha cho tt c cc bit (v thi gian tn hiu reset
i ti mi FF l khc nhau), c mt s FF vn cn
trong trng thi reset v mt s FF bt u hot
ng sm hn mt s khc, vic ny n n
vic mch s chy sai.

c n i in n n c n iin

rong khi ly mu gi tr ti cc cng vo (khng k Async eset), fli-flo i hi cc cng vo hi gi
nguyn gi tr khng c thay i. C th l gi tr cng vo hi n nh trc sn ca clock mt
khong thi gian gi l thi gian thit l (set-u time) v gi nguyn n sau sn ca clock mt
khong thi gian gi l thi gian gi (hol time). Sn l sn ly mu ca clock, c th sn ln, xung
hoc c hai trong trng h DD (ouble-data-rate). Set-u time v hol-time l thng s ca FF ty
thuc vo qu trnh ch to FF. Cc FF xn s c set-u time v hol-time nh, cho h mch s chy
vi tc cao hn.
hi gian thit l (setu time)
(hnh v)
hi gian gi (hol time)
(hnh v)
goi Setu-time v hol-time, FF cn thng s khc ng cho chn reset khng ng b l
emoval ime v ecovery ime. i vi chn reset khng ng b (Asyn eset), chn ny cn hi tha
mn iu kin thi gian gi l emoval ime (tm ch l thi gian chn) v ecovery ime (thi gian
hi hc). thi gian ny c xt khi chn reset c thot ra khi khng nh (e-asserte). Khi chn
reset khng nh, FF trong trng thi reset v khng thay i tn hiu g cho n khi chn reset c
e-asserte. hi im chn c chuyn t khng nh sang h nh hi tha cc iu kin nh sau:
- Sau sn ca clock mt khong thi gian emoval ime
- rc sn k ti ca clock mt khong thi gian ecovery ime
-



i ni cc cn ic
Khi mch s thc hin vic x l, c th cc h tnh ch quanh i qun li gm: AD, ,
v . Cc bng sau gi l bng chn tr ca tn hiu .
AND OR XOR NOT
A B O A B O A B O A O
0 0 0 0 0 0 0 0 0 0 1
0 1 0 0 1 1 0 1 1 0 1
1 0 0 1 0 1 1 0 1 1 0
1 1 1 1 1 1 1 1 0 1 0

t mch nhiu inut rt quan trng l mch multilexer. rong mch -ra-1 multilexer khi gi tr S0,
u ra s theo gi tr ca mt cng, khi S1, u ra s theo gi tr ca cng khc. h vy, mch thc
hin vic chn la inut. ng t bn s c -ra-1 multilexer, mch -ra-1 c bit chn la v ta c
trng h ( ngha l khng quan tm). Lu rng mulilexer trong mch s khc vi multlexer
trong mch tng t. mch s, gi tr u ra c ti to li cho bng gi tr u vo. mch tng
t, multilexer s to mt ng n vt l t u vo ti u ra.

2-to-1
Multiplexer
4-to-1 Multiplexer
A B S O A B C D S0 S1 O
0 0 0 0 0 X X X 0 0 0
0 1 0 0 1 X X X 0 0 1
1 0 0 1 X 0 X X 0 1 0
1 1 0 1 X 1 X X 0 1 1
0 0 1 0 X X 0 X 1 0 0
0 1 1 1 X X 1 X 1 0 1
1 0 1 0 X X X 0 1 1 0
1 1 1 1 X X X 1 1 1 1




i ni cc n

rong mch s, mc cao 1 v mc th 0 c th hin bng in th ca tn hiu. in th thay
i ch l s i chuyn ca cc ht in tch. in th ti mt im cn c thi gian chuyn ln cao
hoc xung th. Do , tt c cc thnh hn in t u c tnh cht tr.
V vi DFF, gi s ti mt chu k no u vo thay i gi tr. rn l thuyt, u ra s thay i gi
tr theo ngay ti sn ca clock. hng trn thc t gi tr u ra s n nh sau sn ca clock 1 thi
gian gi l t
CKQ
(time clock to Q, thi gian t sn ca clock n khi u Q c gi tr ng).
i vi cc cng logic trong mch kt h cng vy, khi inut thay i, th hi mt mt thi gian tr
outut th hin gi tr ng. hi gian tr ny ca cc cng gi l tr lan truyn (roagation elay).
(Hnh v)
Khi mt mch gm c FF v cc cng logic c kt ni vi nhau, tr ca cc thnh hn trong mch s
quyt nh mch c th chy tn s no. Ly v nh hnh v bn i. Gi s thi gian tr ca cng
AD l t
AND
, ca cng l t
OR
, th khi tn hiu sigA hay sigB thay i, thi gian gi tr ti cng D ca
FF ng v n nh bng:
t
A-D
= t
CKQA
+ t
AND
+ t
OR
+ t
Routing1
t
C-D
= t
CKQC
+ t
OR
+ t
Routing2

t
Routing
l thi gian tr ca cc y n.
hn trc chng ta tho lun v thi gian Set-u time v Hol-time ca FF. tha yu cu ny
th t
A-D
v t
C-D
hi nh hn t
Cycle
t
Set-up
, -

Set-up
. Chnh iu ny quyt nh tn s m mch c th chy
c. y l mt iu kin quan trng khi thit k mch s. Cc hn mm hn tch thi gian (iming
Analysis ool) s t ng kim tra tt c cc ng tr v s bo nu c ng tr no vi hm iu
kin ny.


Tip: D thy rng, khi t
Skew
ng th chng ta c
li hn v tCycle c th nh hn tn s ca
mch ln hn. Khi nim ny ng cho tt c
cc ng tr ng b, ngay c khi cc cng I

i ni cc c cc
By gi, hc t hn cht, chng ta tnh n chuyn tn
hiu clock khng n cc FF cng mt thi im gi l
(clock skew, lch clock). Gi s thi gian lch gia clock
ca FF A v D l t
SkewAD
, t
SkewAD
c th m hoc ng.
t
SkewAD
ng khi clock n A trc, m khi clock n D
trc. Ly sn ca clock ti FFA lm chun (thi im
0) th thi gian n ca tn hiu (ata arrival time) ti cng D ca FFD l:
t
D-arrival
= t
CKQA
+ t
AND
+ t
OR
+ t
Routing1

tnh set-u time, chng ta tnh thi gian n ca sn ca clock ti FFD l:
t
CK-arrival
= t
Cycle
+ t
SkewAD

u cu l ata hi n trc clock mt khong thi gian Setu ime:
t
D-arrival
<= t
CK-arrival
- t
Setup

t
Cycle
>= t
CKQA
+ t
AND
+ t
OR
+ t
Routing1
+ t
Setup
- t
SkewAD

Cn hol-time th sao Chuyn g xy ra nu t
SkewAD
ln hn t
D-arrival
Lc tn hiu s n FFD trc c
sn m sinh ra tn hiu . iu ny l sai v theo thit k cn chu k tn hiu mi n c cng Q
ca FFD. kim tra iu kin hol-time, thi gian n ca clock c tnh bng thi gian n ca sn
m sinh ra tn hiu:
t
CK-arrival
= t
SkewAD

V tn hiu hi n sau sn mt khong thi gian t
hold
:
t
D-arrival
>= t
CK-arrival
+ t
hold

t
CKQA
+ t
AND
+ t
OR
+ t
Routing1
>= t
SkewAD
+ t
hold

u t
Skew
nh hn hoc bng 0 th iu kin hol-time thng s tha v thol thng rt nh gn bng
0.







AND
sigA
sigClk
sigA_
D
sigOut




sigClk

sigB
sigC




Tip: V sao cn hi hiu c cu trc ca
FPGA Khi thit k bng ngn ng m t hn
cng cho nn FPGA, n lc cui cng mch s
c x ln cc hn t c bn m FPGA h
tr. Cho nn khng hi tt c nhng g bn m
t c th tng h trn FPGA Coe c th
tng h c cho nn FPGA gi l
synthesizable , khng tng h c gi l
unsynthesizable. Khi vit coe, bn hi hiu
coe c th tng h c cho ng FPGA m
bn mun hng n hay khng

n i

Bo ch, google, wikipedia v rt rt nhiu ebsite ni v FPGA, mnh khng mun ni li nhiu. Ch
xin tm tt mt vi im c bn cc bn no cha lm vic vi FPGA bao gi c th hnh ung c
n lm vic nh th no.
FPGA Fiel Programmable Gate Array. rc tin phi hiu ci tn ca n. Mt mt thi gian di mnh
mi hiu c ch FIELD ngha l ni s dng con Chp. Mnh thy nhiu ch dch l dng trng g g
l khng ng, FIELD PGAABLE ngha l c th l trnh c ti ni ca ngi s dng khc
vi mt s chip khc Phi lp trnh ti ni sn xut.
FPGA c to thnh t mt mng (matrix hay array) cc phn t nh kh trnh nn gi l
PROGRAMMABLE GATE ARRAY.
Lm th no c c mt PROGRAMMABLE GATE (Cng kh trnh)?Trong FPGA, PROGRAMMABLE
GAE c to thnh t MEMORY. Chng qua l ngi ta s dng b nh mt cch khc so vi thng
thng. V d ban c mt b nh c 2 nh, mi nh c1 bit. By gi nh s khng cha gi tr 1,
nh s 1 cha gi tr 0. Ly a ch (address) lm input, th khi input = 1 th output = 0, input = 0 thi
output = 1 --> Bn to c cng . l l o ngi ta gi cc FPGA thng dng by gi s dng
cng ngh SRAM. Trong FPGA, cc nh to thnh logic nh vy gi l Look-up-table (LUT, bng tra
cu). a s cc FPGA by gi s dng cc LUT c 4 inputs, mt s s dng 5-input LUT (Virtex5), 6-input
LUT (Virtex 6) ... Vi mt LUT c 4 inputs bn c th
dng n d to thnh bt k mch logic no c 4
inputs:
F = X1X2+X2X3+X4.X2 ... v chung qui li vn s ch c
16 trng hp m thi.

Mt iu quan trng khc cn phi bit l cc
PGAABLE GAE ni trn c kt ni vi
nhau thng qua mt mng li gi l ti nguyn dn
(UIG ESUCE). Cc ng dy dn ny chy
theo hng Nam-bc, ng ty v c kt ni
bng cc hp chuyn tip (SWITCH BOX). Cc SWITCH
B ny cng kh trnh, c nhim v r tn hiu sang
hng khc nh trong hnh v sau:
http://en.wikipedia.org/wiki/File:Switch_box.svg

Bng cch cu hnh cho cc LUT v SWITCH BOX, chng ta c th to ra c mch LOGIC nh . Khi
thit k vi FPGA, cc bn ang thit k mch in ch khng phi ang lp trnh cho chip n chy .
im hay l chng ta c th xa, sa thit k v ci t li trong khong thi gian ngn, khng mt nhiu
cng sc. l cng im quan trng khc ca FPGA: thi gian cho ra sn phm ngn (Short Time-to-
Market).
Cu hi nh: bn th ln trang eb ca ilinx m atasheet ca ng Chi Sartan [] v Virtex 4 [],
hn gii thiu cu trc ca Configurable Logic Block (CLB) v hn I esource v th tr li my cu
hi sau:
- Bn c th tong mt fli-flo m ly mu c sn c khng (DD) v ng c
u
- Gi s bn c CLB, 1 CLB cc Fli-flo c ng vi cu hnh sn ln, 1 CLB cc FF c s
ng vi cu hnh sn xung. u ng Sartan, CLB ny c th c chung 1 tn hiu clock
c khng u ng Virtex-4, 2 CLB ny c chung mt tn hiu clock c ko
Cu hi trn nhm nhn mnh cu trc ca FPGA s nh hng ti vic thit k nh th no. iu quan
trong mun ni l bn ng FPGA ca hng no th cng cn bit cu trc c bn ca ng FPGA .
i liu ny khng nhm mc ch lit k ht tt c s khc bit.
.

Tip: FPGA ngy nay khng ch c s ng thit
k logic, m cn c lnh vc nh h thng nhngm
(embedded system). cc h thng embee, c
cc b vi x l, cc b vi x l ny c th c thit k
ng loi mm (softcore) hoc loi cng (harcore).
Cu trc ca FPGA hon ton c th xy ng mt vi
x l ng mm v vi x l chng qua l mt t h
cc cng logic v thanh ghi. Hoc FPGA c th cha vi
x l ng cng harcore, vi x l ny nh mt ti
nguyn trn FPGA, v vn nm nu khng c s
ng. NISII v icroblaze l softcore c s
ng h bin. hit k h thng nhng gm cu
hnh hn cng (bng cc hn mm nh SOPC, Qsys,
EDK) v bc ht trin hn mm gm cc giao in
vit coe v cc trnh ch.

c bc i
1) hit k FPGA bt u vi vic m t h thng
hn cng m bn mun xy ng. Vic m t c
th thc hin bng cch c bn:
- V s mch (schematic)
- Vit coe VHDLVerilog
goi ra, ty thuc vo hn mm bn s ng, bn
c th m t bng cch khc, cao c hn, gn gi
vi ngn ng hn mm hn v trc quan hn v
nh : ImulseC, SystemGenerator ...
) Sau khi m t thit k, bn hi m hng thit
k kim tra xem thit k bn c chy ng cha
3) Bc th l tng h v x ln mch FPGA v
chy th trn hn cng tht, hn ny c lm
bng cc hn mm t ng. ch logic ca bn m
t hn 1 s c x ln cc ti nguyn sn c
trn FPGA. Phn mm ch coe ca bn bng cc
temlate hay tm ch l nh ng mu. hn thit k vi ngn ng Verilog, bn s lm quen vi
cc nh ng mu ny. ham kho thm trang eb [6][7] hiu ro cc cng on trong thit k
FPGA cho ng ca ilinx v Altera.
) Bc cui l kim tra xem mch c tng h c tha mn cc yu cu v thi gian hay khng, v
nh tr

rc khi lm vic vi FPGA, ti mun nhn mnh mt chi tit vi cc bn mi lm quen vi FPGA.
rong thit k, tn hiu clock ch l mt on y n nh mi tn hiu khc nhng trn FPGA tht, tn
hiu clock c truyn n trn mt loi ti nguyn c bit nh ring cho clock. Cn hi lm iu
ny gim ti a lch clock nh ni hn trn.
rn FPGA, clock c li (rive) bng cc buffer mnh gi l clock buffer. t s hn mm s t ng
ht hin clock v chn buffer ny cho bn. rong mt s trng h, hn mm khng t chn m bn
hi chn bng cch s ng trc ti ti nguyn buffer ny.
hc li mt ln na, tn hiu clock l c bit v hi x l khc cc tin hiu khc.
hc li mt ln na, tn hiu clock khng ging cc tn hiu khc, khi cn thao tc trn tn hiu clock
hi ng cc ti nguyn sn c trn ng FPGA ang thit k.

Tip: Khi vit coe Verilog bn cn lm quen vi
cch ngh ny:
- 1 bn ang m t hn cng, cc hn
mm synthesis s c coe ca bn v
cho ra cc mch in theo ca bn.
Phn mm thc hin iu ny bng cc
nh ng mu (temlate). V s c
nh ng mu cho mt thanh ghi c
reset ng b, khng ng b, c cng
enable hay khng c Bn cn hi
tun theo nu khng trnh tng h s
tng h sai.
- khi m hng, hn mm m hng s
c coe ca bn t trn xung i
nh hn mm, bn cn hiu mt s
khi nim v quy tc hiu c trnh
m hng s hiu coe ca bn nh
th no
i n i nn n i n
Phn ny gi bn:
- C th to mt moule bng ngn ng Verilog
- Vit mt s statement n gin m t hn cng bn mun thc hin
- hit k trn mi trng QuartusII
- hit l rng buc v thi gian cho mch bng imeQuest
- C th to c mt bn kim tra (testbench) kim tra moule ca bn
- M phng trn mi trng moelsim
- hc hin 1 vi mo nh khi ly tn hiu t cc cng tc v nt n
hn n hng gi bn n vng tt c cc c i ca ngn ng rilog
Verilog l ngn ng m t hn cng. H thng hn
cng ln l mt t h cc h thng nh c kt ni
vi nhau qua cc cng. V my tnh ca bn c cc
moule l cc car nh vieo car, Ethernet car c
gn kt qua cc cng giao ti ca otherboar. rn
motherboar li c cc moule khc nh hn l cc con
chi c kt ni qua cc chn I. rn mi chi li l
mt t h cc moule nh hn na nh CPU th c
cache, ALU Do , m t moule l mt vic c bn
m cc ngn ng m t hn cng trong c Verilog
h tr. t moule c m t bng hn, cc cng
vo ra ca moule v cch hot ng ca n. y l
cch m bn nh ngha mt moule:
module UpCounter( input clk, input rst, input run,
output [7:0] counter_value);

endmodule
Cc keyor: mouleenmoule ng gii hn
hn coe m bn ng m t moule ny. Sau keyor moule l tn ca moule, UCounter, ti
n l hn xc nh cc cng inut v outut. Output :0 l cch ngi ta ng ch outut l
mt bus gm nhiu ybit, trong trng h ny l bit, c nh s t 0(LSB-least significant bit, bit
c ngha t nht) n (SB, bit c ngha nhiu nht).
Counter_value 01000001 nh hn 6 h m th hn, th bit 0 v bit 6 1, cc bit cn li bng
0. Chuyn t gi tr nh hn sang gi tr th hn:
6
+2
0
=65.
rong v ny, chng ta s m t mt b m ln c cc c tnh (secifications) nh sau:
Tip: wire v register
- Khi tng hp: wire dung m ta
mt on dy dn, ni cac block li
vi nhau. reg dung m ta cac
thanh ghi khi c gan gia tr ti
sn cua clock. Trinh tng hp c
th tng hp reg thnh dy dn nu
reg c gan gia tr khng phai ti
sn.
- Khi m phong: wire khng ghi nh
c gia tr v lun thay i khi cac
bin u vo thay i. reg thi ghi
nh c gia tr chi thay i khi
c gan mt gia tr khac
- u vo Clock l tn hiu clock ng chy mch
- Reset, khi rst 1, countervalue 0 ngay l tc (asynchronous)
- Khi rst = 0,
o u un 1, mch s m ln tng n v sau mi sn ln ca clock
o u un 0, mch gi nguyn gi tr
Sau hn interface l hn m bn ng m t hot ng ca moule. rong v ny, chng ta cn
mt thanh ghi -bit ghi nh gi tr m, thanh ghi ny s c chn reset khng ng b ni vi inut
reset. hanh ghi ny hot ng khi un1, nu un 0 th khng hot ng.
khai bo ng mt thanh ghi bit:
reg [7:0] counter;
khai bo mt thanh ghi c chn clock, cng reset khng ng b, v hot ng bng tn hiu run:
always@(posedge clk or posedge reset)
if(reset==1)
counter < h0;
else if(run==1)
counter <= counter_add_1;
on coe trn l mt nh ng mu (template)
ng m t thanh ghi couter c bit, c clock c
ni vo tn hiu clk, cng enable ni vo tn hiu run,
cng D c ni vo tn hiu countera1.
Countera1 l u ra ca mch logic cng 1. ch
cng 1 -bit c m t nh sau:
wire [7:0] counter_add_1;
assign counter_add_1 = counter+1;
u ra ca mch logic lun hi c khai bo vi kiu
wire v c gn bng cu lnh assign gi l cu
lnh gn lin tc (continuous assignment). Cu lnh
gn lin tc ch ng c cho tn hiu kiu ire v
ng m t cc y n v u ra cc cng logic
(khng c kh nng nh). Cui cng l bn hi ni
cng countervalue vo thanh ghi counter:
assign counter_value = counter;
h vy l bn m t c mt b m hon chnh gm c:
- Cc cng vo ra
- hanh ghi bit ng ghi nh gi tr m, vo sn ln ca clock v run1, thanh ghi s ghi
nh gi tr ca u ra ca mch cng 1.
- ch logic cng 1

hng thit k vi oelSim v Verilog
Sau khi m t h thng ca bn, bn cn hi xc minh xem cc moule bn m t c chy ng vi
mun ca bn hay khng. lm c iu ny, bn to mt moule ln gi l testbench, moule ny
cha moule m bn va thit k. oule testbench l mt moule o ng chy m hng v to
ra cc tn hiu test, cho nn n khng c cc cng vo ra. Sau y l cch bn khai bo mt moule
testbench:
`timescale 1ns/100ps
module testbench;
.
endmodule
timescale l mt trong s cc irectives, tm ch l ng hng n chng trnh ch
khi c coe ca bn. imescale ng iu chnh hn gii ca chng trnh m hng.
1ns100s c ngha l n v chun khi m hng l 1 ns, v bc nhy thi gian nh nht l 100s, nh
vy bn s khng th thay i tn hiu vo cc thi im nh 6.ns, bn s thy tn hiu thay i lc
6.6 ns.
Sau bn s khi to (instantiate) moule m bn mun xc minh. Khi to mt moule c ngha l c
th ha moule thnh mt thc th. Ging nh trn mch bn c nhiu t in cng mt loi chng
hn C100uF. h mi t in l mt instance (thc th) ca moule C100uF. C h khi to
moule nh sau:
ModuleName InstantiationName (
.portname1 (netname)
.portname2(netname)
);
rong lc khi to thc th, chng ta hi kt ni cc cng ca thc th. Ging nh khi bn t mt con
chip ln boar mch, bn cn hi i y kt ni con chi vi mi th xung quanh. Trong verilog bn
m t vic ny bng u ., sau l tn ca cng vo ra ca moule, sau l tn ca tn hiu
moule hin thi m bn mun kt ni vo cng vo ra, trong ngoc n.

V chng ta t tn cho thc th ca UCounter l yUCounter:
UpCounter MyUpcounter(
.clk(myclock),
.rst(myreset),
.run(KichHoat),
. counter_value(giatridem)
);
heo on coe ny, cng clock c ni vo tn hiu myclock, cng reset c ni vo tn hiu
myreset, cng run c ni vo tn hiu KichHoat, v cng counter_value c ni vo tn hiu
giatridem.
k, sau khi kt ni cc tn hiu, bn s hi gi l cc tn hiu to ra m trng m thit k ca bn
s hot ng. Bn cn nh rng nhng g bn m t trong testbench l unsynthesizable, ch s ng
m hng. Khi to tn hiu gi l, tt c cc tn hiu kt ni vi u vo ca thit k hi c khai bo
vi kiu reg, tn hiu ni vi u ra khai bo vi kiu wire. na, chng ta s tho lun k hn khi nim
gia reg v wire.
to clock, bn ng temlate sau:
reg myclock=1b0;
always@*
begin
#10 myclock <= ~myclock
end

kay, by gi tm hiu


References
[1] http://www.aubraux.com/design/rise-fall-time.php
[2] http://www.maxim-ic.com/app-notes/index.mvp/id/3359
[3] Removal and Recovery Timing:
http://www.alteraforum.com/forum/attachment.php?attachmentid=994&d=1237566835
[4] http://www.xilinx.com/support/documentation/user_guides/ug070.pdf
[5] http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf
[6] http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_fpga_design_flow_overview.htm
[7] http://www.altera.com/literature/tt/tt_my_first_fpga.pdf


goi Setu-time v hol-time, Fli-flo (FF) cn thng s khc ng cho chn reset khng ng b
l emoval ime v ecovery ime. i vi chn reset khng ng b (Asyn eset), chn ny cn hi
tha mn iu kin thi gian gi l emoval ime (tm ch l thi gian chn) v ecovery ime (thi
gian hi hc). thi gian ny c xt khi chn reset c thot ra khi khng nh (e-asserte). Khi
chn reset khng nh, FF trong trng thi reset v khng thay i tn hiu g cho n khi chn reset
c e-asserte. hi im chn c chuyn t khng nh sang h nh hi tha cc iu kin
nh sau:
- Sau sn ca clock mt khong thi gian emoval ime
- rc sn k ti ca clock mt khong thi gian ecovery ime
Trong mch c hng trm FF, iu kin ny ng bo m tt c cc fli-flo c cng tn hiu reset
bt u hot ng bnh thng ti cng mt sn ca clock. Lm th no tha mn iu ny, bn
cn 1 mch nh cho tn hiu reset ca bn:

module Test(input Reset, input Clk, ...);

reg Reset_D1, Reset_D2;
wire global_reset;

always@(posedge Clk or posedge Reset)
if( Reset == 1'b1) begin
Reset_D1 <= 1'b1;
Reset_D2 <= 1'b1;
end else begin
Reset_D1 <= 1'b0;
Reset_D2 <= Reset_D1;
end

assign global_reset = Reset_D2;

Tn hiu global_reset s l tn hiu reset cho ton mch. Mch ny bo m khi thot khi reset, tn hiu
global_reset s ng b vi clock v s khng vi phm cc timing trn.

Chuyn g xy ra nu khng dng mch trn? Nu mch c nhiu FF, th c th mt s FF s tr v
trng thi bnh thng chm hn cc FF khc o tn hiu reset n tr. Nu cc FF ny l ca my trng
thi th c th my trng thi ri vo trng thi bt nh.












endmodule