Unit-IV 8255-PIO-Programmable Input-Output Port

• 8255 has 24 I/O lines which may be individually programmed in two groups of 12 lines each or three groups of eight lines. • The two groups of I/O pins are named as Group-A and Group-B. • There are three ports – Port-A can be used as an 8-bit I/O port – Port-B can be used as an 8-bit I/O port – Port-C can be used as an 8-bit I/O port as two 4-bit ports, or to produce handshake signals for ports A&B.

8255 Internal Architecture
• 8 Data lines allow you to write data bytes to a port or the control register and to read bytes from a port or the status register under the control of the RD and WR lines. • The address inputs, A0 and A1, allow you to selectively access one of the three ports or the control register. • The internal address for the device are: Port-A 00; Port-B 01; Port-C 10; control register 11. • Asserting the CS input of the 8255 enables it for reading or writing. • The RESET input of the 8255 is connected to the system reset line so that, when the system is reset, all the port lines are initialized as input lines.

Modes of Operation of 8255
• There are 2 basic modes of operation of 8255
–I/O Mode –BSR Mode (Bit Set-Reset Mode) In the I/O mode, the 8255 ports work as programmable I/O ports, while BSR mode only Port C (PC0-PC7) can be used to set or reset its individual port bits.

BSR Mode
In this mode, any of the 8-bits of Port-C can be reset depending on D0 of the control word. The bit to be set or reset is selected by bit selected flags D3,D2 & D1 of the CWR (Control Word Register).

I/O Mode
–Mode 0 –Mode 1 –Mode 2

–Mode 0 (Basic I/O Mode) • When you want to use a port for simple input or output without handshaking, you initialized that port in mode 0. • If both Port-A and Port-B are initialized in mode 0, then the two halves of Port-C can be used together as an additional 8-bit port, or they can be used individually as two 4-bit ports. • When used as outputs, the Port-C lines can be individually set or reset by sending a special control word to the Control Register address. • The two halves of Port-C are independent, so one half can be initialized as input, and the other half initialized as output.

–Mode 1 (Strobed I/O Mode)
• When you want to used Port-A or Port-B for a handshake (Strobed) input or output operation, you initialize that port in Mode1. • In this mode, some of the pins of Port-C function as handshake lines. Then Port-C pins PC0,PC1 & PC2 function as handshake lines for Port-B if it is initialized in Mode 1. • If Port-A is initialized in Mode 1, then Port-C pins PC3,PC4,PC5 function as handshake signals. Pins PC6,PC7 are used as I/O lines. • If Port-A is initialized in Mode1 output port, pins PC3,PC6,PC7 function as handshake signals. Pins PC4,PC5 are used as I/O lines.

– Mode 2 (Strobed Bidirectional I/O)
• Only Port-A can be initialized in Mode 2. • In mode 2, Port-A can be used for bidirectional handshake data transfer. This means that data can be output or input on the same eight lines. • The 8255 might be used in this mode to extend the system bus to a slave microprocessor or to transfer data bytes to and from FDC board. • If Port-A initialized in mode 2, then Port-C pins
• PC3-PC7 are used as handshake lines for Port-A • PC0-PC2 are used for I/O if Port-B is in Mode 0 • PC0-PC2 are used for handshake lines if Port-B is in Mode 1

Construction and sending 8255 Control Word • MSB of the control word tells the 8255 which control word (i.e Mode Definition control word or Bit Set/Reset control word). • Mode Definition control word format tells the device what modes you want the ports to operate in. • Bit Set/Reset control word format can use to set or reset the output on a pin of Port-C or when you want to enable the interrupt out put signals for handshake data transfers. • Both control words are sent to the control register of the 8255.

Keyboard Interfacing
• In most keyboards, the key switches are connected in a matrix of Rows and Columns. • Getting meaningful data from a keyboard requires three major tasks: 1. Detect a keypress 2. Debounce the keypress. 3. Encode the keypress (produce a standard code for the pressed key). • A logic ‘0’ is read by the microprocessor when the key is pressed. • Key Debounce:  Whenever a mechanical push-bottom is pressed or released once, the mechanical components of the key do not change the position smoothly, rather it generates a transient response. These may be interpreted as the multiple pressures and responded accordingly.

• The rows of the matrix are connected to four output Port lines, & columns are connected to four input Port lines. • When no keys are pressed, the column lines are held high by the pull-up resistors connected to +5v. • Pressing a key connects a row & a column. • To detect if any key is pressed is to output 0’s to all rows & then check columns to see it a pressed key has connected a low (zero) to a column. • Once the columns are found to be all high, the program enters another loop, which waits until a low appears on one of the columns i.e indicating a key press.

• A simple 20/10 msec delay is executed to debounce task. • After the debounce time, another check is made to see if the key is still pressed. If the columns are now all high, then no key is pressed & the initial detection was caused by a noise pulse.

To avoid this problem, two schemes are suggested: 1. Use of Bistable multivibrator at the output of the key to debounce it. 2. The microprocessor has to wait for the transient period (at least for 10 ms), so that the transient response settles down and reaches a steady state. If any of the columns are low now, then the assumption is made that it was a valid keypress. The final task is to determin the row & column of the pressed key & convert this information to Hex-code for the pressed key. The 4-bit code from I/P port & the 4-bit code from O/P port (row & column) are converted to Hex-code.

;interface a 4x4 keyboard with 8086 using 8255 and write an ALP for detecting a key closure and return the key code in AL. The debouncing period for a key is 10ms. Use software key debouncing techniqe. DEBOUNCE is an available 10ms delay routine. Port-A .. Output .... for selecting a row of keys Port-B .. Input …. For sensing a closed key. Port address: Port-A 8000h Port-B 8002h CWR 8006h Construct the control word CWR = 1 0 0 0 0 0 1 0B = 82h

;ALP for key board interface code segment assume cs:code start: mov al,82h mov dx,8006h out dx,al mov bl,00h ;for key code xor ax,ax ;clear flags mov dx,8000h ;port-A address out dx,al add dx,02 ;port-b address wait: in al,dx ; read columns and al,0fh ;mask data lines D7-D4 cmp al,0fh jz wait call DEBOUNCE ;wait 10ms

mov al,7fh mov bh,04h ;set row counter nextrow: rol al,01 ;to ground next row mov ch,al ;save rotated data sub dx,02 ;port-A address out dx,al add dx,02 ;port-B address to get keypress in al,dx and al,0fh ;mask D7-D4 mov cl,04 ;set column counter nextcol: ror al,01 ;move D0 in CF jnc codekey ;key closure is found if CF=0 inc bl ;for get next key code dec cl jnz nextcol

mov al,ch dec bh jnz nextrow jmp wait codekey: mov al,bl mov ah,4ch int 21h

;move key code to al ;return to DOS prompt

DEBOUNCE PROC NEAR mov cl,0e2h back: nop dec cl jnz back ret DEBOUNCE endp code ends end start

• • In most of the cases, the PIO 8255 is used for interfacing the analog to digital converters with a microprocessor. The analog to digital converter is treated as an input device by the microprocessor, that sends an initializing signal to the ADC to start the analog to digital data conversion process. The process of analog to digital conversion is a slow process, and the microprocessor has to wait for the digital data till the conversion is over. After the conversion is over, the ADC sends end of conversion EOC signal to inform the microprocessor about it and the result is ready at the output buffer of the ADC. These tasks of issuing an SOC pulse to ADC, reading EOC signal from the ADC and reading the digital out put of the ADC are carried out by the CPU using 8255 I/O ports.

• The time taken by the ADC from the active edge of SOC pulse till the active edge of EOC signal is called as the conversion delay of the ADC. • The selection of ADC for a particular application is done, keeping in mind the required speed, resolution and the cost factor. • General algorithm for ADC interfacing contains the following steps 1. Ensure the stability of analog input, applied to the ADC 2. Issue start of conversion SOC pulse to ADC 3. Read end of conversion EOC signal to mark the end of conversion process 4. Read digital data output of the ADC as equivalent digital output. • If may be noted that the analog input voltage must be a constant at the input of the ADC right from the beginning to the end of the conversion to get correct result. • Sample & hold circuit which sample the analog signal and holds it constant for a specified time duration.

ADC 0808/0809
• • The analog to digital converter chips 0808 and 0809 are 8-bit CMOS, successive approximation converters. It is fastest technique. The conversion delay is 100 µs at a clock frequency of 640 kHz, which is quite low as compared to other converters.

Block Diagram of ADC 0808/0809 • • • • This converter internally has a 3:8 analog multiplexer, so that at a time 8 different analog inputs can be connected to the chips. Out of these 8 inputs only one can be selected for conversion by using 3 address lines A,B,C. The CPU may drive these lines using output port lines in case of multichannel applications. In case of single input applications these may be hardwired to select the proper input.

Analog input selected I/P0 I/P1 I/P2 I/P3 I/P4 I/P5 I/P6 I/P7

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

These are unipolar Analog to Digital (A to D) converters, they are able to convert only positive analog input voltages to their digital equivalents. This chips do not contain any internal sample & hold circuit.

Interfacing between ADC to Microprocessor
Problem:Interface ADC 0808 with 8086 using 8255 ports. Use Port A of 8255 for transferring digital data output of ADC to the CPU & Port C for control signals. Assume that an analog input is present at I/P2 of the ADC and a clock input of suitable frequency is available for ADC. Draw the schematic & timing diagram of different signals of ADC0808. Solution:• The analog input I/P2 is used & therefore address pins A,B,C should be 0,1,0 respectively to select I/P2. • The OE (Out put latch Enable) & ALE pins are already kept at +5v to select the ADC and enable the outputs. • Port C upper acts as the input port to receive the EOC signal while Port C lower acts as the output port to send SOC to ADC. • Port A acts as a 8-bit input data port to receive the digital data output from the ADC.

8255 Control Word:
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 0 0 = 98H Program: MOV AL,98H ; Initialize 8255, send AL to control word (CWR) OUT CWR, AL MOV AL, 02H;Select I/P2 as analog I/P OUT Port B, AL ;Port B as output MOV AL, 00H; Give start of conversion pulse to the ADC OUT Port C, AL MOV AL, 01H OUT Port C, AL MOV AL, 00H OUT Port C, AL WAIT: IN AL, Port C ; check for EOC by reading Port C upper & rotating RCL ; through carry. JNC WAIT IN AL, Port A ; if EOC, read digital equivalent in AC HLT ; stop.

Interfacing Digital to Analog Converters (DAC)
• The Digital to Analog Converters (DAC) convert binary numbers into their analog equivalent voltages. • The DAC find applications in areas like
– Digitally controlled gains – Motor speed controls – Programmable gain amplifiers etc.

AD 7523 8-Bit Multiplying DAC:-• Intersil’s AD 7523 is a 16 pin DIP, multiplying digital to analog converter, containing R-2R ladder (R=10K) for digital to analog conversion along with NMOS switches to connect the digital I/Ps to the ladder.
 Power supply +5v to +15v  Vref -> -10v to +10v  The maximum analog output voltage will be +10v  A Zener is connected between OUT1 & OUT2 to save the DAC from negative transients.

 An operational amplifier is used as a current – to – voltage converter at the output of AD 7523.  An external feedback resister acts to control the gain. Interfacing of AD 7523 with 8086
Problem:-Interface DAC AD7523 with the 8086 running at 8MHz & write ALP to generate a saw tooth waveform of period 1ms with Vmax 5v. Solution:-Code segment Assume cs:code Start: MOV AL, 80H OUT CWR, AL AGAIN: MOV AL, 00H BACK: OUT Port A, AL INC AL CMP AL, 0F2H JB BACK JMP AGAIN Code ends End Start

Display interface
Interface an 8255 with 8086 at 80h as an I/O address of port-A. interface five 7 segment displays with the 8255. write a sequence of instructions to display 1,2,3,4 and 5 over the five displays continuously as per their positions starting with 1 at the least significant position. CWR address is 86h.

Number to be displayed PA7d PA6 p a 1 2 3 4 5 1 1 1 1 1 1 0 0 1 0

PA5 b 0 0 0 0 1

PA4 c 0 1 0 0 0

PA3 d 1 0 0 1 0

PA2 e 1 0 1 1 1

PA1 f 1 1 1 0 0

PA0 g 1 0 0 0 0

Code CF 92 86 CC A4

All these codes are stored in a look up table starting at 2000:0001.

; ALP for display interface again: mov cl,05h ;count for displays mov bx,2000h ;initialize the data segment for mov ds,bx ; look-up table mov ch,01h ;1st no. to be displayed mov al,80h out 86h,al ;load control word in the CWR mov dl,01h ;enable code for least significant 7-seg display nxtdgt: mov bx,0000h ;set pointer to look-up table mov al,ch ;store number to be display xlat ;find code from table out 80h,al mov al,dl out 82h,al ;enable the display rol dl;go for next digit display inc ch dec cl ;decrement counter jnz nxtdgt ;go for next digit display jmp again

Stepper Motor Interfacing
• A stepper motor is a device used to obtain an accurate position control of rotating shafts. • It employs rotation of its shaft in terms of steps, rather than continuous rotation as in case of AC or DC motors. • In dot-matrix printer one small stepper motor which is used to advance the paper to the next line position & another small stepper motor which is used to move the print head to the next character position. • In floppy disk stepper motor is used to position the read/write head over the desired track. • To rotate the shaft of the stepper motor, a sequence of pulses is needed to be applied to the windings of the stepper motor, in a proper sequence. • The no. of pulses required for one complete rotation of the shaft of the stepper motor are equal to its number of internal teeth on its rotor.

• The stator teeth the rotor teeth lock with each other to fix a position of the shaft . • With a pulse applied to the winding input, the rotor rotates by one teeth position or an angle x. The angle x may be calculated as:

x = 3600 / no. of rotor teeth
• After the rotation of the shaft through angle x, the rotor locks itself with the next tooth in the sequence on the internal surface of stator. • The stepper motors have been designed to work with digital circuits. Binary level pulses of 0-5v are required at its winding inputs to obtain the rotation of shafts. • The sequence of pulses can be decided, depending upon the required motion of the shaft. • The count for rotating the shaft of the stepper motor through a specified angle may be calculated from the no. of rotor teeth
C = no. of rotor teeth / 3600 *


Interfacing Stepper Motor Winding Wa
Each of the winding of a stepper motor need this circuit for its interfacing with the output port. A Stepper Motor may have  Operating voltage 12V  Current rating 0.2A  Step angle 1.80 i.e 200 steps/revolution. A Stepper Motor using Wave Switching Scheme: – In this scheme, the windings Wa, Wb, Wc, Wd are applied with the required voltage pulses, in a cyclic fashion. By reversing the sequence of excitation, the direction of rotation of the stepper motor shaft may be reversed.

Motion Clockwise

Step 1 2 3 4 5

A 1 0 0 0 1 1 0 0 0 1

B 0 1 0 0 0 0 0 0 1 0

C 0 0 1 0 0 0 0 1 0 0

D 0 0 0 1 0 0 1 0 0 0


1 2 3 4 5

Problem Design a stepper motor controller and write an ALP to rotate shaft of a 4phase stepper motor: i. In clockwise 5 rotations ii. In anticlockwise 5 rotations. The 8255 port A address is 0740h. The stepper motor has 200 rotor teeth. The port A bit PA0 drives winding Wa, PA1 drives winding Wb and so on. The stepper motor has an internal delay of 10msec. Assume that the routine for this delay is already available. Solution: ALP: Assume cs:Code Code segment Start:

MOV AL, 80H OUT CWR, AL MOV AL, 88H; Bit pattern 10001000 MOV CX, 1000 Again1: OUT Port A, AL CALL DELAY ROL AL, 01 DEC CX JNZ Again1 MOV AL, 88H MOV CX, 1000 Again2: OUT Port A, AL CALL DELAY ROR AL, 01 DEC CX JNZ Again2 MOV AH, 4CH INT 21H Code ends End start

Sign up to vote on this title
UsefulNot useful