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Low-Voltage Pulsewidth Control Loops for SOC Applications

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 10, OCTOBER 2002

Po-Hui Yang, Jinn-Shyan Wang

Speaker: Wen-Lung Chang Date: 10. 28.2009

Outline
 Abstract

& Introduction  Circuit architecture  Experimental results  Conclusion

Abstract & Introduction
 In

this paper, adopts the conventional PWCL, but with a new duty-cycle detector and a pulse generator. this architecture, the output of PWCL has fixed rising edge. architecture can combine PLL/DLL with PWCL to perform phase locking and adjust pulsewidth.

 Using

 This

Abstract & Introduction
 The

design goal in this paper is proposing a PWCL operates at low-voltage and highfrequency. features of operating at low voltage, providing variable duty cycle, and being able to cooperate with PLL/DLL make the new PWCL suitable for system-on-chip applications.

 The

Circuit architecture

Conventional PWCL

Circuit architecture

phase-fixed PWCL.

Conventional PWCL
 There  When

are two problems when using this circuit.

the PWCL works together with PLL/DLLs, the phase change by the PWCL disturbs. charge pumps and differential amplifier are used to act as a duty-cycle detector to generate the control voltage for the pulse generator.

 The

Conventional PWCL

New building blocks

Simulations waveforms

New building blocks

Simulations waveforms

Experimental results
 The

pulsewidth of the clock to the multiplier is 0.62 ns, and the jitter is 92 ps.

Experimental results

Conclusion
 In

the new building blocks, the maximum clock frequency can be increased tremendously. the building blocks used in the new PWCL have simple circuit structures, which makes the PWCL suitable for low-voltage operation. measurement results of the test chip designed with a 0.35-um CMOS with only 1.8-V prove the feasibility of the proposed techniques

 All

 The