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Introduction:

A Viterbi decoder uses the Viterbi algorithm for decoding a bitstream that has been encoded using Forward

Error Correction based on a convolutional code (Convolutional encoding is a process of adding redundancy

to a signal stream in order to increase its robustness). In the decoder, the convolutional coded sequences

that have been corrupted by channel noise are decoded back to the original sequence.

Many digital transmit-receive systems use a Viterbi decoder for decoding the convolutionally coded data.

The digital data stream (e.g., voice, image or any packetized data) is first convolutionally encoded,

modulated and transmitted through a wired or wireless channel. Various noises may enter the transmission

channel. At the receiver side, the received data from the channel is demodulated and then decoded using

the Viterbi decoder. By using the minimum likelihood algorithm, the Viterbi decoder core is able to correct for

errors in the data caused by channel noise. The decode output is equivalent to the transmitted digital data

stream.

Salient Features:

o Constraint length k = 7, rate = ½, G0 = OCT”171”, G1 = OCT”133”

High speed design

o Operating frequency of 45 MHz (for XCV600)

o Output data rates of up to 45 Mbps (for XCV600)

Latency of 111 clocks.

Parallel architecture design

Trace-back logic for continuous decoding

Trace back length of 35.

Soft decision decoding design

Fully synchronous design.

Rate i.e. output rate (frequency) relative to the input is 1/2. This means, output rate is twice that of

the input rate. Two bits are output for every single bit that is input.

Location of the taps on the shift register

o G0 = OCT”171”. This implies octal code for the lower connections to the shift register.

o G1 = OCT”133”. This implies octal code for the upper connections to the shift register.

Input/Output Block:

The Input/Output block diagram of the Viterbi decoder is shown in Figure 1. Table 1 gives a brief description

about the Input/Output pins.

VXL Technologies Ltd. Kolkata - 700 001 India Tel.: +91-33-2213 3685/86 E-Mail : sales@vxldesign.com www.vxldesign.com

SCLR

DOUT1

CLK

VIN1 VOUT

DATAINI (2:0)

OUTOFSYNC

DATAINQ (2:0)

CLK in Input clock

VIN1 in Active high input data valid signal

www.vxldesign.com

DATAINI in 3-bit in-phase input data component

DATAINQ in 3-bit Quadrature input data component

DOUT1 out Decoder output

VOUT out Active high output valid signal

OUTOFSYNC out Active high signal determines whether decoder

is out of synchronization

The functional block diagram of Viterbi decoder is shown in Figure 2. The decoder has three functional

blocks:

Add compare select Unit

Register Exchange Unit

Symbol Branch Metric Compare Metric Register Bit Stream

Metric Select Exchange

Expected Unit Unit Unit

Symbol

This unit calculates the branch metrics. The branch metric block structure is shown in figure 3.

For hard decision decoding, branch metric is calculated using hamming distance between received symbol

and expected symbol. In this case, received symbol is noisy input to the decoder and the expected symbol is

the actual output generated due to the state transition of 6-bit state register.

2

Received symbol

Count the

XOR number Branch metric

of 1s

Expected symbol

Internal block structure of the Add compare select unit is shown in figure 4. This block selects the surviving

branches based on minimum path metrics.

PM0 PM1

www.vxldesign.com

Compare Compare

Select Select

PM0’ PM1’

Note: PM’s and BM’s are path metrics and branch metrics respectively.

PM’s are calculated by adding BM’s with corresponding PM’s at every state. In add compare select unit,

selection is started immediately after the clocking when all PM’s are available in the trellis.

This unit generates the decoded data bit. The register exchange information generation method is depicted

in figure 5.

The register exchange approach assigns a register to each state. The register records the decoded output

sequence along the path starting from the initial state to the final state. After completion of receiving the

data, minimum PM is selected at a particular state. Register contained data corresponding to the state with

minimum PM is picked out and this data is the required decoding output. Since there is no need to trace

back, register exchange is high speed decoding technique.

3

S63

S48 11

S32 1 10

S16 01

S0 0 00

www.vxldesign.com

Figure 5: Register Exchange information generation method

CLK

SCLR

VIN

DATAINI

DATAINQ

VOUT

DOUT1

4

Test Results:

Number of input data to the encoder is 10000. Table 2 shows the bit error rate at different values of signal to

noise ratio. A graph is plotted for the above values which is shown in Figure 7.

0 0.4290

1 0.3592

2 0.2768

3 0.2037

4 0.0879

5 0.0441

6 0.0222

7 0.0051

8 0.0013

9 0.0008

10 0

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Table 2: Test results of bit error rate

Note:

Eb/No is Signal-to-Noise Ratio (SNR).

AWGN: Additive White Gaussian Noise

BER

Eb/No (dB)

5

Synthesis Abstract:

Number of slice Flip Flops : 1395 out of 13824 10%

Number of 4 input LUTs : 3267 out of 13824 23%

Number of IOs : 12

Number of bonded IOBs : 12 out of 320 3%

Number of BRAMs :5 out of 24 20%

Number of GCLKs :1 out of 4 25%

Timing summary:

Speed Grade : -6

Minimum input arrival time before clock : 19.95 ns

Maximum output required time after clock : 9.13 ns

Implementation Details:

www.vxldesign.com

Supported families Xilinx Spartan 3, Virtex, Virtex 2/Pro, Virtex 4, Virtex 5

Synthesis Xilinx XST

HDL VHDL

Xilinx Virtex V600BG432-6 45 1700 5

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