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Viterbi Decoder

IP Cores Technical Datasheet

Introduction:

A Viterbi decoder uses the Viterbi algorithm for decoding a bitstream that has been encoded using Forward
Error Correction based on a convolutional code (Convolutional encoding is a process of adding redundancy
to a signal stream in order to increase its robustness). In the decoder, the convolutional coded sequences
that have been corrupted by channel noise are decoded back to the original sequence.

Many digital transmit-receive systems use a Viterbi decoder for decoding the convolutionally coded data.
The digital data stream (e.g., voice, image or any packetized data) is first convolutionally encoded,
modulated and transmitted through a wired or wireless channel. Various noises may enter the transmission
channel. At the receiver side, the received data from the channel is demodulated and then decoded using
the Viterbi decoder. By using the minimum likelihood algorithm, the Viterbi decoder core is able to correct for
errors in the data caused by channel noise. The decode output is equivalent to the transmitted digital data
stream.

Salient Features:

The main features of the Viterbi decoder core are:

 Industry standard Decoder


o Constraint length k = 7, rate = ½, G0 = OCT”171”, G1 = OCT”133”
 High speed design
o Operating frequency of 45 MHz (for XCV600)
o Output data rates of up to 45 Mbps (for XCV600)
 Latency of 111 clocks.
 Parallel architecture design
 Trace-back logic for continuous decoding
 Trace back length of 35.
 Soft decision decoding design
 Fully synchronous design.

Industry Standard for Viterbi Decoder:

The following is the Industry standard for Viterbi decoder:

 Length of the number of stages in the shift register is 7.


 Rate i.e. output rate (frequency) relative to the input is 1/2. This means, output rate is twice that of
the input rate. Two bits are output for every single bit that is input.
 Location of the taps on the shift register
o G0 = OCT”171”. This implies octal code for the lower connections to the shift register.
o G1 = OCT”133”. This implies octal code for the upper connections to the shift register.

Input/Output Block:

The Input/Output block diagram of the Viterbi decoder is shown in Figure 1. Table 1 gives a brief description
about the Input/Output pins.

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SCLR
DOUT1
CLK

VIN1 VOUT

DATAINI (2:0)
OUTOFSYNC
DATAINQ (2:0)

Figure 1: Input/Output block diagram of Viterbi decoder

Pin Name Direction Description

SCLR in Active high synchronous clear


CLK in Input clock
VIN1 in Active high input data valid signal

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DATAINI in 3-bit in-phase input data component
DATAINQ in 3-bit Quadrature input data component
DOUT1 out Decoder output
VOUT out Active high output valid signal
OUTOFSYNC out Active high signal determines whether decoder
is out of synchronization

Table 1: Input/Output Pin Description

Functional block diagram:

The functional block diagram of Viterbi decoder is shown in Figure 2. The decoder has three functional
blocks:

 Branch Metric Unit


 Add compare select Unit
 Register Exchange Unit

Received Branch Add Path Decoded Data


Symbol Branch Metric Compare Metric Register Bit Stream
Metric Select Exchange
Expected Unit Unit Unit
Symbol

Figure 2: Viterbi Decoder block diagram

Branch Metric Unit:

This unit calculates the branch metrics. The branch metric block structure is shown in figure 3.

For hard decision decoding, branch metric is calculated using hamming distance between received symbol
and expected symbol. In this case, received symbol is noisy input to the decoder and the expected symbol is
the actual output generated due to the state transition of 6-bit state register.

2
Received symbol
Count the
XOR number Branch metric
of 1s

Expected symbol

Figure 3: Branch Metric Unit

Add compare select unit:

Internal block structure of the Add compare select unit is shown in figure 4. This block selects the surviving
branches based on minimum path metrics.

PM0 PM1

BM0 + BM1 + BM2 + BM3 +

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Compare Compare

Select Select

PM0’ PM1’

Figure 4: Add compare select unit

Note: PM’s and BM’s are path metrics and branch metrics respectively.

PM’s are calculated by adding BM’s with corresponding PM’s at every state. In add compare select unit,
selection is started immediately after the clocking when all PM’s are available in the trellis.

Register Exchange unit:

This unit generates the decoded data bit. The register exchange information generation method is depicted
in figure 5.

The register exchange approach assigns a register to each state. The register records the decoded output
sequence along the path starting from the initial state to the final state. After completion of receiving the
data, minimum PM is selected at a particular state. Register contained data corresponding to the state with
minimum PM is picked out and this data is the required decoding output. Since there is no need to trace
back, register exchange is high speed decoding technique.

3
S63

S48 11

S32 1 10

S16 01

S0 0 00

t=0 t=1 t=2 t=n

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Figure 5: Register Exchange information generation method

Decoder Timing Diagram:

CLK

SCLR

VIN

DATAINI

DATAINQ

VOUT

DOUT1

111 Clock Latency

Figure 6: Timing Diagram of Viterbi Decoder

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Test Results:

Number of input data to the encoder is 10000. Table 2 shows the bit error rate at different values of signal to
noise ratio. A graph is plotted for the above values which is shown in Figure 7.

Eb/No (dB) (AWGN) Bit error rate (x 10-4)

0 0.4290
1 0.3592
2 0.2768
3 0.2037
4 0.0879
5 0.0441
6 0.0222
7 0.0051
8 0.0013
9 0.0008
10 0

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Table 2: Test results of bit error rate

Note:
Eb/No is Signal-to-Noise Ratio (SNR).
AWGN: Additive White Gaussian Noise
BER

Eb/No (dB)

Figure 7 Graphical representation of the Bit Error Rate test

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Synthesis Abstract:

Device utilization summary:

Selected device : v600bg432-6

Number of slices : 1991 out of 6912 28%


Number of slice Flip Flops : 1395 out of 13824 10%
Number of 4 input LUTs : 3267 out of 13824 23%
Number of IOs : 12
Number of bonded IOBs : 12 out of 320 3%
Number of BRAMs :5 out of 24 20%
Number of GCLKs :1 out of 4 25%

Timing summary:

Speed Grade : -6

Minimum Period : 39.50 ns (Maximum Frequency: 25.31 MHz)


Minimum input arrival time before clock : 19.95 ns
Maximum output required time after clock : 9.13 ns

Implementation Details:

Simulation ModelSim PE or other standard simulators.

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Supported families Xilinx Spartan 3, Virtex, Virtex 2/Pro, Virtex 4, Virtex 5
Synthesis Xilinx XST
HDL VHDL

Device utilization summary:

Target Device Max. Frequency (MHz) Slice’s used Block RAMs


Xilinx Virtex V600BG432-6 45 1700 5