Dual-Band RF Receiver Chip-Set for Galileo/GPS

applications
M. Detratti, E. López, E.Pérez, R.Palacio and M. Lobeira
Acorde Technologies S.A
Avda. Los Castros s/n, 39005 Santander, Spain

Abstract — This paper describes the development of a highly linear
Radio Front-End, able to operate with Galileo and GPS satellite signals
suitable for coexisting in a cellular hostile environment for location
based services, satisfying the basic requirements for a mass market
product such as low cost, low footprint, good accuracy, low power
consumption and high sensitivity. The target is a high sensitivity Galileo
E1/E5A and GPS L1/L5 Dual-System Dual Band GNSS switching
receiver front-end with a low-IF architecture. The first step toward the
implementation of a fully integrated mass-market product has been
carried out implementing three different multifunction chips using a
low-cost commercial 018µm CMOS technology: a dual band LNA, a
downconverter with integer PLL synthesizer and a broadband IF
section comprising a digitally controlled VGA and tunable filter. The
complete multi-chip assembly could be housed in a low cost 4x4mm2
package with overall 2.5dB Noise Figure, 117dB Gain, 9MHz
Bandwidth and consuming 54mW @1.8V.
Index terms — Dual-band front-end, Galileo, GPS, Mass Market
Receiver, CMOS technology, Wireless Communication Systems
I. INTRODUCTION
The integration of positioning capabilities into electronic
and handheld devices is experiencing a very fast grow-up
while the number of location based services (LBS) and
positioning applications to deal with in everyday life is
foreseen to increase in the next few years. This strongly
demands for a continuous reduction in power consumption,
layout area and costs for the radio implementations. Moreover,
with the appearance of new GPS civil signals and the
concurrent development of Galileo (Fig.1), new possibilities
will be offered to location capabilities in difficult scenarios
like indoor and dense urban which have been the most critical
for positioning services so far. For these reasons, GNSS
multi-frequency receivers are likely to become the product of
choice for accurate positioning inside buildings or personal
navigation in hostile signal environments, allowing the use of
the improved individual characteristics of the new signals to
implement higher quality and more reliable services. The
basic requirements for such type of receivers are evident: high
sensitivity, good positioning accuracy and robust navigation.
As the GNSS receiver will be working most of the time, it
should also be capable of co-exist with a wide range of
wireless communication systems (WCS) which can be
embedded in the same electronic device posing a set of
additional requirements compared with traditional standalone
navigation receivers.
For a cost-optimized and power-efficient mass-market
product, only the narrowband L1 frequency signals (GPS-L1
and Galileo-E1) shall be supported. This solution has been the
scope of different European research programs ([1]-[3]) and
adopted in multiple commercial GPS receivers ([4]-[6] among
others). The main drawback of such navigation systems is still
its poor sensitivity performance in non-line-of-sight (NLOS)
and multipath environments. Additionally, the precision may
become soon unacceptable for future advanced applications.
Processing a second frequency block among the new Open
Service (OS) GNSS signals with the possibility of using even
broader bandwidth (BW) would allow the users to subscribe
premium services with higher accuracy and multipath
performance, hence reducing the navigation errors even at the
cost of higher complexity and power consumption. The
objective of a dual-band hybrid Galileo/GPS receiver aimed
at the consumer mass market should be to maximize RF
resources re-use, maintaining size and power consumption
with respect to present single-band solutions. This represents
the scope of the research activities on the radio Front-End
within the GREAT project [7], whose results will be detailed
in the following sections.
This paper is organized as follows: first of all, the selected
receiver architecture and the application scenario will be
presented. In section III the fundamental front-end
requirements are described while section IV discusses the
basic building blocks of the targeted receiver. The
performances and simulated results of the implemented
prototypes will be reported in section V. A careful
comparison with state of the art implementations is discussed
in section VI, while conclusions will be drawn in section VII.
Figure 1: Spectral location of O pen Service Galileo and GPS Signals

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 II. DUAL-BAND RECEIVER ARCHITECTURE
A. System Overview
A complete GNSS receiver is built-up by two main blocks:
an RF Front-End and a Baseband subsystem, the former is
associated to the RF signal processing while the latter in
charge of the digital demodulation process. In spite of the
demonstration of some GPS systems on chip (SoC) that have
already been done ([8], [9]), integration into a single die
might not be always be the optimum solution in terms of yield
(due to large size), performance degradation (due to the
effects of the digital circuitry), testing costs and design
complexity. Another important disadvantage is also
associated to the fact that RF and digital technologies are
developed at a different speeds (and prices) and that at any
given time there is no single technology available that results
in optimal cost for a fully integrated single die solution. A
single chip design will hardly lower the cost of a dual chip
solution, as demonstrated in [10]. It has thus been decided to
investigate a dual chip solution, separating analog Front-End
(FE) and baseband Subsystem (Fig.2) and following a system
on package (SoP) approach for the integration, to be
addressed in the next stages of the project. The development
of the RF part is addressed in this paper.
B. RF Architecture
Direct conversion topologies are the best candidate for the
FE implementation. A zero-IF or low-IF architecture in
CMOS technology must be selected for the radio due to the
high integration and low cost capabilities [11]. Given the
CMOS selection and the nature of GNSS signals, with
significant amount of energy located close to DC, a Zero-IF
implementation is unpractical and difficult due to the
presence of strong flicker (1/f) noise. For this reason a low-IF
solution is preferred. Generally, the use of this type of
architecture requires complex and power hungry on-chip
image rejection schemes. However, as long as the digital
processing is able to work with complex signals and perform
the final down-conversion, it can be shown ([10], [11]) that it
is possible to implement the receiver using only real low-pass
filters and no image rejection topologies. Image-suppression
is performed by digital baseband, with clear advantages in
Figure 2: High Level System Architecture
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terms of power consumption and matching which would be
needed if image rejection were performed at RF.
Considering the GNSS frequency spectrum depicted in Fig.
1, it appears clear that the best solution for a dual-band hybrid
receiver would be the selection of L5 as the second frequency
block. In this case, GPS and Galileo share the same spectrum,
and the decoding of this second group of signals does not
generate additional charges for the user. As it is unlikely that
both channels at L1 and L5 will be used simultaneously, in
order to save power and size to meet mass market
requirements this selection allows to share most of the RF
resources.
For maximum HW reuse, a common bandwidth must be
selected to ensure a good trade-off between power
consumption and the quality of the demodulated signal at
both bands. The main problem is associated to the E5a signal,
whose power is spread over a 25MHz band (Table I).
Assuming that not all the users need the same position
accuracy and that E5a processing is not needed all the time;
some losses can be tolerated. It has been shown in [12] that
9MHz of receiving bandwidth is sufficient to limit the power
loss to 1.2dB, which has been considered acceptable for most
applications. This bandwidth comprises multiple lobes of
E1/L1 signals thus reducing the integration time to provide
good sensitivity. A common bandwidth approach leads to a
switching receiver architecture, which should allow better
accuracy and multipath mitigation because of the different
wavelengths and the higher chipping rate on E5a band. For
E5a, an acquisition engine is not needed, since the
information from L1 acquisition could be used to initialize
E5a tracking as well. The switching process however must be
fast enough, because the code phase of every signal must not
change significantly during this time to virtually track both
bands at the same time. The measurement of the delay
difference between the L1 and E5a signals would also enable
ionospheric errors correction. This approach is very
innovative and it is not clear yet how the switching will affect
the performances, but it seemed the most interesting solution
in terms of power consumption and reusability. In fact, even
if this architecture doesn’t allow the simultaneous acquisition
of both signals, the use of a quadrature downconverter and
two separate IF sections for the I and Q paths, preserves the
TABLE I
GALILEO/GPS SIGNAL CHARACTERISTICS AT L1/E1-L5/E5A
Standard GPS L1 GPS L5 E1 E5a
Frequency(MHz) 1575.42 1176.45 1575.42 1176.45
Bandwidth(MHz) 2.046 20.46 4.092 25.575
Modulation BPSK BPSK BOC(1,1) BPSK
Data rate (bps, Rb) 50 100 250 50
Chip rate (Mcps, RC) 1.023 10.23 1.023 10.23
Rx Power, LOS (dBm) -128 -124 -127 -125

Figure 3: Simplified Block diagram of the Dual-band receiver
Figure 4: Integration Scenario
information necessary to separate them and the same circuitry
could be used in case of simultaneous reception.
The receiver architecture is shown in Fig.3 in which the
basic circuits that will be implemented are indicated. An
external band-pass filter between the input LNA and the
down-converter is needed to attenuate the WCS interferers
and relax the linearity requirement of the receiver (Sec. III)
avoiding too high power consumption. Depending on the
selected band, the RF signal is I/Q demodulated and
downconverted to 3.42MHz (E1/L1) or 3.25MHz (E5a/L5).
The choice of the IF frequencies is motivated by conflicting
factors: gain-bandwidth product of the amplifiers in the IF
section and low frequency noise effect. The former demands
for the lowest possible IF (especially in a broadband receiver)
while the latter for an IF high enough to easily eliminate DC
offset and 1/f noise effect. In our case, the above mentioned
selection represents a good trade-off. This choice makes the
transmitted spectrum zeros to be located close to the origin,
further reducing flicker noise effect on the demodulation
accuracy.
III. RADIO FRONT END REQUIREMENTS
Under ideal operating conditions, standalone navigation
receivers deals uniquely with the signals they are intended for
and their characteristics (summarized in Table I) are the
factors that determine their requirements. Now, the likely
integration scenario is the one depicted in Fig. 4, with
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separate antennas for positioning and communication systems
as the most common choice. Co-existence with multiple
WCSs can lead to the degradation of the receiver performance,
so the goal is that the designed GNSS receiver should be
capable of working correctly in a hostile environment, in
which both GSM and CDMA signals can be present. A highly
linear and low noise receiver, operating at low power
consumption is thus required.
The received signal is below the input referred thermal
noise (~ -104.45dBm for a 9MHz bandwidth), and is only
after the digital demodulation process that the signal is
despreaded and raised above noise by the processing gain
associated to the modulation scheme. Once known the
required minimum value of C/No (or Eb/N0) for demodulation
to take place, and the degradation caused by intrinsic noise
and the presence of interferers, this has to be minimized by
proper system specifications. The main causes of such
degradation are Noise Figure (NF), Intermodulation distortion
and LO phase noise.
The NF requirement can be calculated knowing that the
input referred thermal noise must be lower or equal to the
maximum acceptable noise power (PN, determined by the
required minimum sensitivity and modulation characteristics)
in absence of interfering signals:
PN =-174dBm/Hz +NF +10log10 (BW). (1)
In the intermodulation (IMD) test case (both in-band and
out-of-band) the received signal is assumed to be 3dB above
the minimum sensitivity and the allowed noise contribution is
fixed 7dB below input referred noise (20% contribution).
Second-order distortion is neglected because of the low-IF
topology. To calculate the required performance, the amount
of interference coming from other services has to be known.
This is mainly determined by the physical separation between
antennas and their type and characteristics. Previously
published results [13], demonstrate that isolation values in the
order of 35dB, at lower, and 45dB, at upper WCS frequencies
can be obtained with less than 4cm separation. The worst-case
scenario can be considered the E1 reception with a DCS
interferer, which is only 135MHz far from the wanted signal
and can be present at the radio (LNA) input with -15dBm
(Table II). As no interferers are specified in GNSS standard,
we must specify an auxiliary signal to produce an in-band
TABLE II
WCS TRANSMISSION AND SPURIOUS EMISSIONS WITHIN A HANDSET
DEVICE
Max. Tx. Power
Standard Tx. Freq. (MHz)
(dBm)
IS-95 824-849,
CDMA2000 1850-1910
+23
E-GSM 880-915 +30
DCS 1710-1785 +30
PCS 1850-1910 +30
UMTS 1920-1980 +24
E-GSM, DCS,PCS
1000-1700 -47
Spurious
IS-95, CDMA,UMTS
Spurious
1000-1700 -30
 intermodulation product. For this purpose, out-of-band CW TABLE III
interference at 67.5 MHz with -57dBm power (e.g. a GSM SUMMARY OF RECEIVER REQUIREMENTS
spurious emission with 10dB path loss attenuation; but the
Parameter Requirement Comments
same value has been deduced in [14] for a Bluetooth signal)
RF freq 1176.45MHz and 1575.42MHz E5a/L5 - E1/L1
has been used, resulting in an out-of-band IIP3 requirement of -144dBm sensitivity
NFRx <2.5dB
-11.5dBm. It is worth noting that this requirement affects at E1
Input
mainly the input LNA because the interferers are strongly match
<-10dB
attenuated after the post-LNA filter. Concerning the in-band BW 9MHz
IMD, the spurious emissions described in Table II ([15]) and IF freq 3.25MHz and 3.42MHz L5/E5a and L1/E1
a minimum of 10dB path loss have been considered. Values >-11.5dBm out-of-band (LNA)
45dB isolation
atDCS1710
for the in-band IIP3 are in the order of -25dBm, which in this IIP3
10dB min. path loss
>-24dBm in-band (Rx.)
case demands high linearity throughout the RF chain, unless between antennas
higher values of path losses were assumed. Phase <-85dBc/Hz average in-band 20dB pre mixer
Noise <-145dBc/Hz @130Mhz offset selectivity
The phase noise of the local oscillator (LO) also corrupts OP1dB >1Vpp At the IF outputs
the spectrum and degrades the C/No as it can mix-up with the GV 116dB Voltage Gain
interferer and overlap the GNSS signal (Fig.5). To keep the ∆GV 40dB Min. gain range
reciprocal mixing product below maximum acceptable noise
in the worst case scenario (assuming 10% contribution), the broadband operation and low power requirement sets very
phase noise of the LO should be better than demanding block specifications compared to single-band
~ -165dBc@130Mhz offset, which is a challenging value for standalone solutions. In the following sections, the referred
low-power CMOS VCO. Reducing the interferer power at the building blocks will be presented.
input of the downconverter, the requirements of not only the
VCO, but also the mixer, can be relaxed. For this reason a A. Dual Band LNA
post-LNA filter has been included. The value of 20dB
selectivity was deemed satisfactory (and easily achievable) to Two alternatives solutions are valid for the input LNA: a
simplify the design. single broadband circuit or two narrow band solutions
Details on the complete deduction of the front-end centered at each band. The NF and gain requirements are very
requirement is out of the scope of this work (the interested stringent as they set a minimum in the attainable receiver NF
reader can refer to [16] for an extensive analysis). A summary and should limit mixer noise contribution. Power
of the targeted radio specifications is reported in Table III. consumption and linearity must be also carefully considered.
Due to these reasons, the option of a broadband LNA with
IV. CHIP-SET DESIGN sufficiently small NF and low power consumption seems to
be unfeasible ([17], [18]), leaving the narrowband design able
to be tuned to operate at both bands, as the only practical
As a first step toward the implementation of a fully choice. A single-ended common-source inductively
integrated mass-market product, three different multifunction degenerated cascode topology has been selected as the basis
chips have been designed to implement the chosen for the design, so as to provide good noise performance at
architecture and taking into account the specific requirements: reduced power consumption. Sub 1-dB NF and a high gain
a dual-band LNA circuit, a downconverter with integer were the main design targets, together with high out-of-band
synthesizer and an IF chip. The need of supporting such kind linearity. The schematic of the designed LNA is presented in
of specifications combined with the multifrequency and Fig. 6, where the external inductor used for matching the
amplifier at the two frequencies of interest, is also shown. The
external inductor solution has been preferred due to the low
quality of the inductors which can be fabricated with the low-
cost selected process (only a 2µm thickness of top metal layer
is allowed). The input DC-blocking capacitor and the gate
polarization network are implemented on-chip and two
properly sized input parallel transistors are used to simplify
the matching, enhance the gain and improve the linearity of
the inductive degenerated topology. The drain inductor is
used for biasing and output matching together with a
reconfigurable on-chip network. By means of a control bit the
output response can be matched to the selected band, allowing
the use of the same design at both frequencies. A power down
feature permits to save power by deactivating the LNA of the
Figure 5: Reciprocal Mixing of LO with WCS interferer (Worst case) band that is not being received at a given time.

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 Figure 6: Input LNA topology

B. I/Q Downconverter
The designed quadrature downconverter is built up by a
low noise preamplifier and two mixers, and is common for all
bands. The input is matched to 50Ω, as it has to be connected
to an external filter. Local oscillator (LO) inputs and I/Q
outputs are fully differential and matched to synthesizer and
IF impedance. In order to reduce the size and power
consumption of the downconverter, the preamplifier is
designed with single ended input and output, and the
conversion to differential is performed in the mixers. To
eliminate the need of large input broadband matching
networks and minimize the degradation of NF, the
preamplifier is implemented using a common gate topology.
As far as the mixing core is concerned, a quadrature single
balanced topology is selected to save power and reduce noise
with respect to the Gilbert cell structure. A single
transconductor is used for both I and Q mixer, limiting the
power consumption and improving the LO to RF leakage due
to LO cancellation on the transconductor. The size of the
active devices in the mixer has been traded-off taking into
account both linearity and noise. Moreover, a second order
low pass filtering is used at mixer output to attenuate
interferers and the local oscillator component, generated by
the single balanced topology. Complete schematic of the
down-converter is presented in Fig. 7.
C. Synthesizer with VCO
The PLL-based frequency synthesizer uses a double
mutually-synchronized cross coupled quadrature VCO
(QVCO) to achieve wide tuning range and good noise
performance with reduced power consumption. Two
symmetrical oscillators synchronized with each other
oscillates in quadrature ([19]) and are thus capable of
generating the four signals required by the mixers, whose
inputs are directly connected to the QVCO tanks. Input
impedances are essentially capacitive, which allows high
voltage swing while keeping low power consumption. Fig. 8
shows the schematic of one of the VCOs. In consideration of
covering both frequency bands over all possible temperature
Figure 7: Quadrature down-conversion stage
Figure 8: QVCO cell schematic
and process parameters deviations, four banks of digitally
switched capacitors have been added. This also allows a
precise control over the tuning range of the VCO by selecting
the frequency interval in which the lock is achieved at the
proper varactor voltage. The automatic selection of these
switches is performed by the control circuitry after a self-
calibration process during power-up. The loop prescaler is a
dual-modulus 32/33 divider, comprising a divide-by-8/9
prescaler and a modulus-4 counter (Fig. 9). All the logic cells
are full-custom designs. A low power differential-to-single
ended stage, connected to one of the differential outputs of
the QVCO is used to drive the input clock signal. The rest of
the loop divider uses standard CMOS cells. Phase-frequency
detector operates at 1MHz, and the design is based on a
typical dual flip-flop implementation. The input frequency
reference is selectable between two values (13 and 26 MHz)
which are quite common in WCS implementations.
Simplified charge-pump schematic is shown in Fig. 9.
Feedback circuitry ensures precise matching between
up/down current sources in order to minimize spurs [20].The
charge-pump current also has a 4-bit control to provide 15
different loop gain values as well as a power-down state. All
digital control is performed by an integrated SPI interface.

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 drifts associated to the process parameters variations. The
circuit features the 9 MHz cut-off frequency with less than
0.5dB in-band ripple and attenuation greater than 16dB at 12
MHz. As the baseband is the limiting block of the receiver
linearity performance, an active-RC implementation has been
preferred to gm-C solutions even at the cost of higher power
consumption. A two-stage fully differential Miller
compensated OpAmp is used as basic cell for all the stages in
(a)
the section.
The VGA consists of 4 stages, each of which provides 3
variable gain steps controlled by and integrated SPI interface.
The overall gain control range is in the order of 45dB in 1-dB
steps. A fixed gain output buffer stage, capable of driving up
to 10pF capacitive loads, has been used to allow the interface
with most ADCs, resulting in an overall IF gain of more than
77dB. Overall current consumption is 7.3mA for a single
chain (to be used twice in the receiver). AC-coupling is also
performed throughout the chain by means of on chip RC
networks, to avoid the propagation of the DC-offset and the
consequent saturation of the last amplifying stages. The
complete schematic of the analog IF circuitry is shown in
(b) Fig.11 and the simulated results plotted in Fig.12.
Figure 9: Simplified schematic of (a) Dual-modulus 32/33 prescaler
and (b) charge pump basic
V. EXPERIMENTAL RESULTS

D. IF Analog Section
The presented circuits have been implemented in a
The signal which entering the IF section is essentially commercially available low cost 0.18µm 1P6M RFCMOS
broadband noise plus interferers, with the GNSS signals still technology from UMC. Fig. 13 depicts the complete FE chain
below thermal noise. A low-pass filter (LPF) selects the with external filters and band selection switch, housed in a
useful signals and attenuates the out-of band jammers, while a hypothetical 4x4mm package and containing the newly
variable gain amplifier (VGA) raises the signal up to a developed MMIC.
detectable level compatible with ADC input. In the IF strip Unfortunately the measurement of the whole receivers was
the signal should be also filtered for anti-aliasing purposes, not possible due to layout errors in the PLL and the IF section.
providing at least 15dB attenuation at half the sampling rate.
To cope with low power ADC solutions in the baseband, the
sampling rate has been fixed to 24MHz. This, together with
the 9MHz BW, sets stringent requirements on the filter which
should have a very steep out of band response.
The filter implements a 4th order Chebychev function using
a Tow-Thomas topology (Fig.10). The high-Q biquad is
placed first in the filter chain to minimize noise contribution Figure 11: Schematic of the analog IF section
of the filter. Every capacitor is actually composed of 5-bit
binary weighted array of capacitors to allow digital
adjustment of the filter cut-off frequency, due to possible

Figure 10: 4th order Tow-Thomas active filter Figure 12: Simulated response of the complete IF chain at different
gain settings

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Figure 13: Radio FE SoP solution (4mmx4mm, in scale)
A fault was found in the input reference prescaler, which led
to metastability in some sections of the digital block, thus
preventing the PLL from locking. On the other side, an
underestimation in the tolerances of the miller capacitance
used in the OpAmps lead to a common mode oscillation in
the IF strip, making that block unusable. Nevertheless, the
remainder of the blocks and individual circuits were tested
showing promising results with very good agreement with the
simulations.
Figure 14: Measurement and simulation results of the LNA
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The LNA is capable of low noise performance (less than
1dB NF at E1/L1) with enough linearity to be used in an
interference hostile environment at both bands by simply
changing the input SMD inductor. Measured gain and NF,
centered at the two operating frequencies, are shown in Fig.14.
The measured input 1dB compression point is around -12dBm,
while IIP3 is -5/-9dBm at E1/E5a respectively, with only
3.9mA current consumption. These results are in line with
state-of-the-art LNAs that can be found in literature [21].
Compared with commercial GPS products [22], the fabricated
LNA achieves similar performance with lower power
consumption.
The measured and simulated results for the downconverter
are compared in Fig. 15. A broadband input match is obtained
without the need of external components, in good agreement
with the simulations. The 3mA power consumption is very
low considering the measured 11dB NF and the high value of
-14dBm of input IP3. The measurement of the mismatch
between downconverter outputs when this was fed by the
integrated QVCO, lead to less than 1º phase and 1%
amplitude mismatches, showing the degree of symmetry
achieved in both the QVCO and the downconverter layouts.
The cascade of the LNA and mixer was also characterized
giving an overall gain always greater than 40dB with les than
2.2dB NF. These values can be considered enough to mask
the NF worsening caused by the IF section. Only 0.2dB NF
degradation has been observed placing an external filter
between the two circuits (Fig.16).
Even if the synthesizer was not working, the separate
characterization of the QVCO has been carried out. It is
capable of spanning the frequency range from 1.05 to 2.15
Figure 15: Measured and simulated Downconverter performance
Figure 16: NF performance of the RF section (LNA and Mixer) with and
without external filter
 TABLE I V
RF MEASURED PERFORMANCE
Parameter Result Units Notes
RF freq 1176.45and 1575.42 MHz
NFRF 2,4 dB with filter
GRF >40 dB LNA+Downconverter
S11 >-13/-15 dB LNA/ Downconverter
IF freq 3.25 and 3.42 MHz E5a/L5 and E1/L1
>-9 dBm LNA out-of-band
IIP3 LNA+Downconverter
-30 dBm
in-band
Figure 17: QVCO phase noise performance (E1) LNA+Downconverter
IP1dB -38* dBm
in-band
GHz with less than 6mA consumption. This corresponds to a PhN@1MHz -107/-115 dBc/Hz E5a/E1
huge tuning range of 70% centred at 1.6GHz. Fig. 17 shows *
Sufficient to tolerate the highest in-band jammer of -40dBm
the measured phase noise of the QVCO in one of the
frequency intervals that would allow the L1/E1 lock. Phase [23], can be justified with the very high performance used
noise measurements are slightly worse than simulations, technology (a 0.18µm SiGe with 5.25µm top metal layer)
albeit fully compliant with the requirements of the intended which allows the use of inductors with more than twice the
application. The fact that the circuit was measured inside the quality factor and bipolar transistors to save a large amount of
faulty synthesizer, whose digital block could be the source of current, especially in the VCO (which consumes only 1.2mA).
additional noise through the calibration lines, might Nevertheless, almost all the solutions use a single frequency
contribute to this discrepancy. VCO, while the proposed QVCO achieves an outstanding
As stated previously, due to the oscillation problem, the IF 70% tuning range with better phase noise performance except
section could not be characterized. However, considering the from [14] which targets a VCO for simultaneous cellular
very good agreement between simulations and measurement applications with very low phase noise, but whose power
observed for the RF circuitry, and the preliminary consumption is not detailed.
implementation results [16], it should be expected that once As a remark regarding the NF, it should be noted that to
solved the oscillation issue (simply changing the miller meet stringent sensitivity GNSS requirements, solutions [4],
capacitor value), IF section behaviour almost matched [23], and [24], would require and external LNA or active
simulations. A summary of the carried out RF measurements antenna. This would cause further increase in power
is given in Table IV. consumption and a detriment of the overall receiver chain
linearity.
All the receivers offer quite narrow receiving BW (only [9]
VI. STATE OF THE ART COMPARISON AND DISCUSSION has a larger BW) which would not allow the reception and
demodulation of the E5a signal. If consideration is made on
A comparison between the performance (measured and the fact that the designed IF section consumes almost 50% of
extrapolated from simulations) of the implemented chip-set the total current mainly because the 9 MHz BW requirements
and present state-of-the-art single band GPS receivers for (twice to four times the commonly used value), the results are
cellular applications ([9], [14], [23]) and Galileo capable front even more encouraging.
ends ([4],[24]) is reported in Table V. It shows how the For these reasons, the authors consider that once solved the
proposed solution could be favorably compared if the fabrication problems, the proposed dual-band solution would
multiple band and broadband features of the proposed represent a big step in the performance of broadband receiver
implementation are taken into account. for the consumer market. To confirm these results, a new
The 30mA current consumption is comparable to the one MMIC run has been taped-out, as the layout errors could be
reported in [9] and [14] implemented with more scaled 90µm easily recovered, with a further degree of system integration
(IF section integrated with the downconverter and synthesizer
and 130µm CMOS technologies. Even if power dissipation in
and a common SPI interface) and to achieve a receiver fully
[9] is by far higher than all the presented values, it should be
stated that it includes voltage regulators and the complete compliant with the original specifications.
SoC implementation, so the radio current consumption is
difficult to estimate. An ADC is not required for the FE VII. CONCLUSIONS
developed in this work (Fig.2), however all the receivers
include only low resolution ADCs (1 or 2 bits), which
contribute to the overall power consumption in no more than In this paper, the development of a Galileo E1/E5A and
2-3mW. Results in [4] and [24] have lower power GPS L1/L5 Dual-System Dual-Band GNSS receiver chip-set
consumption, but almost no information on linearity is for the operation in a handset hostile environment has been
contained, as these solutions do not have to operate in presented. The circuits have been implemented in a
interference hostile environment. The remarkable results in commercial low cost 0.18CMOS technology. Even if parts of

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 TABLE V
COMPARISON WITH STATE OF THE ART G ALILEO/GPS RADIOS

Parameter This Work [9] [14] [23] [4] [24] Units

+
NFRF1 2.2-2.5 * 1.8 N.A 4 N.A N.A dB
+
NFRx 2.6 2.0 2.2 5 4.5 10 dB
+
RX Bandwidth 9 <4 <2.5 2 6 4.4 MHz
LNA IIP3 ++
-5/-9dB *(E1-E5a) 5 -22** -8*** - - dBm
out-of-band
RX IIP3
-30* Low2 -23 -8*** -57+++ - dBm
in-band
LO Phase Noise -115@1MHz * -113dB@1MHz -130@1.25MHz -108@1MHz -80@100kHz - dBc/Hz
+
Voltage Gain 117 - 68.2 80**** 105 100 dB
Supply Voltage 1.8 1.4 1.2 1.8 2.7 1.8 V
Power dissipation 60/84
(radio FE) 30/54 *+ (full SoC)
41/50 11.4/20 19/51.3 17/30 mA/mW
* + ++
Measured Simulated Complete Receiver at PCS ** 1-dB NF desensitization at 725MHz offset *** 1dB desensitization at 725MHz +++offset input P1dB
(VGA min gain) **** extrapolated
1
Only LNA and Mixer 2 In-band jammers which are 14dB higher than GPS signal level are mentioned

[8] G. Gramegna, et al. “A 56mW 23mm2 Single-Chip 180-nm CMOS GPS

the fabricated chips had shown unrecoverable layout errors,
preventing the complete RF chain characterization, the results
extrapolated from the measurements of the working blocks
have been very encouraging in terms of overall performance.
The power consumption is expected to be in the order of
30mA at a 1.8V supply, including the input LNA. The
measured 2.5dB radio NF includes the effect of the input
external filter, and the receiver BW is almost twice the value
commonly used in mass market GNSS receivers. To the
authors’ knowledge, this is the only documented attempt of
implementing an integrated dual-band interference-robust
broadband mass market Front End for hybrid Galileo-GPS
applications.
ACKNOWLEDGMENT
This work has been carried out within the GREAT project
(Galileo Receiver for the mAss market) which is co-funded
by the European GNSS Supervisory Authority (GSA) with
funding from the 6th Framework Programme of the European
Community for research and technological development.
M. Detratti and M. Lobeira would like to thank the support
received from the Spanish Ministry of Science and the
European Social Fund, through “Torres Quevedo” program.
The authors wish to acknowledge Clemens Bürgi from U-
blox for his valuable discussions and suggestions on Galileo
and GPS systems. They would like also to thank Pedro
Lázaro and Marta Fuentes for the chips and PCB assemblies.
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