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An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions. It is a combination of software and hardware and some other mechanical parts to perform a task. Embedded system means the processor is embedded into that application. An embedded product uses a microprocessor or micro controller to do one task only. In an embedded system, there is only one application software often called firmware that is typically burned into ROM or Flash memory chips rather than a disk drive. It often runs with limited computer hardware resources: small or no keyboard, screen, and little memory. Embedded processors can be broken into two broad categories: ordinary microprocessors (μP) and microcontrollers(μC), which have many more peripherals on chip, reducing cost and size. Contrasting to the personal computer and server markets, a fairly large number of basic CPU architectures are used; there are Von Neumann as well as various degrees of Harvard architectures, RISC as well as non-RISC and VLIW; word lengths vary from 4bit to 64-bits and beyond (mainly in DSP processors) although the most typical remain 8/16-bit. Most architectures come in a large number of different variants and shapes, many of which are also manufactured by several different companies. Embedded Systems talk with the outside world via peripherals, such as Serial Communication Interfaces (SCI)( RS-232, RS-422, RS-485 etc) ,Synchronous Serial Communication Interface(I2C, JTAG, SPI, SSC and ESSI), Universal Serial Bus (USB) ,Networks: Ethernet, Controller Area Network, Lon Works, Timers: PLL(s), Capture/Compare and Time Processing Units ,Discrete IO: Input/Output (GPIO) ,Analog to Digital/Digital to Analog (ADC/DAC) As for other software, embedded system designers use compilers, assemblers, and debuggers to develop embedded system software Example: printer, keyboard, video game player etc. General Purpose
INTRODUCTION TO ETHERNET
HISTORY: Invented by Robert Metcalfe and David Boggs at Xerox PARC in 1973, Ethernet first ran at 2.94 Mbps. Metcalfe later joined Digital where he facilitated a joint venture between Digital, Intel and Xerox to collaborate further on Ethernet. Version 1 was finalized in 1980, and products shipped in the following year. In 1983, the IEEE approved the Ethernet 802.3 standard.
Ethernet is a network standard of communication using either coaxial or twisted pair cable. The most widely used for of LAN communication, Ethernet typically runs at 10 megabytes per second, though newer systems use 100Mbps, or ever gigabits of transfer.Ethernet is the IEEE standard 802.3. It has several different flavors, with the original Ethernet designed with 10base5. The "10" stands for 10 megabytes per second. Base is the Base band communications it uses. The "5" stands for a maximum distance of 500 meters to communicate with. Original Ethernet used coaxial wiring, while newer versions use twisted-pair cabling. There are several flavors of Ethernet, including 10Base2 (10 Mbps, 200 meters), 10BaseT (10 Mbps, 100 meters, twisted-pair), and 100BaseT (100 Mbps, 100 meter, twisted-pair). A specification for "LAN," "LAN connection" or "network card" automatically implies Ethernet without saying so. Ethernet connects devices to a company or home network as well as to a cable modem or DSL modem for internet access. Almost all PCs and Macs come with 10/100 Ethernet ports that connect internally to circuits on the motherboard. A 10/100 Ethernet port supports two speeds: 10 Mbps (10BaseT) and 100 Mbps (100BaseT). Computers also come with 10/100/1000 ports, which includes Gigabit Ethernet at 1Gbps. Gigabit Ethernet (GigE) is commonly used as a high-speed link between switches and servers. Ethernet devices negotiate with each other and transmit at the highest speed possible. However, if a 100 Mbps switch is communicating with a 10Mbbps client, the slower speed is used. Ethernet is wired in a star configuration with a hub or switch in the middle. Hubs, which predated switches, are shared media devices. All stations attached to the hub share the total bandwidth. Switches provide each sender and receiver pair with the full bandwidth and are
significantly faster than hubs. Like the client machines, Ethernet switches and hubs also support 10/100 and 10/100/1000 speeds. Ethernet Frames Ethernet transmits variable length frames from 72 to 1518 bytes in length, each containing a header with the addresses of the source and destination stations and a trailer that contains error correction data
Ethernet version 2 frame format
preamble(8 byte) Destination Source Type (2 Information field Frame Check Address (6 Address (6 bytes) (46 - 1500 bytes) Sequence (4 bytes) bytes) bytes) Preamble is a sequence of 7 bytes, each set to “10101010”, Used to synchronize
receiver before actual data is sent. Type field is a demultiplexing key used to determine which higher level protocol the frame should be delivered to. Addresses:unique, 48-bit unicast address(example: 8:0:e4:b1:2:5) assigned to each adapter. Each manufacturer gets their own address range. For broadcast: all 1s The Frame Check Sequence (FCS) is a part of the frame put in place to verify that the information each frame contains is not damaged during transmission. If a frame is corrupted during transmission, the FCS on the frame will not match with the recipient's calculated FCS. Any frames that do not match the calculated FCS will be discarded Collision Detection Ethernet uses the CSMA/CD technology to broadcast each frame onto the physical medium (wire, fiber, etc.). All stations attached to the Ethernet are "listening," and the station with the matching destination address accepts the frame and checks for errors. Ethernet is a data link protocol (MAC layer protocol) and functions at layer 1 and 2 of the OSI model. .
INTRODUCTION OSI REFERENCE MODEL
The Open Systems Interconnection Basic Reference Model (OSI Reference Model or OSI Model for short) is a layered, abstract description for communications and computer network protocol design. It was developed as part of the Open Systems Interconnection (OSI) initiative and is sometimes known as the OSI seven layer models. From top to bottom, the OSI Model consists of the Application, Presentation, Session, Transport, Network, Data Link, and Physical layers. A layer is a collection of related functions that provides services to the layer above it and receives service from the layer below it. For example, a layer that provides error-free communications across a network provides the path needed by applications above it, while it calls the next lower layer to send and receive packets that make up the contents of the path. The most major difficulty with the OSI model is that is does not map well to the real world. The OSI was created after many of today’s protocols were already in production use. These existing protocols, such as TCP/IP, were designed and built around the needs of real users with real problems to solve. The OSI model was created by academicians for academic purposes. The OSI model is a very poor standard, but it's the only well-recognized standard we have which describes networked applications. The easiest way to deal with the OSI model is to map the real-world protocols to the model, as well as they can be mapped. The difficulty with this approach is that there is no general agreement as to which layer of the OSI model to map any specific protocol. You could argue forever about what OSI model layer SSH maps to. A much more accurate model of real-world networking is the TCP/IP model:
TRANSMISSION CONTROL PROTOCOL/INTERNET PROTOCOL(TCP/IP) TCP is a reliable stream delivery service that guarantees to deliver a stream of data sent from one host to another without duplication or losing data, making it suitable for applications like file transfer and e-mail. It is so important in the Internet protocol suite that sometimes the entire suite is referred to as "the TCP/IP protocol suite." TCP is the transport protocol that manages the individual conversations between web servers and web clients. TCP divides the HTTP messages into smaller pieces, called segments, to be sent to the destination client. It is also responsible for controlling the size and rate at which messages are exchanged between the server and the client.Is the basic communication language or protocol of the Internet. TCP/IP is a two-layered program Transmission Control Protocol - Manages the assembling of a Message or file into smaller packets Internet Protocol- Handles the address part of each packet so that it gets to the right destination The Internet Protocol suite—like many protocol suites—can be viewed as a set of layers. Each layer solves a set of problems involving the transmission of data, and provides a well-defined service to the upper layer protocols based on using services from some lower layers. Upper layers are logically closer to the user and deal with more abstract data, relying on lower layer protocols to translate data into forms that can eventually be physically transmitted. The TCP/IP reference model consists of five layers.
OSI Reference Model & TCP/IP OSI Reference Model & TCP/IP
Application Presentation Session Transport Network Data Link IP TCP UDP
ICMP, ARP, OSPF, RIP
Description of layers
Physical Layer The Physical Layer is layer one of the OSI model. It is responsible for bit-level transmission between network nodes. In copper networks, It is responsible for defining specifications for electrical signals. In fiber optic networks, It is responsible for defining the characteristics of light signals. The Physical Layer defines items such as: connector types, cable types, voltages, and pin-outs. Standards which operate at the Physical Layer include:RS-232,T1,and 10Base-T(CAT5) Data Link Layer The Data Link Layer is layer two of the OSI model. It is responsible for communications between adjacent network nodes. Hubs and switches operate at the Data Link Layer. It is logically divided into two sub-layers, The Media Access Control (MAC) Sub-layer and the Logical Link Control (LLC) Sub-layer.
7 Layer of Open System Interconnection Model
5 Layer of TCP/IP Protocol Model
Logical Link Control
Media Access Control
Media Access Control Sub-layer The MAC Sub-layer is responsible for addressing on the Local Area Network. It is also responsible for determining when nodes on a Local Area Network are allowed to transmit. In Ethernet, this is accomplished using the CSMA/CD protocol. Logical Link Sub-layer The LLC Sub-layer is responsible for synchronizing frames, error checking, and flow control. Standards which operate at the Data Link Layer include: Ethernet, Wi-Fi, Frame Relay, ATM, and PPP. Network Layer The Network Layer is layer three of the OSI model.It is responsible for establishing paths for data transfer through the network.It extends the Data Link Layer beyond the local network into an internetwork by providing for routing and forwarding of packets.It is also responsible for packet sequencing, congestion control, and error handling.Routers operate at the Network Layer. Standards which operate at the Network Layer include: IP and ICMP. Transport Layer The Transport Layer is layer four of the OSI model.It is responsible for delivering messages between networked hosts.As part of this, It is also responsible for fragmentation and reassembly.In addition, some Transport Layer protocols also provide services to manage flow control and end-to-end error recovery. Standards which operate at the Transport Layer include: TCP and UDP. Session Layer The Session Layer is layer five of the OSI model. It is responsible for establishing process-to-process communications between networked hosts. Standards which operate at the Session Layer include: RPC, Named Pipes, and NetBIOS.
Presentation Layer The Presentation Layer is layer six of the OSI model. It is responsible for defining the syntax which two network hosts use to communicate. Encryption and compression should be Presentation Layer functions, although they are frequently provided on other layers. Standards which operate at the Presentation Layer include: HTTP, SMTP, and SNMP. Application Layer The Application Layer is layer seven of the OSI model. It is responsible for providing end-user services, such as file transfers, electronic messaging, e-mail, and virtual terminal access. It is the layer with which the user interacts. Standards which operate at the Application Layer include: FTP, telnet, and SSH.
48 x 82 graphical LCD Display Interface
Hello World… I’m Ethernet!!!
Atmel/Phillip Micro Controller 89C51
Motor1 Motor2 Motor3
We followed a wide variety of standards for Ethernet, Address Resolution Protocol (ARP), Internet Protocol (IP), ICMP (Internet Control Message Protocol) UDP (User Defined Protocol). Ethernet needed to be built so that packets could go in and out; ARP was to be built on top of Ethernet to allow for other computers to discover the existence of our controller; IP needed to be built in order to provide transport of our packets; ICMP was to be built so that we could effectively ping our controller; UDP is used as the main transmitter and receiver of packets.
Ethernet uses economical twisted pair cables and standard RJ-45 connectors 10BASET: 10BASE-T was the first vendor-independent standard implementation of Ethernet on twisted pair wiring. This system operates over two pairs of wires, one pair used for receive data signals and the other pair used for transmit data signals. The two wires in each pair must be twisted together for the entire length of the segment; a standard technique used to improve the signal carrying characteristics of a wire pair.It is essentially StarLAN-10 with the addition of a link status pulse. The link status pulse prevents the use of half-connected links on which one side would be unable to avoid or detect collisions. 10BaseT "Twisted Pair" Ethernet
• • • • •
Transmission Rate: 10 Mbps Max. Segment Length:100 meters (328 feet) Cable Type: Two pairs of Category 5 ( unshielded twisted pair (UTP) cabling). Connector Technology: RJ-45 style modular jack Signal Encoding: Manchester encoding
CAT 5(UTP,Unshielded Twisted Pair): Category 5 cable, commonly known as Cat 5 or "Cable and Telephone", is a twisted pair cable type designed for high signal integrity.The cable consists of four pairs of 24-guage twisted copper pairs terminating in an RJ-45 jack. Many such cables are unshielded but some are shielded.It includes four twisted pairs in a single cable jacket. A typical subset of these four twisted pair colors (white/blue, /white/brown, white/orange, white/green) shows up in most UTP cables.
1.Jacket 2.Protective skin 3.Shield-foil 4.Drain wire 5.Solid twisted pair Twisted pair cabling is a form of wiring in which two conductors are wound together for the purposes of canceling out electromagnetic interference (EMI) from external sources, electromagnetic radiation from the UTP cable, and crosstalk between neighboring pairs.This lack of shielding results in a high degree of flexibility as well as rugged durability.
This type of cable is often used in structured cabling for computer networks such as Ethernet, and is also used to carry many other signals such as basic voice services, token ring, and ATM (at up to 155 Mbit/s, over short distances) and often used in data networks for short and medium length connections because of its relatively lower cost, lighter, thicker compared to fiber and coaxial cabling.
A network card is an expansion card which installs into a computer and enables that computer to physically connect to a local area network. The most common form of network card in current use is the Ethernet card. Ethernet network cards most often use RJ-45 jacks.Other terms for network card include network adapter, network interface card (NIC). RJ-45(REGISTERED JACK):RJ-45 is the standard connector Ethernet, ISDN, T1, and modern digital telephone systems utilized on 4-pair (8-wire) UTP (Unshielded Twisted Pair).It is most commonly used for 10Base-T and 100Base-TX Ethernet connections.
Pin 1 2 3 4 5 6 7 8
Color White/Orange Orange White/Green Blue White/Blue Green White/Brown Brown
Name/Description N/A N/A Receive+ Transmit + Transmit Receive -48VDC (optional) -48VDC Return (optional)
The Internet Protocol (IP) is a data-oriented protocol used for communicating data across a packet-switched internetwork.IP is a network layer protocol in the Internet protocol suite and is encapsulated in a data link layer protocol (e.g., Ethernet). As a lower layer protocol, IP provides the service of communicable unique global addressing amongst computers. An IP packet consists of a header section and a data section.Header
4–7 Header length
8–15 Type of Service
32 64 96 128 160 160 or 192+
Identification Time to Live Protocol
Fragment Offset Header Checksum
Source Address Destination Address Options
Version The first header field in an IP packet is the 4-bit version field. For IPv4, this has a value of 4 (hence the name IPv4). Internet Protocol version 4 (IPv4) is the fourth iteration of the Internet Protocol (IP) and it is the first version of the protocol to be widely deployed. It is a best effort protocol in that it does not guarantee delivery. It does not make any guarantees on the correctness of the data; It may result in duplicated packets and/or packets out-of-order. These aspects are addressed by an upper layer protocol (e.g., TCP, and partly by UDP). Internet Header Length (IHL) The second field is a 4-bit Internet Header Length (IHL) telling the number of 32bit words in the header. The minimum value for this field is 5 ,which is a length of 5×32 = 160 bits. Being a 4-bit field the maximum length is 15 words or 480 bits. Type of Service (TOS) The 8 bits were allocated to a Type of Service (TOS) field:
• • • • •
bits 0-2: precedence bit 3: 0 = Normal Delay, 1 = Low Delay bit 4: 0 = Normal Throughput, 1 = High Throughput bit 5: 0 = Normal Reliability, 1 = High Reliability bits 6-7: Reserved for future use
Total Length This 16-bit field defines the entire datagram size, including header and data, in bytes. The minimum-length datagram is 20 bytes (20 bytes header + 0 bytes data) and the maximum is 65,535 — the maximum value of a 16-bit word. The minimum size datagram that any host is required to be able to handle is 576 bytes, but most modern hosts handle much larger packets.
Identification This16 bit field is an identification field and is primarily used for uniquely identifying fragments of an original IP datagram. Some experimental work has suggested using the ID field for other purposes, such as for adding packet-tracing information to datagrams in order to help trace back datagrams with spoofed source addresses. Flags A 3-bit field follows and is used to control or identify fragments. They are (in order, from high order to low order): 00 01 02 R DF MF R, reserved. 1 bit. Should be cleared to 0. DF, don’t fragment. 1 bit. Controls the fragmentation of the datagram. Value Description 0 Fragment if necessary. 1 Do not fragment. MF, More fragments. 1 bit. Indicates if the datagram contains additional fragments. Value Description 0 This is the last fragment. 1 More fragments follow this fragment. Fragment Offset The fragment offset field, measured in units of 8-byte blocks, is 13-bits long and specifies the offset of a particular fragment relative to the beginning of the original unfragmented IP datagram. The first fragment has an offset of 0. This allows a maximum offset of 65,528 () which would exceed the maximum IP packet length of 65,535 with the header length included.
Time To Live (TTL) An 8-bit time to live (TTL) field helps prevent datagram’s from persisting (e.g. going in circles) on an internet work. Historically the TTL field limited a datagram's lifetime in seconds, but has come to be a hop count field. Each packet switch (or router) that a datagram crosses decrements the TTL field by one. When the TTL field hits zero, the packet is no longer forwarded by a packet switch and is discarded. Typically, an ICMP message (specifically the time exceeded) is sent back to the sender that it has been discarded. Protocol This 8bit field defines the protocol used in the data portion of the IP datagram Header Checksum The 16-bit checksum field is used for error-checking of the header. At each hop, the checksum of the header must be compared to the value of this field. If a header checksum is found to be mismatched, then the packet is The checksum field is the 16-bit one's complement of the one's complement sum of all 16-bit words in the header. For purposes of computing the checksum, the value of the checksum field is zero. In other words, all 16-bit words are summed together using one's complement (with the checksum field set to zero). The sum is then one's complemented and this final value is inserted as the checksum field. Source address An IP address is a 32 bit field. This address is the address of the sender of the packet. Destination address Identical to the source address field but indicates the receiver of the packet. Options Optional, if present must be padded to 32 bit multiples Data The last field is not a part of the header and, consequently, not included in the checksum field. The contents of the data field are specified in the protocol header field and can be any one of the transport layer protocols.
ADDRESS RESOLUTION PROTOCOL
IP is an upper layer protocol to the data link layer. The data link layer of underlying physical network segment over which two communicating computers are directly connected (typically through a hub or a switch) uses its own addressing scheme at hardware level. In order to send a packet from computer A to B, A needs to know the hardware address of B. This discovery and mapping of IP addresses onto the hardware addresses is done using Address Resolution Protocol(ARP). In computer networking, ARP is the standard method for finding a host's hardware address when only its network layer address is known.ARP is a protocol used to do address resolution in the TCP/IP protocol suite. It is required on multi-access channels and relies on the ability to broadcast.It is not an IP-only or Ethernet-only protocol; it can be used to resolve many different network-layer protocol addresses to hardware addresses. It is also used for IP over other LAN technologies, such as Token Ring, FDDI, or IEEE 802.11, and for IP over ATM. ARP is used in four cases of two hosts communicating: 1. When two hosts are on the same network and one desires to send a packet to the other 2. When two hosts are on different networks and must use a gateway/router to reach the other host 3. When a router needs to forward a packet for one host through another router 4. When a router needs to forward a packet from one host to the destination host on the same network The first case is used when two hosts are on the same physical network (that is, they can directly communicate without going through a router). The last three cases are the most used over the Internet as two computers on the internet are typically separated by more than 3 hops. In the first case, you would have two hosts on the same LAN segment, A and B. If, for example, Host A wants to send an IPv4 packet to Host B, Host A must already have an IPv4 address for Host B (the network layer address). However, in order to be able to send
the packet on the LAN to Host B, Host A must also have a data link layer address, i.e. a MAC address, for Host B. If it doesn't already know that MAC address, it would send an ARP request to ask for that MAC address, in the hopes of getting a reply from Host B, or another host on the network, giving that MAC address. Upon receipt the hardware address is used to send the original packet.
The following is the packet structure used for ARP requests and replies. On Ethernet networks, these packets use an EtherType of 0x0806, and are sent to the broadcast MAC address of FF:FF:FF:FF:FF:FF. Note that the packet structure shown in the table has SHA, SPA, THA, & TPA as 32-bit words but this is just for convenience — their actual lengths are determined by the hardware & protocol length fields.
Hardware type (HTYPE): Each data link layer protocol is assigned a number used in this field. For example, Ethernet is 1. Protocol type (PTYPE): Each protocol is assigned a number used in this field. For example, IPv4 is 0x0800. Hardware length (HLEN): Length in bytes of a hardware address. Ethernet addresses are 6 bytes long. Protocol length (PLEN): Length in bytes of a logical address. IPv4 address are 4 bytes long.
Operation: Specifies the operation the sender is performing: 1 for request, and 2 for reply. Sender hardware address (SHA) Hardware address of the sender. Sender protocol address (SPA) Protocol address of the sender. Target hardware address (THA) Hardware address of the intended receiver. This field is zero on request. Target protocol address (TPA) Protocol address of the intended receiver. Example Request If a host with IPv4 address of 10.10.10.123 (0A.0A.0A.7B in hexadecimal notation) and MAC address of 00:09:58:D8:11:22 wants to send a packet to another host at 10.10.10.140 (0A.0A.0A.8C in hexadecimal notation) but it does not know the MAC address, then it must send an ARP request to discover the address. The packet shown shows what would be broadcast over the local network. + 0 32 64 96 128 160 192 Bits 0 - 7 Hardware type = 1 Hardware length = 6 Protocol length = 4 SHA (first 32 bits) = 0x000958D8 SHA (last 16 bits) = 0x1122 SPA (last 16 bits) = 0x0A7B TPA = 0x0A0A0A8C SPA (first 16 bits) = 0x0A0A THA (first 16 bits) = 0xFFFF 8 - 15 16 - 31 Protocol type = 0x0800 Operation = 1
THA (last 32 bits) = 0xFFFFFFFF
Example Reply Given the scenario laid out in the request section, if the host 10.10.10.140 is running and available, then it would receive the ARP request and send a reply packet as shown below. (This reply assumes that the host 10.10.10.140 has a MAC address of 00:09:58:D8:33:AA.) Note that the sender and target address blocks have been swapped (the sender of the reply is the target of the request; the target of the reply is the sender of the request). Furthermore, the host 10.10.10.140 has filled in its MAC address in the 21 www.mictechcenter.org
sender hardware address.Any hosts on the same network as these two hosts would also see the request (since it is a broadcast) so they are able to cache information about the source of the request. The ARP reply (if any) is directed only to the originator of the request so information in the ARP reply is not available to other hosts on the same network. + 0 32 64 96 128 160 192 Bits 0 - 7 Hardware type = 1 Hardware length = 6 Protocol length = 4 SHA (first 32 bits) = 0x000958D8 SHA (last 16 bits) = 0x33AA SPA (last 16 bits) = 0x0A8C TPA = SPA (first 16 bits) = 0x0A0A THA (first 16 bits) = 0x0009 8 - 15 16 - 31 Protocol type = 0x0800 Operation = 2
THA (last 32 bits) = 0x58D81122
INTERNET CONTROL MESSAGE PROTOCOL
The Internet Control Message Protocol (ICMP) is one of the core protocols of the Internet protocol suite. It is chiefly used by networked computers' operating systems to send error messages—indicating, for instance, that a requested service is not available or that a host or router could not be reached. It is present in network layer. The version of ICMP for Internet Protocol version 4 is also known as ICMPv4. ICMP differs in purpose from TCP and UDP in that it is not used to send and receive data between end systems. It is usually not used directly by user network applications, with some notable exceptions being the ping tool. ICMPs generate several kinds of useful messages, including Destination Unreachable, Echo Request and Reply, Redirect, Time Exceeded, and Router Advertisement and Router Solicitation. If an ICMP message cannot be delivered, no second one is generated. This is to avoid an endless flood of ICMP messages. When an ICMP destination-unreachable message is sent by a router, it means that the router is unable to send the package to its final destination. The router then discards the original packet. Two reasons exist for why a destination might be unreachable. Most commonly, the source host has specified a nonexistent address. Less frequently, the router does not have a route to the destination. Destination-unreachable messages include four basic types: network unreachable, host unreachable, protocol unreachable, and port unreachable. Network-unreachable messages usually mean that a failure has occurred in the routing or addressing of a packet. Hostunreachable messages usually indicates delivery failure, such as a wrong subnet mask. Protocol-unreachable messages generally mean that the destination does not support the upper-layer protocol specified in the packet. Port-unreachable messages imply that the TCP socket or port is not available. PING Ping is a computer network tool used to test whether a particular host is reachable across a network; it is also used to self test the network interface card of the computer. It works by sending ICMP “echo request” packets to the target host and listening for ICMP “echo response” replies. Ping estimates the round-trip time, generally in milliseconds, and records any packet loss, and prints a statistical summary when finishedIP 23 www.mictechcenter.org
implementations are required to support this protocol. ICMP is considered an integral part of IP, although it is architecturally layered upon IP. ICMP provides error reporting, flow control and first-hop gateway redirection. Packet Structure MAC header IP header ICMP header Data ::: ICMP header:
Type. 8 bits. Specifies the format of the ICMP message. Type Description 0 Echo reply. 1 Reserved. 2 Reserved. 3 Destination unreachable. 4 Source quench. 5 Redirect. 6 Alternate Host Address. 7 8 Echo request. 9 Router advertisement. 10 Router solicitation. 11 Time exceeded. 12 Parameter problem. 13 Timestamp request. 14 Timestamp reply. 15 Information request. 16 Information reply. References
17 Address mask request. 18 Address mask reply. 19 Reserved (for security). 20 29 30 31 32 33 34 35 36 37 38 39 40 41 42 255 Code: 8 bits. Further qualifies the ICMP message. ICMP Header Checksum 16bits Checksum that covers the ICMP message. This is the 16-bit one's complement of the one's complement sum of the ICMP message starting with the Type field. The checksum field should be cleared to zero before generating the checksum. Data: Variable length. Contains the data specific to the message type indicated by the Type and Code fields. Reserved (for robustness experiment). Traceroute. Conversion error. Mobile Host Redirect. IPv6 Where-Are-You. IPv6 I-Am-Here. Mobile Registration Request. Mobile Registration Reply. Domain Name request. Domain Name reply. SKIP Algorithm Discovery Protocol. Photuris, Security failures. Experimental mobility protocols. RFC 4065 Reserved.
ICMP Echo Request/Response (Ping)
. An ICMP echo-request message, which is generated by the ping command, is sent by any host to test node reach ability across an internet work. The host must respond to all
echo requests with an echo reply containing the exact data received in the request message. The ICMP echo-reply message indicates that the node can be successfully reached and, is mandatory for all hosts and routers.In a ping operation the entire packet is echoed (or pinged as in ping-pong) back to the sender.
Octet Len Name
ICMP Type Message Type 8 = Echo request 0 = echo reply Code Checksum Identifier Sequence Data Code = 0 Used by sender to identify operation. Used by sender to identify operation. Optional Data field.
1 2-3 4-5 6-7 8+
1 2 2 2 ?
Sample of a successful ping
[localhost]ping 188.8.131.52 –w 5000 -t Pinging [184.108.40.206] with 32 bytes of data: Reply from 220.127.116.11: bytes=32 time=57ms TTL=44 Reply from 18.104.22.168: bytes=32 time=59ms TTL=44 Reply from 22.214.171.124: bytes=32 time=59ms TTL=44 Reply from 126.96.36.199: bytes=32 time=54ms TTL=44
Ping statistics for 188.8.131.52: Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), Approximate round trip times in milli-seconds:
Minimum = 54ms, Maximum = 59ms, Average = 57ms
USER DATAGRAM PROTOCOL
UDP (User Datagram Protocol) is one of the two main transport protocols utilized in IP networks and was designed by David P. Reed in 1980.It exists on the Transport Layer of the OSI reference model and an unreliable connectionless protocol. 27 www.mictechcenter.org
When we say that UDP is unreliable because it does not provide mechanisms for error detection and error correction between the source and the destination. Because of this, UDP utilized bandwidth more efficiently than TCP. By connectionless, we mean that a network node can communicate with another network node using UDP without first negotiating any kind of handshaking or creating a connection. Because of this, UDP is very efficient for protocols that send small amounts of data at irregular intervals known as datagrams.UDP is sometimes called the Universal Datagram Protocol UDP is a simple to implement protocol because it does not require to keep track of every packet sent or received and it does not need to initiate or end a transmission. Because of this it is mainly designed for communications where you either don't care what the response will be or you pretty much know it. UDP messages are generally faster than TCP provided that the communication link functions properly. UDP is widely utilized to send DNS (Domain Name Search) requests, to exchange chat messages, or to access telephone numbers via Internet. Time-sensitive applications often use UDP because dropped packets are preferable to delayed packets. UDP's stateless nature is also useful for servers that answer small queries from huge numbers of clients. Unlike TCP, UDP is compatible with packet broadcast (sending to all on local network) and multicasting(send to all subscribers). Common network applications that use UDP include: Domain Name System (DNS), streaming media applications such as IPTV, Voice over IP (VOIP), Trivial File Transfer Protocol (TFTP) and online games.
UDP (User Datagram Protocol) is a connectionless protocol and represents a lightweight method of sending and receiving data.
Source and destination ports contain the 16-bit UDP protocol port numbers used to demultiplex datagrams for receiving application-layer processes. A length field specifies the length of the UDP header and data. Checksum provides an (optional) integrity check on the UDP header and data. UDP Checksum. If a UDP checksum is present (optional for IPv4, mandatory for IPv6) it is assumed to have a 'psuedo header' field of the following format prepended to the data:
Octet Len Name
0-3 4-7 8 9 10-11 4 4 1 1 2 Source
Source IP address
Destination Destination IP address Zero Protocol Length Always zero Always 17 for UDP Length of UDP packet (excluding this psuedo header)
1. The UDP checksum is computed by including the above 'pseudo header' plus the total UDP packet including the 'real' UDP header. 2. Checksum is IP one's complement standard
RTL8019AS Realtek Full-Duplex Ethernet Controller with Plug and Play Function
FEATURES • • • • • • • • • 100-pin PQFP RTL8019 software compatible Supports PnP auto detect mode (RTL8019AS only) Compliant to Ethernet II and IEEE802.3 10Base5, 10Base2, 10BaseT Software compatible with NE2000 on both 8 and 16-bit slots Supports both jumper and jumper less modes Supports Microsoft‘s Plug and Play configuration for jumper less mode Supports Full-Duplex Ethernet function to double channel bandwidth Supports three level power down modes: - Sleep - Power down with internal clock running - Power down with internal clock halted • • • • • • • • • • Built-in data pre fetch function to improve performance Supports UTP, AUI & BNC auto-detect (RTL8019AS only) Supports auto polarity correction for 10BaseT Support 8 IRQ lines Supports 16 I/O base address options and extra I/O address fully decode mode (RTL8019AS only) Supports 16K, 32K, 64K and 16K-page mode access to BROM (up to 256 pages with 16Kbytes/page) Supports BROM disable command to release memory after remote boot Supports flash memory read/write (RTL8019AS only) 16k byte SRAM built in (RTL8019AS only) Support 4 diagnostic LED pins with programmable outputs
GENERAL DESCRIPTION The Realtek RTL8019AS is an NE2000-compatible IC that is easily integrated into just about any microcontroller project that is being designed to use Ethernet connectivity. The RTL is based on the National DP8390 Network Interface Controller, which like the CS8900A-CQ, provides all the Media Access Control layer functions required for transmission and reception of packets in accordance with the IEEE 802.3 CSMA/CD (Carrier Sense Multiple Access/Collision Detection) standard. RTL perched on a printed circuit board with all of its pins terminated at convenient .1-inch-center header points.Add a 20-MHz crystal, some power supply bypass capacitors, a few choice resistors and some custom magnetic and you have a fully functional 10 Mbps Ethernet engine.
It provides interface auto-detect capability and can choose between an integrated 10BaseT transceiver, a BNC or an AUI interface. Its on-chip 10Base-T transceiver can automatically correct the polarity at its receiving cable pair. In 8-bit mode, the RTL use a 4 Kb on-chip RAM area despite its 16 Kb specification, which only applies to 16-bit mode. In NE2000 fashion, its buffer memory is configured as a ring. RTL uses internal DMA resources to manage and move data between the RTL’s FIFO and the RTL’s internal buffer memory. Within the RTL, the onboard FIFO (First In, First Out) and Local DMA (Direct Memory Access) channels work in conjunction to form a simple packet
management scheme that provides up to 10 megabyte per second internal DMA transfers. The FIFO lies between the network interface and the Local DMA channel. A second RTL Remote DMA channel is included on-chip to get data out of the RTL’s internal Buffer Ring and into microcontroller memory for processing and vice versa. It’s important to remember that the Local DMA channel moves data between the RTL’s internal FIFO and the RTL’s Buffer Ring, and the Remote RTL DMA channel moves data between the RTL’s Buffer Ring and the microcontroller’s working memory.It was originally designed for major Ethernet applications on desktop personal computers. PIN CONFIGURATION
PIN DESCRIPTION Power Pins 6, 17, 47, 57, 70,89(VDD): +5V DC power 14, 28, 44, 52,83, 88(GND): Ground ISA Bus Interface Pins Pin 34 AEN-Address Enable pin. This ISA signal must be low for a valid I/O Command.
Pins 97-100, 1-4 INT7-0- Interrupt request output lines which are mapped to IRQ15, IRQ12,IRQ11, IRQ10, IRQ5, IRQ4, IRQ3, IRQ2/9 respectively. Only one line is selected to reflect the interrupt requests at one time.All other lines are tri-stated. The RTL8019AS also uses these pins as inputs to monitor the actual state of the corresponding interrupt lines on ISA bus. The result is recorded in the INTR register, which may be used by software to detect interrupt conflict. Pin 35
ISA output signal is driven low to insert wait cycles to current host
read/write command. Pin 96 IOCS16B[SLOT16]-Upon power-on reset, this pin acts as an input named SLOT16 to detect whether a 16-bit or 8-bit slot is in use. To do this, it isconnected to a pull-down resistor (about 27KW) externally. At the falling edge of RSTDRV, the RTL8019AS senses this pin's state. If it is sensed high, the adapter is thought to be placed on a 16-bit slot where this pin is connected to the host's IOCS16B pin, which is typically pulled up by a 300W resistor on the mother board. If it is sensed low, the adapter is thought to be placed on an 8-bit slot where this pin is merely pulled low by the 27KW resistor. After having latched the input state, this pin is switched as the IOCS16B signal which is an open-drain.output and is driven low during a 16-bit host data transfer. It is decoded from AEN and SA9-0. Pin 29 IORB-Host I/O read command. Pin 30 IOWB-Host I/O write command. Pin 33 RSTDRV -High active hardware reset signal from the ISA bus. Pulses with high level less than 800ns are ignored.
Pin 27-18, 16, 15, 13-7, 5 SA19-0- Host address bus. SA10 is added to implement the fullydecode of PnP ports, address 279h and A79h. In RTL8019,SA10 is not decoded. In RTL8019AS, SA10 should be 0 for a valid access to PnP ports. Pin 87-88, 90-95, 43-36 SD15-0 -I/O Host data bus. Pin 31 SMEMRB -Host memory read command. Pin 32 SMEMWB-Host memory write command. This pin is added to decode the write command of a flash memory. Memory Interface Pins (including BROM, EEPROM) Pin 75 BCSB-BROM chip select. Active low signal, asserted whenBROM is read. RTL8019AS drives this pin low when SA19-14 matches the selected BROM memory base address and either of the 2 conditions below meets: (1) SMEMRB is low (2) SMEMWB is low and RTL8019AS's flash memory write function is enabled.
Pin 76 EECS-9346 chip select. Active high signal, asserted when 9346 is read/write. Pin 66-69, 71-74 BA21-14 -BROM address.* Pin 77-82, 84-85 BD7-0 (I/O)- BROM data bus.
Pin 79 EESK-9346 serial data clock. Pin 78 EEDI -9346 serial data input Pin 77 EEDO- 9346 serial data output.The following pins are defined for jumper options. Their states are latched at the falling edge of RSTDRV, then they are changed to serve as the SRAM bus. Each of them is internally pulled down by a 100KW resistor. Therefore, the input will be low when left open and high when pulled up by a 10K resistor externally. Pin 66 PNP- When it is high in jumperless mode (i.e. JP=low), the RTL8019AS is forced into Plug and Play mode regardless of the contents of 9346. The following pins are don't care in jumperless mode(JP=low). Pin 72-71, 69-67 [BS4-0] -Select BROM size and base address. Pin 85-84, 82-81 [IOS3-0]- Select I/O base address. Pin 77, 74 [PL1-0]-Select network medium type. Pin 80-78 [IRQS2-0]-Select one interrupt line among INT7-0. Pin 65 JP -When high, this pin selects jumper mode. When low, it selects jumperless modes (including RT jumperless and Plug and Play). Medium Interface Pins Pin 64
AUI -This input is used to detect the usage of an external MAU on the AUI interface. The input should be driven low for embedded BNC and high for external MAU. When the input is high, RTL8019AS sets the AUI bit (bit5) in CONFIG0 and drives LEDBNC low to disable the BNC. If this pin is not used, it should be connected to GND such that RTL8019AS acts like RTL8019. Pin 54,53 CD+,CD- This AUI collision input pair carries the differential collision input signal from the MAU. Pin 56,55 RX+,RX- This AUI receive input pair carries the differential receive input signal from the MAU. Pin 49,48 TX+,TX- This AUI transmit output pair contains differential line drivers which send Manchester encoded data to the MAU. These outputs are source followers and require 270 ohm pulldown resistors to GND. Pin 59,58 TPIN+,TPIN- This TP input pair receives the 10 Mbits/s differential Manchester encoded data from the twisted-pair wire.
Pin 45,46 TPOUT+, TPOUT-This pair carries the differential TP transmit output. The output Manchester encoded signals have been pre-distorted to prevent overcharge on the twisted-pair media and thus reduce jitter. Pin 50 X1-20Mhz crystal or external oscillator input. Pin 51 X2-Crystal feedback output. This output is used in crystal connection only. It must be left open when X1 is driven with an external oscillator. 37 www.mictechcenter.org
LED Output Pins Pin 60 LEDBNC-This pin goes high when RTL8019AS's medium type is set to 10Base2 mode or auto-detect mode with link test failure. Otherwise, this pin is low. This pin can be used to control the power of the DC convertor for CX MAU and connected to an LED to indicate the used medium type. Pin 61 LED0- When LEDS0 bit (in CONFIG3 register of RTL8019AS Page3) is 0, this pin acts as LED_COL. When LEDS0=1, it acts as LED_LINK. Pins 62,63 LED1,LED2-When LEDS1 bit (in CONFIG3 register of RTL8019AS Page3) is 0, these 2 pins act as LED_RX & LED_TX respectively. When LEDS1=1, these pins act as LED_CRS & MCSB. Please refer to section 6.5 for details of the lightening behavior of all LEDs.
REGISTERS RTL includes4 pages of registers which are selected by bit PS0 & PS1 in the CR register.Each page contains 16 registers.
The RTL is controlled through an array of on-chip registers. Its registers are used during initialization, packet transmission and reception. There are also registers for Remote DMA operations on the. Basically, using its internal registers we can perform the same logical operations. The basic operations include defining the hardware physical address, setting the receive parameters and setting the transmission parameters. For the RTL, add configuring DMA channels and allocating transmit and receive Buffer Ring areas to the aforementioned list of operations. In that DMA is an integral part of the RTL8019AS’s microcontroller interface,there must be a control mechanism or register to act as the traffic cop for the data flow between the RTL’s buffers and the microcontroller memory and the RTL8019AS’s MAC engine to Ethernet interface. That control register for the RTL8019AS is the Command Register (CR), which is used to initiate Remote DMA operations as well as data transmission. Remember, Remote DMA operations are used to move data between the RTL buffer and the microcontroller’s memory.
The microcontroller checks for a valid frame by polling an interrupt pin (INT0) on the RTL8019AS. Once a valid level is sensed on the INT0 pin, the micro controller interrogates the RTL Interrupt Status Register (ISR) to determine what type of interrupt has occurred. RTL transmit packets in accordance with the CSMA/CD protocol standards. It schedule retransmission of packets up to 15 times on collisions according to the truncated binary exponential backoff algorithm. Once you cut the transmit process loose, both Ethernet ICs run the show until the transmission cycle is aborted or completed. Assuming buffer memory is allocated and free; transmitting packets with the RTL entails setting up an IEEE 802.3 frame in memory with Ethernet frame of 6 bytes of the destination address (DA),6 bytes of the source address (SA), data length in bytes and data.Once the required frame items are built in the microcontroller’s packet array memory area, the RTL register TPSR (Transmit Page Start Register) represents the upper byte of a 16-bit address and is
loaded with the frame starting address and the TBCR0 (Transmit Byte Count 0) and TBCR1 (Transmit Byte Count 1) registers are filled with the length of the frame. TPSR Register 7 A15 6 A14 5 A13 4 A12 3 A11 2 A10 1 A9 0 A8
TBCR0 Register 7 TBC7 6 TBC6 5 TBC5 4 TBC4 3 TBC3 2 TBC2 1 TBC1 0 TBC0
TBCR1 Register 7 TBC15 6 TBC14 5 TBC13 4 TBC12 3 TBC11 2 TBC10 1 TBC9 0 TBC8
To initiate the transmission of a packet, the TXP (transmit packet) bit of the RTL Command Register is set. If the total length of the Ethernet packet is less than 46 bytes, the RTL cannot be instructed to automatically pad the packet to avoid sending a runt packet onto the network. Therefore, we must as programmers make sure we don’t generate any runt packets. The TCP/IP section checks for runts. The ARP, ICMP and UDP routines use the length of the incoming packets as their guide. Since we will setup the RTL8019AS to not accept runt packets, the UDP and ICMP packets received will always meet the minimum length requirement. The ARP code builds a 60-byte ARP reply packet. The RTL transmit buffer area is allocated according to the contents of its register. The RTL datasheet stresses that if the Buffer Ring area of the RTL is set up correctly at initialization, there should never be any contention for transmit buffer memory under normal operating conditions. It uses its Local DMA channel and FIFO to follow the RTL-generated preamble with valid data. The RTL Local DMA bursts data to the FIFO, which is then serialized out onto the network as clocked NRZ data. Every Ethernet IC on a network has to conform to these standards in order to communicate with each other. The RTL Local DMA refreshes the FIFO when the FIFO “send more” threshold is reached.
The FIFO “send more” threshold is programmable. It continues the transmission as long as the transmission byte count in the byte count registers is greater than zero. Once all bytes are sent, the CRC is calculated by and is sent to complete the packet. If a collision occurs during transmission, the transmission is stopped and 32 ones (a jam sequence) are transmitted to make sure everybody on the network segment knows a collision just took place RTL execute the Standard Back off algorithm and the transmission is retried. When the transmission completes RTL have transmit status registers(TSR) that can be queried to see how the transmission went. TSR Register
we’re working with a bunch of standards that allow differing Ethernet IC manufacturers to design and build products that can communicate with each other over a common medium called Ethernet. Now with that in mind, transmitting data and receiving data from the ether is a process where RTL listen to the wire sense a carrier and start syncing up with the alternating 1/0 preamble that starts a 10 Mbps Ethernet packet.Once the two consecutive ones of the SFD (Start of Frame Delimiter) are sensed, the preamble ends and the MAC engines within the RTL expect everything behind the set of SFD ones to be valid data.It checks the destination address (DA) to see if the incoming packet is addressed to them. If it is not, it is not moved into buffer memory and the packet is discarded. On the other hand, if the packet destination address matches the Ethernet
IC’s address filter setting (hashed or individual), then the frame is moved into the Ethernet IC’s on-chip buffer memory so it can be transferred to the microcontroller’s RAM (Random Access Memory) for processing. If everything goes OK during the receive cycle, it posts receive status in their respective receive status registers and raises an interrupt I/O line. The data coming into the RTL from the network is put into a receive Buffer Ring; The RTL ring buffer is a classic circular, head and tail buffer scheme with four pointers(PSTSRT,PSTOP,CURR,BNRY) controlling the activity in the Buffer Ring A graphical representation of the RTL8019AS Buffer Ring
Although the buffer pointers can hold a 64K value (0xFFFF), note that only 8K of buffer RAM is available in the RTL8019AS. PSTART (Page Start) is the beginning address of the Buffer Ring. PSTOP (Page Stop) is the address of the end of the Buffer Ring. The Buffer Ring size is determined by the number of bytes between PSTART and PSTOP.
PSTART and PSTOP are loaded at initialization time. CURR, the Current Page Pointer, points to the next available buffer area for the next incoming frame. BNRY, or the Boundary Pointer, points to the next frame to be unloadedfrom the Buffer Ring. CURR as the write pointer and the BNRY as the read pointer for the Buffer Ring. As frames come in, the CURR pointer moves ahead of the BNRY pointer around the ring. If CURR reaches BNRY, the Buffer Ring is full. All receptions are aborted, and missed packet registers within the RTL8019AS are updated until this condition is cleared. The RTL Remote DMA channel is the mechanism that removes frames from the Buffer Ring. Representation of an initialized Buffering. An empty ring is signaled by the CURR and BNRY pointers being equal.
Each Realtek RTL8019AS ring buffer segment in Figure above is 256 bytes in length. A valid received frame is placed at location CURR plus a 4-byte offset. Buffer segments are automatically linked together to receive frames larger than 256 bytes. When all the bytes are loaded, the RSR (Receive Status Register) status, a pointer to the next frame and the byte count of the current frame are written into the 4-byte offset. That’s basically how the
RealtekRTL8019AS and any other NE2000-compatible Ethernet IC works. A visual of a frame inside the RTL8019AS’s Buffer Ring is shown in Figure
RTL INITIALIZATION The very first instruction in our project begins the RTL8019AS’s initialization process. Firstly initialize the RTL on-chip hardware resources, then prepare the RTL register set for operation, and then activate the RTL and brings it online to the network.UDP application will use the PORT 0 as an output port to control the devices and the PORT 3 pins to drive some of the RTL8019AS’s bus control pins. RTL is capable of reading some of its initial configuration parameters from an external EEPROM and tries to do this automatically unless it’sheaded off at the pass We doesn’t require any data to be stored on an external EEPROM. To prevent the RTL from expecting data from an external EEPROM at startup, we tell the RTL8019AS that no EEPROM device exists by taking the RTL8019AS’s EEDO (EEPROMData Output) line low (bit clear(EEDO)) and leaving it low forever.
Basically, we want to put everything inside and outside of the RTL8019AS in an operable state and then reset the RTL8019AS. Once the RTL reset pin is activated, we must give the RTL at least 1.6ms to perform the internal reset process. Once we’ve waited long enough and think that the hard reset is finished, a write to the RTL8019AS RSTPORT initiates a soft reset. To be safe, we simply read the RTL8019AS’s Reset Port (RSTPORT) and then write the contents we read from it back into it.The idea is to make sure the RTL8019AS has actually entered the reset state successfully. If the RST bit of the ISR (Interrupt Status Register) is found to be set, the RTL8019AS is in reset state and we can continue. If the RTL8019AS fails to enter reset state, an endless loop is entered that informs the user that the initialization process has failed via the Ethernet serial port. ISR REGISTER
We used the read and write functions to load and read the contents of the RTL internal registers.First, the fromreg macro puts the micro controller I/O pins assigned as the databus in input mode. The register address is then loaded onto the micro controller I/O pins doing the address bus duty. The RTL IORB pin is activated and the RTL register data is presented to the micro controller databus port I/O pins, which are currently configured as inputs. The IORB pin is deactivated, and the byte that was just read from the RTL register is returned in the variable byte_read.
The write function in our Code is very similar to the read function.Register data and address information is presented to the micro controller data and address buses. The micro controller databus pins are configured as outputs by the toreg macro, and the RTL8019AS’s IOWB pin is toggled. After the write operation is completed, the micro controller databus I/O pins are reconfigured as inputs by the fromreg macro. This is done to make sure the databus is free for other devices that may need to use it. First writing an hexa decimal value 0x21 to the RTL8019AS’s CR Register.Taking it from left to right, the PS1 and PS0 bits are called Page Select bits. PS1 and PS0 are both 0 (zero) and point to RegisterPage 0.The Page Select bits in the CR register determine which RTL8019AS Register Page is addressed, and are used by the readreg and writereg functions to select the register inside the Register Page that is to be addressed. RD2, RD1 and RD0 are the Remote DMA Command bits. The ‘1’ in the RD2 position commands the RTL8019AS to abort any DMA activity that may be in progress. This effectively stops packet generation and reception. We want the RTL8019AS to be focused on the initialization process and not out there trying to receive or transmit packets on the network. The TXP bit must be set to initiate a transmission. We’re trying to reset the RTL8019AS and so far we’ve issued an abort DMA command, which resets this bit internally. We don’t want this bit to be set right now as we’re not in any position to begin any type of transmission process. STA is short for START. As far as the RTL8019AS is concerned, this bit actually does nothing at all. The logic level of the STOP bit controls starting and stopping the RTL8019AS. STP is short for STOP. When active, this bit takes the RTL8019AS offline. No packets will be received or transmitted by the RTL8019AS. If any reception or transmission is in progress, it will continue to completion before the reset state is entered.To exit the stopped state, the STP bit must be cleared and the STA bit must be set. To perform a software reset, the STP bit should be set high. Notice that we did not explicitly issue a command to set the STP bit when we performed our soft reset earlier. That’s because the STP defaults to a high state upon RTL8019AS power up. After executing commands to put the RTL8019AS into reset mode, we checked the validity of our software reset by checking the RST bit in the ISR register then we begin a series of writer instructions that are called out in this sequence by the National Semiconductor® 47 www.mictechcenter.org
NE2000 software documentation. The first, write(DCR,dcrval), loads the DCR (Data Configuration Register) register with 0x58. DCR Register 7 6 FT1
Bit 7 is not used, and we begin our discussion of the DCR with the FIFO Threshold Select bits. FT1 and FT0 determine how many bytes are in the RTL8019AS’s FIFO before a call to the Local DMA engine is made. We are set for 8 bytes. The FIFO receive threshold ranges from 2 bytes to 12 bytes depending on the bit pattern set in FT1 and FT0. The ARM bit is set and that allows us to use the Send Packet command and autoinitialize the Remote DMA to extract a frame from the Buffer Ring “send” in a receive operation is that the RTL8019AS’s Remote DMA channel moves data into and out of the RTL buffer queue and literally sends the data to an external microcontroller’s memory.By setting the ARM (Auto-Initialize Remote) bit in the DCR, the RTL Remote DMA channel can be automatically initialized to transfer a single frame from the Receive Buffer Ring. This automated transfer is done by issuing a Send Packet command (writing a 0x1A to the CR Register).The RTL8019AS’s DMA engine will be initialized to the value contained in the Boundary Pointer Register. Remember that the boundaries fall on 256 byte intervals 0x0100). Therefore, the lower byte of the Remote Start Address will always be 0x00. The Remote Byte Count Register pair (RBCR0, RBCR1) is initialized to the value of (0x00,0x01). After the data is transferred, the RTL8019AS Boundary Pointer is advanced to allow the RTL8019AS buffers to be used for new incoming frames. The Remote Read will terminate when the Byte Count reaches zero. When the current Remote Read operation is complete, the RTL Remote DMA engine is then prepared to read the next frame from the RTL8019AS’s Receive Buffer Ring. If the RTL DMA pointer crosses the Page Stop Register, it is reset to the Page Start Address. This allows the RTL Remote DMA engine to remove frames that have wrapped around to the top of the RTL8019AS’s Receive Buffer Ring. The LS (Loopback Select) bit is set at this point to allow the RTL8019AS to operate in normal mode. The LAS bit selects 32-bit or 16-bit dual DMA mode. The RTL8019AS requires that the LAS (Long Address Select) bit be cleared as the RTL8019AS only supports dual 16-bit DMA mode. The DCR is also used to program the 48 www.mictechcenter.org
RTL8019AS to operate in 8-bit or 16-bit DMA mode. We needs to run in 8-bit DMA mode and this is accomplished by clearing the WTS (Word Transfer Select) bit in the DCR. The DCR must be initialized prior to loading the Remote Byte Count Registers. Now that the DCR work is finished, we can safely clear both the RBCR0 and RBCR1 registers. The RCR (Receiver Configuration Register) determines what packets to accept and whether or not to store them in the RTL8019AS’s receive queue.we write a value of 0x04 to the RCR register. RCR Register 7 0 6 0 5 MON 0 4 PRO 0 3 AM 0 2 AB 1 1 AR 0 0 SEP 0
To effect our desired receiver configuration, we must set the AB (Accept Broadcast) bit and clear the PRO (Promiscuous Physical) bit. Putting the RTL8019AS into promiscuous mode allows any packet to be received regardless of its address. You already know that a Broadcast Packet is addressed in the Ethernet DLC area as FF FF FF FF FF FF.To reject packets with errors, the SEP (Save Errored Packets) bit is cleared. We aren’t interested in dealing with runt packets. So, the AR (Accept Runt Packets) bit is cleared to reject packets that are less than 64 bytes in length. The RTL will not be using any multicast addressing schemes. So, the AM (Accept Multicast) bit is alsocleared. And, we want to buffer any valid incoming frames. To enable frame buffering, the MON (Monitor Mode) bit is cleared by the Easy Ethernet W firmware.We write a value (0x40) intothe TPSR (Transmit Page Start Register) TPSR Register 7 A15 0 6 A14 1 5 A13 0 4 A12 0 3 A11 0 2 A10 0 1 A9 0 0 A8 0
The RTL8019AS datasheet tells us point blank to not exceed 0x60 as a PSTOP register value in 8-bit mode. That means our Buffer Ring memory area cannot go beyond physical address of 0x6000. The RTL8019AS has 8 Kb of on-chip memory area.
In days before the RTL, that 8 Kb of memory was not on-chip, and the Buffer Ring addresses were dictated by the hardware. We already have determined that PSTOP will be set for 0x60. Remember that this is the upper byte of a 16-bit address that always falls on a 256-byte boundary (0x0100) PSTOP register is loaded with the value(0x60). Now that we have the top of our Buffer Ring, let’s compute backwards towards the bottom. We know that we have 8 Kb of Buffer Ring area available onchip with the RTL8019AS. If the maximum Buffer Ring memory address is 0x6000, and we subtract 8 Kb (0x2000) from the maximum address, that will give us our bottom Buffer Ring address, which is 0x4000 or PSTART. We’ll allocate the transmit bufferfirst. Since we only use the upper byte to designate the address, that puts 0x40 the pre-defined value in the TPSR. While we’re working on the transmit side of the RTL8019AS house, we need to makesure that the RTL8019AS’s CRC checking and generation processes are enabled. The CRC functions are enabled in normal mode by clearing the CRC bit in the TCR (Transmit Configuration Register). TCR Register 7 0 6 0 5 0 4 OFST 0 3 ATD 0 2 LB1 0 1 LB0 1 9 CRC 0
The RTL8019AS must be put into loopback mode before we set the remaining Buffer Ring pointers. Setting the LB0 bit in the TCR is Figure 12.9 puts the RTL8019AS in internal Loop back mode. Now that we’ve stopped the RTL8019AS’s Local DMA, we can set the PSTART, PSTOP and BNRY pointers. Only one transmit frame will be present at any time in the RTL8019AS transmit buffer. Therefore, we only need enough space for one complete frame or 1518 bytes. 1518 bytes works out to 0x05EE, which doesn’t fall on a 256-byte boundary. We can’t round down. So,the next 256-byte boundary following 0x05EE is 0x0600, which will be the beginning address of the RTL8019AS’s receive buffer relative to the beginning of the Buffer Ring. Doing a bit more memory map math gives us the starting address of the receive buffer:
TPSR (0x4000) + size of one Ethernet frame (0x0600) = Receive buffer starting address (0x4600) We know that the PSTART and BNRY pointers should be set to point at address 0x4600. So, we load the PSTART and BNRY registers with 0x46.We must also initialize the CURR pointer, which lies in Page 1. Writing 0x61 to the CR flips us into Page 1 where we write the 0X46 value to the CURR register.Remember the flip-flop we had to do in our code to write the MAC address into the RTL8019AS, actual code is nothing more than value of (0x00,0x01,0x02,0x03,0x04,0x05)into the RTL8019AS’s Physical Address Registers (PAR0:PAR5), which also happen toreside in Page 1. As far as the RTL8019AS Control Registers are concerned, we’ve thus far established a place for everything, and everything is in its place. Then issues a START command to the RTL8019AS, clears the ISR, enables the packet received OK and overflow interrupts and takes the RTL8019AS out of loopback mode enabling the RTL8019AS’s Local DMA channel. CR Register 7 PS1 0 6 PS0 0 5 RD2 1 4 RD1 0 3 RD0 0 2 TXP 0 1 STA 1 0 STP 0
ISR Register 7 RST 1 6 RDC 1 5 CNT 1 4 OVW 1 3 TXE 1 2 RXE 1 1 PTX 1 0 PRX 1
IMR(Interrupt Mask Register) Register 7 6 5 4 3 2 1 0 RDC CNT OVW TXE RXE PTX PRX 0 0 0 1 1 0 1 1 All bits correspond to the bits in the ISR register. POWER UP=all 0s. Setting individual bits will enable the corresponding interrupts. TCR Register 7 6 5 4 3 51 2 1 9
In CR statement (the START command is given), TCR statement (the RTL8019AS Local DMA is activated). With Ethernet fundamentals, the only things we’ll have to tackle to Ethernet to Internetprotocol life are the differences in the way the RTL8019AS interfaces logically and physically. We still have to use the microcontroller to sense the presence of a valid frame in the RTL8019AS Buffer Ring. The micro controller must also initiate the fetch go get the data from the RTL8019AS’s receive Buffer Ring to the micro controller memory.Once the get_frame function is called by the microcontroller, the presence of the while(1) tells us that this code runs forever, exiting only to retrieve or send a packet. Ethernet frame retrieval code begins by starting the RTL8019AS.The RTL8019AS’s INT0 line is polled. When INT0 goes high, the microcontroller reads the RTL8019AS’s ISR. If the overrun bit (OVW) of the ISR is set, the overrun function is called to recover any latent frames that may be usable if the receive Buffer Ring blows up.If the ISR’s PRX (Packet Received OK) bit is set, the getframe function is called. 0x1A is written to the CR to issue the Send Packet command. Since we “ARM”ed the RTL8019AS in the initialization procedure, the automatic Remote DMA functionality of the RTL8019AS is put into action to retrieve a frame from the receive Buffer Ring. Immediately following the Send Packet command, code reads the 4byte buffer header information. The length of the buffered frame is computed and the bytes are read in from the RTL8019AS’s Remote DMA port. The Remote DMA port is eight bytes long and begins at offset 0x10. Once all of the bytes have been transferred from the RTL8019AS receive Buffer Ring to the micro controller packet array, we wait for the Remote DMA done bit (RDC) in the ISR to signal the end of the Remote DMA operation. After verifying the end of the Remote DMA operation,writing 0xFF to the ISR clears the ISR register.The RTL8019AS receive Buffer Ring can hold more than one frame. The BNRY and CURR pointers are examined. If the BNRY and CURR pointers are not the same value, the receive Buffer Ring contains another frame that needs to be transferred and the getframe function is called again. If the BNRY and CURR pointers match, the RTL8019AS receive Buffer
Ring is empty. The ISR is cleared, and again the same process is repeated.This is the procedure for how the frame is received and transferred using the RTL8019AS Remote DMA engine. Now, let’s examine procedures needed to transmit a packet using the RTL8019AS.
Sending a Frame
After making sure the RTL8019AS is started (loading CR with 0x22), the TPSR must be Initialized to 0x40. This sets the beginning of the transmit buffer area. Since we will be transferring data from the microcontroller to the RTL8019AS’s transmit buffer area, we must set up the Remote DMA start address registers, RSAR0 and RSAR1 with 0x00,0x40,with the address of the transmit buffer and tell the Remote DMA engine how many bytes to transfer in the RBCR0 and RBCR1 register pair. In the meantime, we’ve also cleared the ISR to make sure we can detect the end of the Remote DMA operation. Now that the RTL8019AS transmit buffer is defined and the Remote DMA knows how many bytes to move and where to put them, a Remote Read command (writing 0x12 to the CR) is issued. The RTL8019AS’s Remote DMA port is bidirectional. So, using the same Remote DMA port we used to transfer bytes from the RTL8019AS to the micro controller, we write the number of bytes loaded into the RBCR0 and RBCR1 register set to the RTL8019AS’s transmit buffer. The first 4 bytes in the RTL8019AS frame buffer are the packet header bytes and must not be counted in our transfer length calculations. When the micro controller has transferred all of the required bytes, the ISR’s RDC bit is interrogated to verify the completion of the Remote DMA operation. Even though we’ve specified the TPSR and loaded the RTL8019AS’s transmit buffer, we haven’t sent anything from the RTL8019AS’s MAC engine yet. So, we must load the TBCR0 and TBCR1 (Transmit Byte Count Registers) with 0x60 and 0x00 and issue a Remote Write with the TXP bit set to the CR (0x24).The command
(0x24) kicks off the Local DMA and bytes are transferred from the RTL8019AS’s transmit buffer area to the FIFO through the MAC engine and out to the network. The transmit operation is logically identical to the reply packet function used by UDP and ICMP. As for the rest of the code, if it is bound to the micro controller(checksum calculation, swapping IP and MAC addresses in the packet array)
Its an broadcast message. Those six bytes of FF in the DA uses that same personal computer to generate this frame and 00 E0 29 87 F5 5B matches up with the SA .The next two bytes (08 06) tell us this is an ARP. Since the SA is a broadcast address this is anARP request. if we pegged the SA correctly the IP address should be 192.168.0.150 or C0 A8 00 01a nd just by examining just a few fields you know what type of frame you’re looking at. The 4 bytes of the buffer header: The first byte of the four is the Receive Status Register(RSR).we have the PHY bit and the PRX bits set. The PHY bit being set tells us that the received packet contains a broadcast address because the was received with no errors. buffer header is generated with a PING that generated an ARP request. The PRX bit says that the packet
RSR Register 7 DFR 0 6 DIS 0 5 PHY 1 4 MPA 0 3 0 2 FAE 0 1 CRS 0 0 PRX 1
The second byte of the buffer header points to the next buffer page and the each buffer page is 256 bytes long and in hex that’s 0x0100.The each page falls on a 256-byte boundary and that we set the starting page at 0x46 when we initialized the RTL8019AS. The 0x46 is the upper byte, and the lower byte must always fall on a 256-byte boundary. So, that give us a receive buffer starting address of 0x4600. Adding one page to 0x4600 gives us our next page of 0x4700, which is what the 0x47 represents. The third byte of the buffer header is the low byte of the 16-bit length of the frame that is buffered. We must remember to subtract 4 from this value, as the 4 bytes of the buffer header are included in the count. So, 0x40 is equivalent to 64 decimal and taking into account our 4bytes of header information, the frame is 60 bytes long. Anything coming in that is less than 60 bytes in length would be a runt, and the RTL8019AS has been instructed not to accept runt packets. The last of the buffer header bytes is the upper byte of the length value. RTL8019AS Defined Registers Page 0 (PS1=0, PS0=0) Two registers are defined to contain the RTL8019AS chip ID.
The following table describes the behavior of bits and pins for cabling media.
RTL8019AS Configuration Modes The RTL8019AS supports 3 configuration modes: jumper, RT jumperless, and PnP .
Electrical Specifications and Timings
Absolute Maximum Ratings Operating Temperature ................................................................................... 0. to 70. Storage Temperature .......................................................................................-65. to 140. All Outputs and Supply Voltages, with respect to Ground ............................. -0.5V to 7V A.C. Timing Characteristics ISA I/O Read/Write
• ISA NIC cards
Embedded systems such as ADSL routers, IP sharing routers (NAT), printer servers and cable modems POWER SUPPLY UNIT:
Power supply unit is used to provide a constant 5Volts and 3.3volts supply to different ICs and GPS Receiver. This is a standard circuit using external 12V DC adopter and fixed 3-pin voltage regulator (7805).It integrates the RTL8019 and 16K-byte SRAM in a single chip.
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