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There are various methods of programming a PLC. Two of these
incude Ladder Logic and !unction "oc# Diagrams. The choice of
which method is dependent on whether the operation $eing automated
is machine contro or process contro oriented. Ladder Logic is the
method of choice in the case of machine contro and !unction "oc# for
Eectricians are famiiar and comforta$e with adder schematics.
These diagrams depict two vertica ines caed rais. The rais provide
power to the circuitr% of the schematic. The power can $e AC or DC
and the votage ma% var% depending on the re&uirements. 'tandard
a$eing for rais is L( and L).
Circuitr% is paced $etween the rais connecting the two power ines.
These individua ines are referred to as rungs. The circuitr% is
t%pica% ver% specific for adder schematics. !or instance* in the
foowing diagram note the first rung consists of a start $utton that is
actua% a momentar% switch.
!igure (+. Ladder 'chematic.
Rungs are composed of inputs and outputs. If an imaginar% ine is
drawn down the midde of the previous diagram a the inputs
,switches* etc.- are ocated to the eft. Outputs ,ights* etc.- are
ocated to the right. Locating a inputs on the eft side of a rung and
a outputs on the right is good design practice $ut not re&uired. The
atest software versions aow inputs and outputs to $e intermi.ed on a
Ladder diagrams are ver% simiar to adder schematics. A adder
diagram is a s%m$oic representation of an eectrica circuit. That is*
specifics concerning switches* etc. are repaced with generic s%m$os
$ut the same functionait% is represented. The primar% factor driving
the adder ogic design was the re&uirement to ma#e the s%stem as
famiiar as possi$e to the primar% users/ eectricians. Therefore* the
s%m$os utii0ed cose% resem$e ,if not identica to- schematic
s%m$os for eectrica devices. The foowing diagram is the adder
ogic e&uivaent of the previous adder schematic.
!igure (1. Ladder Diagram with I2O detai incuded.
3ote each device from the adder schematic has $een repaced with an
e&uivaent s%m$o. The resut is a coection of input and output
s%m$os that represent the genera operation of the device $ut not
how that action is achieved. Aso note that representing a switch or
output device generica% means the adder diagram simp% represents
the function of a switch or motor $% whether it is cosed2open or
Outputs and Inputs/Sensors
Outputs from a PLC are referred to as cois on a adder diagram. A coi
ma% represent a motor* ight* pump* counter* timer* rea%* etc. The
foowing dispa%s how a coi is represented in a adder diagram.
!igure (5. Coi representation in a adder diagram.
Inputs2'ensors to a PLC are referred to as Contacts and ma% consist of
switches* $uttons* etc. Contacts $egin in one of two states norma%
open or norma% cosed. A graphica representation of a norma%
open and cosed contact is depicted as it woud appear in a adder
!igure (6. 3orma% Open and Cosed representation in a adder diagram.
These contacts have an initia and foow7on state. The states are $est
descri$ed if the contact is thought of as a switch. 3orma% open
descri$es a switch whose initia state is open. Therefore* with power
appied to $oth rais of a adder diagram the initia state of a norma%
open switch woud not compete the connection. 8hen activated the
switch changes to its foow7on state. That is* the switch coses
competing the connection $etween the adder rais. 'witch positions
for $oth states are shown in the foowing !igure.
!igure (:. The 3O and 3C schematic representation for a imit switch.
3ote that simp% app%ing power to the rais wi not necessari% resut
in a foow7on state for a contact.
The DC e&uivaent circuit and adder diagram for a norma% open
3orma% Cosed descri$es a switch whose initia state is cosed. 8hen
activated the switch changes to an open state. The foowing diagram
depicts a norma% cosed push $utton and how it wi operate when
connected to a ight and $atter%. If the $utton is not pressed then the
circuit is compete and the ight is on. ;owever* if the $utton is
pressed or activated the circuit is $ro#en and the ight is off.
!igure (<. Circuit schematic of a 3C push$utton and ight and the circuit=s truth
ta$e. The ight wi $e on ,initia state- if the push$utton is not pressed.
This circuit is represented in a adder diagram as foows/
If the push $utton* in the diagram* is a norma% open contact then the
initia state woud $e an incompete circuit and the ight wi $e off.
3ot Pressed ,(- On ,(-
8hen pressed the $utton changes states from open to cose and the
circuit is competed there$% powering the ight.
'ituations wi arise that re&uire two or more events to occur prior to
activation of a coi ,output device-. That is* switch A and switch "
must $oth $e cosed ,or $e true- for the ight to turn on. The reation
$etween switches A and " and the ight is referred to as an ?A3D=
function. The foowing depicts a circuit* truth ta$e* and the ogica
gate for this ?A3D= reationship. The truth ta$e shows a the switch
position com$inations and the resuting outcome for the ight. The
A3D gate is a graphica method for representing A3D situations in a
!igure )>. Circuit schematic with an A3D configuration.
The end resut is ever% contact A3Ded together must $e cosed for the
ight to activate.
The corresponding adder diagram for the A3D scenario is/
A pro$em statement depicting an A3D situation might $e/
A dri press re&uires the operator to have one hand on each switch
$efore the machine wi activate. 'witch A and " represent the hand7
activated switches and the ight turning on simuates the dri press
Launching of nucear missies is aso an A3D scenario. Two #e%s must
$e turned simutaneous% to aunch. 8hat is another A3D scenario@
Pro$em statements wi sometimes incude situations caing for an
output to $e triggered $% an% num$er of individua or unreated
events. That is* either switch A or " must $e cosed ,or $e true- for
the ight to turn on. The reation $etween switches A* " and the ight
is referred to as an ?OR= function. The foowing depicts a circuit* truth
ta$e* and the ogica gate for this ?OR= reationship.
!igure )(. Circuit schematic with an OR configuration.
Reviewing the OR truth ta$e indicates the differences $etween ORs
and A3Ds. An% of the OR options is sufficient to activate the ight $%
itsef or in com$ination with an% of the other or a of the OR options.
8hen depicting OR scenarios in adder diagrams each option is
referred to as a $ranch.
The corresponding adder diagram for the previous OR scenario is/
A pro$em statement depicting the OR situation might $e/
'topping a garage door in an emergenc% situation ma% $e
accompished $% either pressing the stop $utton or $% pacing an
o$Aect in the path of the eectric e%e. 'witch A represents the stop
$utton* switch " represents the eectric e%e sensor and the ight
represents the garage door. If the ight is on the garage door is
8hat are some other OR scenarios@
Ladder Diagram Rules
(. A adder diagram is read i#e a $oo#B from eft to right and
from top to $ottom
). The vertica power ines or rais ma% $e a$eed L(* L) or the%
ma% $e a$eed C(* C) when the votage potentia is derived
from a transformer
D. Devices or components are shown in order of importance
whenever possi$e. 'top $uttons shoud $e given a higher
order of importance and therefore $e shown ahead of other
+. Eectrica devices are shown in their norma condition. The
norma condition of eectrica diagrams is the circuit
deenergi0ed and with no e.terna forces such as pressure*
fow* etc. acting on the device.
1. Contacts associated with rea%s* timers* motor starters* etc.
awa%s have the same num$er or etter designation as the
device that contros them. This hods true no matter where
the contacts appear in the circuit. !or e.ampe* in the adder
diagram presented on page (1* note the coi a$eed 4 on
rung (. Then note the two contacts in rungs ) and D $oth
have an 4 $eow them. This signifies these contacts as $eing
controed $% the coi in rung (.
5. A contacts associated with a device change state when the
device is energi0ed. In regard to the previous e.ampe when
the coi in rung ( is activated then an% contact controed $%
that coi wi change from its current state to the foow7on
state. Therefore* in rung ) the 3orma% Cosed ,3C- contact
wi open. The 3orma% Open ,3O- contact in rung D wi
6. Devices that perform a 'TOP function are norma% paced in
series on a rung.
:. Devices that perform a 'TART function are norma% paced in
parae or in a $ranch configuration.
There are often occasions when it is desired to turn on an output for
more than one condition. !or e.ampe* the door$e shoud sound if
either the front or rear door $utton is pushed. The OR option created
$% the front or rear door $utton activating the $e is produced in
adder diagrams through a $ranch. The $ranch produces two paths
that ma% activate the door$e.
!igure D(. An Or $ranch for front and rear door $e operation.
If the front door switch ,A- is cosed* eectricit% can fow to the $e.
Or if the rear door switch ,"- is cosed* eectricit% can fow through the
$ottom $ranch to the $e. That is* if at east one of the parae
$ranches forms a true ogic path* the run ogic is ena$ed.
"ranches ma% $e composed of singe or mutipe components. 3ote in
the foowing the first $ranch consists of an A3D function and the ower
$ranch is simp% a singe component.
!igure D). A compound $ranch configuration.
Coi D is activated when either A and " OR C OR A* "* A3D C are
cosed. On some PLC modes* $ranches ma% $e utii0ed for $oth inputs
and outputs on a rung.
!igure DD. An OR configuration for $oth inputs and outputs.
Parae output $ranching aows a singe input to activate mutipe
outputs simutaneous%. 3ote that if such a configuration is not
permitted $% the PLC design the adder diagram ma% $e reconfigured
to accommodate the needed functionait%. Redesign the adder using
the space $eow.
4emor% organi0ation refers to how certain areas of memor% in a PLC
are utii0ed. 3ot a PLC manufacturers organi0e memor% in the same
manner $ut even so the principes invoved are the same.
Ph%sica addressing* discussed in a previous section* is the a$iit% to
read data from a specific modue termina or write information to a
specific modue termina. 8hen information is read from a contact or
input it is stored in memor%. A portion of memor%* the input image
map* is designated to store this input information. Each input t%pica%
has* at a minimum* a singe $it designated to store its information.
!igure )). Associating input and output data with its corresponding memor%
Data resuting from ogica ana%sis $% the CPG is stored in memor%
a$eed as the output image map. !rom this point the information is
transferred to a designated output modue and then to the particuar
This e.ampe highights how portions of memor% are designated for
particuar operations. The memor% organi0ation or memor% map for a
4icroLogi. PLC is depicted $eow. Each segment is assigned a specific
function or assists in the performance of a function. !or instance* the
Timer fie stores a information reated to an% timer utii0ed $% the
PLC. This incudes status* contro* and $it information. Timer
information wi not $e stored in the counter fie.
Gtii0ing memor% in this manner provides for speed% storage and
retrieva of data. ;owever* the pre7assigned $oc#s of memor% can
!igure )D. 4emor% aocation for the 4icroLogi. (>>>.
ead to inefficienc% in cases where a the memor% space is aocated
$ut more is needed. There might $e free memor% in the counter $oc#
$ut this cannot $e used since it is designated on% for counters.
8hen referencing timers and counters* each wi $e identified as T+.>
and C1.>* respective% for the 4icroogi. (>>>. The T+ corresponds to
the fie ocation. The > identifies the specific timer instance. Each
instance has mutipe pieces of information associated with it such as
timer status and data information.
4emor% utii0ation or assignment in the ControLogi. refects the
schemas incorporated into ever%da% persona computers. 8hen a
timer or counter is added to a adder diagram the memor% addresses
are not automatica% seected from a predefined block. 4ost
recent% designed PLCs wi reserve a segment of memor $ased on
the needs of the singe device2instruction set. The memor% segment is
arge enough to store a the information reated to the
device2instruction. !or instance* a timer wi re&uire memor% to store
$it status and contro $it information so the predefined segment
incudes ocations for each.
This is ver% simiar to the 4icroLogi. memor% schema utii0ation
e.cept the predefined segment can reside an%where in the RA4 of the
PLC. The resut is memor% segments for timers* counters* etc.
interspersed throughout the RA4. This produces a much more
efficient use of memor% $ut re&uires more compe. storage and
retrieva agorithms in comparison to the 4icroLogi. scheme.
The PLC=s CPG monitors the status of a inputs. It ta#es these vaues
and energi0es or de7energi0es the outputs according to the adder
diagram2user program. This is referred to as scanning. A scan does
not consist of a PLC e.ecuting adder diagrams rung $% rung. Instead
the PLC performs an I2O and program scan. The I2O scan transfers
data to and from the output and input modues* respective%. The
information is transferred in the form of $its and stored in image
ta$es. Remem$er image ta$es are $oc#s of memor% designated to
store the input and output $it state. The input and output modues are
the portion of the PLC that interface with the outside word. The actua
$ridge $etween the ph%sica word and the interna word of the PLC is
the optica isoation circuitr%.
!igure )+. Interna view of PLC scan c%ce.
The scan $egins $% transferring data from the output image ta$e to
the output modue. This is foowed $% the PLC ta#ing a snapshot of
the current input signas registered in the input modue. This snapshot
Take some action
n!ut Mo"u#es $ut!ut Mo"u#es
n!ut "ata $ut!ut
E%amine "ata Retu&n &esu#t
!igure )1. Data fow from the PLC to a controed output.
!igure )5. Data fow into the PLC from an input source.
of data is transferred from the input modue to the input image ta$e.
The ne.t phase is the program scan. The CPG utii0es the snapshot of
the input image ta$e to perform a ogica evauation via the adder
ogic. Resuts of this ogica evauation are written to the output image
map during the fina step of the program scan c%ce. If a coi is true
,active* high- a one is written to the corresponding $it in the output
image ta$e* otherwise a 0ero is written to the $it denoting the contact
as fase ,inactive* ow-. Therefore* the CPG $ases its decisions on
states of the inputs prior to entering the program scan. If an input is
changed during the scan it wi not register unti the ne.t scan c%ce.
Competion of the program scan ends a singe scan c%ce and then the
process $egins again with the I2O scan.
!igure )6. Ph%sica and interna view of PLC scan c%ce .
(. Transfer output map $its to the output modue ,I2O
). Input modue signas are fro0en i.e. snapshot is
ta#en ,I2O scan-
D. Transfer input modue $its to the input image map
+. The ne.t phase is initiated $% the CPG reading a data $its
current% in the input image map ,Program scan-
1. CPG evauates2performs adder ogic on current set of data $its
5. Resuts of evauation transferred to the output
!ai7'afe Design is the procedure of programming to assure safet% of
the operator and processes. An e.ampe of this t%pe of design is
re&uiring two hand switches and a part presence sensor to $e cosed
$efore a machine wi activate. In this scenario the design ensures
there is a part in the machine and $oth hands of the operator are in a
Consider the seection of eectrica connections from a !ai7'afe
standpoint. If wires are cut or connections fai* the e&uipment shoud
sti $e safe. !or e.ampe* if a norma% cosed stop $utton is used*
and the connector is $ro#en* it wi cause the machine to stop as if the
stop $utton has $een pressed. !ai7'afe Design rues of thum$ for
seecting 3O or 3C devices are as foows/
3O 9 8hen wiring switches or sensors that start actions* use norma%
open switches so if there is a pro$em with the switch the process wi
3C 9 8hen wiring switches that stop processes use norma% cosed
switches so if the% fai the process wi stop.
!ai7'afe aso incudes scenarios guaranteeing notification of s%stem
faiure. ;ousing aarms utii0e cosed circuits to indicate that a door or
window is in the secure position. 'o if the window or door is opened
the circuit is $ro#en and the aarm s%stem registers this as unsecured.
Additiona%* this method of design ensures that circuit faiures wi $e
detected. 8ireess aarm s%stems depend on $atteries for each
individua door or window. If the $atter% dies then the faiure of the
circuit is registered $% the aarm s%stem prompting investigation. If
an aarm s%stem utii0es open circuits to indicate a secured door or
window and cosed circuits as unsecured then faiure of a circuit ma%
not $e detected.
Design of a fai7safe s%stem re&uires consideration of these a these
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