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# NR

Code No: 54111/MT
M.Tech., I-Semester Regular Examinations, March-2008.

DIGITAL SYSTEM DESIGN
(Common to Digital Systems & Computer Electronics, Digital
Electronics & Communication Systems, VLSI System Design)

Time: 3 hours Max. Marks: 60

Answer any FIVE questions
All questions carry equal marks.
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1.a) What are the basic elements of an ASM chart. Explain clearly with
an example.
b) Draw an ASM chart of JK flip flop. Realize it using SR flip flop and
required gates

2.a) Describe some important features of an FPGA and a CPLD.
b) With an example, explain how an FPGA is useful in the design of a
digital circuit.

3.a) What are the different faults found in combinational circuits? How
can they be categorized?
b) With an example, explain the principle of operation of path
sensitizations method

4.a) Draw the logic circuit which realizes the logic function
z = x, x2 + x3 x4 using And and OR gates. For the circuit realized
above, determine a test vector which detects SA0 fault on input
line ‘x2’.
b) Explain how kohavi algorithm is useful in the detection of faults in
digital circuits.

5.a) What is the difference between ‘Mealy’ and ‘Moore’ models of
sequential machines? Explain using structural diagrams.
b) Conduct a Homing experiment and determine shortest homing
sequence which identifies the final state of the given state machine
M1.
Machine, M1

Ps X=0 Ns1Z X=1
A B, 0 D,0
B A,0 B,0
C D,1 A,0
D D,1 C,0

(Contd…2)
-2- Code.No: 54111/MT

6.a) Explain briefly, the occurrance of various types of hazards in
digital circuits.
b) Implement a hazard free circuit for the following function:
f (ABCD) = ABC + ABC + C D + AC

7.a) List out and explain briefly about the faults that may occur in
PLAs.
b) With an example, explain how faults are detected in a PLA.

8.a) Discuss briefly, the steps involved in the PLA folding algorithm
‘COMPACT’.
b) Describe briefly the various DFT Schemes used in digital circuits.

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