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Code No: A5706

Jawaharlal Nehru Technological University Hyderabad
M. Tech I-Semester Supplementary Examinations September-2009
CPLD & FPGA ARCHITECTURE & APPLICATIONS
(VLSI System Design)
Time : 3 Hours Max.Marks: 60
Answer Any Five Questions
All Questions Carry Equal Marks
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1.a] What are the various interconnect technologies used for the purpose of
programming PLPS? Describe each one them.
b] Determine the size of PROM required to implant a i) 16 to 1 Mux ii) 4-bit
binary adder.
c] Compare in terms of speed and in system programmability of lattice PLSI’s
architecture and CYPRES FLASH 370.

2.a] Draw a basic block diagram of Xilinx Spartan FPGA and explain briefly about
CLB, LUT of their FPGA.
b] State how a CPLD such as Altua’s MAX 7000s deflect from a density PAL of
GAL.

3.a] We have two 2-bit binary number A1A0 and B1B0. Design a PLA to implant a
B

magnitude comparator to produce output for ‘equal to’, ‘not equal to’, ‘less than’
and greater that A1A0 with respect to B1B0.
B

b] How does the architecture of a typical FPGA device differ from that of a CPLD?
In what way does the architecture affect the timing performance in the two cases?

4.a] What are the possible ways of implementation programming links at the single
length interconnects and long interconnects in the arrays.
b] List out the characteristics that describe a CPLD of FPGA.

5.a] List the links to be programmed for a synchronous counter of 4-bit using CLBs of
XC4000.
b] Design an FSM which detects 1011 sequence using one hot encoding and realize
it on PAL.

6.a] Design a system which counts number of 0’s in a register A using shift operation.
Draw ASM chart for the design of control logic and implant the same on PLA.
b] Draw the data path diagram of the above design.

7. Design a parallel adder unit with ‘carry look ahead’ principle. Write HDL code to
be simulated using FPGA advantage. Show the simulated output that is excepted.

Contd -2-
Code No: A5706 -2-

8. Write short notes on:
a) Design flow for FPGA implementation.
b) Meta stability.

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