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Code No: 54203/MT

M.Tech. I-Semester Regular Examinations, March-2008.

CPLD & FPGA ARCHITECTURE & APPLICATIONS
(VLSI System Design)

Time: 3 hours Max. Marks: 60

Answer any FIVE questions
All questions carry equal marks.
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1.a) Distinguish between ROM’s, PLAs and PALS.
b) Mention the features of Altera Flex logic-1000 series CPLD.

2.a) Compare Altera series Max-5000 and 7000 series PLDs.
b) Give the Design Flow for xilinx FPGA’s.

3.a) Give the routing architectures and logic Blocks of FPGA.
b) Give the architecture and salient features of optimized
Reconfigurable cell Array (ORCA) of AT&T.

4.a) Give the xilinx XC4000 features and compare them with Altera’s
Flex 8000 series FPGA.
b) Explain about Top Down Design flow of FSM.

5.a) Explain about Linked state Machines and one-Hot state machine.
b) Explain about the term Synchronization. Give its significance.

6.a) Describe the methodology of Architectures centred around non-
registered PLDS.
b) With an example explain about one Hot design Method using
ASMs.

7.a) Explain about Linked State Machines
b) Give the basic concepts and properties of Petrinetes for state
machines.

8. Write notes on any TWO:
a) Meta stability
b) Parallel Adder sequential circuits
c) ‘FPGA Advantage’ EDA Tool.

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