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m.tech-Vlsi Technology and Design

m.tech-Vlsi Technology and Design

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Published by: srinivas on Dec 14, 2009
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Code No: 54105/MT M.Tech. I-Semester Examinations, February-2007.

VLSI TECHNOLOGY AND DESIGN (Common to Embedded Systems, VLSI System Design, Communication Systems and Digital System and Computer Electronics) Time: 3 hours Max. Marks: 60 Answer any FIVE questions All questions carry equal marks --1.a) b) c) 2.a) b) c) 3.a) b) Give advantages of CMOS over bipolar technologies Explain in detail the electrical model of a MOS transistor Discuss the BICMOS process What are the effects of scaling of Vt? Cascaded inverters can drive large capacitive loads – explain how What are the design rules? Why is metal – metal spacing larger they poly-poly spacing? Explain the delay in combinational logic network and how combinational delay can be reduced. Compute the zero delay signal probabilities for all signals in the network shown

4.a)

b)

What is clock skew? Explain how clock skew affects the digital system. What is the maximum allowable skew for the parameters T =10 ns, tpr = 1 ns, tsr = 1 ns, tsl = 1 ns, tpl = 5 ns, tp = 5 ns. What is the minimum allowable clock period under these conditions? What is ATPG? DFT? Generate a set of Sequential tests for the “01” – string recognizer which test for all stuck – at – 0/1 faults, assuming you don’t know the initial state. Design a Booth Multiplier a) Design the logic for one bit of a adder substractor (leaf cell) b) Design a stick diagram for the adder substractor Contd….2

5.

Code No: 54105/MT 6.a) b) c) d) 7.a) b) c) 8.a) b)

-2-

Give routing techniques to equalize channel utilization What are the problems presented by power distribution? How are they solved? Discuss the clock distribution strategies for VLSI system. How many output pads can be supported by 10λ wide power line in pad ring? Give a generic IC design flow chart and explain. Explain the technology independent and technology dependant strategies of logic optimization used in logic synthesis Explain briefly how the hardware/software Co-simulation and cosynthesis issued are addressed. How would you translate a register transfer structure into a legal 2-phase latched sequential machine? Write short notes on any two of the following: i) Differentiate the devices PAL, PLA and FPGA ii) Cross-talk iii) Placement and routing in floor planning. *****

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