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A

Compal Confidential
1

Model Name : JE50-HR/SJV50-HR


Compal Project Name : P5WE0/P5WS0
File Name : LA-6902P

Compal Confidential
2

JE50-HR/SJV50-HR(P5WE0/P5WS0) M/B Schematics Document


Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
Nvidia N12P GS/GV

2010-10-19

REV:0.1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Cover Page
Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics0.4

Date:

Sheet

Wednesday, October 27, 2010


E

of

61

Fan Control

page 42

PEG(DIS)

PCI-E 2.0x16 5GT/s PER LANE

100MHz

Nvidia
N12P GS/GV

Memory BUS(DDRIII)
204pin DDRIII-SO-DIMM X2
Dual Channel

Intel
Sandy Bridge

133MHz

page 11,12

BANK 0, 1, 2, 3
1.5V DDRIII 1066/1333

Processor

page22~30

rPGA989
page 4~10

HDMI(DIS)

CRT(DIS)

HDMI Conn.
page 33

LVDS(DIS)

FDI x8

LVDS Conn.

CRT Conn.

page 31

page 32

DMI x4

100MHz

100MHz

2.7GT/s

1GB/s x4

LVDS(UMA/OPTIMUS)
CRT(UMA/OPTIMUS)
TMDS(UMA/OPTIMUS)

Intel
Cougar Point-M

USB 2.0 conn x2

Bluetooth
Conn

CMOS Camera

USB port 0,1 on


USB/B
page 38

USB port 13

USB port 10

page 38

USBx14

3.3V 48MHz

HD Audio

3.3V 24MHz

3G connector
USB port 9,12 on 3G/B

page 31

page 37
2

PCH
HDA Codec

100MHz
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz

port 2,3

port 5

USB 3.0 conn x1


NEC uPD720200AF1
with USB3.0 Conn.
page 45

port 1

WLAN, WWAN
USB port 12,13
page 37

BCM57785

SPI ROM x1

page 35,36

Card Reader
Conn. page 35,36

SATA HDD
Conn. page

RJ45
page 36

34

SATA CDROM
Conn. page 34

page 40

LPC BUS

page 43,44

page 39

USB 2.0/B 2Port


USB Port0,1 page 38

LF-6901P

Touch Pad

FPC for USB3.0

Int.KBD

page 40

page 40

page 38

USB 3.0 /B
1 port as USB3.0
1 port as USB2.0

page 38

DC/DC Interface CKT.

page 41

ENE KB930

LS-6904P
Power On/Off CKT.

page 41

Phone Jack x 2

33MHz

Sub-board
LS-6901P
page 13

Int. Speaker

page 13

port 2

port 0,1

RTC CKT.

page 41

SPI

page 13~21

LAN(GbE) &
Card Reader

MINI Card x2

ALC271X/277X

989pin BGA

BIOS ROM
page 40

LS-6903P
4

3G/B
page 37

Power Circuit DC/DC


page 46~59

LS-6902P + LS-6905P

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 40
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

PWR/B

Title

Block Diagrams
Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Sheet

Wednesday, October 27, 2010


E

of

61

Voltage Rails
Power Plane

Description

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

BATT+

Battery power supply (12.6V)

N/A

N/A

N/A

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

Core voltage for CPU

ON

OFF

OFF

+VGA_CORE

Core voltage for GPU

ON

OFF

OFF

+VGFX_CORE

Core voltage for UMA graphic

ON

OFF

OFF

+0.75VS

+0.75VP to +0.75VS switched power rail for DDR terminator

ON

OFF

OFF

+1.05VSDGPU

+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU

ON

OFF

OFF

+1.05VS_VTT

+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU

ON

OFF

OFF

+1.05VS_PCH

+1.05VS_VCCP to +1.05VS_PCH power for PCH

ON

OFF

OFF

+1.5V

+1.5VP to +1.5V power rail for DDRIII

ON

ON

OFF

+1.5VS

+1.5V to +1.5VS switched power rail

ON

OFF

OFF

Vcc
Ra/Rc/Re

+1.5VSDGPU

+1.5VS to +1.5VSDGPU switched power rail for GPU

ON

OFF

OFF

Board ID

(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU

ON

OFF

OFF

+1.8VSDGPU

+1.8VS to +1.8VSDGPU switched power rail for GPU

ON

OFF

OFF

+3VALW

+3VALW always on power rail

ON

ON

ON*

+3VALW_EC

+3VALW always to KBC

ON

ON

ON*

+3V_LAN

+3VALW to +3V_LAN power rail for LAN

ON

ON

ON*

0
1
2
3
4
5
6
7

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

ON

ON

ON*

+3VALW to +3VS power rail

ON

OFF

OFF

+5VALW

+5VALWP to +5VALW power rail

ON

ON

ON*

+5VALW_PCH

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

ON

ON

ON*

+5VS

+5VALW to +5VS switched power rail

ON

OFF

OFF

+VSB

+VSBP to +VSB always on power rail for sequence control

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

Device

Address

Smart Battery

0001 011X b

Board ID
0
1
2
3
4
5
6
7

EC SM Bus2 address
Device

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

BOARD ID Table

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Address

Device

Address

Clock Generator (9LVS3199AKLFT,


RTM890N-631-VB-GRT)

1101 0010b

DDR DIMM0

1001 000Xb

PCB Revision
0.1
0.2
0.3
0.4
1.0

DDR DIMM2

1001 010Xb

USB Port Table


USB 2.0 USB 1.1 Port

UHCI0

3G & BT & USB30 & USB20 Config


USB30 SKU: USB30@
OPTMIUS SKU: OPT@
3G SKU: 3G@
BT SKU: BT@
USB20 SKU: USB20@
Non-OPTMIUS SKU: NOPT@
LAN Chip A0 version: A0@ N12P-GS: GS@
LAN chip B0 Version: B0@ N12P-GV: GV@
BOM Config
BT@/3G@/USB30@/UMA@/UMAO@/NOPT@/A0@
UMA Only:
OPTIMUS(N12P-GS): BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@/GS@
DIS Only(N12P-GS): BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@/GS@
OPTIMUS(N12P-GV): BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@/GV@
DIS Only(N12P-GV): BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@/GV@

UHCI2
UHCI3
UHCI4
EHCI2

UHCI5
UHCI6

VRAM P/N :
64*16
Samsung : SA000035700
Hynix : SA000032400/SA0000324C0
128*16
Samsung : SA00003MQ40
Hynix : SA00003VS00

UHCI1
EHCI1

0
1
2
3
4
5
6
7
8
9
10
11
12
13

3 External
USB Port
USB/B (Right Side)
USB/B (Right Side)
USB3.0 colay USB2.0 Conn.
USB/B Colay USB3.0

BTO Item
UMA Only
UMA with OPTIMUS
Dis with OPTIMUS
DIS Only
OPTIMUS
Non-OPTIMUS
3G
Blue Tooth
USB2.0
USB3.0
VRAM
Connector
Unpop
LAN Chip A0 version
LAN Chip B0 version
N12P-GS
N12P-GV

2010/10/15

BOM Structure
UMAO@
UMA@
DIS@
DISO@
OPT@
NOPT@
3G@
BT@
USB20@
USB30@
X76@
CONN@
@
A0@
B0@
GS@
GV@

Compal Electronics, Inc.


2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

EVT
EVT2
DVT
PVT
Pre-MP

Mini Card 1(WLAN)


3G/B(WWAN)
Camera
Mini Card 2(Reserved)
3G/B(SIM Card)
BlueTooth
Compal Secret Data

Security Classification

Issued Date

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

BTO Option Table

PCH SM Bus address


3

Board ID / SKU ID Table for AD channel

+1.8VS

+3VALW_PCH

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

HIGH

Full ON

+CPU_CORE

+3VS

SIGNAL

STATE

Title

Notes List
Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Sheet

Wednesday, October 27, 2010


E

of

61

+1.05VS_VTT

ZZZ
DA60000KC00

JCPU1A
D

15
15
15
15

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

B28
B26
A24
B23

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

15
15
15
15

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

G21
E22
F21
D21

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

15
15
15
15

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

G22
D22
F20
C21

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

15
15
15
15
15
15
15
15

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

A21
H19
E19
F18
B21
C20
D18
E17

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

15
15
15
15
15
15
15
15

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

A22
G19
E20
G18
B20
C19
D19
F17

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

15 FDI_FSYNC0
15 FDI_FSYNC1

15 FDI_INT

R145
24.9_0402_1%

15 FDI_LSYNC0
15 FDI_LSYNC1

J18
J17

FDI0_FSYNC
FDI1_FSYNC

H20

FDI_INT

J19
H17

FDI0_LSYNC
FDI1_LSYNC

A18
A17
B16

eDP_COMPIO
eDP_ICOMPO
eDP_HPD

C15
D15

eDP_AUX
eDP_AUX#

C17
F16
C16
G15

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

C18
E16
D16
F15

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

DMI

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

EDP_COMP

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

eDP

eDP_COMPIO and ICOMPO signals should


be shorted near balls,
Trace Width for EDP_COMPIO=4mils,
EDP_ICOMPO=12mils,
and both length less than 500 mils...
should not be left floating
,even if disable eDP function...

B27
B25
A25
B24

PCI EXPRESS* - GRAPHICS

+1.05VS_VTT

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

Intel(R) FDI

15
15
15
15

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

Sandy Bridge_rPGA_Rev0p61
CONN@

J22
J21
H22

R517
24.9_0402_1%
PEG_COMP

PEG_GTX_C_HRX_N15
K33
PEG_GTX_C_HRX_N14
M35
PEG_GTX_C_HRX_N13
L34
PEG_GTX_C_HRX_N12
J35
PEG_GTX_C_HRX_N11
J32
PEG_GTX_C_HRX_N10
H34
PEG_GTX_C_HRX_N9
H31
PEG_GTX_C_HRX_N8
G33
PEG_GTX_C_HRX_N7
G30
PEG_GTX_C_HRX_N6
F35
PEG_GTX_C_HRX_N5
E34
PEG_GTX_C_HRX_N4
E32
PEG_GTX_C_HRX_N3
D33
PEG_GTX_C_HRX_N2
D31
PEG_GTX_C_HRX_N1
B33
PEG_GTX_C_HRX_N0
C32
PEG_GTX_C_HRX_P15
J33
PEG_GTX_C_HRX_P14
L35
PEG_GTX_C_HRX_P13
K34
PEG_GTX_C_HRX_P12
H35
PEG_GTX_C_HRX_P11
H32
PEG_GTX_C_HRX_P10
G34
PEG_GTX_C_HRX_P9
G31
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P7
F33
PEG_GTX_C_HRX_P6
F30
PEG_GTX_C_HRX_P5
E35
PEG_GTX_C_HRX_P4
E33
PEG_GTX_C_HRX_P3
F32
PEG_GTX_C_HRX_P2
D34
PEG_GTX_C_HRX_P1
E31
PEG_GTX_C_HRX_P0
C33
B32
PEG_HTX_GRX_N15
PEG_HTX_GRX_N14
M29
PEG_HTX_GRX_N13
M32
PEG_HTX_GRX_N12
M31
PEG_HTX_GRX_N11
L32
PEG_HTX_GRX_N10
L29
PEG_HTX_GRX_N9
K31
PEG_HTX_GRX_N8
K28
PEG_HTX_GRX_N7
J30
PEG_HTX_GRX_N6
J28
PEG_HTX_GRX_N5
H29
PEG_HTX_GRX_N4
G27
PEG_HTX_GRX_N3
E29
PEG_HTX_GRX_N2
F27
PEG_HTX_GRX_N1
D28
PEG_HTX_GRX_N0
F26
E25
PEG_HTX_GRX_P15
PEG_HTX_GRX_P14
M28
PEG_HTX_GRX_P13
M33
PEG_HTX_GRX_P12
M30
PEG_HTX_GRX_P11
L31
PEG_HTX_GRX_P10
L28
PEG_HTX_GRX_P9
K30
PEG_HTX_GRX_P8
K27
PEG_HTX_GRX_P7
J29
PEG_HTX_GRX_P6
J27
PEG_HTX_GRX_P5
H28
PEG_HTX_GRX_P4
G28
PEG_HTX_GRX_P3
E28
PEG_HTX_GRX_P2
F28
PEG_HTX_GRX_P1
D27
PEG_HTX_GRX_P0
E26
D25

C46 1
C49 1
C51 1
C53 1
C60 1
C71 1
C75 1
C82 1
C92 1
C93 1
C102 1
C111 1
C113 1
C125 1
C129 1
C144 1

PEG_ICOMPI and PEG_RCOMPO signals should be


shorted and routed,
max length = 500 mils,trace width=4mils
PEG_ICOMPO signals should be routed with - max
length = 500 mils,trace width=12mils
spacing =15mils

PEG_GTX_HRX_N15
2 DIS@ 0.22U_0402_10V6K
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N14
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N13
PEG_GTX_HRX_N12
2 DIS@ 0.22U_0402_10V6K
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N11
PEG_GTX_HRX_N10
2 DIS@ 0.22U_0402_10V6K
PEG_GTX_HRX_N9
2 DIS@ 0.22U_0402_10V6K
PEG_GTX_HRX_N8
2 DIS@ 0.22U_0402_10V6K
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N7
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N6
PEG_GTX_HRX_N5
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N4
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N3
DIS@
0.22U_0402_10V6K
2
PEG_GTX_HRX_N2
2 DIS@ 0.22U_0402_10V6K
PEG_GTX_HRX_N1
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N0
2 DIS@ 0.22U_0402_10V6K

PEG_GTX_HRX_N[0..15] 22
PEG_GTX_HRX_P[0..15] 22

PEG_HTX_C_GRX_N[0..15] 22
PEG_HTX_C_GRX_P[0..15] 22

PEG_GTX_HRX_P15
PEG_GTX_HRX_P14
PEG_GTX_HRX_P13
PEG_GTX_HRX_P12
PEG_GTX_HRX_P11
PEG_GTX_HRX_P10
C68 1
PEG_GTX_HRX_P9
2 DIS@ 0.22U_0402_10V6K
C81 1
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P8
C86 1
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P7
C89 1
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P6
C100 1
2 DIS@ 0.22U_0402_10V6K
PEG_GTX_HRX_P5
C105 1
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P4
C106 1
2 DIS@ 0.22U_0402_10V6K
PEG_GTX_HRX_P3
C117 1
DIS@
0.22U_0402_10V6K
2
PEG_GTX_HRX_P2
C119 1
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P1
C135 1
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P0
C138 1
2 DIS@ 0.22U_0402_10V6K
PEG_HTX_C_GRX_N15
C516 1
2 DIS@ 0.22U_0402_10V6K
PEG_HTX_C_GRX_N14
C520 1
2 DIS@ 0.22U_0402_10V6K
PEG_HTX_C_GRX_N13
C529 1
2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N11
C534 1
DIS@ 0.22U_0402_10V6K
C538
1
2 2DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N9
C540 1
2 DIS@ 0.22U_0402_10V6K
PEG_HTX_C_GRX_N8
C542
2 DIS@ 0.22U_0402_10V6K
C544 1 1
2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N7
C546 1
2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N6
C548 1
2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N5
C550
2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N4
C552 1 1
2 DIS@ 0.22U_0402_10V6K
PEG_HTX_C_GRX_N3
C554
2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N2
C556 1 1
2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N1
C558 1
DIS@
0.22U_0402_10V6K
2
PEG_HTX_C_GRX_N0
C560 1
2 DIS@ 0.22U_0402_10V6K
PEG_HTX_C_GRX_P15
C515 1
2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P14
C528 1
2 DIS@ 0.22U_0402_10V6K
PEG_HTX_C_GRX_P13
C533 1
2 DIS@ 0.22U_0402_10V6K
PEG_HTX_C_GRX_P12
C536 1
2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P11
C539 1
PEG_HTX_C_GRX_P10
2 DIS@ 0.22U_0402_10V6K
C541 1
2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P9
C543 1
2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P8
C545 1
2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P7
C547 1
2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
C549
0.22U_0402_10V6K
C551
0.22U_0402_10V6K
1 1 2 DIS@
2 DIS@
PEG_HTX_C_GRX_P4
C553 1
2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P3
C555 1
2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P2
C557 1
2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0
C559
DIS@ 0.22U_0402_10V6K
1
C561 1
2 2DIS@ 0.22U_0402_10V6K

C47
C50
C52
C56
C66

1
1
1
1
1

2 DIS@ 0.22U_0402_10V6K
2 DIS@ 0.22U_0402_10V6K
2 DIS@ 0.22U_0402_10V6K
2 DIS@ 0.22U_0402_10V6K
2 DIS@ 0.22U_0402_10V6K

Typ- suggest 220nF. The change in AC capacitor


value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

Compal Secret Data

Security Classification

2010/10/15

Issued Date

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size
Document Number
Custom

JE50-HR/SJV50-HR M/B Schematics

Date:

W ednesday, October 27, 2010

Sheet
1

of

61

Rev
0.4

Buffered reset to CPU


+3VS

+3VALW

R87
43_0402_1%
1
2 BUF_CPU_RST#

okCPUreset

O
A

4 PM_SYS_PWRGD_BUF

1
R204

2
130_0402_5%

PM_DRAM_PWRGD_R

R203
39_0402_1%

40,50 H_PROCHOT#

18 H_THRMTRIP#

H_PECI_ISO

R92
56_0402_5% H_PROCHOT#_R
1
2

CLOCKS

A16
A15

PECI

AL32

PROCHOT#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

R8

AK1
A5
A4

PRDY#
PREQ#

H_CPUPWRGD_R

OK

AM34

AP33

PM_SYNC

UNCOREPWRGOOD

UNCOREPWRGOOD: CORE

PM_DRAM_PWRGD_R

V8

SM_DRAMPWROK

SM_DRAMPWROK:DRAM power ok
BUF_CPU_RST#

AR33

RESET#

JTAG & BPM

18 H_CPUPWRGD

R81
0_0402_5%
1
2

H_PM_SYNC_R

PWR MANAGEMENT

1 10K_0402_5%

R96
0_0402_5%
1
2

1 1K_0402_5%
1 1K_0402_5%

+1.05VS_VTT

If use External Graphic or


use integrated without eDP
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT

SM_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

SM_DRAMRST# 6

R231

1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%

2
R566 2
R571 2

DDR3 Compensation Signals

THERMTRIP#

TCK
TMS
TRST#

TDI
TDO

R03 modify

AP29
AP27

15 H_PM_SYNC

R516 2
R518 2

CLK_CPU_DMI 14
CLK_CPU_DMI# 14

CATERR#

AN33

R97
0_0402_5% H_THEMTRIP#_R
AN32
1
2

DPLL_REF_SSCLK
DPLL_REF_SSCLK#

A28
A27

AR26
AR27
AP30

AR28
AP26

DBR#

AL35

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

TCK
TMS
TRST#

TDI
TDO

DBRESET#_R

PAD
PAD
PAD

T66
T67
T68

PAD
PAD

T69
T70

@
@
@

+3VS

H_PECI

1 62_0402_5%
H_PROCHOT#

SKTOCC#

BCLK
BCLK#

CLK_CPU_DMI
CLK_CPU_DMI#

@
@

R101
0_0402_5%
1
2

R40
1K_0402_5%

18,40

2 R91

@
R93
0_0402_5%
1
2

AL33

SNB_IVB#

DDR3
MISC

Processor Pullups

H_CATERR#

PAD

MISC

AN34

T6

JCPU1B

C26

17 H_SNB_IVB#

R84 2

SNB_IVB# had changed the name to


PROC_SELCT#,function for future platform,
connect to the DF_TVS strap on the PCH

+1.05VS_VTT

RESET#:

15 SYS_PWROK
15 PM_DRAM_PWRGD

R88
0_0402_5%
@

SN74LVC1G07DCKR_SC70-5

200_0402_1%

U11
74AHC1G09GW_TSSOP5

4 BUFO_CPU_RST#

R205

U7

R90
75_0402_1%

1
1

C307
0.1U_0402_16V4Z

THERMAL

+1.5V_CPU_VDDQ

PLT_RST#

Y
G

PLT_RST#

NC

+1.05VS_VTT

C162
0.1U_0402_16V4Z

17

@
R782 2 1
1
0_0402_5%
R64 2 2
1
0_0402_5%

XDP_DBRESET#

XDP_DBRESET# 15

Sandy Bridge_rPGA_Rev0p61
CONN@

Compal Secret Data

Security Classification

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PROCESSOR(2/7) PM,XDP,CLK

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010

Sheet

of

61

JCPU1D

11 DDR_A_D[0..63]

11 DDR_A_BS0
11 DDR_A_BS1
11 DDR_A_BS2

AE10
AF10
V6

11 DDR_A_CAS#
11 DDR_A_RAS#
11 DDR_A_WE#

AE8
AD9
AF9

SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]

SA_CLK[2]
SA_CLK#[2]
SA_CKE[2]

SA_CLK[3]
SA_CLK#[3]
SA_CKE[3]

DDR SYSTEM MEMORY A

C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

SA_CAS#
SA_RAS#
SA_WE#

Sandy Bridge_rPGA_Rev0p61

@ R184
0_0402_5%
1
2

R217
1K_0402_5%

DIMMreset

DIMM_DRAMRST#_R
1
Q12
BSS138_NL_SOT23-3

SM_DRAMRST#

5 SM_DRAMRST#

R186
4.99K_0402_1%

11,12,14 RST_GATE

SA_CLK_DDR1 11
SA_CLK_DDR#1 11
DDRA_CKE1_DIMMA 11

AB4
AA4
W9

AB3
AA3
W10

DDRA_CS0_DIMMA# 11
DDRA_CS1_DIMMA# 11

SA_ODT[0] AH3
SA_ODT[1] AG3
SA_ODT[2] AG2
SA_ODT[3] AH2

SA_ODT0 11
SA_ODT1 11

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

DDR_A_DQS#0
C4
DDR_A_DQS#1
G6
DDR_A_DQS#2
J3
DDR_A_DQS#3
M6 DDR_A_DQS#4
AL6 DDR_A_DQS#5
AM8 DDR_A_DQS#6
AR12 DDR_A_DQS#7
AM15

DDR_A_DQS#[0..7]

DDR_A_DQS0
DDR_A_DQS1
D4
DDR_A_DQS2
F6
DDR_A_DQS3
K3
DDR_A_DQS4
N6
AL5 DDR_A_DQS5
AM9 DDR_A_DQS6
AR11 DDR_A_DQS7
AM14

DDR_A_DQS[0..7]

DDR_A_MA0
AD10 DDR_A_MA1
W1 DDR_A_MA2
W2 DDR_A_MA3
W7 DDR_A_MA4
DDR_A_MA5
V3
DDR_A_MA6
V2
W3 DDR_A_MA7
W6 DDR_A_MA8
DDR_A_MA9
V1
W5 DDR_A_MA10
AD8 DDR_A_MA11
DDR_A_MA12
V4
DDR_A_MA13
W4
DDR_A_MA14
AF8 DDR_A_MA15
V5
V7

DDR_A_MA[0..15] 11

11

11

12 DDR_B_BS0
12 DDR_B_BS1
12 DDR_B_BS2

12 DDR_B_CAS#
12 DDR_B_RAS#
12 DDR_B_WE#

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7
R6

AA10
AB8
AB9

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]

SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]

AE2
AD2
R9

SB_CLK_DDR0 12
SB_CLK_DDR#0 12
DDRB_CKE0_DIMMB 12

AE1
AD1
R10

SB_CLK_DDR1 12
SB_CLK_DDR#1 12
DDRB_CKE1_DIMMB 12

AB2
AA2
T9

SB_CLK[2]
SB_CLK#[2]
SB_CKE[2]

AA1
AB1
T10

SB_CLK[3]
SB_CLK#[3]
SB_CKE[3]

AD3
AE3
AD6
AE6

SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDRB_CS0_DIMMB# 12
DDRB_CS1_DIMMB# 12

SB_ODT[0] AE4
SB_ODT[1] AD4
SB_ODT[2] AD5
SB_ODT[3] AE5

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

D7
F3
K6
N3
AN5
AP9
AK12
AP15

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

C7
G3
J6
M3
AN6
AP8
AK11
AP14

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

SB_ODT0 12
SB_ODT1 12

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS#[0..7]

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS[0..7]

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_MA[0..15] 12

12

12

Sandy Bridge_rPGA_Rev0p61
CONN@

+1.5V

AA5
AB5
V10

CONN@

R155
1K_0402_5%
2

CPU

Follow CRB1.0

SA_CLK_DDR0 11
12 DDR_B_D[0..63]
SA_CLK_DDR#0 11
DDRA_CKE0_DIMMA 11

SA_CS#[0] AK3
SA_CS#[1] AL3
SA_CS#[2] AG1
SA_CS#[3] AH1

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_BS[0]
SA_BS[1]
SA_BS[2]

AB6
AA6
V9

DDR SYSTEM MEMORY B

JCPU1C

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

C293
0.047U_0402_16V7K

DIMM_DRAMRST# 11,12

S0
RST_GATE hgih ,MOS ON
SM_DRAMRST# HIGH,DIMM_DRAMRST# HIGH
Dimm not reset
S3
RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# HIGH
Dimm not reset
S4,5
RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# low
Dimm reset

Compal Secret Data

Security Classification
Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.


PROCESSOR(3/7) DDRIII

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010


1

Sheet

of

61

CFG Straps for Processor

CFG2

R112
1K_0402_5%
D

PEG Static Lane Reversal - CFG2 is for the 16x

JCPU1E

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

1
R513
10K_0402_5%

J15

RSVD24
RSVD25
RSVD26

CFG4

RSVD51
RSVD52

1 : Disabled; No Physical Display Port


attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG6

B34
A33
A34
B35
C35

CFG5

R107
1K_0402_5% @

R108
1K_0402_5%

AJ32
AK32

AH27 change to VCC_DIE_SENSE


RSVD53

PAD

AH27

T7

PCIE Port Bifurcation Straps


RSVD54
RSVD55

RSVD56
RSVD57
RSVD58

AN35
AM35

RSVD54 and RSVD55 had changed to


BCLK_ITP and BCLK_ITP#

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG[6:5]

*10: x8, x8 - Device 1 function 1 enabled ; function 2

disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

AT2
AT1
AR1

RSVD27

1/NC : (Default) +1.05VS_VTT

KEY

B1

CFG7

0: +1.0VS_VTT

A19

For 2012 CPU support

J20
B18
A19

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

AR35
AT34
AT33
AP35
AR34

RSVD26 had changed the name to VCCIO_SEL


Need PH +3VALW 10K at +1.05VS_VTT source
for 2012 processor +1.05V and +1.0V select

R102
1K_0402_5%

Sandy Bridge_rPGA_Rev0p61

VCCIO_SEL

VCCIO_SEL

F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29

T8
J16
H16
G16

R164
1K_0402_5%

R154
1K_0402_5%

VCCIO_SEL
B

RSVD6
RSVD7

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
For Future CPU M3 support,
Sandey bridge not supportM3,
Check list1.0&CRB say can NC

B4
D1

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

11 SA_DIMM_VREFDQ
12 SB_DIMM_VREFDQ

AJ26

0:Lane Reversed

CFG4

AT26
AM33
AJ27

Display Port Presence Strap

RESERVED

RSVD6 and RSVD7 had changed to


SA_DIMM_VREFDQ and SB_DIMMVREFDQ

definition matches

R109
1K_0402_5%

AJ31
AH31
AJ33
AH33

1: Normal Operation; Lane #


socket pin map definition

CFG2

CFG4
CFG5
CFG6
CFG7

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

CFG2

AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

L7
AG7
AE7
AK2
W8

CFG0

CONN@

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB


de assertion
0: PEG Wait for BIOS for training

Compal Secret Data

Security Classification

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PROCESSOR(4/7) RSVD,CFG

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010

Sheet

of

61

JCPU1F

QC 94A
DC 53A

PEG AND DDR

R02 modify
@

ME interefer,not pop!!

J23

+1.05VS_VTT

CORE SUPPLY

C641
22U_0805_6.3V6M

C291
22U_0805_6.3V6M

C816
220U_B2_2.5VM_R35

C292
22U_0805_6.3V6M

C229
22U_0805_6.3V6M

INTEL Recommend
2*330uF,12*22uF
from PDDG 1.0

R447
75_0402_1%

SVID

VIDALERT#
VIDSCLK
VIDSOUT

R448
43_0402_1%
1
2
R446
R449
2 0_0402_5%
1 1
2 0_0402_5%

H_CPU_SVIDALRT#
AJ29 H_CPU_SVIDCLK
AJ30 H_CPU_SVIDDAT
AJ28

VR_SVID_ALRT# 55
VR_SVID_CLK 55
VR_SVID_DAT 55

Place the PU
resistors close to VR

Place the PU
resistors close to CPU

+CPU_CORE

2010/10/15

VCC_SENSE
VSS_SENSE

VCCSENSE_R
VSSSENSE_R
AJ35
AJ34

R444 1
R443 1

VSSIO_SENSE
B10
A10
VCCIO_SENSE
VSSIO_SENSE
VSSIO_SENSE

2
2

VCCSENSE 55
VSSSENSE 55

0_0402_5%
0_0402_5%

VCCIO_SENSE 53

change to
VSS_SENSE_VCCIO

R442
100_0402_1%
R163
10_0402_5%

SENSE LINES

R445
100_0402_1%

Should change to connect form


power cirucit & layout differential
with VCCIO_SENSE.

Compal Secret Data


2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

R450
130_0402_5%

Sandy Bridge_rPGA_Rev0p61

C638
330U_D2_2V_Y

1
@

C232
22U_0805_6.3V6M

1
@

C616
330U_D2_2V_Y

C648
22U_0805_6.3V6M

C288
22U_0805_6.3V6M

+1.05VS_VTT

Security Classification
IssuedCONN@
Date

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

C289
22U_0805_6.3V6M

VCCIO40

+1.05VS_VTT

C649
22U_0805_6.3V6M

2 3

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

C652
22U_0805_6.3V6M

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

C650
22U_0805_6.3V6M

2 3

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

C647
22U_0805_6.3V6M

C606
22U_0805_6.3V6M

2 3

C562
470U_D2_2VM_R4M

PAW00
use 470uF*2
330uF*3

C151
470U_D2_2VM_R4M

2 3

C626
470U_D2_2VM_R4M

C233
470U_D2_2VM_R4M

2 3

C152
470U_D2_2VM_R4M

C160
22U_0805_6.3V6M

Follow Power Suggestion ,


place 3-pin Cap for CPU_CORE

C607
22U_0805_6.3V6M

+CPU_CORE

C171
22U_0805_6.3V6M

C608
22U_0805_6.3V6M

C172
22U_0805_6.3V6M

C609
22U_0805_6.3V6M

C610
22U_0805_6.3V6M

C575
22U_0805_6.3V6M

C635
22U_0805_6.3V6M

C226
22U_0805_6.3V6M

C225
22U_0805_6.3V6M

C627
22U_0805_6.3V6M

C574
22U_0805_6.3V6M

INTEL Recommend
4*470uF,16*22uF and 10*10uF
from PDDG 1.0

C224
22U_0805_6.3V6M

C622
22U_0805_6.3V6M

+1.05VS_VTT

8.5A

C651
22U_0805_6.3V6M

+CPU_CORE

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

C290
22U_0805_6.3V6M

C222
10U_0805_10V4Z

C202
10U_0805_10V4Z

C207
10U_0805_10V4Z

C203
10U_0805_10V4Z

C218
10U_0805_10V4Z

C204
10U_0805_10V4Z

C223
10U_0805_10V4Z

C227
10U_0805_10V4Z

C205
10U_0805_10V4Z

2
D

C206
10U_0805_10V4Z

POWER

+CPU_CORE

SV type CPU

Title

Compal Electronics, Inc.


PROCESSOR(5/7) PWR,BYPASS

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010

Sheet

of

61

SENSE
LINES

2
1

VREF

2
1

PAD-OPEN 4x4m
@
+1.5VS

J2

PAD-OPEN 4x4m
@

Short for +1.5VS to +1.5V_1

INTEL Recommend
1*330uF,6*10uF
from PDDG 1.0

+VCCSA

6A
+VCCSA

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VCCSA_SENSE

M27
M26
L26
J26
J25
J24
H26
H25

1
@

R1371

1
+

2 0_0402_5%

VCCSA_SENSE

If possible,use os-con cap


if not,use the D2 size

R1411

2 0_0402_5%

VSSSA_SENSE 52

VCCSA_SENSE 52

H23

VCCSA

VCCSA_VID0

FC_C22
VCCSA_VID1

VCCSA_VID1

C22
C24

FC_C22
change to
VCCSA_VID0

VCCSA_VID1 52

R143
10K_0402_5%

VID0

VID1

Vout

2011CPU

2012CPU

0.9V

0.8V

0.725V

0.675V

R138
@ 0_0402_5%

CONN@

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

INTEL Recommend
1*330uF,3*10uF
from PDDG 1.0

Sandy Bridge_rPGA_Rev0p61

Issued Date

DDR3 -1.5V RAILS

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

INTEL Recommend
1*330uF,1*10uF and 2*1uF(0402)
from PDDG 1.0

VCCPLL1
VCCPLL2
VCCPLL3

+1.5V

J1

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

C221
220U_B2_2.5VM_R35

B6
A6
A2

+1.5V_CPU_VDDQ

10A

C213
10U_0603_6.3V6M

C653
1U_0402_6.3V6K

C654
1U_0402_6.3V6K

C655
10U_0805_10V4Z

C664
220U_B2_2.5VM_R35

R575
100_0402_1%
2

C219
10U_0805_10V4Z

+1.8VS_VCCPLL

C605
10U_0805_10V4Z

1.2A

R528
0_0805_5%
1
2

C688
0.1U_0402_16V4Z

C214
10U_0805_10V4Z

+1.8VS

+V_SM_VREF

AL1

motherboard design (Gfx VR keeps VAXG from


floating) if the VR is stuffed

SM_VREF

R582
100_0402_1%

C355
330U_D2_2V_Y

supports external graphics and if GFX VR is not


stuffed in a common motherboard design,

VAXG can be left floating in a common

+V_SM_VREF should
have 20 mil trace width

C361
10U_0805_10V4Z

Can connect to GND if motherboard only

+1.5V_CPU_VDDQ

C365
10U_0805_10V4Z

Vaxg

VCC_AXG_SENSE 55
VSS_AXG_SENSE 55

C341
10U_0805_10V4Z

UMA@ 2

AK35
AK34

C362
10U_0805_10V4Z

UMA@ 2

VAXG_SENSE
VSSAXG_SENSE

C364
10U_0805_10V4Z

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

C363
10U_0805_10V4Z

UMA@
1

C599
22U_0805_6.3V6M

C600
22U_0805_6.3V6M

UMA@

C273
22U_0805_6.3V6M

UMA@
1

C275
22U_0805_6.3V6M

UMA@
1

C242
22U_0805_6.3V6M

UMA@
1

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

SA RAIL

POWER

JCPU1G

MISC

C271
22U_0805_6.3V6M

C208
22U_0805_6.3V6M

C274
22U_0805_6.3V6M

C645
330U_D2_2V_Y

C646
330U_D2_2V_Y

UMA@
1

C209
22U_0805_6.3V6M

C210
22U_0805_6.3V6M

UMA@
1

UMA@
1

C231
22U_0805_6.3V6M

UMA@
1

C211
22U_0805_6.3V6M

UMA@
1

C272
22U_0805_6.3V6M

UMA@
1

C212
22U_0805_6.3V6M

UMA@
1

C625
22U_0805_6.3V6M

UMA@
1

C611
22U_0805_6.3V6M

R151
0_0402_5%
DISO@

QC 33A
DC 26A

GRAPHICS

+VGFX_CORE

1.8V RAIL

INTEL Recommend
2*470uF,12*22uF
from PDDG 1.0

Title

Compal Electronics, Inc.


PROCESSOR(6/7) PWR

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010

Sheet

of

61

JCPU1H
D

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

JCPU1I

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

Sandy Bridge_rPGA_Rev0p61

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

VSS

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

Sandy Bridge_rPGA_Rev0p61

CONN@

CONN@

Compal Secret Data

Security Classification

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PROCESSOR(7/7) VSS

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Sheet

Wednesday, October 27, 2010


1

10

of

61

+1.5V

+1.5V

DDR_A_D[0..63]

DDR_A0_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

DDR_A_D0
DDR_A_D1

DDR_A_DQS#1
DDR_A_DQS1

All VREF traces should


have 10 mil trace width

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

Layout Note:
Place near JDIMM1

DDR_A_DQS#2
DDR_A_DQS2

+1.5V
DDR_A_D18
DDR_A_D19

C409
1U_0402_6.3V6K

C410
1U_0402_6.3V6K

C385
1U_0402_6.3V6K

C371
1U_0402_6.3V6K

DDR_A_D24
DDR_A_D25
DDR_A0_DM3
DDR_A_D26
DDR_A_D27

DDRA_CKE0_DIMMA

6 DDRA_CKE0_DIMMA

+1.5V

DDR_A_BS2

6 DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

C414
10U_0603_6.3V6M

C415
10U_0603_6.3V6M

C378
10U_0603_6.3V6M

C384
10U_0603_6.3V6M

DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

SA_CLK_DDR0
SA_CLK_DDR#0

6 SA_CLK_DDR0
6 SA_CLK_DDR#0

+1.5V

1
+

DDR_A_MA13
DDRA_CS1_DIMMA#

6 DDRA_CS1_DIMMA#

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

+0.75VS

DDR_A0_DM5

C388
1U_0402_6.3V6K

C394
1U_0402_6.3V6K

C395
1U_0402_6.3V6K

C393
1U_0402_6.3V6K

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51

Layout Note:
Place near JDIMM1.203,204

DDR_A_D56
DDR_A_D57

DDR_A0_DM7

+3VS
+0.75VS

R301
10K_0402_5%

R302
10K_0402_5%

C416
2.2U_0603_6.3V6K

R285
R318
R283
R312

DDR_A_D58
DDR_A_D59

DDR_A0_DM0
DDR_A0_DM1
DDR_A0_DM2
DDR_A0_DM3
DDR_A0_DM4
DDR_A0_DM5
DDR_A0_DM6
DDR_A0_DM7

R315
R284
R286
R316

C404
0.1U_0402_16V4Z

1
1
1
1
1
1
11

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

2
2
2
2
2
2
22

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

205 G1
FOX_AS0A626-U8SN-7F G2

206

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13
DDR_A0_DM1
DDR3_DRAMRST#

DIMM_DRAMRST# 6,12

DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A0_DM2

DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDRA_CKE1_DIMMA

DDRA_CKE1_DIMMA 6

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

SA_CLK_DDR1
SA_CLK_DDR#1

SA_CLK_DDR1 6
SA_CLK_DDR#1 6

DDR_A_BS1
DDR_A_RAS#

+1.5V

DDR_A_BS1 6
DDR_A_RAS# 6

DDRA_CS0_DIMMA#
SA_ODT0

SA_ODT1

DDRA_CS0_DIMMA# 6
SA_ODT0 6

R267
1K_0402_5%

SA_ODT1 6
+VREF_CA

DDR_A_D36
DDR_A_D37

DDR_A0_DM4

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

C373
0.1U_0402_16V4Z

DDR_A_D32
DDR_A_D33

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_A_D4
DDR_A_D5

C372
2.2U_0603_6.3V6K

C407
330U_D2_2V_Y

DDR_A_WE#
DDR_A_CAS#

6 DDR_A_WE#
6 DDR_A_CAS#

C383
10U_0603_6.3V6M

C412
10U_0603_6.3V6M

DDR_A_MA10
DDR_A_BS0

6 DDR_A_BS0

C413
10U_0603_6.3V6M

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

6,12,14 RST_GATE
DDR_A_DQS#[0..7]

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C411
0.1U_0402_16V4Z

BSS138_NL_SOT23-3

R319
1K_0402_5%

C408
2.2U_0603_6.3V6K

1
Q46
@

+1.5V

JDIMM1
1 VREF_DQ
3 VSS2
5 DQ0
7 DQ1
9 VSS4
11 DM0
13 VSS5
15 DQ2
17 DQ3
19 VSS7
21 DQ8
23 DQ9
25 VSS9
27 DQS#1
29
DQS1
31 VSS11
33 DQ10
35 DQ11
37 VSS13
39 DQ16
41 DQ17
43 VSS15
45 DQS#2
47 DQS2
49 VSS18
51 DQ18
53 DQ19
55 VSS20
57 DQ24
59 DQ25
61 VSS22
63 DM3
65 VSS23
67 DQ26
69 DQ27
71 VSS25

+V_DDR_REFA

7 SA_DIMM_VREFDQ

@ R133
0_0402_5%
1
2

R266
1K_0402_5%

R320
1K_0402_5%

M3 support

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A0_DM6

DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

D_CK_SDATA
D_CK_SCLK

D_CK_SDATA 12,14
D_CK_SCLK 12,14

+0.75VS

CONN@

<Address(SA1,SA0): 00>

DIMM_1 Reserve H:8mm

Compal Secret Data

Security Classification
Issued Date

2010/10/15

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Title

Compal Electronics, Inc.


DDRIII DIMMA

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

1
Wednesday, October
27, 2010

Sheet

11

of

61

+1.5V

+1.5V

DDR_B_D8
DDR_B_D9

6,11,14 RST_GATE
D

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_D[0..63]

All VREF traces should


have 10 mil trace width

6
6

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_MA[0..15]

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

Layout Note:
Place near JDIMM2

DDR_B_D24
DDR_B_D25

+1.5V

DDR_B0_DM3

DDR_B_D26
DDR_B_D27

C429
1U_0402_6.3V6K

C430
1U_0402_6.3V6K

C444
1U_0402_6.3V6K

C445
1U_0402_6.3V6K

DDRB_CKE0_DIMMB

6 DDRB_CKE0_DIMMB

DDR_B_BS2

6 DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

+1.5V

DDR_B_MA8
DDR_B_MA5

C449
10U_0603_6.3V6M

C450
10U_0603_6.3V6M

C425
10U_0603_6.3V6M

C424
10U_0603_6.3V6M

DDR_B_MA3
DDR_B_MA1

SB_CLK_DDR0
SB_CLK_DDR#0

6 SB_CLK_DDR0
6 SB_CLK_DDR#0

DDR_B_MA10
DDR_B_BS0

6 DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

6 DDR_B_WE#
6 DDR_B_CAS#

<BOM Structure>
+1.5V

6 DDRB_CS1_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B0_DM5
DDR_B_D42
DDR_B_D43

+0.75VS

C428
1U_0402_6.3V6K

DDR_B_D48
DDR_B_D49

C439
1U_0402_6.3V6K

C427
1U_0402_6.3V6K

C440
1U_0402_6.3V6K

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

+3VS

DDR_B0_DM7

2
1

1 R347
1 R317
1 R348

+3VS

+0.75VS

R345
10K_0402_5%

0_0402_5% 2
0_0402_5% 2
0_0402_5% 2

DDR_B0_DM0
DDR_B0_DM1
DDR_B0_DM2
DDR_B0_DM3
DDR_B0_DM4
DDR_B0_DM5
DDR_B0_DM6
DDR_B0_DM7

C436
2.2U_0603_6.3V6K

1 R349
1 R322
1 R321
1 R338
1 R323

DDR_B_D58
DDR_B_D59

C435
0.1U_0402_16V4Z

0_0402_5% 2
0_0402_5% 2
0_0402_5% 2
0_0402_5% 2
0_0402_5% 2

R344
10K_0402_5%

Layout Note:
Place near JDIMM2.203,204

205

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

G1
G2
FOX_AS0A626-U4RN-7F
CONN@

206

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13
DDR_B0_DM1
DDR3_DRAMRST#

DIMM_DRAMRST# 6,11

DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21

DDR_B0_DM2
DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDRB_CKE1_DIMMB

DDRB_CKE1_DIMMB 6

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
C

DDR_B_MA2
DDR_B_MA0
SB_CLK_DDR1
SB_CLK_DDR#1
DDR_B_BS1
DDR_B_RAS#

DDRB_CS0_DIMMB#
SB_ODT0
SB_ODT1

SB_CLK_DDR1 6
SB_CLK_DDR#1 6

+1.5V

DDR_B_BS1 6
DDR_B_RAS# 6

DDRB_CS0_DIMMB# 6
SB_ODT0 6

R351
1K_0402_5%

SB_ODT1 6

+VREF_CC

DDR_B_D36
DDR_B_D37

DDR_B0_DM4
DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

C446
0.1U_0402_16V4Z

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_B_D4
DDR_B_D5

C451
2.2U_0603_6.3V6K

C359
330U_D2_2V_Y

C426
10U_0603_6.3V6M

C447
10U_0603_6.3V6M

C448
10U_0603_6.3V6M

DDR_B_MA13
DDRB_CS1_DIMMB#

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_B_D2
DDR_B_D3

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

1
Q47

3
BSS138_NL_SOT23-3

DDR_B0_DM0

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

R340
1K_0402_5%

DDR_B_D0
DDR_B_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

R350
1K_0402_5%

C437
0.1U_0402_16V4Z

+V_DDR_REFC

C438
2.2U_0603_6.3V6K

7 SB_DIMM_VREFDQ

@ R346
0_0402_5%
1
2

+1.5V

JDIMM2

R341
1K_0402_5%

M3 support

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
B

DDR_B0_DM6
DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK

D_CK_SDATA 11,14
D_CK_SCLK 11,14

+0.75VS

<Address(SA1,SA0): 10>

DIMM_2 Reserve H:4mm

Compal Secret Data

Security Classification

Issued Date

2010/10/15

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Title

Compal Electronics, Inc.


DDRIII DIMMB

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

1
Wednesday, October
27, 2010

Sheet

12

of

61

PCH_RTCX1

+RTCVCC

+RTCBATT

OSC

OSC

NC

C682

NC

32.768KHZ_12.5PF_Q13MC14610002

Y3

18P_0402_50V8J

PCH_RTCX2

2
10M_0402_5%

C686
18P_0402_50V8J

1
R568

JBATT2

2 1M_0402_5%

SM_INTRUDER#

2 330K_0402_5%

PCH_INTVRMEN

CONN@

R567 1
R585 1

SUYIN_060003HA002G202ZL

INTVRMEN

Integrated VRM enable


* HLIntegrated
VRM disable

20101019 add

(INTVRMEN should always be pull high.)

RTCRST close RAM door


+3VS

C356
1U_0603_10V6K

PCH_SRTCRST#

J8
0_0603_5%
@

HDA_SYNC_PCH

42

HDA_SDIN0

N34

L34

PCH_SPKR

T10
HDA_RST_PCH#

HDA_SYNC_PCH

On Die PLL VR Select is supplied by


1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom

K34

E34
G34

Prevent back drive issue.

C34

A34

C36

N32

R674
51_0402_5%
1
2

2
@
R540
0_0402_5%

R03 modify

PCH_JTAG_TDI

+3VALW_PCH

R792
1M_0402_5%

+3VALW_PCH

LPC

HDA_SYNC

SPKR

HDA_SDIN0

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3
HDA_SDO

HDA_DOCK_EN# / GPIO33

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

PCH_JTAG_TDO

J3

H7
K5

H1

JTAG_TCK

JTAG_TMS
JTAG_TDI

AD7
AD5
AH5
AH4

1
R681
PCH_SPI_CS0#_1
1
R651

PCH_JTAG_TDI

2
0_0402_5%
PCH_SPI_CS0#
2
0_0402_5%

PCH_SPI_MISO_1

1
R684
1
R652

2PCH_SPI_MISO
0_0402_5%
2
0_0402_5%

Y14

V4
U3

SATA_PRX_DTX_N0 34
SATA_PRX_DTX_P0 34
SATA_PTX_DRX_N0 34
SATA_PTX_DRX_P0 34

HDD

SATA_PRX_DTX_N2 34
SATA_PRX_DTX_P2 34
SATA_PTX_DRX_N2 34
SATA_PTX_DRX_P2 34

ODD

Y11

SATAICOMPO

R260
37.4_0402_1%
1
2

31

D13

+3VS

JBATT1

1 10K_0402_5%

R624 1

2 4.7K_0402_5%

R02 modify

SATA_COMP

Y10

SATAICOMPI

AB12

R241
49.9_0402_1%
1
2

SATA3_COMP

AB13

R259
10K_0402_5%

+1.05VS_PCH
SGEN#

R258
10K_0402_5%
@

+1.05VS_PCH

SPI_CLK

GPIO21
1

AH1

SATA3RBIAS

R625

2
750_0402_1%

SGEN#

Switchable GPU
*Non-Switchable

SPI_CS0#
SPI_CS1#

<BOM Structure>
PCH_SATALED#

PCH_SATALED#

SATALED#

SPI_MOSI

SATA0GP / GPIO21

SPI_MISO

SATA1GP / GPIO19

P3

41

R654 1

R667 1

PCH_SPI_CS0#_1
SPI_WP1#
2 3.3K_0402_5% SPI_HOLD1#

2 3.3K_0402_5%

V14

PCH_GPIO19

P1

U36

1
3
7
4

Boot BIOS Strap


Boot BIOS
GPIO51 GPIO19
LPC
0
0
0
Reserved
1
1
0
1
1
* SPI

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

PCH_SPI_CLK_1
PCH_SPI_MOSI_1
PCH_SPI_MISO_1

EN25F32-100HIP SOP 8P
SA00003IN00
SPI
ROM FOR ME (4MB)

20mil

0
1

SGEN#

+3VS

2
R375
1K_0402_5%
+RTCBATT_R

R640

+3VS

Y3
Y1
AB3
AB1

+RTCBATT

+CHGRTC

PCH_SATALED#

40

COUGARPOINT_FCBGA989~D
+RTCBATT

1 10K_0402_5%

RBIAS_SATA3

T3

T1

R648
100_0402_1%

Y7
Y5
AD3
AD1

JTAG_TDO

PCH_SPI_MOSI

PCH_SPI_MOSI_1

R275

AB8
AB10
AF3
AF1

SATA3COMPI
PCH_SPI_CLK_1

SERIRQ

AM10
AM8
AP11
AP10

PCH_SPI_CLK

1
2

+3VS

40

PCH_GPIO19

SATA3RCOMPO

R646
200_0402_1%

R636
100_0402_1%

R671
100_0402_1%

SERIRQ

AM3
AM1
AP7
AP5

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SPI

PCH_JTAG_TMS

PCH_JTAG_TDO

SERIRQ

V5

HDA_DOCK_RST# / GPIO13

R637
200_0402_1%

R666
200_0402_1%

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

HDA_RST#

+3VALW_PCH

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

PCH_JTAG_TCK

PCH_JTAG_TMS

42 HDA_SDOUT_AUDIO

A36

Q36
BSS138_NL_SOT23-3
HDA_SYNC_PCH
1
D

42 HDA_RST_AUDIO#

3
S

R544
33_0402_5%
HDA_BITCLK_PCH
2

R542
HDA_SYNC_PCH_R
33_0402_5%
1
2
R545
33_0402_5% HDA_RST_PCH#
1 R555
2
33_0402_5%
HDA_SDOUT_PCH
1
2

42 HDA_SYNC_AUDIO

LPC_FRAME#

E36
K36

SERIRQ

HDA_BCLK

HDA_SDOUT_PCH

INTVRMEN

HDA_SDIN0

+3VS

42 HDA_BITCLK_AUDIO

INTRUDER#

LDRQ0#
LDRQ1# / GPIO23

PCH_SPKR

This signal has a weak internal pull-down

FWH4 / LFRAME#

SRTCRST#

SRTCRST close RAM door


42

1 1K_0402_5%

K22
C17

RTCRST#

LPC_AD0 40
LPC_AD1 40
LPC_AD2 40
LPC_AD3 40

HDA_BITCLK_PCH

+3VALW_PCH

PCH_INTVRMEN

RTCX2

LPC_AD0
C38 LPC_AD1
A38 LPC_AD2
B37 LPC_AD3
C37
LPC_FRAME#
D36

ME debug mode,this signal has a weak internal PD


Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]

R539

SM_INTRUDER#

D20

G22

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

SATA 6G

PCH_RTCRST#

RTCX1

HDA_SDO as Capella ME override (GPIO33)

C20

SATA

HDA_SDO

HDA_SDOUT_PCH

PCH_RTCX2

A20

RTC

R556
1K_0402_5%
@
1
R557
0_0402_5%
1
2

C360
1U_0603_10V6K
1
2
R248 20K_0402_1%
1
2
R243 20K_0402_1%

PCH_RTCX1

J7
0_0603_5%
@

IHDA

U33A

1
+RTCVCC

JTAG

+3VALW_PCH

40

PCH_SPKR

2 1K_0402_5%

HIGH= Enable ( No Reboot )


LOW= Disable (Default)

R294 1

Footprint 200mil

+RTCVCC

20mil

CONN@

CHN202UPT_SC70-3

C471

SUYIN_060003HA002G202ZL

0.1U_0402_16V4Z

20100416 add
5

Compal Secret Data

Security Classification

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.


PCH (1/8) SATA,HDA,SPI, LPC, XDP

Size
Document Number
Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010 1

Sheet

13

of

61

+3VALW_PCH

U33B

BG34
BJ34
AV32
AU32

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
2 0.1U_0402_10V7K PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
2 0.1U_0402_10V7K

BE34
BF34
BB32
AY32

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

BG36
BJ36
AV34
AU34

PERN3
PERP3
PETN3
PETP3

1
1

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

BF36
BE36
AY34
BB34

PERN4
PERP4
PETN4
PETP4

1
1

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5

BG37
BH37
AY36
BB36

39 PCIE_PRX_DTX_N4
39 PCIE_PRX_DTX_P4
39 PCIE_PTX_C_DRX_N4
39 PCIE_PTX_C_DRX_P4

C661
C660

46 PCIE_PRX_DTX_N5
46 PCIE_PRX_DTX_P5
46 PCIE_PTX_C_DRX_N5
46 PCIE_PTX_C_DRX_P5

C813
C814

USB3.0 Left

BJ38
BG38
AU36
AV36

+3VS

R638

1 10K_0402_5%

R273
+3VALW_PCH

1 10K_0402_5%

R618

1 10K_0402_5%

R630

1 10K_0402_5%

R653

1 10K_0402_5%

R238

1 10K_0402_5%

R293

1 10K_0402_5%

PCH_GPIO18
PCH_GPIO20

BG40
BJ40
AY40
BB40

PCH_GPIO73

BE38
BC38
AW38
AY38

PCH_GPIO25

R295

1 10K_0402_5%

PCH_GPIO26
PCH_GPIO44

Y40
Y39

PCH_GPIO45
PCH_GPIO46

PCH_GPIO73

J2
CLK_PCIE_MINI1#
CLK_PCIE_MINI1

38 CLK_PCIE_MINI1#
38 CLK_PCIE_MINI1

Mini Card 1

R650

38 MINI1_CLKREQ#

1 0_0402_5%

USB3.0

R289

V10

1 0_0402_5%

CLK_PCIE_LAN#
CLK_PCIE_LAN

35 CLK_PCIE_LAN#
35 CLK_PCIE_LAN

R621

A8

2 0_0402_5%

38 CLK_PCIE_MINI2#
38 CLK_PCIE_MINI2

Y43
Y45
R664

38 MINI2_CLKREQ#

1 0_0402_5%

46 USB30_CLKREQ#_L

R772

PCH_GPIO26

L12

CLK_PCIE_USB30_L#
CLK_PCIE_USB30_L
V45
V46
PCH_GPIO44
L14
1 0_0402_5%

46 CLK_PCIE_USB30_L#
46 CLK_PCIE_USB30_L

USB3.0 Left

Y37
Y36

PCH_GPIO25

35 LAN_CLKREQ#

Mini Card 2

AA48
AA47

PCH_GPIO20

39 USB30_CLKREQ#

PCIE LAN

M1
CLK_PCIE_USB30#
CLK_PCIE_USB30

39 CLK_PCIE_USB30#
39 CLK_PCIE_USB30

AB49
AB47

PCH_GPIO18

CLK_PEG_VGA#
CLK_PEG_VGA

22 CLK_PEG_VGA#
22 CLK_PEG_VGA

PEG_CLKREQ#_R

AB42
AB40
E6

PCH_GPIO45

V40
V42

PCH_GPIO46

V38
V37

T13

K12

AK14
AK13

PCH_SMBDATA 38

SML0ALERT# / GPIO60
SML0CLK
SML0DATA

RST_GATE
A12

RST_GATE 6,11,12

PERN5
PERP5
PETN5
PETP5

SML1CLK / GPIO58

SML1DATA / GPIO75

PERN7
PERP7
PETN7
PETP7

PERN8
PERP8
PETN8
PETP8

CL_CLK1

PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P

C13
E14

M16

CL_RST1#

P10

PCH_GPIO47
PCH_SML1CLK

CLKOUT_DMI_N
CLKOUT_DMI_P

PCH_SMBDATA

PCIECLKRQ1# / GPIO18

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P

CLKIN_DMI_N
CLKIN_DMI_P

PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P

CLKIN_DMI2_N
CLKIN_DMI2_P

PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

PCIECLKRQ4# / GPIO26

2.2K_0402_5%

R643

2.2K_0402_5%

10K_0402_5%

For DDR
R669
4.7K_0402_5%
1
2 +3VS
D_CK_SDATA

D_CK_SCLK

D_CK_SCLK 11,12

Q40B
DMN66D0LDW-7_SOT363-6

PCH_GPIO47

M10

D_CK_SDATA 11,12

R670
4.7K_0402_5%
1
2 +3VS

AB37
AB38

Pull up at EC side.
For VGA,EC

+3VS
CLK_CPU_DMI#
AV22CLK_CPU_DMI
AU22

CLK_CPU_DMI# 5
CLK_CPU_DMI 5

PCH_SML1DATA

AM12
AM13

EC_SMB_DA2

CLK_BUF_CPU_DMI#
BF18 CLK_BUF_CPU_DMI
BE18

R2331
R234
1

10K_0402_5%
2 210K_0402_5%

CLKIN_GND1#
BJ30 CLKIN_GND1
BG30

R5631

2 10K_0402_5%

R5611

2 10K_0402_5%

CLK_BUF_DREF_96M#
G24 CLK_BUF_DREF_96M
E24

R220
R2211 1

2 10K_0402_5%
2 10K_0402_5%

CLK_BUF_PCIE_SATA#
AK7 CLK_BUF_PCIE_SATA
AK5

R264
R265
1 1

10K_0402_5%
2 210K_0402_5%

R1751

2 10K_0402_5%

EC_SMB_DA2 22,40

Q38A
DMN66D0LDW-7_SOT363-6
PCH_SML1CLK

EC_SMB_CK2

EC_SMB_CK2 22,40

Q38B
DMN66D0LDW-7_SOT363-6

Pull down 10K ohm


for using internal Clock

CLK_BUF_ICH_14M

CLKOUT_PCIE5N
CLKOUT_PCIE5P

REFCLK14IN

K45
CLK_PCI_LPBACK

CLKIN_PCILOOPBACK

PCIECLKRQ5# / GPIO44

XTAL25_IN
XTAL25_OUT

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

CLK_PCI_LPBACK 17

H45
V47
V49

XTAL25_IN
XTAL25_OUT

+1.05VS_VTT

PEG_B_CLKRQ# / GPIO56

R526
90.9_0402_1%
1
2

XCLK_RCOMP

XCLK_RCOMP

Y47

XTAL25_IN

CLKOUT_PCIE6N
CLKOUT_PCIE6P

XTAL25_OUT

PCIECLKRQ6# / GPIO45
CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7# / GPIO46

CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CLKOUTFLEX0 / GPIO64

CLK_FLEX0
K43
CLK_FLEX1

CLKOUTFLEX1 / GPIO65

F47
CLK_FLEX2

CLKOUTFLEX2 / GPIO66

H47
DGPU_PRSNT#

CLKOUTFLEX3 / GPIO67

PAD

T9

T29

1
R527

R04 modify

2
1M_0402_5%
Y2

T73

PAD

25MHZ_20PF_7A25000012

PAD
+3VS

K49

C630
18P_0402_50V8J

C631
18P_0402_50V8J

DGPU_PRSNT#

Pull high @ VGA side

R160
10K_0402_5%
DIS@

0
1

CLK_PCI_LPBACK

C642
22P_0402_50V8J
1
2

R530
33_0402_5%
1
2
@

Reserve for EMI please close to@ UH4

DIS,OPTIMUS
UMA

2 2
G

PEG_CLKREQ# 22

Compal Secret Data

Security Classification
Issued Date

10K_0402_5%

2
2

R280

Q40A
DMN66D0LDW-7_SOT363-6

GPIO67

Q39
2N7002H_SOT23-3
3
R631
1
2
0_0402_5%
R644
DIS@
R668
@
2.2K_0402_5%
@
2.2K_0402_5%

1
1

PCH_SML1DATA

1
5

R642

PCH_GPIO74

PCH_SMBCLK

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

2.2K_0402_5%

R159
10K_0402_5%
UMAO@

for safe

R647

PCH_SML1CLK

M7

T11

PEG_A_CLKRQ# / GPIO47

2.2K_0402_5%

2
2

CL_DATA1

CLKOUT_PCIE0N
CLKOUT_PCIE0P

1
1

+3VS

PERN6
PERP6
PETN6
PETP6

R632
DIS@
10K_0402_5%

2
PEG_CLKREQ#_R

PCH_GPIO74

G12

DGPU_PRSNT#

10K_0402_5%

R677
R662

PCH_SML1DATA

SML1ALERT# / PCHHOT# / GPIO74

1 1K_0402_5%

C8

DGPU_PWR_EN 17,45

R663

PCH_SMBCLK
PCH_SMBDATA

COUGARPOINT_FCBGA989~D

+3VALW_PCH

R608

10K_0402_5%

USB3.0 Right

C9 PCH_SMBDATA

RST_GATE

1
1

PCH_SMBCLK 38

C663
C665

SMBDATA

EC_LID_OUT# 40

H14 PCH_SMBCLK

R240

Mini Card 2

38 PCIE_PRX_DTX_N3
38 PCIE_PRX_DTX_P3
38 PCIE_PTX_C_DRX_N3
38 PCIE_PTX_C_DRX_P3

PERN2
PERP2
PETN2
PETP2

E12 EC_LID_OUT#

SMBUS

C675
C677

Link

38 PCIE_PRX_DTX_N2
38 PCIE_PRX_DTX_P2
38 PCIE_PTX_C_DRX_N2
38 PCIE_PTX_C_DRX_P2

SMBCLK

Controller

Mini Card 1

SMBALERT# / GPIO11

FLEX CLOCKS

1
1

CLOCKS

C672
C669

EC_LID_OUT#

PERN1
PERP1
PETN1
PETP1

PCI-E*

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
2 0.1U_0402_10V7K PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
2 0.1U_0402_10V7K

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_C_DRX_N1
PCIE_PTX_C_DRX_P1

PCIE LAN

35
35
35
35

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.


PCH (2/8) PCIE, SMBUS, CLK

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010

Sheet

14

of

61

+3VS

SUS_PWR_DN_ACK_R

R607

1 10K_0402_5%

R218

1 200K_0402_5%

PCH_ACIN

R247

1 10K_0402_5%

PCH_GPIO72

R610

1 10K_0402_5%

RI#

R597

1 200_0402_1%

PM_DRAM_PWRGD

R559

1 10K_0402_5%

PCH_RSMRST#

4
4
4
4

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

4
4
4
4

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

4
4
4
4

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

4
4
4
4

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

BC24
BE20
BG18
BG20

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW 24
AW 20
BB18
AV18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

+1.05VS_PCH

BJ24
DMI_IRCOMP
2
49.9_0402_1%
RBIAS_CPY
2
750_0402_1%

1
R223
1
R578

BG25

BH21

DMI

+3VALW_PCH

FDI

U33C

DMI_ZCOMP
DMI_IRCOMP

DMI2RBIAS

not support Deep S4,S5 mux


with SUS_PWR_DN_ACK

SUS_PWR_DN_ACK_R

SUSACK#_R

2
0_0402_5%

XDP_DBRESET#_R
2
0_0402_5%

R599
5 XDP_DBRESET#

R678

SYS_PWROK
C

not support AMT APWROK can mux


with PWROK (check list1.0 P.40)

PCH_PWROK

R635

PCH_PWROK_R
0_0402_5%

C12
K3

P12

L22

L10
PM_DRAM_PWRGD

5 PM_DRAM_PWRGD

40 PCH_RSMRST#

R560

2
2

1
R673

40 PBTN_OUT#
22,40,44,45,48

1
R598

40 SUS_PWR_DN_ACK

ACIN

D9

PCH_RSMRST#_R

0_0402_5%

SUS_PWR_DN_ACK_R

0_0402_5%
PBTN_OUT#_R

2
0_0402_5%

PCH_ACIN
2
CH751H-40PT_SOD323-2

B13

System Power Management

4mil width and place


within 500mil of the PCH

SUSACK#
SYS_RESET#

SYS_PW ROK

PW ROK

APW ROK
DRAMPW ROK

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

AW 16

FDI_INT

FDI_INT
FDI_FSYNC0

AV12

FDI_FSYNC1

BC10

FDI_LSYNC0

AV14

FDI_LSYNC1

BB10

DSW VRMEN

A18

DPW ROK

E22

W AKE#

CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63

B9

N3
G8
N14
D10
H4

K16

SUSW ARN# / SUS_PW R_DN_ACK / GPIO30 SLP_S3#

F4

E20

PW RBTN#

H20

RSMRST#

ACPRESENT / GPIO31

SLP_A#

G10

SLP_SUS#

G16

E10

BATLOW # / GPIO72
RI#

PMSYNCH

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

4
4
4
4
4
4
4
4

+RTCVCC

FDI_FSYNC0
FDI_FSYNC1

FDI_LSYNC0
FDI_LSYNC1

DSWODVREN

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

R577

R581

1 330K_0402_5%

1 330K_0402_5%
@

DSWODVREN - On Die DSW VR Enable


H Enable
L Disable

DSWODVREN

not support Deep S4,S5 DPWROK mux with PWROK


check list1.0 P.42

PCH_RSMRST#_R
R615
0_0402_5%
WAKE#
1
2

PCH_PCIE_WAKE# 35,38,39,46

+3VALW_PCH

PCH_GPIO32

SUS_STAT#

T22

PAD

R613

2 10K_0402_5%

PCH_GPIO29

R235

2 10K_0402_5%

SUSCLK

+3VS

SUSCLK 40

PM_SLP_S5#

T23

PAD

T21

PAD

T20

PAD

PCH_GPIO32

R622

2 10K_0402_5%

PM_SLP_S5# 40

PM_SLP_S4#

PM_SLP_S4# 40

@
PM_SLP_S3#

PM_SLP_S3# 40

PAD

WAKE#

T47

Can be left NC
when IAMT is not
support on the
platfrom

PCH_GPIO72

A10

4
4
4
4
4
4
4
4

FDI_INT 4

SLP_S4#

C21

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

AP14

RI#

T16

H_PM_SYNC

PAD
H_PM_SYNC 5

not support
Deep S4,S5 can NC
PCH EDS1.2 P.74

@
PCH_GPIO29

SLP_LAN# / GPIO29

K14

Ring Indicator CRB1.0 PH 10K +3VALW


B

COUGARPOINT_FCBGA989~D

+3VS

5
Y

SYS_PWROK

MC74VHC1G08DFT2G_SC70-5

SYS_PWROK 5

VGATE

40,55

ALL power OK

U35
2 B

40 PCH_PWROK

tell PCH all power ok


but cpu core

R629
10K_0402_5%

R645
10K_0402_5%

Compal Secret Data

Security Classification
Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PCH (3/8) DMI,FDI,PM,

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010 1

Sheet

15

of

61

Pull high at LVDS conn side.


U33D

IGPU_BKLT_EN

IGPU_BKLT_EN

UMA@

31

PCH_ENVDD

J47
M45

31

DPST_PWM

P45

T40
K47

31 LCD_CLK
31 LCD_DATA

1
C193

0.01U_0402_16V7K

2 @

CTRL_CLK
CTRL_DATA

0.01U_0402_16V7K
C191

2 @

2.37K_0402_1%
1
2
UMA@

R189

For RF request
R177

0_0402_5%
1
2
UMA@

+3VS

R174

1 UMA@ 2 2.2K_0402_5%

CTRL_CLK

R158

1 UMA@ 2 2.2K_0402_5%

CTRL_DATA

R156

1 UMA@ 2 2.2K_0402_5%

LCD_CLK

R157

1 UMA@ 2 2.2K_0402_5%

LCD_DATA

31 TXCLK31 TXCLK+

31 TXOUT031 TXOUT131 TXOUT2-

31 TXOUT0+
31 TXOUT1+
31 TXOUT2+

31 TZCLK31 TZCLK+

31 TZOUT031 TZOUT131 TZOUT2-

+3VS

R521
R522

1 UMA@ 2 2.2K_0402_5%
1 UMA@ 2 2.2K_0402_5%

PCH_CRT_DATA

R534

1 UMA@ 2 150_0402_1%

R533

1 UMA@ 2 150_0402_1%

R535

1 UMA@ 2 150_0402_1%

LVDS_IBG

AF37
AF36

LVD_VREF

AE48
AE47

TXCLKTXCLK+

AK39
AK40

TXOUT0TXOUT1TXOUT2-

AN48
AM47
AK47
AJ48

TXOUT0+
TXOUT1+
TXOUT2+

AN47
AM49
AK49
AJ47

TZCLKTZCLK+

AF40
AF39

TZOUT0TZOUT1TZOUT2-

AH45
AH47
AF49
AF45

TZOUT0+
TZOUT1+
TZOUT2+

AH43
AH49
AF47
AF43

PCH_CRT_CLK

31 TZOUT0+
31 TZOUT1+
31 TZOUT2+

T45
P39

L_BKLTEN
L_VDD_EN

SDVO_TVCLKINN
SDVO_TVCLKINP

L_BKLTCTL

L_DDC_CLK
L_DDC_DATA

LVD_IBG
LVD_VBG

32 PCH_CRT_B
32 PCH_CRT_G
32 PCH_CRT_R

PCH_CRT_R

32 PCH_CRT_CLK
32 PCH_CRT_DATA

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

N48
P49
T49

CRT_DDC_CLK
CRT_DDC_DATA

32 PCH_CRT_HSYNC
32 PCH_CRT_VSYNC

T39
M40

M47
M49

CRT_IREF

T43
T42

AM42
AM40

SDVO_INTN
SDVO_INTP

AP39
AP40

SDVO_CTRLCLK
SDVO_CTRLDATA

LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

PCH_CRT_B
PCH_CRT_G

AP43
AP45

SDVO_STALLN
SDVO_STALLP

L_CTRL_CLK
L_CTRL_DATA

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

Digital Display Interface

1 0_0402_5%

LVDS

ENBKL

R532

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_CTRLCLK
DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_CTRLCLK
DDPD_CTRLDATA

CRT

40

ENBKL

DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

SDVO_CTRLDATA strap pull high


at level shift page
D

P38 SDVO_SCLK
M39 SDVO_SDATA

SDVO_SCLK 33
SDVO_SDATA 33

AT49
AT47
PCH_DPB_HPD
AT40

PCH_DPB_HPD 33

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

33
33
33
33
33
33
33
33

HDMI D2
HDMI D1
HDMI D0
HDMI CLK

P46
P42

AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

COUGARPOINT_FCBGA989~D

R178
1K_0402_0.5%

Compal Secret Data

Security Classification
Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PCH (4/9) LVDS,CRT,DP,HDMI

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010

Sheet

16

of

61

R166
R169
R170
R172

1
1
1
1

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

R03 modify

2 8.2K_0402_5%

PCH_GPIO55
PCH_GPIO51
PCH_GPIO5
PCH_GPIO52

PCH_GPIO2
DGPU_PWR_EN
PCH_GPIO4
ODD_DA#

B21
M20
AY16
BG46

PCH_GPIO53

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

AV5
AY1

NV_ALE
NV_CLE

TP21
TP22
TP23
TP24

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_RST#
PCH_GPIO52
DGPU_PWR_EN

GPIO51 Internal pull high


14,45 DGPU_PWR_EN

Boot BIOS Strap bit1 BBS1


Bit11 Bit10
GNT1#/
GPIO51
B

PCI

SPI

PCH_GPIO51
PCH_GPIO53
PCH_GPIO55

Boot BIOS
Destination

PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5

Reserved
34

LPC

PAD
5

14 CLK_PCI_LPBACK
40 CLK_PCI_LPC

ODD_DA#

CLK_PCI_LPBACK
CLK_PCI_LPC

C46
C44
E40

D47
E42
F46

G42
G40
C42
D44

K10
PLT_RST#

PLT_RST#

R531
R529

C633
0.01U_0402_16V7K
@ 2

T18

K40
K38
H38
G38

C6
CLK_PCI0
CLK_PCI1
1 22_0402_5%CLK_PCI2
T30
@
2 22_0402_5%
CLK_PCI3
CLK_PCI4
T10 @

2
1PAD
PAD
PAD

T12 @

H49
H43
J48
K42
H40

C632
0.01U_0402_16V7K
2 @

Set to Vss when LOW

DG 1.2 CRB1.0 PH 2.2K series 1K

AT12
BF3
+1.8VS

PIRQA#
PIRQB#
PIRQC#
PIRQD#

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4

USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

USB/B (Right side)

USB Conn. Colay USB3.0


DF_TVS

USB/B (Right side) ,colay USB3.0

2
R626

3D panel

1
1K_0402_5%

H_SNB_IVB# 5

CLOSE TO THE BRANCHING POINT

Mini Card 1 (WLAN)


+3VALW_PCH

3G/B (WWAN)
CMOS Camera (LVDS)

USB_OC0#
USB_OC2#
USB_OC7#
USB_OC5#

Mini2 Card 2 (Reserved)


3G/B(SIM Card )

R596 1
R588

2 10K_0402_5%
2 10K_0402_5%

R595
R590
1

2 10K_0402_5%
2 10K_0402_5%

R773
1
R612 1 1
R592
R616
1

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

BlueTooth

Within 500 mils


1
R558

2
22.6_0402_1%

USB_OC1#
USB_OC4#
USB_OC3#
USB_OC6#

B33
A14
K20
B17
C16
L16
A16
D14
C14

R633
2.2K_0402_5%

USB/B (Right side)

USB20_N8 38
USB20_P8 38
USB20_N9 38
USB20_P9 38
USB20_N10 31
USB20_P10 31
USB20_N11 38
USB20_P11 38
USB20_N12 38
USB20_P12 38
USB20_N13 39
USB20_P13 39

C33

PME#

PLTRST#

39
39
46
46
39
39
39
39
31
31

Some PCH config not support USB port 6 & 7.


USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12
USB20_N13
USB20_P13
USBRBIAS

USBRBIAS#

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4

R03 modify

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB_OC1# 46

COUGARPOINT_FCBGA989~D

R282
0_0402_5%
1
2
@
+3VS

For RF request

5
PLT_RST#

PLTRST_VGA# 22

2
R281
100K_0402_5%
DIS@

DIS@

IN1

IN2

MC74VHC1G08DFT2G_SC70-5

U15

OUT

PLT_RST_BUF# 35,38,39,40,46

R297
100K_0402_5%

R187
1 A
1
2
0_0402_5% DIS@
NC7SZ08P5X_NL_SC70-5

R296
100_0402_1%
1
2
DIS@

U14

PLT_RST#

+3VS

DGPU_HOLD_RST#

Set to Vcc when HIGH

DF_TVS

AY5
BA2

NV_WE#_CK0
NV_WE#_CK1

USB

DMI Termination Voltage

AT8

NV_RE#_WRB0
NV_RE#_WRB1

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

PCI

2 8.2K_0402_5%

DGPU_HOLD_RST#

DF_TVS

AV10

NV_RCOMP
NV_RB#

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

2
2
2
2

AT10
BC8

NV_DQS0
NV_DQS1

1
1
1
1

AY7
AV7
AU3
BG4

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

VCC

R152
R153
R161
R162

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

GND

10K_0402_5% PCI_PIRQA#
10K_0402_5% PCI_PIRQD#
10K_0402_5% PCI_PIRQC#
10K_0402_5% PCI_PIRQB#

2
2
2
2

NVRAM

1
1
1
1

RSVD

R173
R180
R181
R183

R188

U33E

+3VS

R165

Compal Secret Data

Security Classification

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PCH (5/9) PCI, USB, NVRAM

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010 1

Sheet

17

of

61

HDA_SYNC PH(PLL =+1.5VS)

GPIO28

On-Die PLL Voltage Regulator


This signal has a weak internal pull up

H
L

voltage regulator enable


On-Die
On-Die PLL Voltage Regulator disable
R272

2 1K_0402_5% PCH_GPIO28

+3VS

@
ODD_EN#
D

+3VALW_PCH

R768

2 4.7K_0402_5%

R771

EC_KBRST#

2 10K_0402_5%

R279

2 10K_0402_5%

U33F

T7

PCH_GPIO1

A42

DGPU_HPD_INT#

E38

EC_SMI#

C10

PCH_GPIO12

1 NOPT@ 2 10K_0402_5%

R639

1 OPT@

OPTIMUS_EN#

38,39

BT_ON#

P8

BT_ON#

K1

K4

2 10K_0402_5%
34 ODD_DETECT#

R03 modify

38 WWAN_OFF#

ODD_DETECT#

V8

WWAN_OFF#

M5

OPTIMUS_EN#

N2

GPIO38

PCH_GPIO39

M3

OPTIMUS_EN#

OPTIMUS
Non-OPTIMUS

PCH_GPIO48

V13

0
1

R03 modify

38

WL_OFF#

WL_OFF#

V3
PCH_GPIO57

D6

+3VS

R04 modify
WWAN_OFF#

R277
R276
B

1
1

2 200K_0402_5%
PCH_GPIO0
2 10K_0402_5%

R546

2 10K_0402_5%

R191

2 10K_0402_5%

R641

2 10K_0402_5%

R194

2 10K_0402_5%

R290

R649

2 10K_0402_5%

2 10K_0402_5%

DGPU_HPD_INT#

PCH_GPIO22

R291

2 200K_0402_5%

BT_ON#

R619

2 10K_0402_5%

R292

2 10K_0402_5%

R274

2 10K_0402_5%

AH10

SATA2GP / GPIO36

NC_4
SATA3GP / GPIO37

NC_5

P37

VSS_NCTF_15

VSS_NCTF_16

GPIO57

VSS_NCTF_17

BH3

VSS_NCTF_18

BH47

@
BG48

PAD

T44

A45

VSS_NCTF_3

T52

@
@

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

VSS_NCTF_22

BJ46

VSS_NCTF_23

BJ5 @

VSS_NCTF_24

BJ6
C2

B3

VSS_NCTF_7

VSS_NCTF_25

B47

VSS_NCTF_8

VSS_NCTF_26

C48

BD1

VSS_NCTF_9

VSS_NCTF_27

D1

T36

VSS_NCTF_10

VSS_NCTF_28

D49

BE1

VSS_NCTF_11

VSS_NCTF_29

E1

VSS_NCTF_30

E49

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

R554
10K_0402_5%

PAD
PAD

@
PCH_GPIO69

T42
PAD
T50
PAD

T65

PAD

T38

PAD

T63

PAD

T32

PAD

T54

PAD

Project ID
* P5WE0
P7YE0
x
x

T33

PAD

T53
@

+3VS

R550
10K_0402_5%

R548
10K_0402_5%

X76@

@
PCH_GPIO70

PCH_GPIO71

R549
10K_0402_5%

R553
10K_0402_5%

PAD

F1
F49

PAD

BD49

T43

T49

+3VS

PAD

T60

VSS_NCTF_12

R02 modify
+3VS

T45

@
BJ45 @

T37

BF1

PAD

T64

BE49

T59

T40

PAD

PAD

PAD

T56

PAD

T39

@
BJ44

VSS_NCTF_21

T58

BG2

SDATAOUT1 / GPIO48
SATA5GP / GPIO49

VSS_NCTF_20

T51

SDATAOUT0 / GPIO39

VSS_NCTF_19

PAD

Checklist1.0 P.59

SLOAD / GPIO38

VSS_NCTF_2

PAD

130 degree
shut sown

TS_VSS1~4
PD to GND

AK10

VSS_NCTF_1

BF49

WL_OFF#

AK11

NC_3

A44

PAD

PCH_GPIO48

NC_2
GPIO35

PAD T35
@
PAD T57
@

ODD_DETECT#

NC_1
STP_PCI# / GPIO34

T46

A46

H_THRMTRIP# 5

This signal has weak internal


PU, can't pull low,leave NC

AH8

PAD

PAD

R04 modify

GPIO28

BJ4

PAD T55
@
PAD T34
@
PCH_GPIO39

INIT3_3V

A4

non CPU power ok

H_CPUPWRGD 5
H_THRMTRIP#
2
390_0402_5%

GPIO27

T41

CTRL+ALT+DEL

EC_KBRST# 40

T14

T61

PCH_GPIO16
DGPU_PWROK

INIT3_3V#

PAD

PAD

PCH_GPIO1

THRMTRIP#

GPIO24 / MEM_LED

AY11
PCH_THRMTRIP#_R
1
AY10
R627

PECI CPU-EC

5,40

E16

PCH_GPIO28

SCLOCK / GPIO22

PROCPWRGD

H_PECI

T31

PAD

PCH_GPIO27

+3VS

TACH0 / GPIO17

RCIN#

GATEA20 40

P4
PCH_PECI_R
1
2
AU16
0_0402_5% @ R239
EC_KBRST#
P5

E8

SATA4GP / GPIO16

PECI

R551
10K_0402_5%X76@

T5

PCH_GPIO24

R623

D40

A20GATE

DGPU_PWROK

GPIO15

U2

PCH_GPIO22

LAN_PHY_PWR_CTRL / GPIO12

2 0_0402_5%

R278
10K_0402_5%

GPIO8

R193

TACH3 / GPIO7

+3VS

PCH_GPIO70
PCH_GPIO71

1
G2

PCH_GPIO16

54 VGA_PWROK

TACH7 / GPIO71

A40

PCH_GPIO27

SMIB

C41

SMIB

TACH6 / GPIO70

39,46

C4

TACH2 / GPIO6

ODD_EN# 34

PCH_GPIO69

B41

EC_SMI#

H36

CPU/MISC

2 10K_0402_5%

40

EC_SCI#

TACH5 / GPIO69

GPIO

R661

EC_SCI#

TACH4 / GPIO68

TACH1 / GPIO1

NCTF

Deep S4,S5 wake event signal


RTC alarm,Power BTN,GPIO27
PCH_GPIO27 (Have internal Pull-High)
Deep S4,S5 wake event signal
No use PD to GND Check list1.0 P.70

40

ODD_EN#

C40

BMBUSY# / GPIO0

PCH_GPIO0

GPIO69 GPIO70
0
0
0
0
1
0
1
1

GPIO71
PCH_GPIO71

*VRAM 800 MHz


VRAM 900 MHz

0
1

PAD

COUGARPOINT_FCBGA989~D

GPIO24 Unmultiplexed
NOTE: GPIO24 configuration
register bits are not cleared by
CF9h reset event.

+3VALW_PCH

R262

2 10K_0402_5%

R620

2 10K_0402_5%

R672

2 1K_0402_5%

PCH_GPIO24
PCH_GPIO12

CRB1.0 PH10K to +3VALW


A

SMIB
PCH_GPIO57

R263

2 10K_0402_5%

Compal Secret Data

Security Classification
Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PCH (6/9) GPIO, CPU, MISC

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010

Sheet

18

of

61

+VCCADAC should be powered up during S0


system state.Note that Thermal Sensor
shares the same power supply rail with DAC

AN19

PAD

+VCCAPLLEXP

T48 @

BJ22

On-Die PLL voltage regulator enable

AN17
AN21

+1.05VS_PCH

AP24

AT24

+3VS

T19 @

VCCIO[22]
VCCIO[23]

VCCIO[24]

VCCIO[25]
VCCIO[26]

+1.05VS_VCCAPLL_FDI

BG6

+1.05VS_PCH

AP17

AU20

1
1

1
1
C300
22U_0805_6.3V6M
C310
C305
UMA@
0.01U_0402_16V7K
0.01U_0402_16V7K
2
2 UMA@
2 UMA@

+3VS

V33

0.1uH inductor, 200mA

R210
DISO@
0_0402_5%

C313
0.1U_0402_10V7K

Internal PLL and VRM(+1.5VS)

+VCCAFDI_VRM

S0 Iccmax
Current(A)

1.05

0.001

Processor I/F

V5REF

0.001

PCH Core Well Reference Voltage

V5REF_Sus

0.001

Suspend Well Reference Voltag

Vcc3_3

3.3

0.266

I/O Buffer Voltage

VccADAC

3.3

0.001

Display DAC Analog Power. This power is


supplied by the core well.

VccADPLLA

1.05

0.08

Display PLL A power

V_PROC_IO

VCCDMI[1]

20mA
VCCIO[1]

AT20

VCCVRM[2]

AB36

VCCFDIPLL

VCCPNAND[1]

AG16

VCCPNAND[2]

AG17

VCCPNAND[3]

DMI buffer logic

C344
1U_0402_6.3V6K

place near AT20

C308
1U_0402_6.3V6K

Core Well I/O Buffer

place near AB36

+1.8VS

1
AJ16

VccDFTERM should PH +1.8VS or +3VS


C349
0.1U_0402_10V7K

AJ17

+3VS

VCCIO[27]

VCCDMI[2]

VccADPLLB

1.05

0.08

Display PLL B power

VccCore

1.05

1.3

Internal Logic Voltage

VccDMI

1.05

0.042

DMI Buffer Voltage

VccIO

1.05

2.925

Core Well I/O buffers

VccASW

1.05

1.01

1.05 V Supply for Intel R Management


Engine and Integrated LAN

VccSPI

3.3

0.02

3.3 V Supply for SPI Controller Logic

VccDSW

3.3

0.003

3.3v supply for Deep S4/S5 well

VccpNAND

1.8

0.19

1.8V power supply for DF_TVS

VccRTC

3.3

6 uA

Battery Voltage

VccSus3_3

3.3

0.266

Suspend Well I/O Buffer Voltage

2
VCCPNAND[4]

20mA

VCCSPI

V1

For SPI control logi

C703
1U_0402_6.3V6K

On-Die PLL voltage regulator enable

On-Die PLL Voltage Regulator

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2

PCH Power Rail Table


Voltage Rail Voltage

GPIO28
H

I/O Buffer Voltage

V34

AT16

+1.8VS

+VCCTX_LVDS

1
VCC3_3[7]

1
C615
@ 22U_0805_6.3V6M

AP36
AP37

1
C276
22U_0805_6.3V6M

+3VS

CRT
LVDS

22U_0805_6.3V6M

L16 UMA@
0.1UH_MLF1608DR10KT_10%_1608
1
2

AM38

C347
COUGARPOINT_FCBGA989~D
2 1U_0402_6.3V6K

R176
0_0402_5%
DISO@

190mA

VCC3_3[3]

Trace 20mil
1

R149
0.022_0805_1%
1
2
UMA@

VCCIO[21]

AN34

AP16

VCC3_3[6]

C629

+1.05VS_PCH

FDI

PAD

+VCCAFDI_VRM

VCCTX_LVDS[3]

VCCVRM[3]

C322
0.1U_0402_10V7K

VCCTX_LVDS[2]

VCCIO[20]

AN33

BH29
1

2925mA
VCCIO[19]

AP26

VCCTX_LVDS[1]

AK37
AM37

VCCIO[17]

VCCIO[18]

C332
1U_0402_6.3V6K

C342
1U_0402_6.3V6K

C325
1U_0402_6.3V6K

C353
1U_0402_6.3V6K

C314
10U_0805_10V4Z

VCCIO[16]

1
R523
0_0402_5%
2
@

AK36 +VCCA_LVDS

266mA

VCCIO[15]

AN27

AP23

U47

VCCIO[28]
VCCAPLLEXP

AN26

AP21

VSSALVDS

NAND / SPI

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

VCCALVDS

1mA

VCCTX_LVDS[4]

VCCIO

AN16

2
VSSADAC

60mA

On-Die PLL Voltage Regulator


H

VCCADAC

U48

+1.05VS_PCH

1mA

HVCMOS

DMI

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

VCC CORE

C320
1U_0402_6.3V6K

C319
1U_0402_6.3V6K

C346
1U_0402_6.3V6K

C334
10U_0805_10V4Z

PAD-OPEN 4x4m 1

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

C644
0.1U_0402_10V7K

+1.05VS_PCH

C777
0.1U_0402_10V7K

1300mA

C640
0.01U_0402_16V7K

POWER

U33G

J3

+1.05VS_VTT

+3VS

L31
MBK1608221YZF_2P
1
2

+VCCADAC

+VCCAFDI_VRM

VccSusHDA

3.3 / 1.5 0.01

VccVRM

1.8 / 1.5 0.16

+1.5VS

R257

0_0603_5%

High Definition Audio Controller Suspend


Voltage
1.8 V Internal PLL and VRMs (1.8 V for
Desktop)

+VCCAFDI_VRM

VCCVRM==>1.5V FOR MOBILE


VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

HDA_SYNC PH(PLL =+1.5VS)

VccCLKDMI

1.05

0.02

DMI Clock Buffer Voltage

VccSSC

1.05

0.095

Spread Modulators Power Supply

VccDIFFCLKN

1.05

0.055

Differential Clock Buffers Power Supply

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

Analog power supply for LVDS (Mobile


Only)
Analog power supply for LVDS (Mobile
Only)

Compal Secret Data

Security Classification
Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PCH (7/9) PWR

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010

Sheet

19

of

61

Have internal VRM

+3VS_VCC_CLKF33

suppied by internal
1.05V VR must NC
PAD

GPIO28

On-Die PLL voltage regulator enable

T38

+VCCAPLL_CPY_PCH

T11 @

BH23
AL29

+1.05VS_PCH

On-Die PLL Voltage Regulator


H

V12

PAD

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

+VCCSUS1

T13 @

AL24

+1.05VS_PCH

AA24

VCCIO[32]

VCCIO[33]

VCCSUS3_3[7]

119mA

VCCAPLLDMI2

VCCSUS3_3[8]

VCCIO[14]
DCPSUS[3]

VCCASW[1]

VCCSUS3_3[9]
VCCSUS3_3[10]

AD29

AD31
W21

W23
W24

W26
W29
W31

W33

1010mA

VCCIO[34]

1mA

VCCASW[3]

VCCASW[4]

VCCASW[6]

AC31

C348
0.1U_0402_10V7K

N16
Y49

T29

+3VALW_PCH

T24

V23

C330
0.1U_0402_10V7K

Place near
2P24

V24

BD47

+1.05VS_VCCA_B_DPL

BF47

+1.05VS_PCH

VCCASW[7]
VCCASW[8]

VCCASW[9]
VCCASW[10]

VCCASW[11]
VCCASW[12]

VCCASW[13]
VCCASW[14]

+PCH_V5REF_SUS

T26

DCPSUS[4]

AN23

+VCCA_USBSUS
+3VALW_PCH

VCCSUS3_3[1]

AN24

1mA

V5REF

VCCSUS3_3[2]

P34

N20

VCCSUS3_3[3]

N22

VCCSUS3_3[4]

P20

VCCSUS3_3[5]

PAD
suppied
by internal
1.05V VR Must NC

VCC3_3[1]

VCC3_3[8]
VCC3_3[4]

+3V_VCCPSUS

C352
1U_0402_6.3V6K

1
+3VS

P22

VCCASW[19]

VCC3_3[2]

VCCASW[20]

W16

C704

0.1U_0402_10V7K
Place
near
AJ2
2

T34

C343

0.1U_0402_10V7K
Place
near
AA16,W16
2

AG33
+VCCSST

suppied by internal
1.05V VR Must NC

PAD

V16

2 C354
0.1U_0402_10V7K
+1.05VM_VCCSUS

T17
V19

T15 @

+1.05VS_PCH

BJ8

VCCVRM[4]

VCCIO[13]

VCCADPLLA
VCCADPLLB

80mA
80mA

VCCIO[6]

VCCAPLLSATA
VCCVRM[1]

VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[11]

55mA

VCCIO[2]

VCCIO[10]

VCCIO[4]

95mA

+1.05VS_PCH

AJ2
AF13

AH13

C350
1U_0402_6.3V6K

AH14

A22

C687
0.1U_0402_10V7K

C685
0.1U_0402_10V7K

AK1
AF11

+VCCSATAPLL

@ T62

On-Die PLL voltage regulator enable

On-Die PLL Voltage Regulator

PAD

+VCCAFDI_VRM

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

+VCCAFDI_VRM

+1.05VS_PCH

AC16

AC17

C351
1U_0402_6.3V6K

AD17

+1.05VS_PCH

DCPSST
+VCCME_22

DCPSUS[1]
DCPSUS[2]

1mA
V_PROC_IO

VCCASW[22]

VCCRTC

T21

R237

1 0_0603_5%

+VCCME_23

VCCASW[23]

V21

R224
+VCCME_21

VCCASW[21]

10mAVCCSUSHDA

R236

T19

1 0_0603_5%

1 0_0603_5%

+3VALW_PCH

P32

+VCCSUSHDA

COUGARPOINT_FCBGA989~D

R206

1 0_0603_5%

Need +3VALW and 0.1U close PCH


A

C315

Close
P32
0.1U_0402_16V4Z
2

Compal Secret Data

Security Classification
Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

GPIO28

AF14

+RTCVCC

C331
1U_0402_6.3V6K

Place
near BJ8

C693
0.1U_0402_10V7K

C694
0.1U_0402_10V7K

C700
4.7U_0603_6.3V6K

C309

0.1U_0402_10V7K
Place
near
T34
2

DCPRTC

VCCIO[3]

Place
near AF33,
AF34,AG34

C244
1U_0603_10V6K

AA16

VCCASW[18]

MISC

Place
2 near AG33

+PCH_V5REF_RUN

D7
CH751H-40PT_SOD323-2

R148
100_0402_1%

VCCASW[17]

HDA

Place
near AF17

+3VS

+3VALW_PCH

+PCH_V5REF_RUN

VCCASW[16]

CPU

1 C317
1 C312
1U_0402_6.3V6K
1U_0402_6.3V6K

C318
0.1U_0603_25V7K

@ T14

+5VS

VCCASW[15]

RTC

1 C311
1U_0402_6.3V6K

AF17
AF33
AF34
AG34

D8
CH751H-40PT_SOD323-2

SATA

+1.05VS_VCCA_A_DPL

+3VALW_PCH

R202
100_0402_1%

P24

+5VALW_PCH

C333
0.1U_0402_10V7K

Place near

2P24

+PCH_V5REF_SUS

VCCIO[12]

+VCCAFDI_VRM

T23

M26

V5REF_SUS

VCCIO[5]
+VCCRTCEXT

C321
1U_0402_6.3V6K

T27

VCCASW[2]

VCCASW[5]

AC29

P28

+1.05VS_PCH

AA29

AC27

P26

VCC3_3[5]

AA27

AA31

C316
1U_0402_6.3V6K

C327
1U_0402_6.3V6K

C326
1U_0402_6.3V6K

C295
1U_0402_6.3V6K

SGA00001700
220U 2.5V M B2
ESR 35mohm@100Khz

AA26

AC26

+1.05VS_VCCA_B_DPL

C278
220U_B2_2.5VM_R35

L11
10UH_LB2012T100MR_20%

C335
22U_0805_6.3V6M

C296
1U_0402_6.3V6K

C279
220U_B2_2.5VM_R35

+1.05VS_VCCA_A_DPL

AA21

C336
22U_0805_6.3V6M

L12
10UH_LB2012T100MR_20%
1
2

DCPSUSBYP

VCCIO[31]

3mA

VCCSUS3_3[6]
AA19

+1.05VS_PCH

VCCIO[30]

+PCH_VCCDSW

T17 @

VCCIO[29]

VCCDSW3_3

PAD

VCCACLK

T16

N26

C340
0.1U_0402_10V7K

VCCDMI = 42mA detal waiting for newest spec

+1.05VS_PCH

AD49

Not support Deep S4,S5


connect to +3VALW

POWER

U33J

VCC3_3 = 266mA detal waiting for newest spec

+3VALW_PCH

C304
1U_0402_6.3V6K

C277
10U_0805_10V4Z

2
D

USB

+3VS_VCC_CLKF33

+VCCACLK

R167
0_0603_5%
1
2

+1.05VS_PCH

+1.05V analog
internal clock PLL
Can NC

PCI/GPIO/LPC

R150
0_0805_5%
2
@
L14
10UH_LB2012T100MR_20%
1
2

Clock and Miscellaneous

+3VS

Title

Compal Electronics, Inc.


PCH (8/9) PWR

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010

Sheet

20

of

61

U33I

U33H

H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
COUGARPOINT_FCBGA989~D

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19

H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

COUGARPOINT_FCBGA989~D

Compal Secret Data

Security Classification

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PCH (9/9) VSS

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Sheet

Wednesday, October 27, 2010


1

21

of

61

U27A

2
R67

under GPU

XTALIN
XTALOUT

AE9

PLLVDD

AF9

SP_PLLVDD

AD9

VID_PLLVDD

B1
XTAL_OUTBUFF B2
XTAL_SSIN
D1
D2

XTAL_IN
XTAL_OUT

MIOBCAL_PD_VDDQ_NC
MIOBCAL_PU_GND_NC

AA7
AA6

For RF request

@
C197
0.01U_0402_16V7K

I2CS_SCL

EC_SMB_CK2 14,40

CRT

@
C195
0.01U_0402_16V7K

I2CB_SCL
I2CB_SDA

VGA_DDC_CLK
VGA_DDC_DATA
I2CH_SCL
I2CH_SDA

2
OSC_OUT

E3
E4

I2CC_SCL
I2CC_SDA

G3
G2
G1
G4

F6
G6

DACB_RED
DACB_GREEN
DACB_BLUE

DACB_HSYNC
DACB_VSYNC

DACB_VDD
DACB_VREF
DACB_RSET

I2CH_SCL
I2CH_SDA

N/A

GPIO4

OUT

N/A

GPIO5

OUT GPU Core VID0

5
P
G

DIS@

ACIN

GPIO6

OUT GPU Core VID1

15,40,44,45,48

NC7SZ08P5X_NL_SC70-5

GPIO7

OUT

GPIO8

IN

OVERT

GPIO9

OUT

ALERT

GPIO10

OUT

N/A

GPIO11

OUT

GPIO12

IN

GPIO13

OUT

N/A

GPIO14

OUT

N/A

N/A

N/A
PWR_LEVEL

XTALIN

XTALOUT

@
R474
2

1M_0402_5%
1

Y1 DIS@
1
27MHZ_16PF_X5H027000FG1H
1
2

DIS@ C577
18P_0402_50V8J

OSC_OUT

XTAL_OUTBUFF
22_0402_5%

R477 1

VSS

REFOUT

MODOUT

XOUT

XIN/CLKIN

VDD

R455
10K_0402_5%
DIS@

OSC_SPREAD

+3VSDGPU

OSC_SPREAD

@ ASM3P2872AF-06OR_TSOT-23-6

2 10K_0402_5%

R476 1

XTAL_SSIN

2 22_0402_5%

@
C581
0.1U_0402_16V4Z

If External Spread Spectrum not stuff then stuff resistor

R454
10K_0402_5%
DIS@

+DACA_VDD

AJ12
AK12
AK13
AK4
AL4
AJ4

AM1
AM2
R466 2
AG7
1
AK6 @ R467
@ C154
AH7

DIS@

1 10K_0402_5%

2 124_0402_1%
0.1U_0402_16V4Z
2

DMN66D0LDW-7_SOT363-6
+3VSDGPU
Q31A DIS@

I2CB_SCL
I2CB_SDA
I2CA_SCL
I2CA_SDA

2 10K_0402_5%

R462 1 DIS@

AM13
AL13

DACA_VDD
DACA_VREF
DACA_RSET

I2C
DACs

VGA_LCD_CLK
VGA_LCD_DATA

+3VSDGPU

I2CS_SCL
I2CS_SDA

AM15
AM14
AL14

DACA_RED
DACA_GREEN
DACA_BLUE
DACA_HSYNC
DACA_VSYNC

E2
E1

GPIO

MIOACAL_PD_VDDQ_NC
MIOACAL_PU_GND_NC

I2CS_SCL
I2CS_SDA

N/A

OUT

U29

2 10K_0402_5%

R458 1 DIS@

U5
T5

XTAL_OUTBUFF
XTAL_SSIN

External Spread Spectrum

2 10K_0402_5%

T4
W4

MIOA_CLKOUT_NC_N
MIOB_CLKOUT_NC_N

CLK

DIS@ C184
0.1U_0402_16V4Z

DIS@ C186
0.1U_0402_16V4Z

DIS@ C180
0.1U_0402_16V4Z

DIS@ C146
0.1U_0402_16V4Z

R465 1 DIS@

AE1
V4

MIOB_CLKIN_NC
MIOB_CLKOUT_NC
PEX_RST_N
PEX_TERMP

R479 1 DIS@

+GPU_PLLVDD

@ C187
4700P_0402_25V7K

150mA
FBMA-L10-160808-300LMT 0603
DIS@
1
2
1
L9
1
DIS@ C190
10U_0603_6.3V6M

DIS@ C189
22U_0805_6.3V6M

+1.05VSDGPU

AM16
1
DIS@ 2.49K_0402_1% AG21

OUT

GPIO3

R44
17 PLTRST_VGA#

GPIO2

N/A

HPD_IFPC

N2
P5
N5

N4
R4

MIOA_CLKIN_NC
MIOA_CLKOUT_NC

U42

DIS@ C576
18P_0402_50V8J

Y5
W3
AF1

MIOB_DE_NC
MIOB_CTL3_NC
MIOB_VREF_NC

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

IN

MIOA_DE_NC
MIOA_CTL3_NC
MIOA_VREF_NC

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

IN

GPIO1

AJ17
1
AJ18
200_0402_1%

W1
W2

MIOB_HSYNC_NC
MIOB_VSYNC_NC

GPIO0

USAGE

AR16
AR17
AR13

MIOA_HSYNC_NC
MIOA_VSYNC_NC

I/O

1
2
OPT@ R113
10K_0402_5%

14 CLK_PEG_VGA
14 CLK_PEG_VGA#

2
10K_0402_5%

R418

MIOB_D0_NC
MIOB_D1_NC
MIOB_D2_NC
MIOB_D3_NC
MIOB_D4_NC
MIOB_D5_NC
MIOB_D6_NC
MIOB_D7_NC
MIOB_D8_NC
MIOB_D9_NC
MIOBD_10_NC
MIOB_D11_NC
MIOB_D12_NC
MIOB_D13_NC
MIOB_D14_NC

GPIO

+3VSDGPU

DIS@ C124
0.1U_0402_16V4Z

1 DIS@

+3VSDGPU
14 PEG_CLKREQ#

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

MIOA_D0_NC
MIOA_D1_NC
MIOA_D2_NC
MIOA_D3_NC
MIOA_D4_NC
MIOA_D5_NC
MIOA_D6_NC
MIOA_D7_NC
MIOA_D8_NC
MIOA_D9_NC
MIOA_D10_NC
MIOA_D11_NC
MIOA_D12_NC
MIOA_D13_NC
MIOA_D14_NC

K1
R808 2 DIS@ 1 10K_0402_5%
K2
K3
H3
H2
GPU_VID0
H1
GPU_VID0 54
GPU_VID1
H4
GPU_VID1 54
H5
R78 2 DIS@ 1 10K_0402_5%
H6
+3VSDGPU
R70
DIS@
10K_0402_5%
1
2
J7
K4
K5
R74 2 DIS@ 1 10K_0402_5%
H7 VGA_ACIN
+3VSDGPU
J4
ACIN_BUF
2
1
J6
D31
CH751H-40PT_SOD323-2
L1
L2
DIS@
R03 modify
L4
M4
DIS@
L7
VGA_HDMI_DET
R118 1 10K_0402_5%
L5
2
ACIN_BUF
DIS@
K6
VGA_PNL_PWM
R117 1 10K_0402_5%
2
L6
DIS@
M6
ENVDD
R72 1 10K_0402_5%
M7
2
DIS@
VGA_BKL_EN
R115 1 10K_0402_5%
N1
2
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6
+3VSDGPU
Y1
I2CS_SCL
Y2
R495 1 DIS@ 2 2.2K_0402_5%
I2CS_SDA
Y3
I2CH_SCL
AB3
R494 1 DIS@ 2 2.2K_0402_5%
I2CH_SDA
R122
DIS@
2.2K_0402_5%
AB2
R121 1 1DIS@ 2 22.2K_0402_5%
I2CB_SCL
AB1
R120
1 DIS@ 2 2.2K_0402_5%
I2CB_SDA
AC4
R119
DIS@
2.2K_0402_5%
1
2
VGA_LCD_CLK
AC1
VGA_LCD_DATA
R502 1 DIS@ 2 2.2K_0402_5%
AC2
R497 1 DIS@ 2 2.2K_0402_5%
AC3
VGA_DDC_CLK
AE3
VGA_DDC_DATA
AE2
R123 1 DIS@
DIS@ 22.2K_0402_5%
2.2K_0402_5%
R124
1
2
U6
W6
VGA_CRT_R
Y6
R45 1 DIS@ 2
150_0402_1%
VGA_CRT_G
R48 1 DIS@ 2
150_0402_1%
VGA_CRT_B
N3
R49 1 DIS@ 2
150_0402_1%
L3

AL17
AM17
AM18
AM19
AL19
AK19
AL20
AM20
AM21
AM22
AL22
AK22
AL23
AM23
AM24
AM25
AL25
AK25
AL26
AM26
AM27
AM28
AL28
AK28
AK29
AL29
AM29
AM30
AM31
AM32
AN32
AP32

PEG_GTX_HRX_P0
PEG_GTX_HRX_N0
PEG_GTX_HRX_P1
PEG_GTX_HRX_N1
PEG_GTX_HRX_P2
PEG_GTX_HRX_N2
PEG_GTX_HRX_P3
PEG_GTX_HRX_N3
PEG_GTX_HRX_P4
PEG_GTX_HRX_N4
PEG_GTX_HRX_P5
PEG_GTX_HRX_N5
PEG_GTX_HRX_P6
PEG_GTX_HRX_N6
PEG_GTX_HRX_P7
PEG_GTX_HRX_N7
PEG_GTX_HRX_P8
PEG_GTX_HRX_N8
PEG_GTX_HRX_P9
PEG_GTX_HRX_N9
PEG_GTX_HRX_P10
PEG_GTX_HRX_N10
PEG_GTX_HRX_P11
PEG_GTX_HRX_N11
PEG_GTX_HRX_P12
PEG_GTX_HRX_N12
PEG_GTX_HRX_P13
PEG_GTX_HRX_N13
PEG_GTX_HRX_P14
PEG_GTX_HRX_N14
PEG_GTX_HRX_P15
PEG_GTX_HRX_N15

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

Part 1 of 7

DIS@
R65
124_0402_1%

4
4
4
4
4
4
4
4
4
4
4
4

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PCI EXPRESS
DVO

AP17
AN17
AN19
AP19
AR19
AR20
AP20
AN20
AN22
AP22
AR22
AR23
AP23
AN23
AN25
AP25
AR25
AR26
AP26
AN26
AN28
AP28
AR28
AR29
AP29
AN29
AN31
AP31
AR31
AR32
AR34
AP34

4 PEG_HTX_C_GRX_P0
4 PEG_HTX_C_GRX_N0
4 PEG_HTX_C_GRX_P1
4 PEG_HTX_C_GRX_N1
4 PEG_HTX_C_GRX_P2
4 PEG_HTX_C_GRX_N2
4 PEG_HTX_C_GRX_P3
4 PEG_HTX_C_GRX_N3
4 PEG_HTX_C_GRX_P4
4 PEG_HTX_C_GRX_N4
4 PEG_HTX_C_GRX_P5
4 PEG_HTX_C_GRX_N5
4 PEG_HTX_C_GRX_P6
4 PEG_HTX_C_GRX_N6
4 PEG_HTX_C_GRX_P7
4 PEG_HTX_C_GRX_N7
4 PEG_HTX_C_GRX_P8
4 PEG_HTX_C_GRX_N8
4 PEG_HTX_C_GRX_P9
4 PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_N15

N12P-GV1-A1_BGA973

I2CS_SDA

DIS@

EC_SMB_DA2 14,40

Compal Secret Data

Security Classification

DMN66D0LDW-7_SOT363-6
Q31B DIS@

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Title

Compal Electronics, Inc.


N12P PEG 1/9

Size Document Number


Custom JE50-HR/SJV50-HR M/B Schematics
Date:

Wednesday, October 27, 2010 E

Sheet

Rev
0.4

22

of

61

MDA[15..0]

MDA[15..0]

27

MDA[31..16]

28

MDA[47..32]

28

MDA[63..48]

29

MDC[15..0]

MDA[47..32]

29

MDC[31..16]

MDA[63..48]

30

MDC[47..32]

30

MDC[63..48]

U27B

FBA_CLK0
FBA_CLK0_N

N12P-GV1-A1_BGA973

FBA_CLK1
FBA_CLK1_N

DQSA#[3..0] 27

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

DQSA[3..0] 27

DQSA#[7..4] 28

DQSA[7..4] 28

P29
R29
L29
M29
AG29
AH29
AD29
AE29
T32
T31

AC31
AC30

+1.5VSDGPU

CLKA0
CLKA0#
CLKA1
CLKA1#

DIS@ 1
K27
2
40.2_0402_1% DIS@
R36
1
2
L27
40.2_0402_1%
R42
DIS@ 1
2
M27
FBB_DEBUG0
60.4_0402_1%
R41
FBB_DEBUG1
G19
G16

27
27
28
28

+FB_PLLAVDD_0

FBA_DEBUG0

60.4_0402_1%
10K_0402_5%

10K_0402_5%

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

FBC_WCK0
FBC_WCK0_N
FBC_WCK1
FBC_WCK1_N
FBC_WCK2
FBC_WCK2_N
FBC_WCK3
FBC_WCK3_N

FBCAL_PD_VDDQ
FBCAL_PU_GND
FBCAL_TERM_GND

FBC_CLK0
FBC_CLK0_N

FBC_DEBUG0
FBB_DEBUG1

FBC_CLK1
FBC_CLK1_N

B14
B10
D9
E14
F26
D31
A31
A26

DQMC[3..0] 29

DQMC0
DQMC1
DQMC2
DQMC3
DQMC4
DQMC5
DQMC6
DQMC7

DQMC[7..4] 30

DQSC#0
DQSC#1
DQSC#2
DQSC#3
DQSC#4
DQSC#5
DQSC#6
DQSC#7

DQSC#[3..0]

29

DQSC#[7..4]

30

DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7

DQSC[3..0]

29

DQSC[7..4]

30

C14
A10
E10
D14
E26
D32
A32
B26

G14
G15
G11
G12
G27
G28
G24
G25
E17
D17

D23
E23

CLKC0
CLKC0#

29
29

CLKC1
CLKC1#

30
30

DIS@

+1.5VSDGPU

60.4_0402_1%

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

A16
D10
F11
D15
D27
D34
A34
D28

CMDC0
CMDC1
CMDC2
CMDC3
CMDC4
CMDC5
CMDC6
CMDC7
CMDC8
CMDC9
CMDC10
CMDC11
CMDC12
CMDC13
CMDC14
CMDC15
CMDC16
CMDC17
CMDC18
CMDC19
CMDC20
CMDC21
CMDC22
CMDC23
CMDC24
CMDC25
CMDC26
CMDC27
CMDC28
CMDC29
CMDC30

N12P-GV1-A1_BGA973

DIS@

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

F18
E19
D18
C17
F19
C19
B17
E20
B19
D20
A19
D19
C20
F20
B20
G21
F22
F24
F23
C25
C23
F21
E22
D21
A23
D22
B23
C22
B22
A22
A20
G20

DIS@ 1

DIS@ 1
DIS@ 1

100mA

FBB_DEBUG0
R38

R43
FBA_DEBUG1
R34
FBB_DEBUG1

DIS@ 1

DIS@
+1.05VSDGPU
1
L25
BLM18PG330SN1_2P

+FB_PLLAVDD_1

DIS@
+1.05VSDGPU
1
L26
BLM18PG330SN1_2P

100mA
1

DIS@ C578
10U_0805_10V4Z

FB_VREF_NC
FBA_DEBUG0
FBA_DEBUG1

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CMD31

DIS@ C584
1U_0603_10V6K

FB_DLLAVDD_1
FB_PLLAVDD_1

DQMA[7..4] 28

CMDC[30..0] 29,30

Part 3 of 7

B13
D13
A13
A14
C16
B16
A17
D16
C13
B11
C11
A11
C10
C8
B8
A8
E8
F8
F10
F9
F12
D8
D11
E11
D12
E13
F13
F14
F15
E16
F16
F17
D29
F27
F28
E28
D26
F25
D24
E25
E32
F32
D33
E31
C33
F29
D30
E29
B29
C31
C29
B31
C32
B32
B35
B34
A29
B28
A28
C28
C26
D25
B25
A25

DIS@ C582
0.1U_0402_16V4Z

MEMORY INTERFACE
A

FB_DLLAVDD_0
FB_PLLAVDD_0

MDC[47..32]
MDC[63..48]

DIS@ C101
0.1U_0402_16V4Z

FBA_DEBUG0 J27
FBA_DEBUG1 T30
T29

FBA_WCK0
FBA_WCK0_N
FBA_WCK1
FBA_WCK1_N
FBA_WCK2
FBA_WCK2_N
FBA_WCK3
FBA_WCK3_N

L34
H35
J32
N31
AE31
AJ32
AJ34
AC33

DQMA[3..0] 27

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

DIS@ C501
10U_0805_10V4Z

J19
J18

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

L35
G35
H31
N32
AD32
AJ31
AJ35
AC34

MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63

DIS@ C504
1U_0603_10V6K

+FB_PLLAVDD_1

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

P32
H34
J30
P30
AF32
AL32
AL34
AF35

CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30

DIS@
C55
0.1U_0402_16V4Z

AG27
AF27

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

U30
V30
U31
V32
T35
U33
W32
W33
W31
W34
U34
U35
U32
T34
T33
W30
AB30
AA30
AB31
AA32
AB33
Y32
Y33
AB34
AB35
Y35
W35
Y34
Y31
Y30
W29
Y29

DIS@
C54
0.1U_0402_16V4Z

+FB_PLLAVDD_0

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

DIS@ C505
0.1U_0402_16V4Z

L32
N33
L33
N34
N35
P35
P33
P34
K35
K33
K34
H33
G34
G33
E34
E33
G31
F30
G30
G32
K30
K32
H30
K31
L31
L30
M32
N30
M30
P31
R32
R30
AG30
AG32
AH31
AF31
AF30
AE30
AC32
AD30
AN33
AL31
AM33
AL33
AK30
AK32
AJ30
AH30
AH33
AH35
AH34
AH32
AJ33
AL35
AM34
AM35
AF33
AE32
AF34
AE35
AE34
AE33
AB32
AC35

MDC[31..16]

U27C

CMDA[30..0] 27,28

Part 2 of 7

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

MDC[15..0]

MDA[31..16]

MEMORY INTERFACE C

27

DIS@ C583
0.1U_0402_16V4Z

VRAM Interface

R478

Compal Secret Data

Security Classification
Issued Date

2010/10/15

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


N12P VRAM 2/9

Size Document Number


Custom JE50-HR/SJV50-HR M/B Schematics

Rev
0.4

Date:

Wednesday, October 27, 2010

Sheet

23

of

61

For GB2-128 & GB2b-128 colayout....

STRAP_REF2

2 R779

1
+3VSDGPU

40.2K_0402_1%

H
10K

H
15K

L
15K

L
20K

900 MHz

64MX16
Hynix
SA000041S40

H
45K

L
35K

H
45K

L
15K

H
10K

H
15K

L
15K

L
20K

900 MHz

64MX16
Samsung
SA00004GS10

H
45K

L
35K

H
45K

L
25K

H
10K

H
15K

L
15K

L
20K

800 MHz

128MX16
Samsung
SA00003MQ60

H
45K

L
35K

H
45K

L
45K

H
10K

H
15K

L
15K

L
20K

800 MHz

128MX16
Hynix
SA00003VS10

H
45K

L
35K

H
45K

L
35K

H
10K

H
15K

L
15K

L
20K

R04 modify
R775
20K_0402_5%
GV@

1
2 R778
GV@
10K_0402_5%

L
15K

ROM_SO

ROM_SCLK

strap3

strap4

GV@

For N12P-GV A1 strap table

R776
10K_0402_5%
@

Frenq.

N12P-GS

strap1

strap2

ROM_SI

800 MHz

64MX16
Hynix
SA000032420

H
45K

L
35K

L
5K

L
15K

H
10K

H
5K

L
15K

L
20K

900 MHz

64MX16
Hynix
SA000041S40

H
45K

L
35K

L
5K

L
15K

H
10K

H
5K

L
15K

L
20K

900 MHz

64MX16
Samsung
SA00004GS10

H
45K

L
35K

L
5K

L
25K

H
10K

H
5K

L
15K

L
20K

800 MHz

128MX16
Samsung
SA00003MQ60

H
45K

L
35K

L
5K

L
45K

H
10K

H
5K

L
15K

L
20K

800 MHz

128MX16
Hynix
SA00003VS10

H
45K

L
35K

L
5K

L
35K

H
10K

H
5K

L
15K

L
20K

strap0

ROM_SO

ROM_SCLK

strap3

strap4

STRAP3

R04 modify
R777
15K_0402_5%
GV@

Straps MULTI LEVEL STRAPS


+3VSDGPU

FB_GND

R4881 1DIS@
DIS@ 2 0_0402_5%
0_0402_5%
AD19 R487
2
E35
R486 1 DIS@ 2 0_0402_5%
R7

54

STRAP0
STRAP1
STRAP2

ROM_SI
ROM_SO
ROM_SCLK

1
2

DIS@
R125
15K_0402_1%

GND_SENSE_0
GND_SENSE_1
GND_SENSE_2

@
R128
10K_0402_1%

GCORE_SEN 54

+3VSDGPU

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

VDD_SENSE_0
VDD_SENSE_1
VDD_SENSE_2

R484 1 DIS@
D35 R485
1 DIS@
P7
R483 1 DIS@
AD20

AE4
AD4
AF3
AF2

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N

SERIAL
ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK

GENERAL

+3VSDGPU

A4
@
1
R463

2
10K_0402_5%
STRAP0
STRAP1
STRAP2

AB5
W5
W7
V7

NC/SPDIF_NC

BUFRST_N

MULTI_STRAP_REF0_GND
CEC

MULTI_STRAP_REF1_GND
STRAP0
STRAP1
STRAP2

THERMDP
THERMDN

R403 1

DIS@

2 10K_0402_5%
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST

R417 2 DIS@

PAD T27
PAD T1
PAD T24
PAD T26
PAD T25

@
@
@
@
@

A5

N9
M9

R130

R129 1

2 DIS@

For N12P-GS strap table


(strap 3 and strap4 left NC)

DIS@ 2 10K_0402_5% +3VSDGPU

N12P-GS

strap1

strap2

ROM_SI

800 MHz

64MX16
Hynix
SA000032420

H
45K

L
35K

L
25K

L
5K

L
10K

H
15K

900 MHz

64MX16
Hynix
SA000041S40

H
45K

L
35K

L
25K

L
15K

L
10K

H
15K

900 MHz

64MX16
Samsung
SA00004GS10

H
45K

L
35K

L
25K

L
20K

L
10K

H
15K

800 MHz

128MX16
Samsung
SA00003MQ60

H
45K

L
35K

L
25K

L
45K

L
10K

H
15K

800 MHz

128MX16
Hynix
SA00003VS10

H
45K

L
35K

L
25K

L
35K

L
10K

H
15K

if unuse this pin , pull down 36k

1 36K_0402_1%

R457 2 DIS@

1 40.2K_0402_1%

R456 2 DIS@

1 40.2K_0402_1%

B5
B4

DIS@

strap0

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

ROM_SO

ROM_SCLK

Strap 2 for GV1,


Pull low 45K Ohm

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Issued Date

GV@
R459
45.3K_0402_1%

Frenq.

N12P-GV1-A1_BGA973

110K_0402_5%

R04 modify
ROM_CS#
C3 ROM_SI
D3 ROM_SO
ROM_SCLK
C4
D4

1
2
@ R126
15K_0402_1%

AP35
AP14
AN14
AN16
AR14
AP16

1
2
DIS@ R127
10K_0402_1%

TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

TEST

IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N

X76@ R453
20K_0402_1%

AP4
AN4

1
2
GS@ R459
24.9K_0402_1%

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N

DIS@ R461
34.8K_0402_1%

AP2
AN3

2
@

33 VGA_HDMI_SCLK
33 VGA_HDMI_SDATA
B

R460
45.3K_0402_1%
1
2

IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N

PGOOD

ROM_SI

H
45K

@
R475
15K_0402_1%

R89
4.7K_0402_5%
DIS@

R94
4.7K_0402_5%
DIS@

AL2
AL3
AJ3
AJ2
AJ1
AH1
AH2
AH3

STRAP3

strap2

L
35K

strap0

1
2
@ R480
15K_0402_1%

+3VSDGPU

STRAP4

R04 modify

strap1

H
45K

@ R482
34.8K_0402_1%

IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

STRAP4

N12P-GS
64MX16
Hynix
SA000032420

AH6
AH5
AH4
AG4
AF4
AF5
AE6
AE5

IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

R774
10K_0402_5%
@

Frenq.

800 MHz

AR8
AR7
AP7
AN7
AN5
AP5
AR5
AR4

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29

AM7
AM6
AL5
AM5
AM3
AM4
AP1
AR2

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

NC

AP13
AN13
AN8
AP8
AP10
AN10
AR11
AR10
AN11
AP11

LVDS/TMDS

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

A2
A7
B7
C5
C7
D5
D6
D7
E5
E7
F4
G5
H32
J25
J26
P6
U7
V6
Y4
AA4
AB4
AB7
AC5
AD6
AF6
AG6
AG20
AJ5
AK15
AL7

Part 4 of 7

AM11
AM12
AM8
AL8
AM10
AM9
AK10
AL10
AK11
AL11

For N12P-GV ES strap table

+3VSDGPU

U27D

DIS@ R481
45.3K_0402_1%

Title

N12P LVDS 3/9


Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010

Sheet

24

of

61

U27E

+IFPAB_IOVDD

AG9
AG10

R114
10K_0402_5%
OPT@

1K_0402_5% 2 DIS@

+IFPC_PLLVDD
1 R76

AJ9
AK7

+IFPC_IOVDD

AJ8

PEX_SVDD_3V3
PEX_SVDD_3V3_NC

DIS@ 1 R464
+IFPC_IOVDD

AC6
AB6
AK8

+IFPC_PLLVDD

10K_0402_5%2 DIS@
1K_0402_5% 2 DIS@

10K_0402_5%1 DIS@

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4

IFPC_PLLVDD
IFPC_RSET

AJ6
AL1

2 R68

AE7
AD7

MIOA_VDDQ_NC_0
MIOA_VDDQ_NC_1
MIOA_VDDQ_NC_2
MIOA_VDDQ_NC_3

IFPD_IOVDD

MIOB_VDDQ_NC_0
MIOB_VDDQ_NC_1
MIOB_VDDQ_NC_2
MIOB_VDDQ_NC_3

IFPEF_PLLVDD
IFPEF_RSET
IFPE_IOVDD
IFPF_IOVDD

DIS@
C85
0.1U_0402_16V4Z

DIS@
C90
0.1U_0402_16V4Z

DIS@ C126
1U_0402_6.3V6K

DIS@
C91
1U_0402_6.3V6K

DIS@ C108
4.7U_0603_6.3V6K

DIS@ C103
10U_0603_6.3V6M

DIS@ C183
22U_0805_6.3V6M

Under GPU

DIS@
C98
0.1U_0402_16V4Z

DIS@
C73
0.1U_0402_16V4Z

DIS@
C79
1U_0402_6.3V6K

DIS@
C84
1U_0402_6.3V6K

DIS@ C116
4.7U_0603_6.3V6K

DIS@
C63
10U_0603_6.3V6M

Under GPU

1
L6
MBC1608121YZF_0603

DIS@ C115
1U_0402_6.3V6K

DIS@ C179
4.7U_0603_6.3V6K

2500 mA

DIS@ C120
0.1U_0402_16V4Z

AK16
AK17
AK21
AK24
AK27

DIS@

NV recommand 0720

Under GPU

120mA

AG14

120mA

AG19
F7

R04 modify

2 DIS@ 1
R82
0_0603_5%

+1.05VSDGPU

1
2 @
R98
0_0603_5%

Under GPU

P9
R9
T9
U9

+3VSDGPU

120mA

J10
J11
J12
J13
J9

AA9
AB9
W9
Y9

+1.05VSDGPU

IFPC_IOVDD

IFPD_PLLVDD
IFPD_RSET

R04 modify

+3VSDGPU

2 DIS@

R63
0_0603_5%

Under GPU

R800
10K_0402_5%
DIS@

R801
10K_0402_5%
DIS@

R131
10K_0402_5%
OPT@

1 R468
1 R469

+VDD33

IFPA_IOVDD
IFPB_IOVDD

+IFPC_PLLVDD

1K_0402_5% 2

+PEX_SVDD_3V3

IFPAB_PLLVDD
IFPAB_RSET

DIS@
C99
1U_0402_6.3V6K

1 R71

DIS@ C137
4.7U_0603_6.3V6K

1K_0402_5% 2 DIS@

AK9
AJ11

DIS@ C141
1U_0402_6.3V6K

+IFPAB_PLLVDD

+1.05VSDGPU

+PEX_PLLVDD

PEX_PLLVDD

DIS@ C148
4.7U_0603_6.3V6K

+IFPAB_IOVDD
B

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4

DIS@ C134
0.1U_0402_16V4Z

R103
10K_0402_5%
OPT@

DIS@ C147
0.1U_0402_16V4Z

+IFPAB_PLLVDD

DIS@ C122
0.1U_0402_16V4Z

under GPU

+1.05VSDGPU

2500mA

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

DIS@
C87
0.1U_0402_16V4Z

DIS@ C104
0.1U_0402_16V4Z

DIS@
C64
0.1U_0402_16V4Z

DIS@
C76
0.1U_0402_16V4Z

DIS@
C65
1U_0402_6.3V6K

DIS@
C61
4.7U_0603_6.3V6K

under GPU

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37

POWER

DIS@
C70
0.1U_0402_16V4Z

DIS@
C67
0.1U_0402_16V4Z

DIS@
C58
0.1U_0402_16V4Z

DIS@ C109
0.1U_0402_16V4Z

DIS@
C80
1U_0402_6.3V6K

2
C

DIS@
C69
4.7U_0603_6.3V6K

Part 5 of 7

J23
J24
J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22
N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27

DIS@ C62
22U_0805_6.3V6M

7200mA

DIS@ C118
0.1U_0402_16V4Z

+1.5VSDGPU

N12P-GV1-A1_BGA973
DIS@

+IFPC_IOVDD

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2
5

Compal Secret Data

Security Classification
R77
10K_0402_5%
OPT@

Title

Compal Electronics, Inc.


N12P POWER & GND 4/9

Size Document Number


Custom JE50-HR/SJV50-HR M/B Schematics
Date:

Wednesday, October 27, 2010

Sheet

Rev
0.4

25

of

61

U27F

V2
V5
V9
V12
V14
V16

GND_91
GND_92
GND_93
GND_94
GND_95
GND_96

N12P-GV1-A1_BGA973

+VGA_CORE

U27G

AB11 VDD_0
AB13 VDD_1
AB15 VDD_2
AB17 VDD_3
AB19 VDD_4
AB21 VDD_5
AB23 VDD_6
AB25 VDD_7
AC11 VDD_8
AC12 VDD_9
AC13 VDD_10
AC14 VDD_11
AC15 VDD_12
AC16 VDD_13
AC17 VDD_14
AC18 VDD_15
AC19 VDD_16
AC20 VDD_17
AC21 VDD_18
AC22 VDD_19
AC23 VDD_20
AC24 VDD_21
AC25 VDD_22
AD12 VDD_23
AD14 VDD_24
AD16 VDD_25
AD18 VDD_26
AD22 VDD_27
AD24 VDD_28
L11 VDD_29
L12 VDD_30
L13 VDD_31
L14 VDD_32
L15 VDD_33
L16 VDD_34
L17 VDD_35
L18 VDD_36
L19 VDD_37
L20 VDD_38
L21 VDD_39
L22 VDD_40
L23 VDD_41
L24 VDD_42
L25 VDD_43
M12 VDD_44
M14 VDD_45
M16 VDD_46
M18 VDD_47
M20 VDD_48
M22
VDD_49
M24
VDD_50
P11 VDD_51
P13 VDD_52
P15 VDD_53
P17 VDD_54
P19 VDD_55

DIS@
C72
0.01U_0402_16V7K

DIS@ C130
0.1U_0402_16V4Z

DIS@ C121
0.01U_0402_16V7K

DIS@ C114
0.01U_0402_16V7K

DIS@
C78
0.1U_0402_16V4Z

DIS@
C77
0.047U_0402_16V7K

DIS@
C96
0.047U_0402_16V7K

DIS@ C110
0.01U_0402_16V7K

DIS@ C107
0.01U_0402_16V7K

DIS@
C74
0.047U_0402_16V7K

DIS@
C94
0.01U_0402_16V7K

DIS@
C88
0.01U_0402_16V7K

Put Under GPU

+VGA_CORE

DIS@ C593
47U_0805_4V6

DIS@ C591
22U_0805_6.3V6M

1
DIS@
C604
470U_V_2.5VM

DIS@ C592
4.7U_0603_6.3V6K

DIS@ C595
10U_0603_6.3V6M

1
DIS@
C1
470U_V_2.5VM

DIS@ C594
10U_0603_6.3V6M

R03 modify

P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24

N12P-GV1-A1_BGA973

Issued Date

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110

DIS@

Compal Secret Data


2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Part 7 of 7

POWER

DIS@
C97
0.022U_0402_16V7K

DIS@ C139
1U_0603_10V6K

DIS@C112
0.022U_0402_16V7K

DIS@ C133
0.22U_0603_16V7K

DIS@
C83
0.01U_0402_16V7K

41020mA

Security Classification

DIS@

+VGA_CORE

Under GPU

DIS@ C95
0.022U_0402_16V7K

V18
V20
V22
V24
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AK14
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
AP33

DIS@ C131
0.22U_0603_16V7K

GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192

DIS@ C123
0.22U_0603_16V7K

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90

Part 6 of 7

GND

B3
B6
B9
B12
B15
B21
B24
B27
B30
B33
C2
C34
E6
E9
E12
E15
E18
E24
E27
E30
F2
F31
F34
F5
J2
J5
J31
J34
K9
L9
M2
M5
M11
M13
M15
M17
M19
M21
M23
M25
M31
M34
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R5
R31
R34
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25

Title

Compal Electronics, Inc.


N12P POWER & GND 5/9

Size Document Number


Custom JE50-HR/SJV50-HR M/B Schematics
Date:

Wednesday, October 27, 2010

Sheet
1

Rev
0.4

26

of

61

VRAM DDR3 chips (1GB)

Mode D
Address

0..31

CMD0

64Mx16 DDR3 *8==>1GB

CMD1
CMD2

DQSA[7..0]

DQSA#[7..0]

23,28 DQSA#[7..0]

+MEM_VREF0

DQMA[7..0]

23,28 DQMA[7..0]

MDA[63..0]

23,28 MDA[63..0]

CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14

CMDA[30..0]

23,28 CMDA[30..0]

M8
H1

+1.5VSDGPU

DIS@
R391
240_0402_1%

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+MEM_VREF0

DIS@
R392
240_0402_1%

CMDA12
CMDA27
CMDA26

C495
DIS@
0.1U_0402_16V4Z

M2
N8
M3

CLKA0
CLKA0#
CMDA3

J7
K7
K9

CMDA2
CMDA0
CMDA30
CMDA15
CMDA13

+1.5VSDGPU

DIS@
R23
240_0402_1%

K1
L2
J3
K3
L3

DQSA2
DQSA1

F3
C7

+MEM_VREF1

DIS@
R25
240_0402_1%

DQMA2
DQMA1

C25
DIS@
0.1U_0402_16V4Z

E7
D3

DQSA#2
DQSA#1

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE
310mA
DQSL
DQSU

G3
B7

DQSL
DQSU

ZQ0

T2

RESET

CLKA0

CLKA0

23

2
R12
@
80.6_0402_1%

DIS@
R395
243_0402_1%

2
CLKA0#

J1
L1
J9
L9

DIS@
R15
160_0402_1%
23

L8

ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

CLKA0#

2
R11
@
80.6_0402_1%

@
C4
0.01U_0402_16V7K

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DML
DMU

CMDA5

U4

X76@

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

+MEM_VREF1

MDA18
MDA19
MDA23
MDA17
MDA21
MDA16
MDA20
MDA22

CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14

Group2

MDA12
MDA11
MDA14
MDA8
MDA13
MDA10
MDA15
MDA9

M8
H1

Group1

CMDA12
CMDA27
CMDA26

J7
K7
K9

+1.5VSDGPU
CMDA2
CMDA0
CMDA30
CMDA15
CMDA13

CK
CK
CKE/CKE0

310mA
F3
C7

DQMA0
DQMA3

DQSL
DQSU

E7
D3

DQSA#0
DQSA#3

CMDA5

T2

RESET

L8

ZQ/ZQ0

DIS@
R390
243_0402_1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

E3
F7
F2
F8
H3
H8
G2
H7

Group0

MDA29
MDA26
MDA31
MDA28
MDA27
MDA25
MDA30
MDA24

D7
C3
C8
C2
A7
A2
B8
A3

Group3

+1.5VSDGPU

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

ODT_L

CMD3

CKE

CMD4

A14

A14

CMD5

RST

RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

A15

CMD15

CAS*

CAS*
CS0_H#

CMD16

CMD17

B2
D9
G7
K2
K8
N1
N9
R1
R9

ODT_H

CMD18

CKE_H

CMD19

+1.5VSDGPU

VSS A9
VSS B3
VSS E1
VSS G8
VSS J2
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9

DQSL
DQSU

ZQ1

MDA3
MDA4
MDA2
MDA7
MDA0
MDA5
MDA1
MDA6

VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
VDDQ D2
VDDQ E9
VDDQ F1
VDDQ H2
VDDQ H9

DML
DMU

G3
B7

CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

Not Available
B

CMDA2
CMDA3
CMDA5
CMDA18
CMDA19

B1
B9
D1
D8
E2
E8
F9
G1
G9

R397 1 DIS@ 2
R398 1 DIS@ 2
DIS@
R401R399
1
2
1
R400 1 DIS@
DIS@2

10K_0402_5%
10K_0402_5%

Command Bit

Default Pull-down

ODTx

10K_0402_5%
2 10K_0402_5%
10K_0402_5%

10k
10k

CKEx

DDR3

RST
CS*

10k
No Termination

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

NV recommand 0720

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

K1 ODT/ODT0
L2 CS/CS0
J3 RAS
K3 CAS
L3 WE

DQSA0
DQSA3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M2 BA0
N8 BA1
M3 BA2

CLKA0
CLKA0#
CMDA3

A1
A8
C1
C9
D2
E9
F1
H2
H9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

N3 A0
P7 A1
P3 A2
N2 A3
P8 A4
P2 A5
R8 A6
R2 A7
T8 A8
R3 A9
L7 A10/AP
R7 A11
N7 A12
T3 A13
T7 A14
M7 A15/BA3

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

X76@

VREFCA
VREFDQ

U23

23,28 DQSA[7..0]

32..63

CS0_L#

+1.5VSDGPU

+1.5VSDGPU

DIS@
C35
0.1U_0402_16V4Z

DIS@
C34
0.1U_0402_16V4Z

DIS@
C33
0.1U_0402_16V4Z

Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )


1

AMD :SA00003PF10
(S IC D3 64M16/800 23EY2387MB-12 PG-TFBGA 96P 1.5V)

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

DIS@
C31
0.1U_0402_16V4Z

DIS@
C27
0.1U_0402_16V4Z

DIS@
C18
1U_0603_10V6K

DIS@
C22
1U_0603_10V6K

DIS@
C21
1U_0603_10V6K

DIS@
C19
1U_0603_10V6K

DIS@ C497
0.1U_0402_16V4Z

DIS@ C502
0.1U_0402_16V4Z

DIS@ C506
0.1U_0402_16V4Z

DIS@ C508
0.1U_0402_16V4Z

DIS@ C511
0.1U_0402_16V4Z

DIS@ C512
0.1U_0402_16V4Z

DIS@ C487
1U_0603_10V6K

DIS@ C493
1U_0603_10V6K

2
A

DIS@ C488
1U_0603_10V6K

DIS@ C486
1U_0603_10V6K

Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

N12P DDR3 6/9


Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010 1

Sheet

27

of

61

VRAM DDR3 chips (1GB)

Mode D
Address

64Mx16 DDR3 *8==>1GB

CMD0

0..31

32..63

CS0_L#

CMD1
D

M8
H1

CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14

CMDA[30..0]
DQSA#[7..0]

DQSA[7..0]
MDA[63..0]

+1.5VSDGPU

DIS@
R21
240_0402_1%

CMDA12
CMDA27
CMDA26

M2
N8
M3

+MEM_VREF2

CMDA18
CMDA16
CMDA30
CMDA15
CMDA13

+1.5VSDGPU

G3
B7

DQSL
DQSU

T2

ZQ2

L8

J1
L1
J9
L9

R10
@
80.6_0402_1%
DIS@
R14
160_0402_1%

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

CLKA1#

CLKA1
CLKA1#
CMDA19

+1.5VSDGPU
CMDA18
CMDA16
CMDA30
CMDA15
CMDA13

A1
A8
C1
C9
D2
E9
F1
H2
H9

DQSA7
DQSA6
DQMA7
DQMA6

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQSA#7
DQSA#6

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

CK
CK
CKE/CKE0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

K1 ODT/ODT0
L2 CS/CS0
J3 RAS
K3 CAS
L3 WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mA VDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

F3
C7

E7
D3

DML
DMU

G3
B7

DQSL
DQSU

T2

RESET

L8

MDA58
MDA59
MDA56
MDA63
MDA57
MDA61
MDA60
MDA62

D7
C3
C8
C2
A7
A2
B8
A3

MDA49
MDA53
MDA51
MDA55
MDA48
MDA54
MDA50
MDA52

Group7

Group6

B2
D9
G7
K2
K8
N1
N9
R1
R9

ZQ/ZQ0

ODT_L

CMD3

CKE

CMD4

A14

A14

CMD5

RST

RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

A15

CMD15

CAS*

CAS*
CS0_H#

CMD16
CMD17
+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS A9
VSS B3
VSS E1
VSS G8
VSS J2
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9

CMDA5
ZQ3

E3
F7
F2
F8
H3
H8
G2
H7

+1.5VSDGPU

M2 BA0
N8 BA1
M3 BA2

J7
K7
K9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

CMD2

CMD18

ODT_H

CMD19

CKE_H

CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

Not Available

DIS@
R389
243_0402_1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

@
C3
0.01U_0402_16V7K
+1.5VSDGPU

DIS@ C494
0.1U_0402_16V4Z

DIS@ C496
0.1U_0402_16V4Z

DIS@ C510
0.1U_0402_16V4Z

DIS@ C507
0.1U_0402_16V4Z

DIS@ C509
0.1U_0402_16V4Z

DIS@ C489
1U_0603_10V6K

DIS@ C492
1U_0603_10V6K

DIS@ C491
1U_0603_10V6K

DIS@
C14
1U_0603_10V6K

+1.5VSDGPU

DIS@
C15
1U_0603_10V6K

DIS@
C16
1U_0603_10V6K

NV recommand 0720

CMDA12
CMDA27
CMDA26

B2
D9
G7
K2
K8
N1
N9
R1
R9

M8
H1

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

2
R9
@
80.6_0402_1%

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

+1.5VSDGPU

DIS@ C490
1U_0603_10V6K

CLKA1#

DML
DMU

DIS@
C24
0.1U_0402_16V4Z

23

DQSL
DQSU

CMDA5

DIS@
R24
243_0402_1%
1

ODT/ODT0
CS/CS0
RAS
CAS
WE
310mA

DIS@
C17
1U_0603_10V6K

CLKA1

CK
CK
CKE/CKE0

E7
D3

DQSA#4
DQSA#5

C503
DIS@
0.1U_0402_16V4Z

DIS@
R396
240_0402_1%

23

F3
C7

DQMA4
DQMA5
+MEM_VREF3

K1
L2
J3
K3
L3

DQSA4
DQSA5

DIS@
R393
240_0402_1%

CLKA1

J7
K7
K9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

Group5

DIS@
C20
0.1U_0402_16V4Z

CLKA1
CLKA1#
CMDA19

BA0
BA1
BA2

MDA42
MDA45
MDA40
MDA44
MDA41
MDA47
MDA43
MDA46

D7
C3
C8
C2
A7
A2
B8
A3

CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14

Group4

DIS@
C32
0.1U_0402_16V4Z

C23
DIS@
0.1U_0402_16V4Z

DIS@
R22
240_0402_1%

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

DIS@
C30
0.1U_0402_16V4Z

23,27 DQSA[7..0]
23,27 MDA[63..0]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

+MEM_VREF3

MDA39
MDA35
MDA37
MDA33
MDA38
MDA32
MDA36
MDA34

E3
F7
F2
F8
H3
H8
G2
H7

DIS@
C28
0.1U_0402_16V4Z

23,27 DQSA#[7..0]

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DIS@
C26
0.1U_0402_16V4Z

23,27 CMDA[30..0]

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

X76@

+MEM_VREF2
DQMA[7..0]

23,27 DQMA[7..0]

U24

X76@

U3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

N12P DDR3 7/9


Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010 1

Sheet

28

of

61

Mode D
Address

VRAM DDR3 chips (1GB)

32..63

0..31

CMD0

CS0_L#

CMD1

64Mx16 DDR3 *8==>1GB

CMD2

DQSC[7..0]

DQSC#[7..0]
DQMC[7..0]

+MEM_VREF4

M8
H1

MDC[63..0]

CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14

CMDC[30..0]

+1.5VSDGPU

GS@
R435
240_0402_1%
+MEM_VREF4

CLKC0
CLKC0#
CMDC3

CMDC2
CMDC0
CMDC30
CMDC15
CMDC13

+1.5VSDGPU

DQSC2
DQSC1

GS@
R86
240_0402_1%

DQMC2
DQMC1
+MEM_VREF5

CMDC5

G3
B7

DQSL
DQSU

T2

RESET

L8

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

DQMC0
DQMC3

E7
D3

DQSC#0
DQSC#3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

CMDC5

T2

ZQ5

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

GS@
R50
243_0402_1%

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

Group3

CMD5

RST

RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

A15

CMD15

CAS*

CAS*
CS0_H#

CMD16

+1.5VSDGPU

CMD17
ODT_H

CMD18

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

CKE_H

CMD19
CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

Not Available

Command Bit

CMDC2
CMDC3
CMDC5
CMDC18
CMDC19

B1
B9
D1
D8
E2
E8
F9
G1
G9

R416
R415
1 GS@
1 GS@2 10K_0402_5%
2 10K_0402_5%
R414 1
2 10K_0402_5%
GS@
GS@
R413 1
2 10K_0402_5%
R412 1 GS@
2 10K_0402_5%

DDR3

Default Pull-down

ODTx

10k

CKEx

10k

RST
CS*

10k
No Termination

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

GS@ C566
0.1U_0402_16V4Z

GS@ C567
0.1U_0402_16V4Z

GS@ C571
0.1U_0402_16V4Z

GS@ C163
0.1U_0402_16V4Z

GS@ C164
0.1U_0402_16V4Z

GS@ C166
0.1U_0402_16V4Z

D7
C3
C8
C2
A7
A2
B8
A3

VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
VDDQ D2
VDDQ E9
VDDQ F1
VDDQ H2
VDDQ H9

DML
DMU

G3
B7

MDC28
MDC24
MDC31
MDC25
MDC29
MDC27
MDC30
MDC26

A14

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

GS@ C167
0.1U_0402_16V4Z

GS@ C168
0.1U_0402_16V4Z

GS@ C169
1U_0603_10V6K

+1.5VSDGPU
@
C145
0.01U_0402_16V7K

GS@ C170
1U_0603_10V6K

2
NV recommand 0720

DQSL
DQSU

Group0

A14

+1.5VSDGPU

GS@ C161
1U_0603_10V6K

CLKC0#

ODT/ODT0
CS/CS0
RAS
CAS
WE

F3
C7

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

GS@ C127
1U_0603_10V6K

23

1
2
R61
@
GS@
80.6_0402_1%
R69
160_0402_1%
CLKC0#
1
2
R60
@
80.6_0402_1%

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

310mA

DQSC0
DQSC3

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

CLKC0

CLKC0

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

J1
L1
J9
L9

GS@
R437
243_0402_1%

23

J7
K7
K9

CMDC2
CMDC0
CMDC30
CMDC15
CMDC13

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

CKE

CMD4

ZQ4

DML
DMU

CLKC0
CLKC0#
CMDC3

DQSC#2
DQSC#1

C165
GS@
0.1U_0402_16V4Z

GS@
R85
240_0402_1%

E7
D3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

M2 BA0
N8 BA1
M3 BA2

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

ODT/ODT0
CS/CS0
RAS
CAS
WE

F3
C7

Group1

CMDC12
CMDC27
CMDC26

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

MDC13
MDC10
MDC14
MDC9
MDC12
MDC8
MDC15
MDC11

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSDGPU

BA0
BA1
BA2

J7
K7
K9

Group2

M8
H1

GS@ C568
0.1U_0402_16V4Z

M2
N8
M3

D7
C3
C8
C2
A7
A2
B8
A3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14

MDC3
MDC7
MDC1
MDC4
MDC2
MDC6
MDC0
MDC5

GS@ C569
0.1U_0402_16V4Z

GS@
R436
240_0402_1%

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

+MEM_VREF5

MDC22
MDC16
MDC18
MDC19
MDC23
MDC17
MDC20
MDC21

GS@ C572
0.1U_0402_16V4Z

CMDC12
CMDC27
CMDC26

C570
GS@
0.1U_0402_16V4Z

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

E3
F7
F2
F8
H3
H8
G2
H7

X76@

GS@ C563
1U_0603_10V6K

23,30 CMDC[30..0]

U6

GS@ C573
1U_0603_10V6K

23,30 MDC[63..0]

X76@

GS@ C565
1U_0603_10V6K

23,30 DQMC[7..0]

U28

GS@ C564
1U_0603_10V6K

23,30 DQSC[7..0]
23,30 DQSC#[7..0]

ODT_L

CMD3

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

N12P DDR3 8/9


Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010 1

Sheet

29

of

61

VRAM DDR3 chips (1GB)


64Mx16 DDR3 *8==>1GB
D

DQMC[7..0]

23,29 DQMC[7..0]

CMDC[30..0]

U5

DQSC[7..0]

M8
H1

MDC[63..0]

CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14

+1.5VSDGPU

GS@
R32
240_0402_1%

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+MEM_VREF6

M2
N8
M3

CLKC1
CLKC1#
CMDC19

J7
K7
K9

CMDC18
CMDC16
CMDC30
CMDC15
CMDC13

+1.5VSDGPU

GS@
R407
240_0402_1%

K1
L2
J3
K3
L3

DQSC4
DQSC5

F3
C7

+MEM_VREF7

DQSC#4
DQSC#5

G3
B7

DQSL
DQSU

T2
ZQ6

L8

J1
L1
J9
L9

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

CMDC12
CMDC27
CMDC26

B2
D9
G7
K2
K8
N1
N9
R1
R9

CLKC1
CLKC1#
CMDC19

J7
K7
K9

+1.5VSDGPU
CMDC18
CMDC16
CMDC30
CMDC15
CMDC13

A1
A8
C1
C9
D2
E9
F1
H2
H9

F3
C7

DQMC7
DQMC6

DQSC#7
DQSC#6

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

DQSL
DQSU

E7
D3

DML
DMU

G3
B7

DQSL
DQSU

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CMDC5

T2

ZQ7

L8

GS@
R411
243_0402_1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

CMD0

MDC56
MDC63
MDC57
MDC60
MDC59
MDC61
MDC58
MDC62

32..63

CS0_L#

CMD1
CMD2

Group7

MDC48
MDC55
MDC49
MDC52
MDC51
MDC54
MDC50
MDC53

Group6

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

0..31

+1.5VSDGPU

ODT_L

CMD3

CKE

CMD4

A14

A14

CMD5

RST

RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

A15

CMD15

CAS*

CAS*
CS0_H#

CMD16
A1
A8
C1
C9
D2
E9
F1
H2
H9

CMD17
CMD18

ODT_H

CMD19

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

CKE_H

CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

Not Available

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

+1.5VSDGPU

GS@ C521
0.1U_0402_16V4Z

GS@ C522
0.1U_0402_16V4Z

GS@ C523
0.1U_0402_16V4Z

GS@ C525
0.1U_0402_16V4Z

GS@ C517
1U_0603_10V6K

GS@ C518
1U_0603_10V6K

GS@
C39
0.1U_0402_16V4Z

GS@
C40
0.1U_0402_16V4Z

+1.5VSDGPU

GS@
C41
0.1U_0402_16V4Z

@
C57
0.01U_0402_16V7K

GS@
C37
1U_0603_10V6K

NV recommand 0720

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

K1 ODT/ODT0
L2 CS/CS0
J3 RAS
K3 CAS
L3 WE
310mA

DQSC7
DQSC6

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

M2 BA0
N8 BA1
M3 BA2

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

GS@
C38
1U_0603_10V6K

CLKC1#

GS@
R35
160_0402_1%
CLKC1#
1
2
R37
@
80.6_0402_1%

GS@
C48
1U_0603_10V6K

2
R33
@
80.6_0402_1%

Group5

M8
H1

CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14

GS@ C526
0.1U_0402_16V4Z

23

GS@
R30
243_0402_1%

CLKC1

CLKC1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

ODT/ODT0
CS/CS0
RAS
CAS
WE

CMDC5

23

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

DML
DMU

Group4

MDC42
MDC43
MDC41
MDC46
MDC40
MDC45
MDC44
MDC47

GS@
C42
0.1U_0402_16V4Z

BA0
BA1
BA2

E7
D3

D7
C3
C8
C2
A7
A2
B8
A3

+MEM_VREF7

MDC39
MDC33
MDC38
MDC32
MDC36
MDC34
MDC37
MDC35

+1.5VSDGPU

GS@
C43
0.1U_0402_16V4Z

C524
GS@
0.1U_0402_16V4Z

GS@
R408
240_0402_1%

DQMC4
DQMC5

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

GS@
C45
0.1U_0402_16V4Z

CMDC12
CMDC27
CMDC26

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

GS@
C36
1U_0603_10V6K

C44
GS@
0.1U_0402_16V4Z

GS@
R31
240_0402_1%

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

E3
F7
F2
F8
H3
H8
G2
H7

X76@

GS@ C519
1U_0603_10V6K

23,29 MDC[63..0]

U26

GS@ C532
1U_0603_10V6K

23,29 DQSC[7..0]

+MEM_VREF6

Mode D
Address

X76@

DQSC#[7..0]

23,29 DQSC#[7..0]

23,29 CMDC[30..0]

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

N12P DDR3 9/9


Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010 1

Sheet

30

of

61

LCD POWER CIRCUIT

+LCDVDD

+3VS

+3VALW

W=60mils
R6
10K_0402_5%

R5
300_0603_5%

+LCDVDD

C479
4.7U_0603_6.3V6K

+INVPWR_B+

Place closed to JLVDS1

B+
L2
FBMA-L11-201209-221LMA30T_0805
1
2
L1
FBMA-L11-201209-221LMA30T_0805
1
2

W=60mils

+3VS

2
G

1 UMA@ 2
0_0402_5%

LCDVDD_ON

R1

C2
0.047U_0402_16V7K

Q28
+LCDVDD

C484
0.1U_0402_16V4Z

C485
10U_0805_10V4Z

C11
C9
680P_0402_50V7K

0.1U_0402_16V4Z

W=60mils

C6
68P_0402_50V8J

C483
4.7U_0805_10V4Z

C10
0.1U_0402_16V4Z

LCD/LED PANEL Conn.

R4
C

SM010014520 3000ma
220ohm@100mhz
DCR 0.04

Q1
SSM3K7002F_SC59-3

2
G

PCH_ENVDD

16

AP2301GN-HF_SOT23-3

Q2
SSM3K7002F_SC59-3

R2
1K_0402_5%
1
2

100K_0402_5%

LED PANEL Conn.

W=60mils

JLVDS1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

+INVPWR_B+

1
2
G1
3
G2
4
G3
5
G4
6
G5
7
G6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
IPEX_20143-040E-20F

W=60mils

40

BKOFF#

C5

C8

R13

2 0_0402_5%

R18

2 10K_0402_5%

DISPOFF#

INVTPWM
1 220P_0402_50V7K

DISPOFF#
1 220P_0402_50V7K

16
16
16
16

TZCLK+
TZCLKTZOUT2+
TZOUT2-

16
16

TZOUT1+
TZOUT1-

16
16

TZOUT0+
TZOUT0-

16
16
16
16

TXCLK+
TXCLKTXOUT2+
TXOUT2-

16
16

TXOUT1+
TXOUT1-

16
16
16
16

R02 modify

DISPOFF#
INVTPWM
TZCLK+
TZCLKTZOUT2+
TZOUT2-

TZOUT1+
TZOUT1-

TZOUT0+
TZOUT0-

TXCLK+
TXCLKTXOUT2+
TXOUT2-

TXOUT1+
TXOUT1TXOUT0+
TXOUT0LCD_DATA
LCD_CLK

TXOUT0+
TXOUT0LCD_DATA
LCD_CLK
+3VS

+LCDVDD

+3VS

U1

1 R783
2
100K_0402_5%
16

DPST_PWM

2
3

17
17

USB20_N4
USB20_P4

17
17

USB20_P10
USB20_N10

0_0402_5% 1
+3VS

OE#

VCC

OUT

Reserved for UMA Only and OPTIMA

IN

DPST_PWM_1

GND

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

2 R802

1
1
1
1

2
2
2
2

+5VS

R803
R806
R804
R805

USB20_3D_N4
USB20_3D_P4
+3VS_CAMERA
USB20_CMOS_P10
USB20_CMOS_N10

INVTPWM
1 UMA@ 2
R20
0_0402_5%

41
42
43
44
45
46

CONN@

74AHC1G125GW_SOT353-5

D15
1

1
R16
10K_0402_5%

USB20_CMOS_P10

I/O1

I/O4

REF1 REF2

I/O2

I/O3

+3VS
USB20_CMOS_N10
A

PJUSB208H_SOT23-6

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

LVDS Connector
Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010

Sheet

31

of

61

W=40mils

PCH_CRT_B

1
UMA@ 2

CRT_B_2

C597
10P_0402_50V8J

UMA@ 2

SM010012010 300ma 120ohm@100mhz DCR 0.4


+CRT_VCC

2 0.1U_0402_16V4Z

R147 2

P
2

2
MBC1608121YZF_0603

1
L10

2
MBC1608121YZF_0603

C230
10P_0402_50V8J

CRT_HSYNC_1

1
L13

C589
100P_0402_50V8J

DSUB_12
CRT_VSYNC_2

C220
10P_0402_50V8J

DSUB_15

C623 2
68P_0402_50V8J 1

74AHCT1G125GW_SOT353-5
+CRT_VCC

C586
68P_0402_50V8J

U9

CRT_VSYNC_1

CRT_VSYNC

2 0.1U_0402_16V4Z

OE#

C228 1

JCRT1
6
JCRT1.11 11
@ T71
1
7
12
2
8
13
3
9
14
G 16
4
G 17
10
15
JCRT1.5
5
@ T72
C-H_13-12201513CP
PAD
CONN@

CRT_HSYNC_2

CRT_HSYNC

1 10K_0402_5%

U10

OE#

C243 1

CRT Connector

PAD

CRT_G_2

C614
10P_0402_50V8J

UMA@ 2

C215
0.1U_0402_16V4Z

CRT_R_2

C637
10P_0402_50V8J

C588
22P_0402_50V8J

CRT_B_1

C601
22P_0402_50V8J

CRT_G_1

CH491DPT_SOT23-3

L33
BLM18BA470SN1D_2P
1
2
L30
BLM18BA470SN1D_2P
1
2
L28
BLM18BA470SN1D_2P
1
2

CRT_R_1

C621
22P_0402_50V8J

C596
10P_0402_50V8J

R510
150_0402_1%

C613
10P_0402_50V8J

R524
R520
150_0402_1% 150_0402_1%

C636
10P_0402_50V8J

PCH_CRT_B

PCH_CRT_G

16

PCH_CRT_G

PCH_CRT_R

+CRT_VCC
F1
1.1A_6V_SMD1812P110TF
W=40mils
2
1

+R_CRT_VCC

2
D18
PJDLC05C_SOT23-3

D17
PJDLC05C_SOT23-3

L32
BLM18BA470SN1D_2P
1
2
L29
BLM18BA470SN1D_2P
1
2
L27
BLM18BA470SN1D_2P
1
2

16

PCH_CRT_R

+5VS

D5

CRB1.0 use 47ohm@100Mhz Bead

16

For DISO only


L22,L24,L26
use 0 Ohm

74AHCT1G125GW_SOT353-5
+CRT_VCC

+3VS

16 PCH_CRT_VSYNC

PCH_CRT_HSYNC

R428 2 UMA@ 1 33_0402_5%

PCH_CRT_DATA

16 PCH_CRT_DATA

CRT_HSYNC

R426 2 UMA@ 1 33_0402_5%


PCH_CRT_CLK

16 PCH_CRT_CLK

R142
4.7K_0402_5%

DSUB_12

CRT_VSYNC

PCH_CRT_VSYNC

16 PCH_CRT_HSYNC

R146
4.7K_0402_5%

Q11A
DMN66D0LDW-7_SOT363-6

DSUB_15

Q11B
DMN66D0LDW-7_SOT363-6

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

CRT Connector
Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010

Sheet

32

of

61

SM070001310 400ma 90ohm@100mhz DCR 0.3

@ R242
0_0603_5%
1
2

W=40mils

HDMI_CLK-

+HDMI_5V_OUT

D10

+5VS

1+HDMI_5V

L38
WCM-2012-900T_0805
@
4

1.1A_6V_SMD1812P110TF

C345
0.1U_0402_16V4Z

0_0402_5%

1
1

CH491DPT_SOT23-3

R574 1

F2

HDMI_CLK+

R579 1

HDMI_TX0-

R565 1

HDMI_R_CK-

3 3
0_0402_5%

HDMI_R_CK+

0_0402_5%

HDMI_R_D0-

+3VS

HDMI_HPD

1 0.1U_0402_10V7K
1 0.1U_0402_10V7K

16 PCH_DPB_N2
16 PCH_DPB_P2

1 0.1U_0402_10V7K
1 0.1U_0402_10V7K

HDMI_TX0HDMI_TX0+

16 PCH_DPB_N3
16 PCH_DPB_P3

C285 UMA@ 2
C284 UMA@ 2

1 0.1U_0402_10V7K
1 0.1U_0402_10V7K

HDMI_CLKHDMI_CLK+

PCH_DPB_HPD 16

HDMI_TX1+

4
R593 1

HDMI_TX2+

0_0402_5%
0_0402_5%
2

HDMI_R_D1-

HDMI_R_D0+

R591

L40
WCM-2012-900T_0805
@
4

0_0402_5%

0_0402_5%

R586

HDMI_TX2-

R584 1

1
L39
WCM-2012-900T_0805
@
4

R569 1

HDMI_TX1-

Q14
SSM3K7002F_SC59-3
UMA@
UMA@
R219
100K_0402_5%
S

C283 UMA@ 2
C282 UMA@ 2
C287 UMA@ 2
C286 UMA@ 2

HDMI_TX1HDMI_TX1+

16 PCH_DPB_N1
16 PCH_DPB_P1

HDMI_TX0+

2
G

HDMI_TX2HDMI_TX2+

1 0.1U_0402_10V7K
1 0.1U_0402_10V7K

C280 UMA@ 2
C281 UMA@ 2

16 PCH_DPB_N0
16 PCH_DPB_P0

C324
220P_0402_50V7K

UMA

L36
WCM-2012-900T_0805
@
4

R198
1M_0402_5%
UMA@

HDMI_R_D1+

HDMI_R_D2-

3 3
0_0402_5%

HDMI_R_D2+

R03 modify

HDMI_TX1HDMI_TX1+
HDMI_TX0HDMI_TX0+

HDMI_CLKHDMI_CLK+

RB751V40_SC76-2
R785
0_0402_5%
UMA@

0_0402_5%
0_0402_5%

R252 1 UMA@ 2
R254 1
2
DISO@

0_0402_5%
0_0402_5%

HDMI_SDATA
HDMI_SCLK
HDMI_R_CK-

HDMI_SCLK

Q17

SSM3K7002F_SC59-3

1
HDMI_SDATA

SSM3K7002F_SC59-3

Place closed to JHDMI1

HDMI_R_CK+
HDMI_R_D0-

1109 RF request

Q16

Q37
2
G
SSM3K7002F_SC59-3 S

+HDMI_5V_OUT

16 SDVO_SDATA
24 VGA_HDMI_SDATA

R573 1 UMA@ 2 680_0402_5%


R580 1 UMA@ 2 680_0402_5%

JHDMI1

HDMI_HPD

R249 11 UMA@ 22
R244
DISO@

16 SDVO_SCLK
24 VGA_HDMI_SCLK

D11
RB751V40_SC76-2

D12

Pull high at VGA side

R564 1 UMA@ 2 680_0402_5%


R570 1 UMA@ 2 680_0402_5%

HDMI connector

R03 modify

SDVO_SDATA

1
21
R255
2.2K_0402_5%

1 UMA@ 2 2.2K_0402_5%

R253

+3VS

SDVO_SCLK

1
2
1
R256
2.2K_0402_5%

1 UMA@ 2 2.2K_0402_5%

R250

R583 1 UMA@ 2 680_0402_5%


R587 1 UMA@ 2 680_0402_5%

INTEL use 680 Ohm for terminationn


in DG 1.5
+3VS

+HDMI_5V_OUT

+3VS

R589 1 UMA@ 2 680_0402_5% HDMI_GND


R594 1 UMA@ 2 680_0402_5%

HDMI_TX2HDMI_TX2+

HDMI_R_D0+
HDMI_R_D1-

C357
47P_0402_50V8J
@

HDMI_R_D1+
HDMI_R_D2-

HDMI_R_D2+

C358
47P_0402_50V8J
2 @

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

NV use 499 Ohm for terminationn

20
21
22
23

ACON_HMR2E-AK120D
CONN@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

HDMI Conn
Size Document Number
Custom

Rev

0.4
JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010

Sheet

33

of

61

SATA HDD1 Conn.


CL 4.0 mm
JHDD1
13 SATA_PTX_DRX_P0
13 SATA_PTX_DRX_N0
13 SATA_PRX_DTX_N0
13 SATA_PRX_DTX_P0

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

C708 1
C711 1

2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0
2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

C712 1
C713 1

2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0
2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0

1
2
3
4
5
6
7

R370
0_0805_5%
1
2

+5VS_HDD1

+3VS

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Rsv
GND
12V
12V
12V
GND
GND

C453
0.1U_0402_16V4Z

+5VS_HDD1
C

100mils

C742
1000P_0402_50V7K

CONN@

C743
0.1U_0402_16V4Z

OCTEK_SAT-22DD1G

C740
1U_0402_6.3V6K

C744
10U_0805_10V4Z

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

+3VS

+5VS

GND
RX+
RXGND
TXTX+
GND

SATA ODD Conn.


JODD1
13 SATA_PTX_DRX_P2
13 SATA_PTX_DRX_N2

C643 1
C639 1

13 SATA_PRX_DTX_N2
13 SATA_PRX_DTX_P2

C628 1
C624 1

1 @

0_0402_5%

+5VS_ODD

+5VS

ODD_DA#_R

R765
0_0805_5%
1
2

GND
GND
GND
GND

17
16
15
14

OCTEK_SLS-13SB1G_RV
CONN@

ODD_EN#

Q56
2
G
SSM3K7002F_SC59-3 S
@

S
Q55
SI3456BDV-T1-E3 1N TSOP6

G
@

18

R764
1.5M_0402_5%

ODD_EN

6
5
2
1

C812
1U_0402_6.3V6K

R760
470K_0402_5%
@

+VSB

80mils

DP
+5V
+5V
MD
GND
GND

C192
1000P_0402_50V7K

R763

+5VS_ODD

C200
0.1U_0402_16V4Z

ODD_DA#

8
9
10
11
12
13

GND
A+
AGND
BB+
GND

C201
1U_0402_6.3V6K

+5VS_ODD

1
2
3
4
5
6
7

C199
10U_0805_10V4Z

1 @ R139 2 0_0402_5%
+5VS_ODD

18 ODD_DETECT#
17

SATA_PTX_C_DRX_P2
2 0.01U_0402_16V7K
SATA_PTX_C_DRX_N2
2 0.01U_0402_16V7K
SATA_PRX_C_DTX_N2
2 0.01U_0402_16V7K SATA_PRX_C_DTX_P2
2 0.01U_0402_16V7K

C811
0.1U_0402_16V4Z
@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

HDD & ODD Connector


Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010

Sheet

34

of

61

+1.2V_LAN

0.1U_0402_16V4Z

C678

0.1U_0402_16V4Z
1
1
1
C674
C301
C302

U32

0.1U_0402_16V4Z
+3V_LAN
1
1
C298 C668

C671

+1.2V_LAN

4.7U_0603_6.3V6K 2

2
2
0.1U_0402_16V4Z

2
2
0.1U_0402_16V4Z

BIASVDDH

20

35
61

2
2
0.1U_0402_16V4Z

XTALVDDH

VDDC
VDDC

7
56
62

+3V_LAN

C683

C690

4.7U_0603_6.3V6K 2

VDDO
VDDO
VDDO

0.1U_0402_16V4Z
1
1
1
C667
C680
+LAN_AVDDL

2
2
0.1U_0402_16V4Z

39
45
51

2
0.1U_0402_16V4Z
+LAN_GPHYPLLVDDL

32

47
46

40

R201 1

EC_PME#

+3V_LAN

15,38,39,46 PCH_PCIE_WAKE#
17,38,39,40,46 PLT_RST_BUF#
14 CLK_PCIE_LAN
14 CLK_PCIE_LAN#

PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N

TRAFFICLED#_SERIALDI

GPIO1_LR_OUT

GPIO_0

R225 1

<BOM 2Structure>
0_0402_5%

2 4.7K_0402_5%
LAN_PME#
2 0_0402_5%

SI_EEDATA
CS#_EECLK

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7

11
31
30

CR_DATA0_R
2 47_0402_5%
CR_DATA1_R
47_0402_5% CR_DATA2_R
22 47_0402_5%
CR_DATA3_R
2 47_0402_5% CR_DATA4_R
47_0402_5%CR_DATA5_R
22 47_0402_5%
CR_DATA6_R
47_0402_5%CR_DATA7_R
22 47_0402_5%

R199 1

R207 1
R211
1
R215 1
R168 11
R171

R179 11
R182

PREST#
PCIE_REFCLK_P
PCIE_REFCLK_N

25
24
23
22
52
53
54
55

R04 modify

SR_DISABLE/XD_DETECT#
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7

MS_INS#/XD_CE#
GPIO2_MEDIA_SENSE/XD_RE#
CR_WP#/XD_WP#

CR_LED_CR_BUS_PWR/XD_ALE

+3VS

58

CR_PWR_XD_ALE

R208
R212
1 2

LAN_XTALI
LAN_XTALO_R

R226
4.7K_0402_5%
B0@
1 0_0402_5%
2 10K_0402_5%
4
A0@
19
18

1
R562
200_0402_1%

LAN_XTALO
2

1
R541

14 LAN_CLKREQ#

20mil

LAN_MIDI1- 36
LAN_MIDI1+ 36

LAN_MIDI0LAN_MIDI0+

20mil

R200 2

67

CR_5IN1_LED#_R

R229 2

LAN_ACTIVITY# 36

0_0603_5%R03
2

R214

+VDDO_CR_R

1 0_0402_5%

L15

0_0402_5% CR_5IN1_LED#

B0@ 1

0.1U_0402_16V4Z

modify+VDDO_CR

C294
2

1
2
BLM18AG601SN1D_2P

0.1U_0402_16V4Z

CR_5IN1_LED# 41

+XDPWR_SDPWR_MSPWR
SPROM_DOUT
SPROM_CLK

64
63

+VDDO_CR

CR_XD_WE#_SD_DETECT_R

SR_LX

SR_VFB

LOW_PWR

CR_XD_WE#_SD_DETECT
1 0_0402_5%
CR_XD_DETECT#
1 0_0402_5%
CR_XD_CE#_MS_INS#
2 0_0402_5%

1 0_0402_5%

R576

CR_XD_DETECT#_R

68

R572

CR_XD_CE#_MS_INS#_R

R192

59
CR_XD_RE#_R

R227

CR_WP#_XD_WP#_R

57

R185

R196

CR_PWR_XD_ALE_R

60
CR_CLK_XD_RY_BY#_R

21

R216

CR_CMD_XD_CLE_R

26

R195

1
1

CR_XD_RE#

CR_WP#_XD_WP#
1 0_0402_5%
CR_PWR_XD_ALE
A0@ 1 0_0402_5%
CR_CLK_XD_RY_BY#
2 0_0402_5%
CR_CMD_XD_CLE
47_0402_5%
2

+1.2V_LAN_OUT

L37

CLK_REQ#
BCM57785XA0KMLG_QFN68_8X8

C676

13

C689

1 0.1U_0402_16V4Z
C684

CR_XD_CE#_MS_INS# 36

2
0.1U_0402_16V4Z

CR_XD_RE# 36
CR_WP#_XD_WP# 36
CR_PWR_XD_ALE 36

CR_CLK_XD_RY_BY#

C329

R222

36

2
2 1
@
@
22_0402_5%
0.01U_0402_16V7K

1
CR_CMD_XD_CLE 36

For EMI request

EMI Request...2010/07/27
B

C691
10U_0805_10V4Z

SM010005500 500ma 600ohm@100mhz DCR 0.38

20mil
+LAN_PCIEPLLVDD

4.7U_0603_6.3V6K
C692

C306
0.1U_0402_16V4Z

C328

R232
2
B0@
1 0_0805_5%

+1.2V_LAN

+3V_LAN

15
14

2
4.7U_0603_6.3V6K 2
0.1U_0402_16V4Z

40mil

1
2
4.7UH_PG031B-4R7MS_1.1A_20%

16

40mil

RDAC

C337

CR_XD_DETECT# 36

R826 (+VDDO_CR)
For B0 version

R04 modify

0.1U_0402_16V4Z

SR_VDDP
SR_VDD

CR_XD_WE#_SD_DETECT 36

L18
1
2
BLM18AG601SN1D_2P

1
2

+1.2V_LAN

C303
4.7U_0603_6.3V6K

PLACE NEXT P14

20mil
+LAN_GPHYPLLVDDL

C658

+3V_LAN

R537
4.7K_0402_5%

VCC
WP
SCL
SDA

4.7U_0603_6.3V6K

L17
1
2
BLM18AG601SN1D_2P

1
A0
A1
A2
GND

+1.2V_LAN

+LAN_AVDDL

C656

8
7
6
5

SPROM_CLK
SPROM_DOUT

L35
1
2
BLM18AG601SN1D_2P

20mil

2 0.1U_0402_16V4Z

U31 @

C659

R536
4.7K_0402_5%

C634 1
2

SPROM_DOUT
(EEDATA)

SPROM_CLK
(EECLK)

20mil
+LAN_AVDDH

0.1U_0402_16V4Z

AT24C02

2
L34
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z

LAN_LINK# 36

40mil

12

25MHZ_20PF_7A25000012
1
C681
C679
27P_0402_50V8J
2
27P_0402_50V8J
2

1
2+3V_LAN
BLM18AG601SN1D_2P
0.1U_0402_16V4Z

C323

LAN_MIDI0- 36
LAN_MIDI0+ 36

65

XTALO
XTALI

38

2
1.24K_0402_1%

On chip

L20

+LAN_XTALVDDH

66

TEST1
TEST2

LAN_RDAC 15mil

Y4

10

LAN_XTALO_R
LAN_XTALI

CR_CMD_XD_CLE

VMAIN_PRSNT

69

R824 (CP_PWR_XD_ALE)
for B0 version

4.7K_0402_5%

GND PLANE

2 1K_0402_5%

+3V_LAN

R228

LAN_MIDI2- 36
LAN_MIDI2+ 36

LAN_MIDI1LAN_MIDI1+

LAN_MIDI3- 36
LAN_MIDI3+ 36

LAN_MIDI2LAN_MIDI2+

41
40

C666

4.7U_0603_6.3V6K
2
2
0.1U_0402_16V4Z

LAN_MIDI3LAN_MIDI3+

43
44

C662

CR_CLK/XD_RY_BY#
R190 1

WAKE#

SD_DETECT/XD_WE#
36
36
36
36
36
36
36
36

C657

2 0_0402_5%

R209 1
R213 1

+LAN_AVDDH

C299

28
27
33
34

+LAN_BIASVDDH

PCIE_PLLVDDL

SPD100LED#_SERIALDO
PCIE_PRX_C_DTX_P1
2 C670 PCIE_PRX_C_DTX_N1
2 C673

+3VALW

R543

60mil

PCIE_PLLVDDL

SO_LINKLED#

0.1U_0402_10V7K 1
0.1U_0402_10V7K 1

+3V_LAN

48
42

TRD2_N
TRD2_P

SCLK_SPD1000LED#

PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1
PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

+LAN_XTALVDDH

TRD3_N
TRD3_P

TRD0_N
TRD0_P

GPHY_PLLVDDL

29

14
14
14
14

17

49
50

TRD1_N
TRD1_P

AVDDL
AVDDL
AVDDL

36

+LAN_PCIEPLLVDD

+LAN_BIASVDDH

0_1206_5%

AVDDH
AVDDH

+3V_LAN
D

37

VDDO_CR

0.1U_0402_16V4Z

1
2
3
4

+1.2V_LAN

C297

4.7U_0603_6.3V6K

AT24C04BN-SH-T_SO8

R538
4.7K_0402_5%

1
5

2010/10/15

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R525
4.7K_0402_5%

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Broadcom BCM57785
Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010

Sheet

35

of

61

35
35

LAN_MIDI2LAN_MIDI2+

35
35

LAN_MIDI1+
LAN_MIDI1-

35
35

LAN_MIDI0LAN_MIDI0+

LAN_MIDI3+
LAN_MIDI3-

TCT1
TD1+
TD1-

LAN_MIDI2LAN_MIDI2+

4
5
6

LAN_MIDI1+
LAN_MIDI1LAN_MIDI0LAN_MIDI0+

MCT1
MX1+
MX1-

RJ45_MIDI3+
RJ45_MIDI3-

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

RJ45_MIDI2RJ45_MIDI2+

7
8
9

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

RJ45_MIDI1+
RJ45_MIDI1-

10
11
12

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

15
14
13

RJ45_MIDI0RJ45_MIDI0+

LAN_MIDI3+
LAN_MIDI3-

35
35

24
23
22

D14
PJDLC05C_SOT23-3
@

R02 modify

0.1U_0402_16V4Z

C619

C620

0.1U_0402_16V4Z
2

1
R492
75_0603_1%

R493
75_0603_1%

R491
75_0603_1%

R03 modify

1
1K_0402_5%

2
R384

+3V_LAN

R490
75_0603_1%

220P_0402_50V7K
C473

0.1U_0402_16V4Z

C474,C475 and D14


ME interefer,do not pop!!

C474 68P_0402_50V8J
@
1
2

RJ45_GND

Place close to TCT pin

JRJ1

LAN_LINK#

35 LAN_LINK#

10
RJ45_MIDI0+

BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00


TIMAG:S X'FORM_ IH-160 LAN , SP050006F00

RJ45_MIDI0RJ45_MIDI1+
RJ45_MIDI2+
RJ45_MIDI2-

RJ45_MIDI1-

RJ45_MIDI3+
RJ45_MIDI3-

+3V_LAN

1
2
R385 1K_0402_5% 1
220P_0402_50V7K
C476

R05 modify

10
9
12
15
17
14
7

MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3
MS_SCLK
MS_INS
MS_BS
TAITW _R013-P17-HM_NR
CONN@

6
13
5
20
30
40
41
42

35
35
35
35
35
35
35
35

@
C478
1
2

RJ45_GND

12

Yellow LED-

LANGND

1000P_1206_2KV7K

R04 modify

CR_XD_DETECT# 35
CR_CLK_XD_RY_BY# 35
CR_XD_RE# 35
CR_XD_CE#_MS_INS# 35
CR_CMD_XD_CLE 35
CR_PW R_XD_ALE 35
CR_XD_W E#_SD_DETECT 35
CR_W P#_XD_W P# 35

R04 modify

40mil

2
J10
JUMP_43X118
@

JP3 @
B88069X9231T203_4P5X3P2-2

B88069X9231T203_4P5X3P2-2
L53
JP2
1.2UH_1127AS-1R2N_2.4A_30%
@

R04 modify

D36
PJDLC05C_SOT23-3

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

Issued Date

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Yellow LED+

SD_GND
SD_GND
MS_GND
MS_GND
XD_GND
XD_GND
GND
GND

PR4-

11

40mil

22
23
24
25
26
27
28
29

CR_XD_DETECT#
CR_CLK_XD_RY_BY#
CR_XD_RE#
CR_XD_CE#_MS_INS#
CR_CMD_XD_CLE
CR_PW R_XD_ALE
CR_XD_W E#_SD_DETECT
CR_W P#_XD_W P#

PR2PR4+

EMI Request

XD_CD
XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP-IN

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7

31
32
33
34
35
36
37
38

SD_CLK
SD_CMD
SD_CD
SD_WP
SD/MMC_DAT0
SD/MMC_DAT1
SD/MMC_DAT2
SD/MMC_DAT3

XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

6
7

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_CLK_XD_RY_BY#
CR_XD_CE#_MS_INS#
CR_CMD_XD_CLE

8
16
1
2
4
3
21
19

SD_VCC
MS_VCC
XD_VCC

PR3+
PR3-

R03 modify

CR_CLK_XD_RY_BY#
CR_CMD_XD_CLE
CR_XD_W E#_SD_DETECT
CR_W P#_XD_W P#
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3

11
18
39

4
5

14
13

SANTA_130451-K
CONN@

+XDPW R_SDPW R_MSPW R

PR1PR2+

2
@

C475
@
JP1
B88069X9231T203_4P5X3P2-2
1
2

JREAD1
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7

SHLD1
SHLD2

68P_0402_50V8J

Card Reader Connector


B

Green LEDPR1+

LAN_ACTIVITY#

35 LAN_ACTIVITY#

Green LED+

0.1U_0402_16V4Z
2
2

C618

C617

R03 modify

LAN Connector
1

IH-160
SP050006F00

R02 modify

LAN_ACTIVITY#
LAN_LINK#

T28

1
2
3

Title

LAN Magnetic & RJ45


Size
Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

W ednesday, October 27, 2010

Sheet

36

of

61

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

RTS5138 Card Reader


Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Sheet

Wednesday, October 27, 2010


E

37

of

61

For Wireless LAN


1
+3VS

+3VS_WLAN

R324
0_1206_5%
1
2

60mil

C403
4.7U_0805_10V4Z

+3VS_WLAN

+1.5VS

C735
0.1U_0402_16V4Z

C392
4.7U_0805_10V4Z

C734
0.1U_0402_16V4Z

C423
0.1U_0402_16V4Z

C387
0.1U_0402_16V4Z

WLAN&BT Combo module circuits

Mini Card Power Rating

+1.5VS +3VS_WLAN

@ R702
0_0402_5%
1
2

14 MINI1_CLKREQ#

14 CLK_PCIE_MINI1#
14 CLK_PCIE_MINI1

14 PCIE_PRX_DTX_N2
14 PCIE_PRX_DTX_P2

14 PCIE_PTX_C_DRX_N2
14 PCIE_PTX_C_DRX_P2

+3VS_WLAN

40 E51TXD_P80DATA
40 E51RXD_P80CLK

E51TXD_P80DATA_R
2 0_0402_5% E51RXD_P80CLK_R
2 0_0402_5%

53

GNDGND

54

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

Enable

Disable

BT_CTRL
BT_ON#

WL_OFF#
PLT_RST_BUF#
+3VS_MINI1

R342 1

MINI1_SMBCLK
R337 1
MINI1_SMBDATA
R335 1

2 0_0603_5%
@
@

WL_OFF# 18
PLT_RST_BUF# 17,35,39,40,46
+3VS

2 0_0402_5%
2 0_0402_5%

D32
40,44,52,53 SUSP#

SUSP#

PCH_SMBCLK 14
PCH_SMBDATA 14

BT_ON#

USB20_N8 17
USB20_P8 17

2 0_0402_5%

BT_CTRL

CH751H-40PT_SOD323-2
@
18,39

R306 1

Q57
2
G
SSM3K7002F_SC59-3 S

MINI1_LED# 40

(9~16mA)
R305
100K_0402_5%

R299 1
R287 1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

BT
on module

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

15,35,39,46 PCH_PCIE_WAKE#

JMINI1

BT
on module

+3VS_WLAN

ACES_51711-0520W-001

R300
R288
100K_0402_5% 1K_0402_5%

+3VS_WLAN

CONN@

BT_CTRL

For 3G / GPS

Reserve
+3VS_FULL

To 3G Module Connect
+3VS_FULL

+1.5VS

R03 modify

60mil
C455
4.7U_0805_10V4Z

C467
0.1U_0402_16V4Z

C443
4.7U_0805_10V4Z

C442
0.1U_0402_16V4Z

J3G1

C466
0.1U_0402_16V4Z

22

+3VALW

+1.5VS +3VS_FULL

14 CLK_PCIE_MINI2#
14 CLK_PCIE_MINI2

14 PCIE_PRX_DTX_N3
14 PCIE_PRX_DTX_P3

14 PCIE_PTX_C_DRX_N3
14 PCIE_PTX_C_DRX_P3

+3VS_FULL

E51TXD_P80DATA_R
E51RXD_P80CLK_R

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53
4

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

The same circuit with JMINI1,


but different PCIE & USB....

USB20_N11_R
USB20_P11_R

R329 1

R334 1
R333 1

21
+3VALW

+3VS

R343 1
MINI2_SMBCLK
MINI2_SMBDATA

@
@

R332 1
R331 1

2 0_0402_5%

C531
3G@
0.1U_0402_16V4Z

R03 modify

WL_OFF#
PLT_RST_BUF#

+3VS_MINI1

2 0_0603_5%
PCH_SMBCLK
PCH_SMBDATA
2 0_0402_5%
2 0_0402_5%
USB20_N11
2 0_0402_5%USB20_P11
2 0_0402_5%

Peak: 2.75A
Normal: 1.1A

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+3VALW

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+3VS

R405
100K_0402_5%
3G@
WWAN_OFF#
MINI2_LED#
USB20_N9_R1
USB20_P9_R1

WWAN_OFF# 18
MINI2_LED# 40

R404 0_0402_5%
3G@ 2
1
3G@ 2
1
R402 0_0402_5%

USB20_N9 17
USB20_P9 17

USB20_N12 17
USB20_P12 17

3G_GATE

GND
ACES_87213-2000G
CONN@

R03 modify
USB20_N11 17
USB20_P11 17

14 MINI2_CLKREQ#

JMINI2

MINI2_LED#

3G@
C535
220U_6.3V_M_R17

@ R371
PCH_PCIE_WAKE#
0_0402_5%
(WLAN_BT_DATA)
1
2
(WLAN_BT_CLK)

GND

R03 modify

C441
0.1U_0402_16V4Z

+3VS_FULL

(9~16mA)

1
C527
3G@

C537
3G@
2 10U_0603_6.3V6M

20mil
+VSB

47P_0402_50V8J
44,52,53 SUSP

54

R790
47K_0402_5%
1
2
3G@
D

SUSP

Q58
2
3G@
S
SSM3K7002F_SC59-3

2
G

Close to 3G CONN

1 3G@
C820
0.1U_0603_25V7K

1
0_1206_5%

2
R352

+3VS

BELLW_80003-1021
CONN@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

MINI CARD (WLAN & TV-Tuner)


Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010

Sheet

38

of

61

USB3.0 Conn.

18,46
SMIB
15,35,38,46 PCH_PCIE_WAKE#
40,44,46,51 SYSON
+1.5V

+5VALW

30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

USB/B Conn.

36
35
34
33
32
31

ACES_50050-03071-001_30P

GND
GND
GND
GND
GND
GND

30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
CONN@

29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
JUSB3

29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

+5VALW

PCIE_PTX_C_DRX_P4 14
PCIE_PTX_C_DRX_N4 14
PCIE_PRX_DTX_P4 14
PCIE_PRX_DTX_N4 14
CLK_PCIE_USB30 14
CLK_PCIE_USB30# 14
USB20_N3 17
USB20_P3 17
PLT_RST_BUF# 17,35,38,40,46

OD output

USB30_CLKREQ# 14

JUSB1

(Port 0,1)

R03 modify

+3VALW
+5VALW

17
17

USB20_N2
USB20_P2

17
17

USB20_N0
USB20_P0

1
2
3
4
5
6
7
8
9
10
11
12

SYSON#

44,46 SYSON#

W=100mils

USB20_N2
USB20_P2
USB20_N0
USB20_P0

1
2
3
4
5
6
7
8
9
10
11
12

GND
GND

13
14

ACES_85201-1205N
CONN@

BT Conn.
(Port 11)
10

+BT_VCC

JBT1

GND 8
7
6
5
4
3
2
GND 1

8
7
6
5
4
3
2
1

ACES_87213-0800G
CONN@

USB20_P13 17
USB20_N13 17

(WLAN_BT_DATA)
(WLAN_BT_CLK)

BT Wire Cable Note:


Pin 3, Pin 4 NC

+3VALW
+3VS

18,38

BT_ON#

BT_ON#

1 BT@
2
R710
10K_0402_5%

C731
BT@
1U_0603_10V6K

AP2301GN-HF_SOT23-3

W=40mils

+BT_VCC

C738
BT@
0.1U_0402_16V4Z

Q41

C736
BT@
0.1U_0402_16V4Z

R709
300_0603_5%
BT@

C729
BT@

4.7U_0603_6.3V6K

C730
BT@

0.1U_0402_16V4Z
D

Q42
2
G
SSM3K7002F_SC59-3 S

BT@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

USB / BT / USBB
Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010

Sheet

39

of

61

+3VALW

65W/90W#

R701

1 100K_0402_5%

3S/4S#

R700

1 100K_0402_5%
+5VS

KSO1

R336

2 47K_0402_5%

R339

2 47K_0402_5%

R682

2 1K_0402_5%

KSO2

CLK_PCI_LPC
PLT_RST_BUF#
EC_RST#
EC_SCI#

17 CLK_PCI_LPC
17,35,38,39,46 PLT_RST_BUF#

18

EC_SCI#

EC_SMI#

R359

2 2.2K_0402_5%

R358

2 2.2K_0402_5%
@ R357
33_0402_5%
1
2

@ C462
22P_0402_50V8J
1
2

KSI[0..7]

41

Reserve for EMI please close to U44

KSI[0..7]
KSO[0..17]

41

KSO[0..17]

R361

EC_SMB_CK2
2 2.2K_0402_5%
EC_SMB_DA2
2 2.2K_0402_5%

EC_SCI#

R685

2 10K_0402_5%

R679 1

2 100K_0402_5%

PLT_RST_BUF#

50
50
14,22
14,22

EC_XCLK1

@1
C723

1
OSC

OSC

1 @
C721

INVT_PWM
FAN_SPEED1

43 FAN_SPEED1
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PWR_SUSP_LED#
WLAN_LED#

38 E51TXD_P80DATA
38 E51RXD_P80CLK
41
ON/OFF
41 PWR_SUSP_LED#
41 WLAN_LED#

X1
32.768KHZ_12.5PF_Q13MC14610002

1
R697
R769 2

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

ECAGND

PS2 Interface

SPI Device

GPIO

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

122
123

0_0402_5%

1 100K_0402_5%

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

GPI

XCLK1
XCLK0

ACOFF

V18R

83
84
85
86
87
88

R356 2

C719

1
CH751H-40PT_SOD323-2

ACIN

IMVP_IMON 55

55

R367
0_0402_5%
1
2

VR_HOT#

VR_HOT#

H_PROCHOT#_EC

H_PROCHOT# 5,50

Q26
SSM3K7002F_SC59-3

2
G

EC_MUTE# 42
GFX_CORE_PWRGD 55
WWAN_LED# 41

Latest design guide suggest change QE1 to


74LVC1G06.

TP_CLK 41
TP_DATA 41

65W/90W# 48,50
HDA_SDO 13
LID_SW# 41

EC_SI_SPI_SO
119 EC_SO_SPI_SI
120 EC_SPICLK
126 EC_SPICS#/FSEL#
128

73 EC_PECI
74 FSTCHG
R355 1
89 BATT_GRN_LED#
90
91 BATT_AMB_LED#
92 PWR_LED
SYSON
93
95 VR_ON
121 EC_ACIN
127

15,22,44,45,48

1 100P_0402_50V8J

48,50

EN_DFAN1 43
IREF
48
CALIBRATE# 48

+3VALW

EC_SI_SPI_SO 41
EC_SO_SPI_SI 41
EC_SPICLK 41
EC_SPICS#/FSEL# 41

2 43_0402_1%
FSTCHG
48
BATT_GRN_LED# 41

LID_SW#

H_PECI

R696

1 100K_0402_5%

5,18

BATT_AMB_LED# 41
PWR_LED 41
SYSON
39,44,46,51
VR_ON
55

C815

R780

EC_SPICLK

2
@
22_0402_5%

2
@
0.01U_0402_16V7K

For EMI request

PCH_RSMRST#
100 EC_LID_OUT#
101 EC_ON
102 3S/4S#
PCH_PWROK
103 BKOFF#
104
105
106
107 SA_PGOOD

PCH_RSMRST# 15
EC_LID_OUT# 14
EC_ON
41,49
3S/4S# 48
PCH_PWROK 15
BKOFF# 31

SA_PGOOD 52

108
PM_SLP_S4#
110 ENBKL
EAPD
112
VGATE
114 SUSP#
115 PBTN_OUT#
116
117
118 +V18R

PM_SLP_S4# 15
ENBKL

EAPD
42
VGATE 15,55
SUSP#
38,44,52,53
PBTN_OUT# 15

15mil
1

20mil

1 0_0402_5%

EC_ACIN

DAC_BRIG

97 65W/90W#
98 HDA_SDO
99 LID_SW#
109

KB930QF A1 LQFP 128P

D23

ADP_I

EC_MUTE#
GFX_CORE_PWRGD
WWAN_LED#
H_PROCHOT#_EC
TP_CLK
TP_DATA

124

+3VALW

1 200K_0402_5%

47,48

ECAGND
1 100P_0402_50V8J
BATT_TEMP 50

C452 2

68 EN_DFAN1
70 IREF
71 CALIBRATE#
72

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
Interface SDIDI/GPXID0

GPO

1 10K_0402_5%

MINI2_LED# 38
BEEP#
42

ACOFF

BATT_TEMP
63
64 ADP_I
65 AD_BID0
66
75 IMON_R
76

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

SPI Flash ROM

SM Bus

16

R691
100K_0402_5%

C398
4.7U_0603_6.3V6K

ECAGND

Board ID

L23
1
2
FBMA-L11-160808-800LMT_0603

Analog Board ID definition,


Please see page 3.

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
Int. K/B
KSO5/GPIO25
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

EC_XCLK1
EC_XCLK0

15 SUSCLK

+3VALW

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

SUS_PWR_DN_ACK

15 SUS_PWR_DN_ACK

15P_0402_50V8J

NC

NC

15P_0402_50V8J

77
78
79
80

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
EC_PME#
MINI1_LED#

15 PM_SLP_S3#
15 PM_SLP_S5#
18
EC_SMI#
35
EC_PME#
38 MINI1_LED#

EC_XCLK0

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

DA Output

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

+3VS

R360

AD

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

21
23
26
27

R676

MINI2_LED#
BEEP#

1 100K_0402_5%

R362

R02 modify

PWM Output

EC_SMB_DA1
EC_SMB_CK1

12
13
37
20
38

R735

EC_MUTE#

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

MISC

+3VS

10/1 ENE Recommand

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &

4.7K_0402_5%

+3VALW

1
2
3
4
5
7
8
10

18
GATEA20
18 EC_KBRST#
13
SERIRQ
13 LPC_FRAME#
13
LPC_AD3
13
LPC_AD2
13
LPC_AD1
13
LPC_AD0

0.1U_0402_16V4Z

GATEA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

4.7K_0402_5%

R364

BKOFF#

AGND

C431 2

EC_RST#

69

1 47K_0402_5%

11 GND
24 GND
35
GND
94 GND
113 GND

R328 2

+3VALW

C457
0.1U_0402_16V4Z

AVCC

VCC
VCC
VCC
VCC
VCC
VCC

U20

R363

TP_DATA

9
22
33
96
111
125

C399
1000P_0402_50V7K

C400
1000P_0402_50V7K

C720
0.1U_0402_16V4Z

CLK_PCI_LPC

C728
0.1U_0402_16V4Z

C456
0.1U_0402_16V4Z

@ R675
33_0402_5%
1
2

C418
0.1U_0402_16V4Z

TP_CLK

+3VALW_EC

@C714
@ C714
22P_0402_50V8J
1
2

L21
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA

67

R311
+3VALW
0_0805_5%
1
2

Ra
11

R354
100K_0402_5%
AD_BID0

R353
18K_0402_5%

Rb

C454
0.1U_0402_16V4Z

Issued Date

Compal Secret Data

Security Classification

2010/10/15

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED3 BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL
ELECTRONICS, INC.
2

Title

Compal Electronics, Inc.


EC ENE-KB930

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 20101

Sheet

40

of

61

1
R688

+3VALW

C722 1

2
0_0603_5%

+3VALW

CE#
WP#
HOLD#
VSS

VDD
SCK
SI
SO

8
6
5
2

MX25L1005AMC-12G_SOP8

EC_SPICLK_R
EC_SO_SPI_SI_R
EC_SI_SPI_SO_R

R698 1
R699 1
R692 1

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

ON/OFFBTN#

EC_SPICLK 40
EC_SO_SPI_SI 40
EC_SI_SPI_SO 40

EC_SPICLK_R

SW1
SMT1-05-A_4P
3
1

40

2
2

100P_0402_50V8J

100P_0402_50V8J

KSO6

C251 1

100P_0402_50V8J

C258 1

100P_0402_50V8J

C250 1

100P_0402_50V8J

C257 1

100P_0402_50V8J

C249 1

100P_0402_50V8J

C263 1
C256 1

100P_0402_50V8J

100P_0402_50V8J

C255 1

100P_0402_50V8J

C264 1

100P_0402_50V8J

C265 1

100P_0402_50V8J

C254 1

100P_0402_50V8J

C266 1
C253 1

2
2

100P_0402_50V8J
100P_0402_50V8J

KSO5

MEDIA_LED#

KSO3

C248 1

100P_0402_50V8J

C267 1
C247 1

2
2

100P_0402_50V8J
100P_0402_50V8J

C246 1

100P_0402_50V8J

C245 1
C268 1

CR_5IN1_LED# 35

PCH_SATALED# 13

KSI4
KSO2
KSO1

LED7
HT-191NB5_BLUE
+3VS

KSI5

1
2
R380
499_0402_1%

R05 modify

LED3
HT-191NB5_BLUE

100P_0402_50V8J

KSI6
KSI7

MEDIA_LED#

C269 1

100P_0402_50V8J

C270 1

100P_0402_50V8J

1 1
2 2
LEFT_BTN#
3 3
RIGHT_BTN#
4 4
5 5
6 6
7 GND
8 GND
JTP1
CONN@
ACES_85201-0605N

LED8
HT-191NB5_BLUE
WWAN_LED#

+3VS

1
2
R381 330_0402_5%

EC Request

WWAN_LED# 40

LED4
PWR_LED#

2
2
931_0402_1%

+5VS

HT-191UD5_AMBER

HT-191NB5_BLUE
LED1
2
2
820_0402_5%

1
R377

1
PWR_SUSP_LED#

PWR_SUSP_LED# 40

LED6
+3VALW

HT-191UD5_AMBER

1
R379

2
2
390_0402_5%

BATT_GRN_LED#

SW3
SMT1-05-A_4P
1

RIGHT_BTN#

BATT_AMB_LED# 40

HT-191UD5_AMBER

Q32

2
G

SW2
SMT1-05-A_4P
1

5
6

PWR_LED

5
6

40

D3
PJDLC05C_SOT23-3

BATT_GRN_LED# 40

LEFT_BTN#

BATT_AMB_LED#

2
2
820_0402_5%

LEFT_BTN#
RIGHT_BTN#

LED2
1
R376

2
2
100P_0402_50V8J 100P_0402_50V8J

TP_DATA

D4
PJDLC05C_SOT23-3
C196
0.1U_0402_16V4Z

HT-191NB5_BLUE
PWR_LED#

C216
@

C217
@

TP_CLK

WLAN_LED# 40

2
2
390_0402_5%

WLAN_LED#

+3VS

TP_CLK 40
TP_DATA 40

LED5

+3VS

PWR_LED#
ON/OFFBTN#

TP Conn.

+5VS

100P_0402_50V8J

+3VALW
LID_SW# 40

LID_SW#

MC74VHC1G08DFT2G_SC70-5

KSO0

1
R378

Q7
SSM3K7002F_SC59-3

ACES_85201-0805N
CONN@

U8

KSO4

1
R374

C252 1

KSO7

C259 1

KSI2

+3VALW

6
5

+3VS

R807
10K_0402_5%

KSO12

+3VALW

2
G

R03 modify

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
GND
GND

+3VS

100P_0402_50V8J

KSO14

KSO8

EC_ON

EC_ON

JPWR1

100P_0402_50V8J

KSI3

40,49

EMI request

100P_0402_50V8J

KSO9

@
C727
33P_0402_50V8K

27
28

KSI1

47

PWR/B
G1
G2

KSO10

51ON#

D6
CHN202UPT_SC70-3

KB Conn.

C262 1

KSO11

51ON#

R104

C260 1

KSI0

40

10K_0402_5%

KSO15

KSO13

ON/OFF

KSO17

C261 1

KSI[0..7]

KSO[0..17] 40

KSO16

2
1

KSI[0..7]
KSO[0..17]

ACES_85201-26051
CONN@

@
R695

0_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

JKB1
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

R144
100K_0402_5%

U38
1
3
7
4

+3VALW

ON/OFF BTN

EC_SPICS#/FSEL#
SPI_WP#
2 4.7K_0402_5%
2 4.7K_0402_5%SPI_HOLD#

R694 1
R690 1

2 0.1U_0402_16V4Z

+SPI_VCC

40 EC_SPICS#/FSEL#

SSM3K7002F_SC59-3

R512
100K_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

BIOS, I/O Port & K/B Connector


Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:
7

Wednesday, October 27, 2010

Sheet

41

of

61

+VDDA

BYP

1
2
C741
0.01U_0402_16V7K
@

OUT

2
1

C759 1

BEEP#

1U_0402_6.3V6K
13

R713
0_0603_5%

3
4

2
B

1
1U_0402_6.3V6K

2
2.4K_0402_1%

20mil

SPKL+
SPKL-

2SC2411K_SOT23-3

R7

R8
1

JSPK2

SPK_L+
SPK_L-

2 0_0603_5%
2 0_0603_5%

D29
CH751H-40PT_SOD323-2

1
2

3
4

D1
PJDLC05C_SOT23-3

0.1U_0402_16V4Z
1
C749

+PVDD1_HDA

HD Audio Codec

20mil

45

SPK_OUT_R-

44

2
10U_0805_10V4Z

R730
2

1
20K_0402_1%

HDA_SDIN0_AUDIO

10mil

10mil

29

30
31

SYNC
RESET#

MIC1_VREFO_R

BCLK

10

HDA_SYNC_AUDIO

13

11

HDA_RST_AUDIO#

13

HDA_BITCLK_AUDIO

19

1
39.2K_0402_1% MIC2JD
1
2
R727 40 20K_0402_1%
EAPD

R731

1
R717

LDD_CAP
GPIO0/DMIC_DATA

GPIO1/DMIC_CLK

JDREF

1
R718
1
R715

10U_0805_10V4Z

49

DGND

R720R03

modify

+MIC1_VREFO

D28
PJDLC05C_SOT23-3

R791
22K_0402_5%

SENSE A
SENSE B
EAPD

2 C757
22P_0402_50V8J

@
2
0_0402_5%

For EMI
R705
4.7K_0402_5%

EC_MUTE# 40

MIC1_R

R706

MIC1_R_1
2
1K_0603_5%

2
1K_0603_5%

CODEC_VREF

AVSS1
PVSS2
PVSS1

26
43
42

C767 1

C768 1
Place next

MIC1_R_R

220P_0402_50V7K

2 0.1U_0402_16V4Z

1
2

For EMI

INT_MIC_R

D16

@
PJDLC05C_SOT23-3

D25
PJDLC05C_SOT23-3

SINGA_2SJ-A960-C01
CONN@

SM010004010 300ma 70ohm@100mhz DCR 0.3


R394

220P_0402_50V7K

+INTMIC_VREFO

15mil
10K_0402_5%

PJ2
@ JUMP_43X39
1 1
2 2

PJ3
@ JUMP_43X39
1 1
2 2
PJ5
@ JUMP_43X39
1 1
2 2

PJ4
@ JUMP_43X39
1 1
2 2
PJ6
@ JUMP_43X39
1 1
2 2

GNDA

INT_MIC_L

1
2
FBMA-L11-160808-800LMT_0603

C500
220P_0402_50V7K

Issued Date

2010/10/15

1
2

1
2

G1
G2

ACES_88266-02001
CONN@

Compal Electronics, Inc.

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

JMIC2

3
4

Compal Secret Data

Security Classification

Int. MIC

15mil
L24

PJ1
@ JUMP_43X39
1 1
2 2

GND

4
MIC_PLUG#

C733

R03 modify

AGND

GNDA

2 10U_0805_10V4Z
pin27
@

INT_MIC_L

GND

JMIC1

1
2

MIC1_L_R

C732

10mil

MIC JACK

R708
4.7K_0402_5%

27

VREF

SPDIFO

GND
ALC271X-GR_QFN48_7X7

FBMA-L11-160808-800LMT_0603
L45
1
2
L44
1
2
FBMA-L11-160808-800LMT_0603

MIC1_L_1

R707

20
37

MONO_OUT
AVSS2

DVSS

D27
CH751H-40PT_SOD323-2

D26
CH751H-40PT_SOD323-2

12

PCBEEP

CPVEE

22K_0402_5%

13

MONO_IN

2 2.2U_0402_6.3V6M
10mil 34
SENSE_A
SENSE_B
13
2
18
20K_0402_1%
47
2
0_0402_5%
48

1
C746

MIC1_L

PD#

2
G

Q43
BSS138_NL_SOT23-3 S

MIC1_VREFO_L
1

28

13

1 R721
2
33_0402_5%
HDA_SDOUT_AUDIO
13

SDATA_OUT

CBP
MIC2_VREFO

HDA_SDIN0

COM_MIC

33

HPOUT_R
CBN

C758

HP_PLUG#
MIC_PLUG#

36

10mil
+MIC1_VREFO
+INTMIC_VREFO

C760 1

HP_RIGHT

MIC1_R

MIC_PLUG#
HP_PLUG#

C755
2.2U_0402_6.3V6M
2
+MIC2_VREFO

R722
2.2K_0402_5%

32

HPOUT_L

SDATA_IN

Internal MIC
External MIC

35

HP_LEFT

22
4.7U_0603_6.3V6K

MIC2JD
SPKR-

MIC1_L

Combo MIC

21

LINE1_R

SPK_OUT_R+

CONN@

SPKR+

C762 1

4.7U_0603_6.3V6K
MIC1_C_R

LINE1_L

SINGA_2SJ2326-001111
+MIC2_VREFO

SPKL-

41

MIC1_R

46

SPK_OUT_L-

SPK_OUT_L+

MIC2_L
MIC2_R

SPKL+

40

External MIC

MIC1_C_L

35mA

16

24
C763 1

68mA 600mA

17

4.7U_0603_6.3V6K

23

MIC1_L

LINE2_R

4.7U_0603_6.3V6K
MIC2_C_R

15

2
4

2
2

MIC2_C_L
4.7U_0603_6.3V6K

HP_PLUG#

C765 1
C764 1

LINE2_C_R
4.7U_0603_6.3V6K

JHP1
3
6

2
R719

2
2

R714 1

COM_MIC_R
1
1K_0402_5%

COM_MIC

C770 1
C769 1

LINE2_L

DVDD

1
1K_0402_5%

2
R726

14

R716 1

Combo MIC

INT_MIC

DVDD_IO

Internal MIC

INT_MIC_R

HP_LEFT

Headphone Out

2
C747
COM_MIC
330P_0402_50V7K
1

FBMA-L11-160808-800LMT_0603
L49
HPOUT_L_2
2 75_0603_5% HPOUT_L_1
1
2
L47
HPOUT_R_2
HPOUT_R_1
1
2
2 75_0603_5%
FBMA-L11-160808-800LMT_0603

HP_RIGHT

PVDD2

U41

LINE2_C_L

PVDD1

Place near Pin25, 38

39

2
0.1U_0402_16V4Z
25

2
2
0.1U_0402_16V4Z
Place
near Pin1, 9

C752

C751
330P_0402_50V7K

0.1U_0402_16V4Z
2

C772

1
C753

1
C761

38

C756
10U_0805_10V4Z

1
C754

AVDD1

+3VS
L48 2
1
BLM18AG121SN1D_0603

10U_0603_6.3V6M

+AVDD_HDA

10mil

0.1U_0402_16V4Z
1

AVDD2

+3VS_DVDD

SM010030010 200ma 120ohm@100mhz DCR 0.2


L51 2
1
BLM18AG121SN1D_0603

Singatron 2SJ2326
DC021007151

SM010030010 200ma 120ohm@100mhz DCR 0.2

10mil

Place near Pin39

+VDDA

G1
G2

C750
10U_0805_10V4Z

1
2

ACES_88266-02001
CONN@

2
L50 2
1
FBMA-L11-201209-221LMA30T_0805

MONO_IN

1
R729

Q44
E

SM010014520 3000ma 220ohm@100mhz DCR 0.04


+VDDA

G1
G2

R723

560_0402_5%

R724
2
21
560_0402_5%
1U_0402_6.3V6K

Place near Pin46

1
2

ACES_88266-02001
CONN@

C771 1

PCH_SPKR

1
2

D2
PJDLC05C_SOT23-3

JSPK1

SPK_R+
SPK_R-

40

+PVDD_HDA

20mil

20mil

2 0_0603_5%
2 0_0603_5%

2
1U_0402_6.3V6K

C766

+PVDD_HDA

0.1U_0402_16V4Z
1
C748

C745
10U_0805_10V4Z
@

R46 1
R47 1

R728
10K_0402_5% 10K_0402_5%

L46 2
1
FBMA-L11-201209-221LMA30T_0805
@

SPKR+
SPKR-

R725

SM010014520 3000ma 220ohm@100mhz DCR 0.04

C739

D30
CH751H-40PT_SOD323-2

(output = 300 mA)


D

+VDDA

R712
10K_0402_5%

+3VS

4.75V

SHDN

G9191-475T1U_SOT23-5
@

GND

Int. Speaker Conn.

40mil

IN

+VDDA

U40

60mil
0.1U_0402_16V4Z

2
0_0805_5%

C737

1
R711

+5VS

Title

HD Audio Codec ALC271X


Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 20101

Sheet

42

of

61

H17
H_3P0

H16
H_3P0
@

H18
H_3P0
@

H15
H_3P0

H14
H_3P0

H13
H_3P0

H12
H_3P0

H11
H_3P0

H7
H_3P4

H6
H_3P4

H20
H_4P0

H19
H_4P0

FAN1 Conn

H10
H_3P0

H5
H_3P4

H4
H_3P4

H9
H_3P0

H8
H_3P0

JUSB3 Stand-Off

H3
H_3P4

H2
H_3P4

H1
H_3P4

FAN Stand-Off

+5VS

10U_0805_10V4Z
2

APL5607KI-TRG_SO8

+3VS

R489
10K_0402_5%

40mil
+VCC_FAN1

FAN_SPEED1

C579
1000P_0402_50V7K

H26
H_3P0N

H27
H_3P5X3P0N

JFAN1

1
2
3
ACES_85205-03001
CONN@

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Issued Date

FD4

FD2
@

FD3

FD1

40

H25
H_7P0N

C587
1000P_0402_50V7K
1
2

C585
10U_0805_10V4Z
1
2

C598
0.1U_0402_16V4Z

H24
H_4P2

H23
H_4P2

1
300_0402_5%

2
R509

H22
H_4P2

H21
H_4P2

8
7
6
5

EN_DFAN1

GND
GND
GND
GND

+VCC_FAN1

40

EN
VIN
VOUT
VSET

U30

1
2
3
4

C580
1

2010/10/15

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

FAN & Screw Hole


Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010

Sheet

43

of

61

+5VALW

+5VALW TO +5VS

+1.5V

+1.5VS

1
3

5
4

ACIN

15,22,40,45,48 ACIN

Q15B
DMN66D0LDW-7_SOT363-6

SUSP

R268
510K_0402_5%

Q19B
DMN66D0LDW-7_SOT363-6

Q19A
DMN66D0LDW-7_SOT363-6

Q15A
DMN66D0LDW-7_SOT363-6

1.5VS_GATE

1
2
R269
200K_0402_5%

2
G

R251
10K_0402_5%

2SUSP

C380
0.1U_0603_25V7K

10mil
+VSB

C470
0.1U_0603_25V7K

Q27A
DMN66D0LDW-7_SOT363-6

38,40,52,53 SUSP#

20mil
2 SUSP

5VS_GATE

SUSP

SUSP

38,52,53

R245
470_0603_5%

2
1

C338
1U_0603_10V6K

C339
10U_0805_10V4Z

1
2
3

8
7
6
5

C376
0.1U_0402_16V4Z

R382
470_0603_5%

C377
0.1U_0402_16V4Z

C374
10U_0805_10V4Z

C375
10U_0805_10V4Z

SUSP

C469
1U_0603_10V6K

10mil

1
2
R372
20K_0402_1%

+VSB

C468
10U_0805_10V4Z

20mil

+5VS

U22
DMN3030LSS-13_SOP8L-8
8
1
7
2
3
6
5

C464
10U_0805_10V4Z

C465
10U_0805_10V4Z

R246
100K_0402_5%

U12
AO4430L_SO8

+5VALW
1

+1.5V to +1.5VS

Q21
@
SSM3K7002F_SC59-3

+5VALW
2

R383
100K_0402_5%

+3VALW TO +3VS

39,46 SYSON#

+3VALW_PCH

R614

SUSP

Q25A
DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

R373
100K_0402_5%

40mil

1
0_0805_5%

C463
0.1U_0603_25V7K

+3VALW

Q27B

SYSON

10mil
3VS_GATE

SUSP

39,40,46,51 SYSON

R369
470_0603_5%

C701
10U_0805_10V4Z

+VSB

6 1

R368
47K_0402_5%
1
2

20mil

C461
10U_0805_10V4Z

+3VALW TO +3VALW_PCH(PCH AUX Power)


C458
1U_0603_10V6K

C459
10U_0805_10V4Z

C460
10U_0805_10V4Z

+3VS

U21
DMN3030LSS-13_SOP8L-8
8
1
7
2
3
6
5

+3VALW

5
3

Q25B
DMN66D0LDW-7_SOT363-6

+5VALW TO +5VALW_PCH(PCH AUX Power)

+5VALW_PCH

+5VALW

R197

Q5
SUSP
2
G
SSM3K7002F_SC59-3

11

1 1

Q23 SUSP
2
G
SSM3K7002F_SC59-3

@ R365
470_0603_5%

R508
470_0603_5%
D

Q34SUSP
2
G
SSM3K7002F_SC59-3

+1.5V

R29
470_0603_5%

R366
22_0603_5%
4

+1.8VS

+1.05VS_VTT

+0.75VS

0_0603_5%

Q24
@
SYSON#
2
G
SSM3K7002F_SC59-3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

DC Interface
Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010

Sheet

44

of

61

+1.05VS_VTT to +1.05VSDGPU for GPU

DIS@

10mil

DIS@

R406
470_0603_5%
DIS@

+1.8VSDGPU

2 VGA_ON#

C530
DIS@
0.1U_0603_25V7K

ACIN

15,22,40,44,48 ACIN

DIS@ Q29B
DMN66D0LDW-7_SOT363-6

1.05VSDGPU_GATE

R410
510K_0402_5%

VGA_ON#

DIS@

DIS@ R409
510K_0402_5%
1
2

C825
2
DIS@
220U_B2_2.5VM_R35

20mil
+VSB

4A
1

C499
1U_0603_10V6K

R03 modify

1
2
3

6 1

C498
10U_0805_10V4Z

DIS@
C513
10U_0805_10V4Z

+1.05VSDGPU

+1.05VS_VTT
U25
AO4430L_SO8
8
7
6
5

S SSM3K7002F_SC59-3
@

DIS@ Q29A
DMN66D0LDW-7_SOT363-6

Q30

2
G

R140
2
0_0402_5%

14,17 DGPU_PWR_EN

VGA_ON

1
DIS@

+5VALW

DIS@
R134
100K_0402_5%

VGA_ON#

+1.5VSDGPUH to +1.5VSDGPU for GPU


U2
AO4430L_SO8

100mil(1.5A)

DIS@

AP2301GN-HF_SOT23-3

3VSdelay_gate

DIS@

DIS@
C590
10U_0805_10V4Z

1
DIS@
R514
1K_0402_5%
1
2

VGA_ON

DIS@
C603
0.1U_0603_25V7K

ME interefer,not pop!!

C817
220U_B2_2.5VM_R35
2 @

1 DIS@
C612
0.1U_0603_25V7K

R03 modify

PJ27

+1.5VSDGPUH

JUMP_43X118
C821
1U_0402_6.3V6K
4

C822
0.1U_0402_10V7K
4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

DIS@
Q35A
DMN66D0LDW-7_SOT363-6
3VSdelay_gate
2

PJ28

JUMP_43X118
+1.5V

2
R519
1K_0402_5%

DIS@
DMN66D0LDW-7_SOT363-6
Q35B

DIS@
R511
470_0603_5%

6 1

DIS@
R515
100K_0402_5%

3
Q33

VGA_ON#
2
Q3A
DIS@
DMN66D0LDW-7_SOT363-6

+1.5VSDGPUH

+3VALW

Q4
SSM3K7002F_SC59-3
@

2
1

DIS@
C602
10U_0805_10V4Z

2
G

C29
DIS@
0.1U_0603_25V7K

+ DIS@

ACIN

R03 modify

DIS@ Q3B
DMN66D0LDW-7_SOT363-6

+3VSDGPU

@
R507
0_0805_5%
1
2

5
2

VGA_ON#

R28
510K_0402_5%

1
2
R27
510K_0402_5%
DIS@

R26
470_0603_5%
DIS@

+VSB

1.5VSDGPU_GATE

10mil

+ DIS@

Q8
SSM3K7002F_SC59-3

2
G

VGA_ON

R135
DIS@
22K_0402_5%

+3VS

C826
220U_B2_2.5VM_R35

DIS@
C7
C819
2 DIS@ 2 DIS@
10U_0805_10V4Z 10U_0805_10V4Z

C514
330U_2.5V_M_R15

C818
2 DIS@
10U_0805_10V4Z

DIS@ 1 DIS@
1

C12
1U_0603_10V6K

C823
1
0.1U_0402_10V7K

C13
10U_0805_10V4Z

+3VS to +3VSDGPU for GPU

R03 modify
1
2
3

8
7
6
5

R03 modify 20mil

C824
1U_0402_6.3V6K

51,54

+1.5VSDGPU

+1.5VSDGPUH

2009/08/17 add VGA_ON#


54 VGA_ON#

Title

DC Interface
Size Document Number
Custom

Rev

JE50-HR/SJV50-HR M/B Schematics 0.4

Date:

Wednesday, October 27, 2010

Sheet

45

of

61

GND

2 2

+1.05VR

R603 1 USB30@2 10K_0402_5%


J2
@ R604 1
2 100_0402_1%
J1
SMI_R
R602 1 USB30@2 10K_0402_5%
H1
SMIB_R
R605 1
@
2 0_0402_5%
18,39
SMIB
P4
R600 1 USB30@2 0_0402_5%
+3V_USB3.0
P5
R611 1 USB30@2 10K_0402_5%
SPI_CLK_USB
1 1 2 2
D21
M2
SPI_CS_USB#
1SS355TE-17_SOD323-2
USB_SO_SPI_SI
N2
1
N1
USB_SI_SPI_SO
USB30@
M1
USB30@
2
K13
K14
J13
+3V_USB3.0

C702
1U_0603_10V6K

C14
+3V_USB3.0
USB3_XT1
USB3_XT2

PERSTB
PEWAKEB
PECREQB

AUXDET
PSEL
SMI
SMIB

@ R703
47K_0402_5%

P6

SPI_CS_USB#
USB_SI_SPI_SO

USB30@

+3V_USB3.0

R665
100_0402_1%

Y5

Place as close as
possibile to
U3.N14 and U3.M14

24MHZ_12PF_X5H024000DC1H
1
C709
USB30@
12P_0402_50V8J
1
USB30@
C707
2
12P_0402_50V8J
USB30@
2

Pin compare table for support USB remote wakeup or not

Support USB
remote wakeup
Not support USB
remote wakeup

AUXDET(Pin J2)

CSEL(Pin P6)

CLK

pull high
10k to VDD33

Tied to GND

Must use 24MHz crystal: mount


Y1,R19,C40,C41

Tied to GND
5

pull high
to VDD33

22

Can use either 48MHz or 24MHz When


use 48MHz clock: mount R22,R25

R659 1 @

D7

U2DP2
U3RXDP2

Can be attach to EC, either.

OCI2B
OCI1B

PCI Express/ExpressCard select signal


1:others
0:Express Card or Mini card

PPON2
PPON1

PONRSTB

U3TXDP1
SPISCK
SPISCB
SPISI
SPISO

GND
GND
GND

U3TX_C_DP2
B6
U3TX_C_DN2
A6U2DN2_L
N8
U2DP2_L
P8U3RXDP2_L
B8
U3RXDN2_L
A8

B10
A10
N10

U2DP1
U3RXDP1

P10
B12

RREF
U2AVSS
GND

U3AVSS

U2DN2
4 4

U3RXDP2
4 4

R683 1 @

A12

P12
N12

N11

2 0_0402_5%

2 0_0402_5%

D24

I/O4 6
+USB3_VCCA
5
REF1 REF2
U2DP2
I/O2
I/O3 4

I/O1

U2DN2

C7050.1U_0402_10V7K
U3TXDP2_L
USB30@
2
U3TXDN2_L
1
2
USB30@
C7060.1U_0402_10V7K

PJUSB208H_SOT23-6
@

For ESD request

R03 modify

+3V_USB3.0

U3TXDP2

U3TXDP2

D34

U3RXDP2

R307 1 USB30@2 10K_0402_5%


R308 1
2 10K_0402_5%
USB30@

U3RXDN2

10
U3TXDN2

9
U3RXDP2

7U3RXDN2

3
8

R03 modify
R786
1 USB30@2 0_0402_5%
R787
1 USB30@2 0_0402_5%

R788
1 USB30@2 0_0402_5%
R789
1 USB30@2 0_0402_5%
39,44 SYSON#
R298
1.6K_0402_1%
1
2
USB30@
17

W=60mils

U17

C432
0.1U_0402_10V7K
1
2

1
2
3
4

GND
VIN
VIN
EN

8
7
6
5

VOUT
VOUT
VOUT
FLG

OCI2B

1 @
2
0_0402_5% R313

AP2301MPG-13_MSOP8

U2DN2

USB20_N1

1 @

D6

2
0_0402_5%
USB20@
1 1

R687
L52
2 2

USB20_P1

P14
P11
P9
P7
P2
P1
N13
N9
N7
N3
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
L12
L11
L7
L6

USB30@
RCLAMP0524P.TCT~D
+USB3_VCCA

+5VALW

Resister

4
U2DP2

WCM-2012-900T_0805
1 @
2
overlap
with 0_0402_5%
L52
R686

1
+

2
+USB3_VCCA
U2DN2
U2DP2

JUSB5

1
2
3
4

5
6
7
8

VCC
DD+
GND

+USB3_VCCA

R03 modify

USB20@ USB_OC1# 17
R314 2
B
0_0402_5%

C417
@
0.1U_0402_16V4Z

GND1
GND2
GND3
GND4
SUYIN_020173GB004M25MZL
CONN@

USB2.0 Conn
PN: SP060004B00

Compal Secret Data


2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

WCM-2012-900T_0805

For USB2.0 ESD request

Issued Date

USB30@
U3RXDN2
1 1

R657 1 @

CSEL

UPD720200AF1-DAP-A_FBGA176~DSecurity Classification
USB30@

OCE2012120YZF_0805

R03 modify

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

U2DN2_L

XT1
XT2

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

USB30@
U2DP2
1 1

H14
J14

U3TXDN1
U2DM1

U3RXDN1

U3TXDN2
OCI2B
G14
OCI1B
H13

L43

2 0_0402_5%

L41

U3RXDN2_L

2 0_0402_5%

2 0_0402_5%

R658 1 @

USB30@U3RXDP2_L
USB30@ USB30@ USB30@

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

2 2

C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4

USB30@

R680 1 @
U2DP2_L

C391
470P_0402_50V7K

R634
0_0402_5%

MX25L5121EMC-20G_SO8
USB30@
USB3_XT1
USB3_XT2

A1
A2
A3
A4
A5
A7
A9
A11
A13
A14
B3
B4
B5
B7
B9
B11
B13
B14
C1
C2
C3
C10
C11

U3TXDP2
4 4

For EMI request

C390
150U_B2_6.3VM_R35M

1
2
3
4

17

R628
0_0402_5%

CS#
SO
WP#
GND

VCC
NC
SCLK
SI

U39

8
7
6
5

N14
M14

+3VA_USB3.0
L22
BLM18AG601SN1D_2P
1
2
1
USB30@
C422
10U_0805_10V4Z
USB30@
2

R704
C725
10K_0402_5%
0.1U_0402_10V7K USB30@
USB30@

P13

U3TXDN2
U2DM2

U2PVSS

+3V_USB3.0
B

SPI_CLK_USB
USB_SO_SPI_SI

U2AVDD10

U3AVDO33

H3
H4
L5

H11
K11
K12
L8
VDD10
VDD10
VDD10
VDD10

VDD10
VDD10

VDD10
VDD10
VDD10

E3
E4

E11
E12

C4
C5
C6
C7
D5

C8
C9
D8
D9
VDD10
VDD10
VDD10
VDD10

VDD10
VDD10

U3TXDP2

As short as possible

USB30@

USB30@

U3RXDN2
H2
K1
K2

U3TXDP2_L

+3V_USB3.0

VDD10
VDD10
VDD10
VDD10
VDD10

N4
N5
N6
P3
VDD33
VDD33
VDD33
VDD33

L13
L14
VDD33
VDD33

L9
L10
VDD33
VDD33

F3
G3
G4
VDD33
VDD33
VDD33

D10
F13
F14
VDD33
VDD33
VDD33

PERXP
PERXN

11

+3VA_USB3.0

SPEC Max:+3V---200mA;+1.05V---800mA
Idle mode:0.489W:
+3V---43mA;+1.05V---328mA
D3 mode:0.066W:
+3V---5.4mA;+1.05V---45mA

PETXP
PETXN

0.1U_0402_10V7K

14 USB30_CLKREQ#_L
+3V_USB3.0

F2
F1

PECLKP
PECLKN

0.01U_0402_16V7K
0.1U_0402_10V7K

OD output

R606 1 USB30@2 0_0402_5%


R601 1 USB30@2 0_0402_5%
USB30_CLKREQ#_L

D2
D1

C389

17,35,38,39,40 PLT_RST_BUF#
15,35,38,39 PCH_PCIE_WAKE#

B2
B1

C366
C367

GND

0.01U_0402_16V7K

1
5

VIN
VOUT
VIN/CE VOUT

2 0_0402_5%
USB30@
U3TXDN2
1 1

0.01U_0402_16V7K
0.01U_0402_16V7K

22

U34

RT9701-PB_SOT23-5
USB30@
14 CLK_PCIE_USB30_L
14 CLK_PCIE_USB30_L#
PCIE_PRX_C_DTX_P5
USB30@
14 PCIE_PRX_DTX_P5
PCIE_PRX_C_DTX_N5
C699 1
2 0.1U_0402_10V7K
14 PCIE_PRX_DTX_N5
C698 1
2 0.1U_0402_10V7K
USB30@
14 PCIE_PTX_C_DRX_P5
14 PCIE_PTX_C_DRX_N5

C695
C718

0.01U_0402_16V7K

1 1

0.1U_0402_10V7K

3
4

L42

7K for customer request, can use other kind


of capacitor, like Y5V.

R310
0_0805_5%
1
2

+1.05V_USB3.0

+3V_USB3.0

U19

SYSON

39,40,44,51 SYSON

+3V_USB3.0

0.01U_0402_16V7K

+3VALW

R660 1 @
U3TXDN2_L

USB30@

OCE2012120YZF_0805

USB30@
USB30@

+3VALW to +3V Transfer

C717

1 1

C368

USB30@
USB30@

C396

11

R02 modify

USB30@
C696

0.01U_0402_16V7K
0.1U_0402_10V7K

C715
C716

0.01U_0402_16V7K

USB30@ 1

C369

Vout=0.8(1+10K/32.4K)
1.042 ~ 1.0469 ~ 1.0519V
Spec: 0.9975 ~ 1.05
~ 1.1025

0.01U_0402_16V7K
0.01U_0402_16V7K

APL5930KAI-TRG_SO8
USB30@

USB30@

0.01U_0402_16V7K

1 R325
2
10K_0402_5%
1
USB30@
R326
32.4K_0402_1%
2
USB30@

C405
8P_0402_50V8D

FB

USB30@ 1

C406
0.1U_0402_10V7K

EN
POK

USB30@

USB30@

3
4

C379
0.01U_0402_16V7K

8
7

VOUT
VOUT

C386
8P_0402_50V8D

USB30@ USB30@

VCNTL
VIN
VIN

C419
10U_0603_6.3V6M

SYSON
1
2
R327 5.1K_0402_1%
USB30@

USB30@USB30@

+3VA_USB3.0

C382
0.01U_0402_16V7K

+3VA_USB3.0

C397
0.1U_0402_10V7K

6
5
9

+5VALW

Close to U3.P13

C370
C401

U18

+1.5V

Close to U3.D7
+1.05V_USB3.0

C697

+5VALW

C402
10U_0603_6.3V6M

C420
1U_0603_10V6K

+1.5V

+1.05VR

+3V_USB3.0

+1.5V to +1.05V Transfer


+5VALW

EPAD

Title

USB3.0 PD720200
Size Document Number
Custom
Date:

Wednesday, October 27, 2010

Rev
0.4
1

Sheet

46

of

61

VIN

PL1
SMB3025500YA_2P
1
2

@ PJP1
ACES_50305-00441-001

1
2
3
4
GND
GND

PJ7

+3VALWP

+3VALW

1
PC3
100P_0402_50V8J

PC4
1000P_0402_50V7K

PC2
100P_0402_50V8J

PC1
1000P_0402_50V7K

JUMP_43X118

PJ9

+5VALWP

+VCCSAP

+5VALW

PJ10
+VCCSA

JUMP_43X118

JUMP_43X118

PJ30

JUMP_43X39
PD9
PJSOT24CH_SOT23-3
VIN

+1.8VSP

PD2
LL4148_LL34-2
1
2

2
1

1
2

41

51ON#

VS

+1.5VP

PJ15

+1.5V

+VSBP

PJ16

+VSB

JUMP_43X39

JUMP_43X118

1
@

PC6
0.1U_0603_25V7K

PJ17

@
1

JUMP_43X118

+1.05VS_VCCPP

PJ19

PR4
22K_0402_5%

+1.05VS_VTT

+VGFX_COREP

PJ20

+VGFX_CORE

JUMP_43X118

JUMP_43X118

PJ18

JUMP_43X118

1
PR3
100K_0402_5%

PC5
0.22U_0603_25V7K
1
2

N1

PJ14

JUMP_43X118
PR2
68_1206_5%

PR1
68_1206_5%

PQ1
TP0610K-T1-E3_SOT23-3

+1.8VS

JUMP_43X118

PD1
LL4148_LL34-2

BATT+

PJ12

PJ26

JUMP_43X118
@

+1.5VSDGPUP

B+

PR11
1K_1206_5%
1
2

100K_0402_5%

PR8
1K_1206_5%
1
2

+1.5VSDGPU

PR10
1

+3VLP

PR9
1

1 PR5
2
0_0603_5%

PQ2
TP0610K-T1-E3_SOT23-3

LL4148_LL34-2
PD3
1

100K_0402_5%

+CHGRTC

PR7
1K_1206_5%
1
2

PJ25

JUMP_43X118

PreCHG
VIN

PR12
1K_1206_5%
1
2

12

PR13
100K_0402_5%

2
49

+5VALWP

PD4

ACOFF

BAS40CW_SOT323-3

PQ3
PDTC115EU_SOT323-3

PQ4
PDTC115EU_SOT323-3

PBJ1

+RTCBATT
1 PR252

560_0603_5%

40,48

1 PR253

+RTCBATT

560_0603_5%
@

ML1220T13RE
@

Compal Secret Data

Security Classification
Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PWR DCIN / Pre-charge

Size Document Number


Custom

Rev

JE50-HR/SJV50-HR M/B Schematics0.4

Date:

Wednesday, October 27, 2010

Sheet

47

of

61

EN

CSON

22

CELLS

CSOP

21

ICOMP

CSIN

20

CP mode
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=1.502V, Iinput=4.07A

CSIP

19

PC182
10U_0805_25V6K

LX_CHG

ICM

PHASE

18

VREF

UGATE

17

CHLIM

BOOT

16

5
6
7
8

DH_CHG

PR37
0_0603_5%
BST_CHG
1

PC23
0.1U_0603_25V7K
BST_CHGA
2
1
2

10

ACLIM

VDDP

15

LGATE

14

DL_CHG

11
12

VADJ
GND

PGND

6251VDD
2

PR41
4.7_0603_5%

13

BATT+
1

4 PR34
0.02_1206_1%
3

PD8
RB751V-40_SOD323-2

6251VDDP

<40,41>

TCR=50ppm / C
PL2
10UH_PCMB104T-100MS_6A_20%
CHG
1
2

5
6
7
8

PC26
10U_1206_25V6M
1
2

VCOMP

1
PR30
20_0402_5%
2
PR32
2_0402_5%

PQ16
AO4466L_SO8

PC28
4.7U_0603_6.3V6M

2
G
PQ18
2N7002W -T/R7_SOT323-3

40 CALIBRATE#

ISL6251AHAZ-T_QSOP24
S

1
2
PR44
15.4K_0402_1%

CC=0.6~4.48A

6251VDD

CV mode

Charging Voltage
(0x15)

12.60V

1
PR46
47K_0402_5%

PR47
10K_0402_1%

IREF=0.43V~3.24V
2

12600mV

PR48
10K_0402_1%
1
2

ACIN

15,22,40,44,45

PACIN

PR49
14.3K_0402_1%

Ki
Vchlim=Iref*(PR374/(PR372+PR374))
=Iref*(100K/(80.6K+100K))
=Iref*0.5537
Ichanrge=(165mV/PR369)*(Vchlim/3.3V)
=(165m/20m)*(1/3.3V)*Iref*0.5537
=1.3842*Iref
Iref=0.7224*Ichanrge =>Ki=0.7224

ACPRN

2
PQ19
PDTC115EU_SOT323-3

Kv
Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K
R=514K//31.6K//(15.4K+3k)=11.372K
r=514K//514K//31.6K=28.14K
Vcell=0.175*Vadj+3.99v
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K))
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv
A=Vref*(R/(R+514K))=0.052
Kv=9.451

PQ15
AO4466L_SO8

PR35
4.7_1206_5%

IREF=0.7224*Icharge

PC181
1
2
10U_0805_25V6K

CSOP

PR45
31.6K_0402_1%

Normal 3S LI-ON Cells

40,50 65W/90W#

BATT Type

CSON

1
PC18
0.047U_0402_16V7K
1
2
PR29
20_0402_5%

PC21
0.1U_0603_25V7K
1

6251aclim

PC14
1000P_0402_25V8J
1
2

PR28
20_0402_5%

PC17
2200P_0402_50V7K

23

PQ12
2N7002W -T/R7_SOT323-3

0.1U_0603_25V7K
ACPRN 49

12.1K_0402_1%

PQ17
PDTC115EU_SOT323-3

ACSET ACPRN

2
G

PC25
10U_1206_25V6M
1
2

ACPRN

PC15
1
2

DCIN

ACOFF

PR40

ACOFF

40,47

6251VREF

PR21
100K_0402_5%

PC27
680P_0402_50V7K

PR39
100K_0402_1%

ADP_I

1
PR43
20K_0402_1%

IREF

PR36
80.6K_0402_1%
1
2
1

40

40,50

PR38
47K_0402_5%
1
2

24

PR31

10K_0402_1%
0.01U_0402_25V7K
1
2
PR33 100_0402_1%
1
2
6251VREF
PC22 .1U_0402_16V7K

1 2
1
PR42
2.55K_0402_1%

PC24
0.01U_0402_25V7K
1
2

5
G

PACIN

DCIN

PQ9
PDTC115EU_SOT323-3

PC19 6800P_0402_25V7K
1
2

PC20
1
2

V1

PR15
10K_0402_1%

PQ14B
DMN66D0LDW -7_SOT363-6

VIN

PR23
14.3K_0402_1%

PQ14A
DMN66D0LDW -7_SOT363-6

ACSETIN
6251_EN

VDD

3S/4S#

PR16
47K_0402_1%
2

ACSETIN

40

PQ10
PDTC115EU_SOT323-3

PQ13
PDTC115EU_SOT323-3

1
2

PR26

PR27
150K_0402_1%

6
2
G

PR25 47K_0402_5%
1
2

6251VDD

PD5
RB751V-40_SOD323-2

PU1
100K_0402_1%

V1

PQ8
PDTA144EU_SOT323-3

PR24
0_0402_5%
1
2

FSTCHG

2
6251VDD

47K

40

PR18
191K_0402_1%

VIN PreCHG

47K

PC8
10U_1206_25V6M
1
2

CSIP

PR22
10_1206_5% 1
1
2

PR17
200K_0402_1%

B+

CSIN

PC11
2200P_0402_25V7K
1
2

PL22
1.2UH_1127AS-1R2N_2.4A_30%
1
2

3
2
1

PC7
5600P_0402_25V7K
1
2

1
2

PC12
0.1U_0603_25V7K

1
PR19
200K_0402_1%

8
7
6
5

1
2
3

CHG_B+

B+

PR14 0.02_2512_1%

8
7
6
5

P3

PQ7
AO4407A_SO8

1
2
3

1
2
3

PC181 and PC182 reserve for EMI Isen solution

CP = 85%*Iada ; CP = 4.07A

P2

PQ6
AO4407A_SO8

8
7
6
5

PQ5
AO4407A_SO8

3
2
1

ADP_I = 19.9*Iadapter*Rsense

PC13
2.2U_0603_6.3V6K
1
2

Iada=0~4.74A(90W/19V=4.736A)

VIN

PC9
10U_1206_25V6M
1
2
PC10
0.1U_0603_25V7K
1
2

Compal Secret Data

Security Classification
Issued Date

2010/10/15

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Title

Compal Electronics, Inc.


PWR-CHARGER

Size Document Number


Custom

Rev

JE50-HR/SJV50-HR M/B Schematics0.4

Date:

W ednesday, October 27,


2010
D

Sheet

48

of

61

PC29
1U_0603_10V6K

2VREF_8205

PR50
13K_0402_1%
1
2

PQ27
PDTC115EU_SOT323-3

LG_5V

5
6
7
8
3
2
1
2

NC

RT8205EGQW _W QFN24_4X4

2
3
2
1

2VREF_8205

PC47
4.7U_0805_10V6K

VL

Typ: 175mA

+5VALWP

1
PC43

18

17

19

@ PR60
4.7_1206_5%

LGATE1

@ PC45
680P_0402_50V7K

LGATE2

PL5
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2

5
6
7
8

12

VREG5

LG_3V

VIN

LX_5V

16

PC38
0.1U_0603_25V7K
1
2

1
ENTRIP1

FB1

REF

4
TONSEL

5
FB2

20

13

PC35
4.7U_0805_25V6-K
1
2

ENTRIP1

ENTRIP2

UG_5V

PHASE1

PR57 PC41
0_0603_5% 0.1U_0603_25V7K
2
1
21

220U_6.3VM_R15

TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)


(2)SMPS2=375KHZ(+3VALWP)

+3.3VALWP
Ipeak=5.78A ; 1.2Ipeak=6.94A; Imax=4.05A
f=375KHz, L=4.7UH
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.716A
Vlimit=10*10^-6*110Kohm/10=0.11V
Ilimit=0.11/(18m*1.2)~0.11/(15m)=6.34A~9.13A
Iocp=7.06A~9.85AA (7.06A>6.94A -> ok) -DVT-

+5VALWP
Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
f=300KHz, L=4.7UH,Rentrip=154k ohm
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
Vlimit=10*10^-6*154Kohm/10=0.15V
Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A
Iocp=8.44~11.57A (8.44>8.4 -> OK)

1
2

PC49
2.2U_0603_6.3V6K

EC_ON

Compal Secret Data

Security Classification

2010/10/15

Issued Date

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

40,41

PR66
100K_0402_1%

1
2
PR67
40.2K_0402_1%

1
2
G

21

PHASE2

50

AO4712_SO8
PQ23

PQ24B
DMN66D0LDW -7_SOT363-6

PQ25
PDTC115EU_SOT323-3

VS

UGATE1

11

RT8205_B+

PR64
100K_0402_1%
1
2

2N7002W -T/R7_SOT323-3
PQ26

ACPRN

UGATE2

PR63
0_0402_5%
1
2

VL

48

5
G

BST_5V

10

2
PC48
0.1U_0603_25V7K

3
G

PQ24A
DMN66D0LDW -7_SOT363-6

PR65
200K_0402_5%
1
2

VFB=2.0V

PQ21
AO4466L_SO8

SPOK

LX_3V

PC46
1U_0603_10V6K
1
2

ENTRIP2

ENTRIP1

MAINPWON

22

PR59 @
0_0402_5%
1
2

B+

50

23

BOOT1

PR61
499K_0402_1%
1
2

PR62
100K_0402_1%

PGOOD

BOOT2

1
2
3

VREG3

GND

8
7
6
5

@ PR58
4.7_1206_5%
1
2

MAINPW ON

@ PC44
680P_0402_50V7K
1
2

PQ22
AO4712_SO8

VO1

RT8205_B+

24

VO2

15

PC40
0.1U_0603_25V7K

4.7UH_PCMC063T-4R7MN_5.5A_20%
PL4
1
2

PC42
220U_6.3V_M

PR56
BST_3V
2
21
0_0603_5%
UG_3V

PR55
154K_0402_1%
2

SKIPSEL

P PAD

14

1
2
3

+3VALWP

ENTRIP2

PU2

25

PR54
110K_0402_1%
1
2

PQ20
AO4466L_SO8

+3VLP

PC39
4.7U_0805_10V6K

8
7
6
5

PC34
2200P_0402_50V7K
1
2

PC33
4.7U_0805_25V6-K
1
2

PC32
4.7U_0805_25V6-K
1
2

PC31
0.1U_0603_25V7K
1
2

Typ: 175mA

EN

PL3
HCB4532KF-800T90_1812
1
2

PR53
20K_0402_1%
1
2

PC36
4.7U_0805_25V6-K
1
2
PC37
2200P_0402_50V7K
1
2

PR52
20K_0402_1%
1
2

RT8205_B+
B+

PR51
30K_0402_1%
1
2

Title

Compal Electronics, Inc.


3VALWP/5VALWP

Size
Document Number
Custom

Rev

0.4
JE50-HR/SJV50-HR M/B Schematics

Date:

W ednesday, October 27, 2010

Sheet

49

of

61

PJP2
SUYIN_200275GR008G13GZR
D

10
9
8
7
6
5
4
3
2
1

EC_SMDA
EC_SMCA
TH
PI

PR68
100_0402_1%

PH1 under CPU botten side :


CPU thermal protection at 92 degree C
Recovery at 72 degree C

GND
GND
8
7
6
5
4
3
2
1

PR69
100_0402_1%

EC_SMB_DA1 40

VL

<40,41>
VMB
<40,41>
BATT+

1
PC50
0.1U_0603_25V7K

PR72
21K_0402_1%

PR71
10K_0402_1%

VL

PU3

@ PR74
100K_0402_1%
PR75
1K_0402_1%

+3VALWP

VCC TMSNS1

GND RHYST1

OT1 TMSNS2

PR76
9.53K_0402_1%

OT2 RHYST2

49 MAINPWON
BATT_TEMP 40

G718TM1U_SOT23-8 @ PR77
47K_0402_1%

PC52
0.01U_0402_25V7K

PC51
1000P_0402_50V7K

PR73
6.49K_0402_1%
1
2

1
2

PR70
1K_0402_5%

EC_SMB_CK1 40

PL6
SMB3025500YA_2P
1
2

PH1

PH2 @

100K_0402_1%_NCP15WF104F03RC

100K_0402_1%_NCP15WF104F03RC
PQ28
TP0610K-T1-E3_SOT23-3
B+

+VSBP

PC54
0.1U_0603_25V7K

PC53
0.22U_0603_25V7K

1
2
PR78
100K_0402_1%

PR79
22K_0402_1%
1
2

65W@ PR240
3.92K_0402_1%

PR80
100K_0402_1%

@
PR243
7.15K_0402_1%

PQ29
2N7002W-T/R7_SOT323-3

ADP_I 40,48

D
PQ65
2N7002W-T/R7_SOT323-3

2
G

PU13

1
2

VCC TMSNS1

GND RHYST1

PR241 90W@
16.2K_0402_1%

OT1 TMSNS2

OT2 RHYST2

65W/90W# 40,48

2
G
@
PQ66
2N7002W-T/R7_SOT323-3

5,40 H_PROCHOT#

PR239
100K_0402_1%

90W@
PR240
D
9.09K_0402_1%

PR244
10K_0402_1%

@ PR250
0_0402_5%
1
2

@ PC170
0.1U_0603_25V7K

+3VS

2
G

PR245
0_0402_5%

SPOK

49

+3VALWP
PR81
1K_0402_5%
1
2

PC55
1U_0402_6.3V6K

120W@ PR240
15.4K_0402_1%

Change 5VALW to 3VALW on DVT

VL

PR242
10K_0402_1%

G718TM1U_SOT23-8

65W@ PR241
10.5K_0402_1%

For 65W adapter==>action 70W , Recovery 54W


A

For 90W adapter==>action 97W , Recovery 75W

120W@ PR241
17.4K_0402_1%

For 120W adapter==>action 135W , Recovery 100W


Compal Secret Data

Security Classification

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PWR-BATTERY CONN/OTP

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Wednesday, October 27, 2010

Sheet

50

of

61

PL7
HCB4532KF-800T90_1812
1
2

3
2
1
10
DL_1.5V

PC57
4.7U_0805_25V6-K
1
2

PC61
330U_6.3V_M

4
1

@ PR87
4.7_1206_5%

PQ31

PC62
4.7U_0805_10V6K

@ PC63
680P_0402_50V7K

AO4456_SO8

PC64
4.7U_0603_10V6K

NC
PGND

LGATE

+5VALW

VDDP

14

11

RT8209MGQW _W QFN14_3P5X3P5

CS

+1.5VP

PGOOD

VFB=0.75V

5
6
7
8

LX_1.5V

3
2
1

FB

DH_1.5V

12

PL8
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2

13

PHASE

VDD

UGATE

PR89
15K_0402_1%

BST_1.5V

BOOT

TON
VOUT

PR88
100_0603_5%
1
2

15

1
EN/DEM

2
3

GND

PU4

@
PC60
.1U_0402_16V7K

B+

AO4406AL_SO8

PC59
PR85
0.1U_0603_25V7K
0_0603_5%
BST_1.5V-1
1
2
1
2

+5VALW

39,40,44,46 SYSON

@ PR86
47K_0402_5%

PR83
267K_0402_1%
1
2

PR84
0_0402_5%
1
2

PC56
4.7U_0805_25V6-K
1
2

PQ30

PC172
0.1U_0603_25V7K
1
2

PC173
2200P_0402_50V7K
1
2

5
6
7
8

1.5_8209_B+

<Vo=1.5V> VFB=0.75V
V=0.75*(1+10K/10K)=1.5V
Fsw=298KHz
1

Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.


Ipeak=19.53A, Imax=23.44A, Iocp=13.67A
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.63A
=>1/2Delta I=2.315A
choose Rcs=15K
Iocpmax=((15K*11uA)/0.0045)+2.315A=35.65A
Iocpmin=((15K*9uA)/(0.0056*1.3))+2.315A=23.06A
Iocp=23.06A~35.65A

2
10K_0402_1%
2

PR91
10K_0402_1%

PR90

VGA@ PL9
HCB4532KF-800T90_1812
1
2

14

VGA@ PC66
4.7U_0805_25V6-K
1
2

VGA@ PC65
4.7U_0805_25V6-K
1
2

1
2

NC

3
2
1
5
6
7
8

DL_1.5VDGPU

RT8209MGQW _W QFN14_3P5X3P5
VGA@

VGA@ PC73
4.7U_0603_10V6K

LGATE

VGA@
PC70
330U_6.3V_M

VGA@
PC71
4.7U_0805_10V6K

VGA@
PQ33
AO4456_SO8

@ PC72
680P_0402_50V7K

10

3
2
1

11

+1.5VSDGPUP

@ PR97
4.7_1206_5%

+5VALW

PGOOD

CS
VDDP

VGA@ PL10
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2

LX_1.5VDGPU

12

FB

PGND

VDD

13

PHASE

PR99
10K_0402_1%

15

VFB=0.75V

UGATE

VGA@
PQ32
AO4466L_SO8

B+

DH_1.5VDGPU

BOOT

TON
VOUT

VGA@
PR98
100_0603_5%
1
2

2
3

EN/DEM

@
PC69
.1U_0402_16V7K

GND

1
2

PU5

+5VALW

VGA@
VGA@
PR96
PC68
0_0603_5%
0.1U_0603_25V7K
BST_1.5VDGPU-1
1
2
1
2

2
1

@ PR95
47K_0402_5%

45,54 VGA_ON

4
BST_1.5VDGPU

VGA@ PC175
0.1U_0603_25V7K
1
2

VGA@
PR92
267K_0402_1%
1
2

VGA@
PR94
0_0402_5%
1
2

VGA@ PC174
2200P_0402_50V7K
1
2

5
6
7
8

1.5VDGPU_8209_B+

VGA@

VGA@
PR100
10K_0402_1%
1
2

VGA@
PR101
10K_0402_1%

<Vo=1.5V> VFB=0.75V
V=0.75*(1+10K/10K)=1.5V
Fsw=298KHz
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
Ipeak=10.4A, Imax=12.48A, Iocp=7.28A
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.63A
=>1/2Delta I=2.315A
choose Rcs=10K
Iocpmax=((10K*11uA)/0.0045)+2.315A=24.59A
Iocpmin=((10K*9uA)/(0.0056*1.3))+2.315A=15.95A
Iocp=15.95A~24.59A

Compal Secret Data

Security Classification
Issued Date

2010/10/15

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


PWR-+1.5VP/+1.5VSDGPU

Size Document Number


Custom

Rev

JE50-HR/SJV50-HR M/B Schematics0.4

Date:

W ednesday, October 27,D 2010

Sheet

51

of

61

1.8VSP
Ipeak=3.35A ; 1.2Ipeak=4.02 ;Imax=2.345A
Vout=0.6*(1+(20K/10K))=1.8V

PR105
10K_0402_1%

1
2

1
2

SY8033BDBC_DFN10_3X3

PC78
680P_0402_50V7K

PC79
0.1U_0402_10V7K

2
S

PR106
1M_0402_5%

2
G
PQ67
2N7002W-T/R7_SOT323-3

PC77
22U_0805_6.3VAM

FB=0.6Volt

PC76
22U_0805_6.3VAM

PR103
20K_0402_1%

PC75
68P_0402_50V8J
1
2

1
FB_1.8V

PR102
4.7_1206_5%

PG

TP

NC

FB
EN

+1.8VSP

PR104 100K_0402_5%

38,44,53 SUSP

SVIN

11

38,40,44,53 SUSP#

EN_1.8V

LX

PVIN

LX_1.8V

NC

LX

PC74
22U_0805_6.3VAM

PVIN

JUMP_43X118

10

PL11
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1
2

PU6

PJ22

+5VALW

PL23
HCB3225KF-151T50_1210
1
2
B+

PR107
267K_0402_1%
1
2

14
BOOT

LGATE

0_0402_5%
PR117
1

SA_PGOOD

40

PR114
1
2
0_0402_5%

2
1

@ PC85
470P_0603_50V8J

PC86
4.7U_0805_10V6K

PR118
2K_0402_1%
1
2

VFB=0.75V

PC81
4.7U_0805_25V6-K
1
2

PC84
330U_6.3V_M

2
PR113
0_0402_5%

LG_VCCSAP

RT8209MGQW_WQFN14_3P5X3P5

PC80
4.7U_0805_25V6-K
1
2

1
5
6
7
8

15
NC

VDDP

PGOOD

PQ35
AO4712_SO8

10

@ PR111
4.7_1206_5%

+5VALW

11

PC87
4.7U_0603_6.3V6K

FB

12

1
2
PR115
10K_0402_5%

CS

+3VS

+5VALW

PHASE

VDD

+VCCSAP

LX_VCCSAP

PR112
100_0603_1%
1
2

VOUT

13

PR116
15K_0402_1%

PL12
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1
2

PC82
PR109
0.1U_0603_25V7K
0_0603_5% BST_VCCSAP-1
1
2
1
2
UG_VCCSAP

UGATE

PGND

TON

GND

@ PC83
0.1U_0402_16V7K

@ PR110
47K_0402_5%

EN/DEM

53 VCCPPWRGOOD

PU7

PQ34
AO4466L_SO8

3
2
1

BST_VCCSAP

EN_VCCSAP

PR108
0_0402_5%
1
2

VSSSA_SENSE

3
2
1

PC176
0.1U_0603_25V7K
1
2

5
6
7
8

PC177
2200P_0402_50V7K
1
2

5603_VCCSAP_B+

PR119

VCCSA_SENSE

10_0402_5%
B

+3VS

PR120
15K_0402_1%

2
PR124 @
100K_0402_5%

PQ37
PMBT2222A_SOT23-3
2

VCCSA_VID1

PR125

0_0402_5%

VID[0]
0
0
1
1

VID[1]
0
1
1
1

VCCSA Vout
0.9 V
0.8 V
0.75V
0.65V

<Vo=0.9V> VFB=0.75V
V=0.75*(1+2K/10K)=0.9V
Fsw=298KHz
Cout ESR=15m ohm Rdson(max)=18 mohm Rdson(typ)=15 mohm.
Ipeak=6A, Imax=4.2A, Iocp=7.2A
Delta I=((19-0.9)*(0.9/19))/(L*Fsw)=1.31A
=>1/2Delta I=0.655A
choose Rcs=15K
Iocpmax=((15K*11uA)/0.015)+0.655A=11.48A
Iocpmin=((15K*9uA)/(0.018*1.2))+0.655A=7.27A
Iocp=7.27A~11.48A

@ PR126
10K_0402_5%

@ PC88
4700P_0402_25V7K

PQ36
2N7002W-T/R7_SOT323-3

2
G

PR122
30K_0402_1%

PR121
10K_0402_5%

PR123
10K_0402_5%
1
2

Require on 2011/ 2012 Required


Yes/Yes
Yes/Yes
No/Yes
No/Yes

Note:Use VCCSA_SEL to switch High & Low Level for VID[1]


(ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.

Compal Secret Data

Security Classification

Issued Date

2010/10/15

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PWR +VCCSAP

Size
C
Date:

Document Number

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics


Wednesday, October 27, 2010
1

Sheet

52

of

61

PU8

GND

NC

VREF

NC

VOUT

NC

TP

VCNTL

VIN

+3VALW
PC90
1U_0603_10V6K

PR127
1K_0402_1%

PC89
4.7U_0805_6.3V6K

+1.5V

+0.75VS
1

1
S

PR129
1K_0402_1%

PC93
10U_0603_6.3V6M

SUSP
2
G
PQ38
2N7002W -T/R7_SOT323-3

PQ39
2N7002W -T/R7_SOT323-3

PC92
1U_0402_6.3V6K

2
G
3

PR128
24.9K_0402_1%
1
2

38,44,52 SUSP

PC91
.1U_0402_16V7K
1
2

G2992F1U_SO8

PL13
HCB4532KF-800T90_1812
1
2

PR130
267K_0402_1%
1
2

PQ40
AO4406AL_SO8

PR131
680K_0402_5%
1
2

VDDP

10

LGATE

@ PR133
4.7_1206_5%

DL_1.05VS_VCCP

PC99
330U_6.3V_M

PR134
@ PC100
680P_0402_50V7K 0_0603_5%

RT8209MGQW _W QFN14_3P5X3P5

4
PQ41
AO4456_SO8

1
2

+5VALW

PC101
4.7U_0603_10V6K

3
2
1

PGOOD

LX_1.05VS_VCCP

11

1 2

VFB=0.75V

12

CS

+1.05VS_VCCPP

FB

PHASE

PL14
1UH_FDUE1040D-1R0M-P3_21.3A_20%

5
6
7
8

13

3
2
1

VDD

UGATE

VOUT

BOOT

NC

EN/DEM

TON

15

1
2

2
PR135
100_0603_5%
1
2

BST_1.05VS_VCCP
DH_1.05VS_VCCP

PC98
PR132
0_0603_5% 0.1U_0603_25V7K
1
2
1
2

PR136
15K_0402_1%

+5VALW

PU9
PC97
4.7U_0603_6.3V6K

PGND

PQ68
2N7002W -T/R7_SOT323-3

@ PR249
47K_0402_5%

GND

2
G

SUSP

14

4
1

38,40,44,52 SUSP#

B+

PC95
4.7U_0805_25V6-K
1
2

PC179
2200P_0402_50V7K
1
2

5
6
7
8

PC178
0.1U_0603_25V7K
1
2
PC94
4.7U_0805_25V6-K
1
2

1.05VS_51117_B+

PC102
4.7U_0805_10V6K
B

PR137
4.02K_0402_1%
1
2

PR140
10_0402_5%
1
2

52

VCCPPW RGOOD

PR139

PR138
10K_0402_1%

+3VALW

VCCIO_SENSE

10K_0402_1%

PR141 @
10K_0402_1%

<Vo=1.05V> VFB=0.75V
V=0.75*(1+4.02K/10K)=1.052V
Fsw=298KHz
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
Ipeak=12.866A, Imax=9A, Iocp=15.439A
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=3.33A
=>1/2Delta I=1.665A
choose Rcs=15K
Iocpmax=((15K*11uA)/0.0045)+1.665A=37.62A
Iocpmin=((15K*9uA)/(0.0056*1.3))+1.665A=23.02A
Iocp=23.02A~37.62A

Compal Secret Data

Security Classification

2010/10/15

Issued Date

Deciphered Date

2011/10/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PWR +1.05VS_VCCPP/+0.75VSP

Size
Document Number
Custom

Rev

0.4
JE50-HR/SJV50-HR M/B Schematics

Date:

W ednesday, October 27, 2010

Sheet
1

53

of

61

VGA@ PL15
HCB3225KF-151T50_1210
1
2

B+

B+_CORE

BST_VCORE

DH_VCORE

EN

SW

SW_VCORE

VFB

V5IN

RF

DRVL

3
2
1

1
VGA@ PR150
10_0402_5%

VGA@ PC171
470U_V_2.5VM

VGA@ PC109
680P_0402_50V7K

VGA@ PR152
0_0402_5%
1
2

VGA@ PR151
2 0_0402_5%
1
2

VGA@ PC108
470U_V_2.5VM

24

FB_GND

GCORE_SEN

GCORE_SEN 24

VGA@ PR153
1.82K_0402_1%

VGA@
PQ46
2N7002W-T/R7_SOT323-3

GS@
PR157
6.49K_0402_1%
+3VSDGPU

2
G

VGA@ PC110
.1U_0402_16V7K

Switch freq. (RF pin setting)


47K ==>450KHz
100K ==>390KHz
200K ==>350KHz (Currently setting)
470K ==>300KHz

VGA@ PR147
4.7_1206_5%

45 VGA_ON#

ESR=10mohm
VGA@
PC106
1U_0603_6.3V6M

VFB=0.6V

VGA@ PR149
10K_0402_1%
1
2

VGA_ON

TPS51218DSCR_SON10_3X3

45,51 VGA_ON

+VGA_CORE

DL_VCORE

11

VGA@
PQ45
TPCA8028-H_SOP-ADVANCE8-5
1
2
1
2

TP

VGA@
PL16
0.36UH_MMD-12CE-R36M-M1L_34A_20%
1
2

+5VALW

VGA@ PR148
200K_0402_1%

VGA@ PR144
0_0603_5%
1
2

VGA@
PQ43
TPCA8030-H_SOP-ADV8-5

10
9

3
2
1

VBST
DRVH

VGA@
PQ44
TPCA8028-H_SOP-ADVANCE8-5

1
@
PR146
10K_0402_5%

PGOOD
TRIP

VGA@ PC105
0.1U_0603_25V7K
1
2

+3VS

1
2

VGA@ PR143
0_0603_5%
1
2

VGA@ PR145
75K_0402_1%
1
2

VGA@

3
2
1

PU10

3
2
1

18 VGA_PWROK

VGA@
PQ42
TPCA8030-H_SOP-ADV8-5

5
2

@ PR142
10K_0402_5%

VGA@ PC107
10U_1206_25V6M

VGA@ PC104
10U_1206_25V6M

+3VS

VGA@ PC103
10U_1206_25V6M

VGA@ PR156
10K_0402_1%

VGA@ PC114
4700P_0402_25V7K

@ PR161
10K_0402_5%

+3VSDGPU

1
VGA@ PC115
4700P_0402_25V7K

@ PR165
10K_0402_5%

VGA@ PQ48A

VGA@ PR166
10K_0402_5%
1
2

GPU_VID1 22
VGA@ PR167
10K_0402_5%

DMN66D0LDW-7_SOT363-6

@ PR164
10K_0402_5%

VGA@ PQ47B
DMN66D0LDW-7_SOT363-6

VGA@ PR162
10K_0402_5%

VGA@ PR163
10K_0402_5%
1
2

Cout ESR=12m ohm Rdson(max)=3.2 mohm Rdson(typ)=2.6 mohm.


Ipeak=41.02A, Imax=28.714A, Iocp=43A
Delta I=((19-0.9)*(0.9/19))/(L*Fsw)=6.8A
=>1/2Delta I=3.4A
choose Rcs=75K
Iocpmax=((75K*11uA)/0.0013)+3.4A=75.52A
Iocpmin=((75K*9uA)/(0.0016*1.35))+3.4A=48.42A
Iocp=48.42A~75.52A

GV@ PR160
16.2K_0402_1%

VFB=0.7V
V=0.7*(1+Rtop/Rbottom)
Fsw=350KHz

Vtrip range ==> 0.2V ~ 3V

DMN66D0LDW-7_SOT363-6
VGA@ PQ47A
+3VSDGPU

VGA@ PR159
10K_0402_5%
1
2

GS@
PR160
8.25K_0402_1%

VGA@ PR158
10K_0402_5%

VGA@ PC113
2200P_0402_25V7K

GV@ PR157
12.4K_0402_1%

TPCA8057-H Rds=2.6m/3.2m ohm

+3VSDGPU

NVIDIA/N12P-GS

NVIDIA/N12P-GV1
D

P8/P12

0.825V(0.827V)

0.825V(0.827V)

VGA@

PQ48B

DMN66D0LDW-7_SOT363-6

0.975V(0.982V)

P0(Cold)

1.0V(1.024V)

----

0.90V(0.907V)

GPU_VID0 22
VGA@ PR170
10K_0402_5%

P0(Hot)

@ PR168
10K_0402_5%

VGA@ PR169
10K_0402_5%
1
5 2
G

11

GPU_VID0

GPU_VID1

0.925V(0.930V)
----

Issued Date

AP

Compal Secret Data

Security Classification

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


+VGA_COREP

Size Document Number


Custom
Date:

Wednesday, October 27, 2010

Rev
0.4

P5WE0
1

Sheet

54

of

61

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

PC117
220U_25V_M

GFX@ PR193
590_0402_1%

ISNG
1

100_0402_1%
@ PR192
2

@
PC137
470P_0402_50V7K

GFX@ PR178
1
24.7_1206_5%

GFX@ PC123
330U_X_2VM_R6M

GFX@ PC119
10U_1206_25V6M
1
2

GFX@ PC118
10U_1206_25V6M
1
2

1
2
1

GFX@ PC130
680P_0402_50V7K

PC139 ISPG
10U_1206_25V6M
1
2

PC138
10U_1206_25V6M
1
2

@ PC136
0.01U_0402_16V7K

+5VS

DIS@ PR195
0_0402_5%

+CPU_CORE

QC@ PR205
10K_0402_1%

1
2

QC@ PR201
10K_0402_1%
1
2

QC@ PR207
1_0402_5%

QC@ PR204
3.65K_0402_1%
1
2

VSUM+

PC140 @
PR202 @
QC@ PR199
680P_0402_50V7K
ISEN3
4.7_1206_5%
10K_0402_1%
1
2

1
1 2
2

PC146
10U_1206_25V6M
1
2

PC145
10U_1206_25V6M
1
2

PL20
+CPU_CORE
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4

PC163
10U_1206_25V6M
1
2
PC164
10U_1206_25V6M
1
2

PL17
HCB4532KF-800T90_1812

PL21
+CPU_CORE
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4

QC@ PR247
10K_0402_1%

PR238
ISEN3
10K_0402_1%
1
2

PR237
1_0402_5%
1
2

ISEN1

@ PC169
680P_0402_50V7K

PR235
10K_0402_1%
PR236
1
2
3.65K_0402_1%
VSUM+
1
2

Compal Electronics, Inc.


PWR +CPU_CORE/+VGFX_CORE

Size Document Number


Custom

Rev

0.4
JE50-HR/SJV50-HR M/B Schematics

Date:

QC@ PR246
10K_0402_1%

PR220
10K_0402_1%
1
2

PR219
1_0402_5%

1
ISEN3

PR218
3.65K_0402_1%
1
2

PR217
10K_0402_1%
VSUM+

ISEN2

1
2

@ PC154
680P_0402_50V7K

B+

1
2
Title

2011/10/15

Deciphered Date

@ PQ64
TPCA8028-H_SOP-ADVANCE8-5

3
2
1

2010/10/15

3
2
1

PQ63
TPCA8028-H_SOP-ADVANCE8-5

1 2

Compal Secret Data

Security Classification

*OCP setting value=37A

ISEN2

*OCP setting value=71.5A

PC168
0.22U_0603_10V7K
4

Issued Date

GFX@ PC132
.1U_0402_16V7K
1
2

.1U_0402_16V7K
GFX@ PC133
1
2

VSUM-

Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A


Rdson=3.6~4.5m ohm
DCR=1.1m ohm
HW output cap:
(1)22U_0805_6.3V *12
(2)470U_D2_2V
*2(ESR=4.5m ohm)

LGATE1

0_0603_5%
PR233

+VGFX_COREP

GFX@ PR184 PH4 GFX@


10K_0402_5%_TSM0A103J4302RE
7.5K_0402_1%
1 2
2
1

@ PR234
4.7_1206_5%

3
2
1

@ PQ62
TPCA8030-H_SOP-ADV8-5

5
4

BOOT1

Icc-max=53A
Rdson=3.6~4.5m ohm
DCR=1.1m ohm
HW output cap:
(1)10U_0805_4V
*10
(2)22U_0805_6.3V *15
(3)470U_D2_2V
*4(ESR=4.5m ohm)

GFX@ PR180
1_0402_5%

GFX@ 11K_0402_1%
1 PR187 2

@ PR216
4.7_1206_5%

@ PQ58
TPCA8030-H_SOP-ADV8-5

@ PQ59
TPCA8028-H_SOP-ADVANCE8-5

3
2
1
5

PHASE1

*Iccmax in Turbo Mode for SV (35W) is 53A


+CPU_CORE

TPCA8030-H_SOP-ADV8-5

3
2
1
TPCA8030-H_SOP-ADV8-5

3
2
1

5
3
2
1

2.61K_0402_1%

@PR231
@ PR231
100_0402_1%

+VGFX_COREP

5
3
2
1

3
2
1

PQ60
TPCA8028-H_SOP-ADVANCE8-5

PR223

0.068U_0402_16V7K
PR227
1
2
11K_0402_1%

PC160
1

PQ57
TPCA8030-H_SOP-ADV8-5

5
2

0_0603_5%
PR251

3
2
1

@ PC166
330P_0402_50V7K

.1U_0402_16V7K
2

3
2
1

1000P_0402_50V7K

DC@ PR229
1
2
698_0402_1%

QC@
PL19
0.36UH_PCMC104T-R36MN1R17_30A_20%
4

CPU_B+

PH6
VSUM10KB_0603_5%_ERTJ1VR103J
UGATE1
PC167
1
2

2
PC165

VSUM+

1
2
10_0402_1%

0_0603_5%
PR214 2
1
1
PC149
0.22U_0603_10V7K4

0.22U_0603_25V7K

@
2

330P_0402_50V7K
1
2

PHASE2

LGATE2

0.33U_0603_10V7K

QC@ PR229
1.24K_0402_1%

PR228
PC161

BOOT2

PC151
1
2

1U_0603_10V6K

PC152
1

ISEN1

PC156
1
2

1
10_0402_1%

(Ipeak=56A)
(Vboot=0)

0_0603_5%
PR230

4
DC@
PR212
4.32K_0402_1%

CPU_B+

1_0603_5%

PC159
1

PR222

CPU_B+

0_0603_5%
PR215
+5VS
1
2

QC@
PR212
590_0402_1%

PU12

24

23

22

20

21

18

19

17

16

13
2

@ PQ54

GFX@ PR179
10K_0402_1%

@ PQ55
TPCA8028-H_SOP-ADVANCE8-5

BOOT1
26

TPCA8028-H_SOP-ADVANCE8-5

3
2
1

3
2
1

PHASE1
28
UGATE1
27

25

2
PR200
0_0402_5%

29

3
2
1

QC@
PC131
0.22U_0603_10V7K

1
2

37
LGG

PHG
PROG1

31

@
PQ52

DC@ PR198
0_0402_5%

LGATE1
30

PR232

@
PC180
100P_0402_50V8J

PHASEG

LGATEG

38

39

BOOTG

UGG
VIN

VDD

ISUMN

ISUMP

VSEN

BOOT1

22P_0402_50V8J

330P_0402_50V7K

@
8 VCCSENSE
PR248
2K_0402_1%
8 VSSSENSE

QC@ PC129
1U_0603_10V6K

UGATEG

1
BOOTG

40

41

42
NTCG

PROG2

43

44
ISPG

ISNG

46

48

45
RTNG

FBG

VSENG

UG1
RTN

VW

QC@ PC150
0.22U_0402_6.3V6K
VSUM1
2
PC153
1
2
1
2
1
2
PC157 0.22U_0402_6.3V6K
499_0402_1%
1
2
DC@ PR225
470P_0402_50V7K
0.22U_0402_6.3V6K
PR224
1
2
2.15K_0402_1%
412K_0402_1%
1
1
2

NTC

12

PH1

+5VS

UGATE2

DC@ PC148

VSSP1

32

PR211

+CPU_CORE

QC@
PR225
3.83K_0402_1%

LG1

ISL95831CRZ-T_TQFN48_6X6

VR_HOT#

11

PGND

PC142
2.2U_0603_10V6K
1
2

IMON

ISEN3

PC147
1000P_0402_50V7K

PR213
8.06K_0402_1%

47

PGOOD

PC162
1
2

PC143
47P_0402_50V8J

2
PC158
150P_0402_50V8J

ISNG

ISPG

PWM3

LGATE

GND

GFX@ PL18
0.36UH_PCMC104T-R36MN1R17_30A_20%

CPU_B+

ISEN1

499K_0402_1%

B+

VSUM-

VDDP

VR_ON

PC155
33P_0402_50V8J

PR221

PHASE

34

PH5
470K_0402_5%_TSM0B474J4702RE
PR210 1
2
27.4K_0402_1%

3.83K_0402_1%

LG2

SCLK

470P_0402_50V7K

PWM

33
VSSP2 LGATE2

ALERT#

PR209

change from 43P to 47P


for shortage problem
2010-03-15

PH2

ISEN1

PC144
1 @
2

ISL6208ACRZ-T_QFN8_3X3

36
BOOT2 UGATE2

SDA

10

UGATE

QC@ PR194
0_0402_5%

35
UG2 PHASE2

ISEN2

1 PR203

COMPG

GND

49
5

BOOT2

PGOODG

15

1
2

@ PR208
499_0402_1%

@
1

SVID_SCLK

0_0402_5%

PC141
0.047U_0603_16V7K

For shortage changed

VR_HOT#

+1.05VS_VTT

SVID_ALERT#

VR_ON

BOOT

FCCM

2
PL24
HCB4532KF-800T90_1812
GFX@

ISEN2

1
2
PR206
19.1K_0402_1%

40

VCC

ISEN1

40

15,40

VSSSENSE

IMVP_IMON

SVID_SDA

ISEN2

VGATE

QC@ PR186
0_0603_5%

PU11 QC@

IMONG

ISEN3/ FB2

1.91K_0402_1%
C

VWG

COMP

FB

GFX_CORE_PWRGD

14

+3VS

2
PR196 GFX@
1
1.91K_0402_1%

8 VR_SVID_CLK

8 VR_SVID_ALRT#

40

PR189 @
16.5K_0402_1%

0.22U_0603_10V7K
GFX@

LGATEG

+3VS

8 VR_SVID_DAT

PR197

2.2_0603_5%
GFX@

VSS_AXG_SENSE 9

GFX@ PR183
1
2
10_0402_1%

330P_0402_50V7K
PC127
1
2
GFX@
1000P_0402_50V7K

PC122
1
2

QC@
PQ53
TPCA8030-H_SOP-ADV8-5

+5VS
VCC_AXG_SENSE 9

NTCG

PR191
54.9_0402_1%

2
1

1
2
130_0402_1%
PR190

GFX@ PC134
0.047U_0603_16V7K

GFX@
PR188
18.2K_0402_1%
1
2

For shortage changed

Parallel and tune length

PR175

BOOTG

QC@
PQ56
TPCA8028-H_SOP-ADVANCE8-5

PC121 GFX@
1
2

1
2
GFX@ PR182
2.55K_0402_1%

+1.05VS_VTT
PC135 @
.1U_0402_16V7K

PHASEG

QC@ PR185
0_0402_5%
1
2

PC125 GFX@
1
2

PC124 GFX@
680P_0402_50V7K
1
2

GFX@ PR174 +VGFX_COREP


10_0402_1%
1
2

GFX@ PR173
27.4K_0402_1%

3
2
1

4
1

GFXVR_IMON

VSS_AXG_SENSE

@
PQ50

5
3
2
1
GFX@
PQ51
TPCA8028-H_SOP-ADVANCE8-5 TPCA8030-H_SOP-ADV8-5

0_0603_5%
PR226
UGATEG

GFX@
PQ49

GFX@ PR171
3.83K_0402_1%

GFX@ PR177
1
2
422_0402_1%

PC128
GFX@
150P_0402_50V8J
1
2
1 PR181 GFX@
2
475K_0402_1%

NTCG

330P_0402_50V7K

PC120 GFX@
1000P_0402_50V7K

PR172 GFX@
8.06K_0402_1%
1

1
PR176 @
499K_0402_1%

GFX_B+

GFX@
PH3
470K_0402_5%_TSM0B474J4702RE
1
2
1

PC126
GFX@
39P_0402_50V7K
1
2

VSUM-

@
PC116
470P_0402_50V7K
1
2

PQ61
TPCA8030-H_SOP-ADV8-5

Alert# PU resister need close CPU,


so the PU resister in HW schematic.
but DAT and CLK need close PWM-IC,
so the PU resister in POWER schematic.

Wednesday, October 27, 2010 1

Sheet

55

of

61

Version change list (P.I.R. List)

Item Fixed Issue

Page 1 of 1
for PWR

Reason for change

Rev.PG#

Date

Modify List

Phase

Shut down for


PWM3
pin floating

IF the PWM3 no used,


please pull high it for
+5VS and not floating

OVP problem
with PWR and
HW side

If the HW side is 0V,


through the jumper will
cause the sense pin to
over the votage setting
and it may happen OVP
problem.

0.1

(1)Add PR638(0_0603_5%)
between PWM3 and +5VS
P.55 (2)connect the ISNG to +5VS

0.1

P.55

Change the +VGFX_CORE


to +VGFX_COREP

2010-03-29

DVT

2010-03-29

DVT

COMPAL ELECTRONICS

Title

PIR POWER1

<Title>
Size
A
Date:
5

Document Number

Rev

PAW00(LA-6361P)
Wednesday, October 27, 2010
2

0.1
Sheet

56

of
1

61

VR_ON

(PU1000)
ISL6266ACRZ-T

+CPU_CORE

+1.5VS_DMC

TQFN48
VGA_ON

Page 55

(PU998)
APW7138NITRL
SSOP16

ADAPTER
SYSON

VS_ON

BATTERY

(SUSP#)

VCCPWRGOOD

SUSP

(U13)
SI4800BDY-T1-GE3

VGA_ON#

+1.5VS

Page 44

(PU5)
RT8209BGQW

+1.5V

SUSP

Page 51

(PU6)
RT8209BGQW
WQFN14

(PU8)
APL5331KAC-TRL
SO8

+1.05V_VCCP

Page 53

PJP25

U38

(PU3)
RT8205EGQW

(U40)
AO4430L
SO8

Page 54

WQFN14

B+

+VGA_CORE

+1.5VSDGPU

Page 44

+0.75VS

Page 53
L76

+CLK_1.05VS

+1.05VS_PCH

+1.05VSDGPU

+VCCSA

WQFN24

CHARGER

Page 49

(PU3)
RT8205EGQW
WQFN24

Page 49

+5VALW

SUSP

SYSON#

(U49)
SI4800BDY
SO8

(U46)
TPS2062ADR

Page 44

+3VALW

PCH_PWR_EN#

SUSP

(PU6)
SY8033BDBC
DFN10

Page 51

SO8

SUSP

SUSP

(U14)
SI4800BDY

R599

(RE1)

Page 44

(U68)
SI4800BDY

(UB1)
RT9701-PB

SO8

SOT23-5

Page 44

Page 45

+5VS

+USB_VCCB

+1.8VS

+3VALW_PCH

+3V_LAN

(U39)
BCM57780

+CRT_VCC

+3VALW_EC
ENVDD

ENVDD

(Q51)
AO3413L
SO23-3

+HDMI_5V_OUT

+3V

+3VS

+3VS_CK505
Page 37

+1.2V_LAN

VGA_ON

(Q30)
AO3413L

(Q34)
AO3413L

SO23-3

SO23-3

Page 30

Page 24

+DVDD_AUDIO
+BT_VCC

+LCDVDD

+3VSDGPU

+5VS_HDD1
+3V_WLAN
+5VS_ODD

+3V_DMC
A

+5VAMP

+VDDA

Compal Secret Data

Security Classification

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Power Rail

Size Document Number


Custom
Date:

Rev

0.4
JE50-HR/SJV50-HR M/B Schematics
Sheet

Wednesday, October 27, 2010


1

57

of

61

A3

PU3

+3VALW

B4

EC

B7

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_A#
PM_SLP_SUS#

H_CPUPWRGD
PLT_RST#

14

15

CPU
C

+1.5V
PU5

U68
+3VS

+1.8VSDGPU
U37

U13
+1.5VS
PU8
+0.75V

11
VGATE

+1.5VSDGPU
U40

VCCPPWRGOOD

VGA
B

+1.05VSDGPU
U38

+VGA_CORE
PU998

PU7
+VCCSA

PU9
+1.05VS_VCCP

U49
+5VS

+3VSDGPU
Q6

SUSP#,SUSP

8a (DIS) VGA_ON

SYSON#

DGPU_PWR_EN

SYSON

ON/OFF

B6

A4

PBTN_OUT#

A5

EC_ON

PCH

PM_DRAM_PWRGD

V V

PCH_RSMRST#

V V

B3

SYS_PWROK

13

PQ2

51ON#

+3VALW_PCH
+5VALW_PCH

B+

B2

B7

B1

A5

BATT

B5

B+

U14,+3VALW_PCH
QH4,+5VALW_PCH

A2

PU2

VV

VIN

V V

BATT
MODE

A1

AC
MODE

PCH_PWR_EN#

VGA_PWROK

8b (DIS)

U47
CK505

VR_ON

PU1000
+CPU_CORE

10

Compal Secret Data

Security Classification

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Power sequence

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Sheet

Wednesday, October 27, 2010


1

58

of

61

Page 1

V ersion Change L ist ( P. I. R . L ist )


Item Page#
1

P.18

Title
PCH_GPIO71

D ate
09/01

R equest
O w ner

Solution D escription

Issue D escription

SW

R ev.

For identofy VRAM 900 or 800 MHz

0.2

P.31

DPST buffer

09/03

HW

Change U1 from NOT gate to Buffer

0.2

P.39

EC_MUTE# pull high

09/03

HW

Change EC_MUTE# Pull high from +3VALW to +3VS

0.2

P.40

TP Conn. Reverse

09/03

HW

TP Mudule change,so reverse TP pin

0.2

P.13

09/03

HW

Already pull high R655~

0.2

P.45

09/03

HW

P.35

P.5

R624 pop @
Change Cap from
0.1u to 0.01u
Change 0 Ohm
to 47 Ohm

09/04
09/17

Broadcom

C696,C368,C717,C718,C695,C366,C697,
C401,C370,C369,C715 change to 0.01U
Follow Vendor Suggest ..

0.2

R199,R207,R211,R215,R168,R171,R179,
R182,R195,R216,R192 change to 47 Ohm
Follow Vendor Suggest ..

0.2

CPU XDP socket take off

HW

0.2
C

TP pin reverse

P.40

09/17

HW

10

P.13

09/17

HW

R624 change to 4.7K

0.2

11

P.45

09/17

HW

OCI2B(R313) place @ for BOM

0.2

12

P.33

09/17

HW

HDMI output from PCH (by UMA)

0.2

13

P.35

09/17

0.2

switch the LAN MIDI0 and MIDI2 pin

HW

0.2

Change IO port PLT_RST# to PLT_RST_BUF#

0.2

OPTIMUS_EN# pull high, pull low resistor


value both change to 10K

0.2

14

P.17,35
,37,38,
39,45

09/17

HW

15

P.18

09/17

HW

16

P.24

09/20

HW

modify the VRAM strap pin ROM_SI


pull low resistor for implement VRAM 900MHz

0.3

17

P.33

09/23

HW

Add R784 and R785 for DDC pull high...

0.3

18

P.44

09/23

HW

Add C818 and C819 for coupling noise


from other spare trace...

0.3

19

P.45

09/23

HW

Add R786,R787,R788 and R789 pull down


from vendor's suggestion..

0.3

20

P.37

09/23

HW

Add C820,R790 and Q58 for 3G/B


and change source voltage from +3VS to +3VALW..

09/23

HW

Add C821,C822,C823,C824 for +1.5V...


and move the PJ26 & PJ27 between
1.5V to 1.5VSDGPUH

09/24

HW

Change JUSB5 to USB2.0 Conn.


Add D34 as ESD Diode for USB3.0

21

22

P.45

P.46

0.3

0.3

0.3

Compal Secret Data

Security Classification

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


EE P.I.R (1)

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Sheet

Wednesday, October 27, 2010


1

59

of

61

Page 2

V ersion Change L ist ( P. I. R . L ist )


Item Page#

Title

D ate

R equest
O w ner

Solution D escription

Issue D escription

R ev.

24

P.22

09/24

HW

25

P.36

09/29

HW

Add R791 pull down 22k Ohm to ground


Vendor's request...
Add D31 to connect to ACIN
Vendor's request...
Add JP1,JP2 and JP3 for
ESD protection

26

P.36

09/29

ME

Update the JREAD1 symbol

0.3

27

P.13

09/29

HW

Add R792 follow DG1.5

0.3

28

P.33

09/29

HW

Change HDMI termination R to 680 Ohm

0.3

29

P.44

09/29

30

P.17,38
,45

09/30

HW

31

P.5

10/04

HW

32

P.17,18

10/04

HW

Change the M/B to USB port to port 1


Sub/B to port 0 and port 2
Add test point for TCK,TMS,
TRST#,TDO,TDI
WWAN_OFF# from GPIO51 to GPIO37
WL_OFF# from GPIO55 to GPIO49

33

P.17,45

10/04

HW

M/B USB port from port 2 change to port1

0.3

34

P.26

10/04

HW

C1 and C604 chaneg to 470uF

35

P.36

10/04

HW

Add C827 as DGND and RJ45_GND bridge

0.3
0.3

36

P.36

10/04

HW

Change R490,R491,R492 and R493 to 0603 package

37

P.35

10/04

HW

Chaneg R214 to 0603 package

0.3

38

P.35

10/04

HW

Chaneg R192,R195,R199,R207,R211
,R215,R168,R171,R179,R182 to 0 Ohm

0.3

39

P.40

10/04

HW

follow broadcom suggestion,add R496

0.3

40

P.40

10/04

HW

Add keyboard cap for EMI

0.3

41

P.44

10/04

HW

Add C826 for +1.5VSDGPU

0.3

42

P.37

10/05

HW

43

P.13

10/12

HW

44

P.14

10/12

HW

23

P.41

09/24

HW

0.3
D

0.3

HW

0.3

0.3

Add C825 fro +1.05VSDGPU

0.3
C

0.3
0.3

0.3

Add RTS5138 circuit


Add D35 ,R799 and C838 for
changing the RTC to samll size...
and can be charged!!

0.4

Add CLK_SD_48M for Card Reader 5138

0.4

0.4

45

P.24

10/12

HW

Pop R129 follow NV suggestion

0.4

46

P.25

10/12

HW

Pop R82 and De-pop R92 follow NV suggestion

0.4

47

P.25

10/12

HW

Add R800 and R801 10K Ohm pull down


follow NV suggestion

0.4

48

P.24

10/12

HW

Change R775,R777,R778 and R779 to GV@

0.4

Compal Secret Data

Security Classification

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


EE P.I.R (2)

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Sheet

Wednesday, October 27, 2010


1

60

of

61

Page 3

V ersion Change L ist ( P. I. R . L ist )


Item Page#

Title

D ate

R equest
O w ner

Solution D escription

Issue D escription

R ev.

Compal Secret Data

Security Classification

Issued Date

2010/10/15

2011/10/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


EE P.I.R (3)

Size Document Number


Custom

Rev
0.4

JE50-HR/SJV50-HR M/B Schematics

Date:

Sheet

Wednesday, October 27, 2010


1

61

of

61