Assignment 2

VLSI DSP
Date of issue: 31
st
July 2014
Date of submission: on or before 5.00 PM on 8
th
August 2014
Submit to the Email ID: assignments.arunachalam@gmail.com
Task:
1. Analyze the architecture in terms of number of adders (FAs and HAs) and critical path.
2. Write the Verilog HDL code with comments wherever necessary.
3. Write the suitable test-bench as a separate code.
4. Simulate and take timing diagram for your implementations functional correctness.
5. Synthesize the code and estimate Area, Power and timing details of each adder /
multiplier circuit. (If ASIC, then use one technology library for all the implementations.
If FPGA, then use one particular FPGA chip for all implementations).
6. For all implementations take input word length as 8-bits.

Signed Adder/subtractor to be implemented:
1. Serial adder
2. Parallel adder Carry save adder
3. Parallel adder carry ripple adder
Signed Multipliers to be implemented:
1. Parallel array multiplier Carry save
2. Parallel array multiplier carry ripple
3. Baugh-Wooley multiplier
4. Modified Booth multiplier
Reference:
Keshab K. Parhi, VLSI Digital Signal Processing Systems-Design and Implementation, Weily
Publication, 1999. Chapter 13, Pages 477 to 511.