Professional Documents
Culture Documents
Data Sheet
June 1999
Ordering Information
PART NUMBER
IRF510
PACKAGE
TO-220AB
File Number
1573.3
Features
5.6A, 100V
rDS(ON) = 0.540
Single Pulse Avalanche Energy Rated
SOA is Power Dissipation Limited
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Related Literature
- TB334 Guidelines for Soldering Surface Mount
Components to PC Boards
Symbol
BRAND
IRF510
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
166
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 1999
IRF510
Absolute Maximum Ratings
IRF510
100
100
5.6
4
20
20
43
0.29
19
-55 to 175
UNITS
V
V
A
A
A
V
W
W/oC
mJ
oC
300
260
oC
oC
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
BVDSS
100
VGS(TH)
2.0
4.0
25
IDSS
ID(ON)
IGSS
rDS(ON)
gfs
td(ON)
Rise Time
tr
td(OFF)
Fall Time
250
5.6
VGS = 20V
100
nA
0.4
0.54
1.3
2.0
11
ns
25
36
ns
15
21
ns
12
21
ns
5.0
7.7
nC
2.0
nC
3.0
nC
tf
Qg(TOT)
Qgs
Qgd
Input Capacitance
CISS
135
pF
Output Capacitance
COSS
80
pF
Reverse-Transfer Capacitance
CRSS
20
pF
3.5
nH
4.5
nH
7.5
nH
3.5
oC/W
80
oC/W
LD
LS
Junction to Case
RJC
Junction to Ambient
RJA
167
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
D
LD
G
LS
S
IRF510
Source to Drain Diode Specifications
PARAMETER
SYMBOL
ISD
ISDM
Test Conditions
Modified MOSFET
Symbol Showing the
Integral Reverse
P-N Junction Diode
MIN
TYP
MAX
UNITS
5.6
20
2.5
VSD
trr
4.6
96
200
ns
QRR
0.17
0.4
0.83
NOTES:
2. Pulse test: pulse width 300s, duty cycle 2%.
3. Repetitive rating: pulse width limited by max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 25V, start TJ = 25oC, L = 910H, RG = 25, peak IAS = 5.6A.
1.0
0.8
0.6
0.4
0.2
0
25
125
50
75
100
TC , CASE TEMPERATURE (oC)
150
175
25
50
75
125
100
150
175
ZJC, TRANSIENT
10
THERMAL IMPEDANCE (oC/W)
1.2
0.5
1
0.2
0.1
0.05
0.1
PDM
0.02
0.01
t1
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZJC + TC
0.01
10-5
10-4
0.1
10-2
10-3
t1, RECTANGULAR PULSE DURATION (S)
168
10
IRF510
Typical Performance Curves Unless Otherwise Specified
10
OPERATION IN THIS
REGION IS LIMITED
BY rDS(ON)
VGS = 10V
ID, DRAIN CURRENT (A)
100
10s
10
100s
1ms
1
DC
TC = 25oC
TJ = 175oC
SINGLE PULSE
0.1
(Continued)
VGS = 8V
6
VGS = 7V
4
VGS = 6V
2
VGS = 5V
VGS = 4V
0
102
10
103
10
VGS = 10V
8
VGS = 8V
6
VGS = 7V
4
VGS = 6V
2
VGS = 5V
VGS = 4V
0
2
4
6
8
VDS, DRAIN TO SOURCE VOLTAGE (V)
10
0.1
3.0
NORMALIZED ON RESISTANCE
ON RESISTANCE ()
2
VGS = 10V
VGS = 20V
1
0
12
16
169
TJ = 25oC
TJ = 175oC
2
4
6
8
VGS , GATE TO SOURCE VOLTAGE (V)
10
VDS 50V
PULSE DURATION = 80s
DUTY CYCLE = 0.5% MAX
10-2
0
10
50
40
10
30
20
20
2.4
1.8
1.2
0.6
0
-60 -40
-20
20
40
60
80
IRF510
Typical Performance Curves Unless Otherwise Specified
(Continued)
1.25
500
1.15
C, CAPACITANCE (pF)
ID = 250A
1.05
0.95
200
CISS
COSS
0.85
100
0.75
-60 -40 -20
CRSS
0
20
40
80
60
TJ = 25oC
1.5
TJ = 175oC
1.0
0.5
4
6
ID, DRAIN CURRENT (A)
102
10
TJ = 175oC
TJ = 25oC
0.1
0
10
0.4
0.8
1.2
1.6
VSD, SOURCE TO DRAIN VOLTAGE (V)
20
ID = 3.4A
VDS = 80V
VDS = 50V
VDS = 20V
16
12
4
6
Qg, GATE CHARGE (nC)
10
170
2.0
10
100
2.5
2.0
IRF510
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
IAS
RG
VDS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01
tAV
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
RG
VDD
10%
10%
DUT
90%
VGS
VGS
0.2F
50%
PULSE WIDTH
10%
VDS
(ISOLATED
SUPPLY)
CURRENT
REGULATOR
12V
BATTERY
50%
VDD
Qg(TOT)
SAME TYPE
AS DUT
50k
Qgd
0.3F
VGS
Qgs
D
VDS
DUT
0
IG(REF)
0
IG CURRENT
SAMPLING
RESISTOR
VDS
ID CURRENT
SAMPLING
RESISTOR
171
IG(REF)
0
IRF510
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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172
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ASIA
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