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1 bit register truth table

Clear Enable Clock Data Q


1 X X X 0
0 0 X X Q
0 1 Down 1 1
0 1 Down 0 0

4 bit register truth table


A3 A2 A1 A0 Enable Clock Clear Y3 Y2 Y1 Y0
0 0 0 0 1 DOWN 0 0 0 0 0
0 0 0 1 1 DOWN 0 0 0 0 1
0 0 1 0 1 DOWN 0 0 0 1 0
0 0 1 1 1 DOWN 0 0 0 1 1
0 1 0 0 1 DOWN 0 0 1 0 0
0 1 0 1 1 DOWN 0 0 1 0 1
0 1 1 0 1 DOWN 0 0 1 1 0
0 1 1 1 1 DOWN 0 0 1 1 1
1 0 0 0 1 DOWN 0 1 0 0 0
1 0 0 1 1 DOWN 0 1 0 0 1
1 0 1 0 1 DOWN 0 1 0 1 0
1 0 1 1 1 DOWN 0 1 0 1 1
1 1 0 0 1 DOWN 0 1 1 0 0
1 1 0 1 1 DOWN 0 1 1 0 1
1 1 1 0 1 DOWN 0 1 1 1 0
1 1 1 1 1 DOWN 0 1 1 1 1
X X X X X X 1 0 0 0 0
X X X X 0 X 0 Q Q Q Q

Buffer Truth Table


EN1 EN2 A3 A2 A1 A0 Y3 Y2 Y1 Y0
0 0 1 1 1 1 x x x x
0 1 1 1 1 1 x x x x
1 0 1 1 1 1 x x x x
1 1 1 1 1 1 1 1 1 1

Task 4-5
Microprocessor gate delay = 18 gates
Propagation delay =72 nanoseconds
72 * (10^-9) = 72 nanoseconds
Frequency = 1.38888888 megahertz

Task 4-6
Hex
Input Enable Y0 Y1 Y2 Y3
0 1 1 0 0 0
1 1 0 1 0 0
2 1 0 0 1 0
3 1 0 0 0 1
Task 4-7
EN1 EN2 A3 A2 A1 A0 Y3 Y2 Y1 Y0
0 0 1 0 1 0 x x x x
0 1 1 0 1 0 x x x x
1 0 1 0 1 0 x x x x
1 1 1 0 1 0 1 0 1 0

Task 4-8
MS
A3 A2 A1 A0 Line Write Line Clock Clear Y3 Y2 Y1
0 0 0 0 1 1 DOWN 0 0 0 0
0 0 0 1 1 1 DOWN 0 0 0 0
0 0 1 0 1 1 DOWN 0 0 0 1
0 0 1 1 1 1 DOWN 0 0 0 1
0 1 0 0 1 1 DOWN 0 0 1 0
0 1 0 1 1 1 DOWN 0 0 1 0
0 1 1 0 1 1 DOWN 0 0 1 1
0 1 1 1 1 1 DOWN 0 0 1 1
1 0 0 0 1 1 DOWN 0 1 0 0
1 0 0 1 1 1 DOWN 0 1 0 0
1 0 1 0 1 1 DOWN 0 1 0 1
1 0 1 1 1 1 DOWN 0 1 0 1
1 1 0 0 1 1 DOWN 0 1 1 0
1 1 0 1 1 1 DOWN 0 1 1 0
1 1 1 0 1 1 DOWN 0 1 1 1
1 1 1 1 1 1 DOWN 0 1 1 1
X X X X X X X 1 0 0 0
X X X X 0 0 X 0 Q Q Q
X X X X 0 1 X 0 Q Q Q
X X X X 1 0 X 0 Q Q Q

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