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Question:1

Ans.
1. In the first figure, Gselect branch predictor will best predict the the branching behavior of this
trace. There is identical global history at b13 and b15, so the PC needs to differentiate them.

2. In the second figure, Local branch predictor will best predict the branching behavior of this trace.
There is identical global history at b1, so global history doesnt work. The local history of b1 shows
it alternates taken and not taken.

3. In the third figure, Bimodal branch predictor will best predict the branching behavior of this
trace. All the branches in this trace have a constant behavior, so bimodal predicts well.

Question:2
Ans.
Floating Point
Instruction
Initial state
F0<=LD,a
F2<=LD,0(Rx)
F2<=MULTD,F0,F2
F4<=LD,0(Ry)
F4<=ADDD,F2,F4
F2<=LD,0(Rx)
F2<=MULTD,F0,F2
F4<=LD,0(Ry)
F4<=ADDD,F2,F4

Pending target return


queue after
instruction rename

Free List after


Instruction Completed

0
2.0
0
4.0
0
33.0
0
34.0
0

32,33,34,35,36,37,38,39
33,34,35,36,37,38,39
34,35,36,37,38,39
34,35,36,37,38,39,2
35,36,37,38,39,2
35,36,37,38,39,2,4
36,37,38,39,2,4,33
37,38,39,2,4,33
37,38,39,2,4,33,34

Map

Table

Select

F0

F2

F4

0
32
32
32
32
32
32
32
32
32

2
2
33
33
33
33
35
35
35
35

4
4
4
4
34
34
34
34
36
36

Question:3
Ans.

Question: 4
Ans. Critical path is 1+3+3=7 cycles
Prob. 18 executes in 7 cycles.
Therefore, Tomasulo algorithm executes this at
the dataflow limit.

Question: 5
Ans.
Load Reservation Station

1
2
3
4
5
6
7
8
9
10
11
12

Store Reservation
Station

Store Buffer

Cache
Address

Cache
Write
Data

St A
Ld B
Ld A
Ld A
Ld A
Ld A
Ld A

Ld E
Ld D
Ld D
Ld D
Ld D
Ld D
Ld D
Ld D

Ld A
Ld A
Ld A
Ld A
Ld A

St D

St A
St A
St A
St A
St A

Ld B
St D
St D
St D
St D
St D
St D

Ld E
St A
Ld A
Ld A

Data

St D
Ld D

Data

Question: 6
Ans.
Reference
Address
[int state]
200
A0
200
E0
B0
80
200
A0
80

Hit/Miss

M
M
M
M
M
M
H victim
H victim
H victim

Line 0
200

Direct Mapped Cache


Line 1
Line 2
110
-

Line 3
FF0

Victim Cache
Line 0
Line 1
1F0
210/LRU

A0
200
E0

1F0/LRU

A0

200
80
80/LRU
A0

A0/LRU
A0/LRU
E0
E0/LRU

B0
80
200

E0
A0
80