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Digital Logic Lab 1

Aim To simulate a Full Adder using both sequential and concurrent statements.

Sequential
Code
Process(I1,I2,I3)
begin
if I1='0' and I2='0' and I3='0' then SUM <='0'; CARRY <='0';
elsif I1='0' and I2='0' and I3='1' then SUM <='1'; CARRY <='0';
elsif I1='0' and I2='1' and I3='0' then SUM <='1'; CARRY <='0';
elsif I1='0' and I2='1' and I3='1' then SUM <='0'; CARRY <='1';
elsif I1='1' and I2='0' and I3='0' then SUM <='1'; CARRY <='0';
elsif I1='1' and I2='0' and I3='1' then SUM <='0'; CARRY <='1';
elsif I1='1' and I2='1' and I3='0' then SUM <='0'; CARRY <='1';
elsif I1='1' and I2='1' and I3='1' then SUM <='1'; CARRY <='1';
else SUM<='0';CARRY<='0';
end if;
end Process;

Waveform

TTL Schematic

Concurrent
Code
SUM <= '0' when I1 ='0' and I2='0' and I3='0' else
'1' when I1 ='0' and I2='0' and I3='1' else
'1' when I1 ='0' and I2='1' and I3='0' else
'0' when I1 ='0' and I2='1' and I3='1' else
'1' when I1 ='1' and I2='0' and I3='0' else
'0' when I1 ='1' and I2='0' and I3='1' else
'0' when I1 ='1' and I2='1' and I3='0' else
'1' when I1 ='1' and I2='1' and I3='1' else
'0';

CARRY <= '0' when I1 ='0' and I2='0' and I3='0' else
'0' when I1 ='0' and I2='0' and I3='1' else
'0' when I1 ='0' and I2='1' and I3='0' else
'1' when I1 ='0' and I2='1' and I3='1' else
'0' when I1 ='1' and I2='0' and I3='0' else
'1' when I1 ='1' and I2='0' and I3='1' else
'1' when I1 ='1' and I2='1' and I3='0' else
'1' when I1 ='1' and I2='1' and I3='1' else
'0';

Waveform

TTL Schematic

Test bench Code


I1<='0';
I2<='0';
I3<='0';
wait for 100 ns;
Other cases are similarly added

Conclusion
As the order of the statements is same (binary order) both sequential ,concurrent statements result
in the same TTL Schematic. In more complex cases generally Sequential commands result in a circuit
with a larger delay than an equivalent concurrent code. The implementation was tested using the
testbench and the obtained waveform confirms the correctness of the implemented Full Adder