Power Planning Signal Route Closure PDF

CAE Best Practices for
Power Planning at Advanced Nodes

Enabling Signal Routing Closure
Router CAE Team

September 2013
2014 Synopsys, Inc. All rights reserved. 1
CONFIDENTIAL INFORMATION
The following material is confidential information of Synopsys and is being
disclosed to you pursuant to a non-disclosure agreement between you or your
employer and Synopsys. The material being disclosed may only be used as
permitted under such non-disclosure agreement.
IMPORTANT NOTICE
In the event information in this presentation reflects Synopsys future plans,
such plans are as of the date of this presentation and are subject to
change. Synopsys is not obligated to develop the software with the features
and functionality discussed in these materials. In any event, Synopsys
products may be offered and purchased only pursuant to an authorized quote
and purchase order or a mutually agreed upon written contract.
Objectives
Designing a power plan at emerging nodes
Understand the challenges introduced by advanced rules
associated with the power mesh
Learn design guidelines and best practices
Improve signal routing closure and design predictability
Agenda
Power Mesh Structure
Challenges and guidelines
Effects of various power mesh structures
Pin Access
set_pnet_options
Obstructions from the power meshs via array
Design Rule Closure
Global routing and detail routing predictability

Double patterning technology
Fat spacing
Wide metal jogs
Forbidden spacing
Customized contact codes

Trend from established to advanced nodes
Process (nm)
Width (um)
Space (um)
minWidth (um)
130~250
10~20
< 500
0.16
65~90
5~10
< 100
0.10
28~40
<2
20~30
0.05
14~20
< 0.5
~5
0.032
Larger width and interval

Smaller width and interval

Challenges to signal routing closure
Pin access blocked
More routing resources and tracks consumed
Detours at a later signal routing stage predictability
issue
Pin access points
not utilized
Blocked signal
wire tracks
T3
S_fat
T1
T0
T2
T4
W_fat
Detours and jogs

around PG vias

Guidelines for advanced process nodes
Minimize PG mesh on double-patterning layers
Spare M3 and M4 space for signal routes
Avoid high via walls
Avoid clusters of via arrays
Adjust PG wires to improve signal routability

Minimize the number of tracks occupied by PG wires
Increase PG wire width (smaller widths can trigger additional DRC
rules, especially at advanced process nodes)
Use preferred routing direction only
Consider impact during PG rail implementation

Dual PG rails; both M1 and M2
Might need wider M2 rail to improve electromigration and voltage drop

Avoid high via walls
Stacked via arrays create high walls
Leads to high wire density and detours around via walls
Two-tier mesh
Multi-tier mesh
M8
M8
M8
M7
M7
M7
M6
M6
M6
M5
M5
M5
M4
M4
M4
M3
M3
M3
M2
M2
M2
M1
M1
M1

Avoid clusters of via arrays
Clustered via arrays lead to detours and jogs
M8 detours
Pair distributed
P G
M7 detours
P G
P
G
Pitch
P
G
M3 detours
Cluster of PG via
arrays can impact
the routability on
double-patterning
layers

Improvement by avoiding clusters of via arrays
Fewer detours
Good utilization of routing tracks
M8
Evenly distributed
P
P
Sy
M3
G
Sx
P
M7

Paired versus evenly distributed PG meshes
Pros and Cons
Paired PG provides more routing
tracks but creates clustered via
arrays that impact routing
closure on double-patterning
(DPT) layers
Evenly distributed PG provides a
better routing pattern in the
preferred direction but has fewer
routing tracks for signals
In every 4x4um
window
Paired PG
(# tracks)
Even PG
(# tracks)
M5: (Vertical straps

on non-DPT layers)
44
41
M3: (Via arrays on

DPT layers)
See further analysis on the next page

51
(Clustered
via arrays)
53
Paired Versus Even PG Mesh

Detours to DPT layers invoke additional routing rules
Layer
M1 :
192 micron
Layer
M2 :
265950 micron
Layer
M3 :
584545 micron
Layer
M4 :
688482 micron
Layer
M5 :
486747 micron
Layer
M6 :
34731 micron
Paired: M3
Even: M3
Recommendations (2-tier mesh)

Build a paired PG mesh on upper layers
and do not connect all the way to rails
Build an evenly distributed PG mesh on
lower layers and connect through rails
Utilize Routing Tracks Efficiently

Shift PG wires
Shift PG wires for the fewest number of blocked tracks
4 tracks blocked
Now only 3 tracks blocked
Utilize Routing Tracks Efficiently

Widen PG wires
Expand PG wire width without impacting adjacent tracks
For electromigration and voltage-drop improvement
At emerging nodes, a wider strap might have fewer design rules
T3
T3
T1
T1
W2
T0
W1
T2
T4
T0
W1
T2
T4
PG Rail Implementation
Improve reliability
Dual PG rail both M1 and M2 rail
Might require a wider M2 rail for electromigration and voltage-drop
improvement
Use a wider width to utilize adjacent tracks
T3
T1
W2
M1 Rail
M2 Rail
T0
T2
T4
W1
Summary for Power Mesh Structure

Use PG straps in pairs at higher (non-double-patterning)
layers
Prevent clusters of via arrays on double-patterning layers
Always utilize routing tracks from PG wires efficiently
Agenda
Pin Access
set_pnet_options
Obstructions from power meshs via array
Design Rule Closure
Global routing and detail routing predictability

Fat spacing
Wide metal jogs
Forbidden spacing
Pin Access
Expose more room by using set_pnet_options
Some designs use very thin M3 straps for the secondary
power mesh
Need set_pnet_options to allow standard cells under
the M3 mesh and still expose sufficient space for pin access
M3 strap
M2 pin
Legalize
placement
M3 strap
M2 pin
Pin Access Versus VIA2 PG Array

M3 enclosure obstructs the signal wires incoming
Cause:
A bigger M3 enclosure for the power mesh via array on VIA2
blocks the M3 access to M1 and M2 pins
Fewer pin access points
Recommendation: Use a thinner PG array

VIA2 PG array
Use a thinner array
M1 Rail
a
M1 pin
c
M1 Rail
b
M3 wire
a
M1 pin
c
b
M3 wire
Pin Access Versus PG Cut Spacing

PG cut types affect a pins via landing
VIA1
VIA1
M1 Rail
X
M1 pin
M1 Rail
X
M2 wire
This pin has only one access point;

the other two points are blocked due
to the larger minimum spacing
between a square cut and a
rectangle cut
M1 pin
M2 wire
This pin has three access points; two

additional points are gained due to the
smaller minimum spacing between
two square cuts
Pin Access Versus VIA2 PG Array

Real example M3 vacancy leads to limited pin access
In this standard cell, four M1 access points (a, b, c and d)
are NOT available due to M3 obstruction from the PG array
on VIA2
This issue is caused by the end-of-line spacing requirement
d
VIA2 PG array
VIA2 PG array
VIA2 Array
Pin Accessibility While Cell Shrinks

More problems occur on double-patterning layers
Fewer horizontal M2 tracks available for pin access
Vertical M3 tracks limited by the end-of-line spacing rule
Staggered via arrays increase local congestion on
M2 and M3
M3 end-of-line and via
spacing rules take effect
Clustered PG
via arrays
12-track
9-track
Summary for Pin Access

Avoid M3 PG straps
Can use set_pnet_options to better expose pins

Avoid clustering of via arrays on double-patterning
(lower) layers
Choose proper cut type for smaller spacing requirements
Agenda
Pin Access
set_pnet_options
Obstructions from power meshs via array
Design Rule Closure
Correlation between global routing and detail routing

Fat spacing
Wide metal jogs
Forbidden spacing
Challenges to Design Closure

Rapidly growing advanced design rules
Predictability from global routing to
detail routing
Detours
Timing fluctuation
Long buffer chain
Net detouring occurs only

during detail routing
DRC convergence
1
Violations along
PG via arrays
Advanced design
rule violation
DRC over fixed that tracks

were not properly utilized
Global Routing to Detail Routing Closure

Global Router Did Not Consider End-of-Line Spacing
Lessons learned:
-
Global router did not see additional spacing requirement around

PG via arrays
No congestion seen during global routing but many DRC
violations left after detail routing
Detours occurred during detail routing when the nets were
rerouted to fix DRC violations
Numerous violations
along PG VIA arrays
End-of-line spacing
violation
Detour net only seen until

DR stage
Global Routing to Detail Routing Closure

Workaround for End-of-Line Spacing Issue
Workaround steps:
-
Increase size of PG via arrays, and then run global routing

The global router makes more accurate congestion estimation by
seeing the additional tracks required from the larger via array
Change PG via arrays back to original size, and then run detail
routing
The detail router has more room to meet the end-of-line spacing
rule introduced by the original thin via array
Solution:
-
Global router enhanced in 2011 to estimate the cost of the end-ofline rule
Global Router Predictability Enhancement

Honors exclude range of fat metal spacing rule
fatTbl*ExcludedSpacingRange defines regions where
spacing checks are ignored
fatTblPrefWidthThreshold
= (W1, W2, W3,.)
fatTblPrefToPrefXMinSpacing
= (0.042,0.042, 0.042,
spacing
0.042,0.080, 0.080,
)
fatTblPrefYExcludedSpacingRange = ("0.044, 0.070", "0.044, 0.070",

)
Spacing checks
ignored
In I-2013.12-SP3, the global router honors these regions

and provides accurate congestion estimation
Design Rule Closure

Double-patterning spacing rule
Cause:
VDD1 and VDD2 rails on M1 are
separated by mininum spacing
No double-patterning violations
because routes in preferred routing
direction
VDD1
VDD2
After placing standard cells, M1

odd cycle is formed by the metal
shapes inside cells and PG rails
1
2
VSS
VDD1
3
VDD2
Solution: Increase spacing between M1 rails for different

supply voltages
Design Rule Closure

Fat metal spacing rule
Cause: Smaller wire width can trigger more design rules
= (0.068,0.086,0.136,..)
fatTblPrefYExcludedSpacingRange = (-1, -1, -1, .
fatTblPrefYParallelLengthDimension = 3
-1, "0.044, 0.070", "0.044, 0.070",
fatTblPrefYParallelLengthThreshold = (0,0.150,0.200,)
-1, "0.044, 0.070", "0.044, 0.070",
-1, "0.044, 0.070", "0.044, 0.070",
= (0.034,0.034,0.034,
0.034,0.082,0.082,
0.034,0.110,0.110,
T3
S=0.082
T1
T0
T2
T4
W=0.09
Exclude spacing check

in these regions
Design Rule Closure

Fat metal spacing rule - Improvement
Solution: Widen wire to make the next track available for
signal routing
= (0.068,0.086,0.136,..)
fatTblPrefYExcludedSpacingRange = (-1, -1, -1, .
fatTblPrefYParallelLengthDimension = 3
-1, "0.044, 0.070", "0.044, 0.070",
fatTblPrefYParallelLengthThreshold = (0,0.150,0.200,)
-1, "0.044, 0.070", "0.044, 0.070",
-1, "0.044, 0.070", "0.044, 0.070",
= (0.034,0.034,0.034,
0.034,0.082,0.082,
0.034,0.110,0.110,
T3
T3
S=0.082
T1
T0
S=0.110
T1
W=0.09
T0
T2
T2
T4
T4
W=0.14
Design Rule Closure

Wide metal jog spacing rule
Cause: Redundant via insertion
fatMetalJogTblSize
fatMetalJogThresholdTbl
= (0.275,0.490,0.700,)
OK
fatMetalJogLengthTblSize
=2
fatMetalJogLengthTbl
= (0,0.22)
fatMetalJogMinSpacingTbl = (0.07,0.15,
0.07,0.18,
P G
P
G
P G
Failed
A
Wide metal
jog violation
Design Rule Closure

Wide metal jog spacing rule - Improvement
Solution: Space the PG pair further apart to avoid wide
metal jog rule violations
OK
A
Design Rule Closure

Forbidden spacing rule How does it happen?
Forbidden spacing violation blocks 2 to 3 routing tracks
Occurs when a metal shape is off-track or wider
Can cause detours after rerouting
Ideal case: all wires on track
T0
T1
T2
T3
DRC violation occurs when off track
T0
T1
T2
C
T3
Design Rule Closure

Forbidden spacing rule Where does it happen?
Generally occurs around PG via arrays
Off-track PG via array
Forbidden spacing violations
PG mesh
P
Wide PG via array
P
Sy
G
Sx
P
Design Rule Closure

Forbidden spacing rule - Improvement
Three Solutions:
1. Move a thin via array on track
2. Shift the edge of a wide via array outside the forbidden region
T0
T1
T2
C
T3
T0
T1
T2
minWidth
T3
A
B
Design Rule Closure

Forbidden spacing rule Improvement (Continued)
3. Pick a wider via array that can be waived from the
forbidden*MaxWidth* rule
forbiddenSpacePrefForbiddenWireMaxWidthTbl
= (Wmax1, Wmax2)
forbiddenSpaceWireMaxWidthThreshold
= Wmax
forbiddenSpacePrefTblSize
= .
forbiddenSpaceWireMaxSpacingThreshold
= .
forbiddenSpacePrefWireWidthTbl
forbiddenSpaceWireParallelLength
forbiddenSpacePrefWireSpacingTbl
forbiddenSpaceRangeTblSize
forbiddenSpacePrefRangeTbl
forbiddenSpaceRangeTbl
T2
T2
C
T3
T3
> Wmax
Design Rule Closure

Customize contact codes
Add new contact codes with specific dimensions for PG routing, but
exclude them for signal routing
ContactCode
"V1_PG_Only" {
contactCodeNumber
= 220
cutLayer
= "via1"
excludedForSignalRoute
=1
upperLayerEncWidth
upperLayerEncHeight
.
minCutSpacing
Exclude contact codes for PG routing to prevent DRC violations

ContactCode
"V1_Signal_Only" {
contactCodeNumber
cutLayer
= 220
= "via1"
excludedForPGRoute = 1
Design Rule Closure

Customize contact codes - Example
ContactCode
"V2_PG_Only" {
contactCodeNumber
= 220
cutLayer
= "via2"
excludedForSignalRoute
=1
upperLayerEncWidth
upperLayerEncHeight
lowerLayerEncWidth
lowerLayerEncHeight
minCutSpacing
To avoid forbidden spacing rule violations,

Ensure both ends of the via array have exactly half-width
extension from the routing track
Via array dimension R = NxPitch+minWidth for both

vertical and horizontal directions
Summary
Design rules at emerging nodes bring new

challenges to PG planning and design closure
Use PG mesh to provide pin access and routing
tracks for signals
Minimize the PG shapes on double-patterning
technology layers
Thank You

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CAE Best Practices for

Power Planning at Advanced Nodes

Router CAE Team

2014 Synopsys, Inc. All rights reserved. 1

2014 Synopsys, Inc. All rights reserved. 2

Improve signal routing closure and design predictability

2014 Synopsys, Inc. All rights reserved. 3

Design Rule Closure

Global routing and detail routing predictability

2014 Synopsys, Inc. All rights reserved. 4

Power Mesh Structure

Larger width and interval

Smaller width and interval

Power Mesh Structure

Detours and jogs

Power Mesh Structure

Adjust PG wires to improve signal routability

Consider impact during PG rail implementation

Power Mesh Structure

2014 Synopsys, Inc. All rights reserved. 8

Power Mesh Structure

2014 Synopsys, Inc. All rights reserved. 9

Power Mesh Structure

2014 Synopsys, Inc. All rights reserved. 10

Power Mesh Structure

M5: (Vertical straps

M3: (Via arrays on

See further analysis on the next page

Paired Versus Even PG Mesh

Recommendations (2-tier mesh)

Utilize Routing Tracks Efficiently

Now only 3 tracks blocked

2014 Synopsys, Inc. All rights reserved. 13

Utilize Routing Tracks Efficiently

2014 Synopsys, Inc. All rights reserved. 14

2014 Synopsys, Inc. All rights reserved. 15

Summary for Power Mesh Structure

Always utilize routing tracks from PG wires efficiently

2014 Synopsys, Inc. All rights reserved. 16

Design Rule Closure

Global routing and detail routing predictability

2014 Synopsys, Inc. All rights reserved. 17

2014 Synopsys, Inc. All rights reserved. 18

Pin Access Versus VIA2 PG Array

Recommendation: Use a thinner PG array

Use a thinner array

Pin Access Versus PG Cut Spacing

This pin has only one access point;

This pin has three access points; two

Pin Access Versus VIA2 PG Array

2014 Synopsys, Inc. All rights reserved. 21

Pin Accessibility While Cell Shrinks

2014 Synopsys, Inc. All rights reserved. 22

Summary for Pin Access

Can use set_pnet_options to better expose pins

2014 Synopsys, Inc. All rights reserved. 23

Design Rule Closure

Correlation between global routing and detail routing

2014 Synopsys, Inc. All rights reserved. 24

Challenges to Design Closure

Net detouring occurs only

DRC over fixed that tracks