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ABSTRACT

The Flip-Flop is the basic element in Digital Circuits. The Flip-Flop of masterslave type is used in processor. The Flip-Flop is designed using CMOS Technology.
Power consumption, speediness and accuracy are common requirement of system. To
obtain an accurate system design, a new type of Flip-Flop called Pulse Triggered FlipFlop is implemented. In this Flip-Flop, Pulse Generator circuit is part of Flip-Flop
gives a edge triggered pulse for clock system which will used for sharing pulse signal
to other Flip-Flop's to reduce power consumption.
In this project, several Flip-Flops are evaluated and computation of delays and
power are observed. The proposed implementation of Flip-Flop based on Signalfeed
Through Scheme (STSFF) is designed and implemented, where large power saving
with less delay is required. These schemes having Pulse Generator, Modified True
Single Phase Clock (TSPC) latch and Keeper Device elements. Some part of output
signal is feedback to TSPC latch which improves signal further. Simulation results
shows that the proposed design gives better performance compared to existing FlipFlops in terms of power, delay, area, Power Delay Product (PDP).
The proposed circuits are analyzed through simulation using
1. T-Spice
2. L-Edit
3. S-Edit
software tools of Tanner EDA. We can observe in this thesis that Tanner EDA tool is
a powerful tool for the interactive design in most of the CMOS Design and
engineering calculations.