What is the criteria for choosing CORE TO IO DISTANCE??

How should i select the

core to IO distance
This really depends on the requirements of the design, but a typical thing to d
o is to leave enough space between the IO ring and the core for your core power
rings.
If i'm have a power ring width of 5u for VDD and 5u for VSS and a spacing of 2.5
u between the rails can you say some approximate core to IO distance.Can i fix t
he distance as 5u+5u+2.5u=12.5u.
Also please tell me what is the significance of adding a offset for the power ra
ils from the core? How should i fix that distance?
You definitely want enough space for your VDD and VSS ring plus the space betwee
n them (5u+5u+2.5u), but also add some space for the distance from the edge of y
our IO cells to the start of the pwr/gnd ring and from the other side of the pwr
/gnd ring to the core, so that you don't have metal spacing violations in these
areas. You could look in your LEF file for the largest spacing rule for the meta
ls and use that value (use the spacing rule for the widest metal on the IO side,
since there may be wide metal busses inside the IO).
what is the criteria for selecting core utilization?? When i import a design int
o encounter , a core area comes by itself with a default core utilization.?On wh
at basis the tool does this? How could i get an optimized value for my CORE AREA
, CORE UTILIZATION?
It really depends on the technology, library, number of routing layers, etc. It
can also depend on the timing and how much timing margin you want. For example,
if you want to fix hold timing with 100ps extra margin, you will need more room
for buffers. I typically start a block at about 65%. Sometimes we find we need a
lower util, sometimes we find we can squeeze it tighter. It can also depend on
how much of your design is std cells and how much is RAM or other IP.
The die size is determined by die corner rule, seal ring width and scribe line
You can pick a size that gives you a starting core utilization of, say, 55%, the
n take the design through place and route and see how things look. Is there plac
ement congestion? Routing congestion? Do you have enough room for any special re
quirements, like space around analog macros, room for shielded analog routes, et
c? The more designs you do, the more of a feel you'll get for sizing the core. I
t's very design/technology dependent, and there's no simple formula.
How to calculate the channel spacing between macros?
The formula would be (width+spacing x number of pins /vertical routing layers)
+ spacing
mincut via violation